3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
5 * Copyright © 2005 Agere Systems Inc.
9 *------------------------------------------------------------------------------
11 * et1310_eeprom.c - Code used to access the device's EEPROM
13 *------------------------------------------------------------------------------
17 * This software is provided subject to the following terms and conditions,
18 * which you should read carefully before using the software. Using this
19 * software indicates your acceptance of these terms and conditions. If you do
20 * not agree with these terms and conditions, do not use the software.
22 * Copyright © 2005 Agere Systems Inc.
23 * All rights reserved.
25 * Redistribution and use in source or binary forms, with or without
26 * modifications, are permitted provided that the following conditions are met:
28 * . Redistributions of source code must retain the above copyright notice, this
29 * list of conditions and the following Disclaimer as comments in the code as
30 * well as in the documentation and/or other materials provided with the
33 * . Redistributions in binary form must reproduce the above copyright notice,
34 * this list of conditions and the following Disclaimer in the documentation
35 * and/or other materials provided with the distribution.
37 * . Neither the name of Agere Systems Inc. nor the names of the contributors
38 * may be used to endorse or promote products derived from this software
39 * without specific prior written permission.
43 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
44 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
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58 #include "et131x_version.h"
59 #include "et131x_defs.h"
61 #include <linux/pci.h>
62 #include <linux/init.h>
63 #include <linux/module.h>
64 #include <linux/types.h>
65 #include <linux/kernel.h>
67 #include <linux/sched.h>
68 #include <linux/ptrace.h>
69 #include <linux/slab.h>
70 #include <linux/ctype.h>
71 #include <linux/string.h>
72 #include <linux/timer.h>
73 #include <linux/interrupt.h>
75 #include <linux/delay.h>
76 #include <linux/bitops.h>
78 #include <asm/system.h>
80 #include <linux/netdevice.h>
81 #include <linux/etherdevice.h>
82 #include <linux/skbuff.h>
83 #include <linux/if_arp.h>
84 #include <linux/ioport.h>
86 #include "et1310_phy.h"
87 #include "et1310_pm.h"
88 #include "et1310_jagcore.h"
89 #include "et1310_eeprom.h"
91 #include "et131x_adapter.h"
92 #include "et131x_initpci.h"
93 #include "et131x_isr.h"
95 #include "et1310_tx.h"
99 static int eeprom_wait_ready(struct pci_dev *pdev, u32 *status)
105 * 1. Check LBCIF Status Register for bits 6 & 3:2 all equal to 0 and
106 * bits 7,1:0 both equal to 1, at least once after reset.
107 * Subsequent operations need only to check that bits 1:0 are equal
108 * to 1 prior to starting a single byte read/write
111 for (i = 0; i < MAX_NUM_REGISTER_POLLS; i++) {
112 /* Read registers grouped in DWORD1 */
113 if (pci_read_config_dword(pdev, LBCIF_DWORD1_GROUP, ®))
116 /* I2C idle and Phy Queue Avail both true */
117 if ((reg & 0x3000) == 0x3000) {
128 * eeprom_write - Write a byte to the ET1310's EEPROM
129 * @etdev: pointer to our private adapter structure
130 * @addr: the address to write
131 * @data: the value to write
133 * Returns 1 for a successful write.
135 static int eeprom_write(struct et131x_adapter *etdev, u32 addr, u8 data)
137 struct pci_dev *pdev = etdev->pdev;
147 * For an EEPROM, an I2C single byte write is defined as a START
148 * condition followed by the device address, EEPROM address, one byte
149 * of data and a STOP condition. The STOP condition will trigger the
150 * EEPROM's internally timed write cycle to the nonvolatile memory.
151 * All inputs are disabled during this write cycle and the EEPROM will
152 * not respond to any access until the internal write is complete.
155 err = eeprom_wait_ready(pdev, NULL);
160 * 2. Write to the LBCIF Control Register: bit 7=1, bit 6=1, bit 3=0,
161 * and bits 1:0 both =0. Bit 5 should be set according to the
162 * type of EEPROM being accessed (1=two byte addressing, 0=one
165 if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
166 LBCIF_CONTROL_LBCIF_ENABLE | LBCIF_CONTROL_I2C_WRITE))
171 /* Prepare EEPROM address for Step 3 */
173 for (retries = 0; retries < MAX_NUM_WRITE_RETRIES; retries++) {
174 /* Write the address to the LBCIF Address Register */
175 if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER, addr))
178 * Write the data to the LBCIF Data Register (the I2C write
181 if (pci_write_config_byte(pdev, LBCIF_DATA_REGISTER, data))
184 * Monitor bit 1:0 of the LBCIF Status Register. When bits
185 * 1:0 are both equal to 1, the I2C write has completed and the
186 * internal write cycle of the EEPROM is about to start.
187 * (bits 1:0 = 01 is a legal state while waiting from both
188 * equal to 1, but bits 1:0 = 10 is invalid and implies that
189 * something is broken).
191 err = eeprom_wait_ready(pdev, &status);
196 * Check bit 3 of the LBCIF Status Register. If equal to 1,
197 * an error has occurred.Don't break here if we are revision
198 * 1, this is so we do a blind write for load bug.
200 if ((status & LBCIF_STATUS_GENERAL_ERROR)
201 && etdev->pdev->revision == 0)
205 * Check bit 2 of the LBCIF Status Register. If equal to 1 an
206 * ACK error has occurred on the address phase of the write.
207 * This could be due to an actual hardware failure or the
208 * EEPROM may still be in its internal write cycle from a
209 * previous write. This write operation was ignored and must be
212 if (status & LBCIF_STATUS_ACK_ERROR) {
214 * This could be due to an actual hardware failure
215 * or the EEPROM may still be in its internal write
216 * cycle from a previous write. This write operation
217 * was ignored and must be repeated later.
228 * Set bit 6 of the LBCIF Control Register = 0.
233 if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
234 LBCIF_CONTROL_LBCIF_ENABLE))
237 /* Do read until internal ACK_ERROR goes away meaning write
241 pci_write_config_dword(pdev,
242 LBCIF_ADDRESS_REGISTER,
245 pci_read_config_dword(pdev,
246 LBCIF_DATA_REGISTER, &val);
247 } while ((val & 0x00010000) == 0);
248 } while (val & 0x00040000);
250 if ((val & 0xFF00) != 0xC000 || index == 10000)
254 return writeok ? 0 : -EIO;
258 * eeprom_read - Read a byte from the ET1310's EEPROM
259 * @etdev: pointer to our private adapter structure
260 * @addr: the address from which to read
261 * @pdata: a pointer to a byte in which to store the value of the read
262 * @eeprom_id: the ID of the EEPROM
263 * @addrmode: how the EEPROM is to be accessed
265 * Returns 1 for a successful read
267 static int eeprom_read(struct et131x_adapter *etdev, u32 addr, u8 *pdata)
269 struct pci_dev *pdev = etdev->pdev;
274 * A single byte read is similar to the single byte write, with the
275 * exception of the data flow:
278 err = eeprom_wait_ready(pdev, NULL);
282 * Write to the LBCIF Control Register: bit 7=1, bit 6=0, bit 3=0,
283 * and bits 1:0 both =0. Bit 5 should be set according to the type
284 * of EEPROM being accessed (1=two byte addressing, 0=one byte
287 if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
288 LBCIF_CONTROL_LBCIF_ENABLE))
291 * Write the address to the LBCIF Address Register (I2C read will
294 if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER, addr))
297 * Monitor bit 0 of the LBCIF Status Register. When = 1, I2C read
298 * is complete. (if bit 1 =1 and bit 0 stays = 0, a hardware failure
301 err = eeprom_wait_ready(pdev, &status);
305 * Regardless of error status, read data byte from LBCIF Data
310 * Check bit 2 of the LBCIF Status Register. If = 1,
311 * then an error has occurred.
313 return (status & LBCIF_STATUS_ACK_ERROR) ? -EIO : 0;
316 int et131x_init_eeprom(struct et131x_adapter *etdev)
318 struct pci_dev *pdev = etdev->pdev;
321 /* We first need to check the EEPROM Status code located at offset
322 * 0xB2 of config space
324 pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS,
327 /* THIS IS A WORKAROUND:
328 * I need to call this function twice to get my card in a
329 * LG M1 Express Dual running. I tried also a msleep before this
330 * function, because I thougth there could be some time condidions
331 * but it didn't work. Call the whole function twice also work.
333 if (pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS, &eestatus)) {
335 "Could not read PCI config space for EEPROM Status\n");
339 /* Determine if the error(s) we care about are present. If they are
340 * present we need to fail.
342 if (eestatus & 0x4C) {
343 int write_failed = 0;
344 if (pdev->revision == 0x01) {
346 static const u8 eedata[4] = { 0xFE, 0x13, 0x10, 0xFF };
348 /* Re-write the first 4 bytes if we have an eeprom
349 * present and the revision id is 1, this fixes the
350 * corruption seen with 1310 B Silicon
352 for (i = 0; i < 3; i++)
353 if (eeprom_write(etdev, i, eedata[i]) < 0)
356 if (pdev->revision != 0x01 || write_failed) {
358 "Fatal EEPROM Status Error - 0x%04x\n", eestatus);
360 /* This error could mean that there was an error
361 * reading the eeprom or that the eeprom doesn't exist.
362 * We will treat each case the same and not try to gather
363 * additional information that normally would come from the
364 * eeprom, like MAC Address
366 etdev->has_eeprom = 0;
370 etdev->has_eeprom = 1;
372 /* Read the EEPROM for information regarding LED behavior. Refer to
373 * ET1310_phy.c, et131x_xcvr_init(), for its use.
375 eeprom_read(etdev, 0x70, &etdev->eepromData[0]);
376 eeprom_read(etdev, 0x71, &etdev->eepromData[1]);
378 if (etdev->eepromData[0] != 0xcd)
379 /* Disable all optional features */
380 etdev->eepromData[1] = 0x00;