3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
5 * Copyright © 2005 Agere Systems Inc.
9 *------------------------------------------------------------------------------
11 * et1310_tx.c - Routines used to perform data transmission.
13 *------------------------------------------------------------------------------
17 * This software is provided subject to the following terms and conditions,
18 * which you should read carefully before using the software. Using this
19 * software indicates your acceptance of these terms and conditions. If you do
20 * not agree with these terms and conditions, do not use the software.
22 * Copyright © 2005 Agere Systems Inc.
23 * All rights reserved.
25 * Redistribution and use in source or binary forms, with or without
26 * modifications, are permitted provided that the following conditions are met:
28 * . Redistributions of source code must retain the above copyright notice, this
29 * list of conditions and the following Disclaimer as comments in the code as
30 * well as in the documentation and/or other materials provided with the
33 * . Redistributions in binary form must reproduce the above copyright notice,
34 * this list of conditions and the following Disclaimer in the documentation
35 * and/or other materials provided with the distribution.
37 * . Neither the name of Agere Systems Inc. nor the names of the contributors
38 * may be used to endorse or promote products derived from this software
39 * without specific prior written permission.
43 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
44 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
45 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
46 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
47 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
48 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
49 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
50 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
51 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
52 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
53 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
58 #include "et131x_version.h"
59 #include "et131x_defs.h"
61 #include <linux/pci.h>
62 #include <linux/init.h>
63 #include <linux/module.h>
64 #include <linux/types.h>
65 #include <linux/kernel.h>
67 #include <linux/sched.h>
68 #include <linux/ptrace.h>
69 #include <linux/slab.h>
70 #include <linux/ctype.h>
71 #include <linux/string.h>
72 #include <linux/timer.h>
73 #include <linux/interrupt.h>
75 #include <linux/delay.h>
77 #include <linux/bitops.h>
78 #include <asm/system.h>
80 #include <linux/netdevice.h>
81 #include <linux/etherdevice.h>
82 #include <linux/skbuff.h>
83 #include <linux/if_arp.h>
84 #include <linux/ioport.h>
86 #include "et1310_phy.h"
87 #include "et1310_pm.h"
88 #include "et1310_jagcore.h"
90 #include "et131x_adapter.h"
91 #include "et131x_initpci.h"
92 #include "et131x_isr.h"
94 #include "et1310_tx.h"
97 static inline void et131x_free_send_packet(struct et131x_adapter *etdev,
99 static int et131x_send_packet(struct sk_buff *skb,
100 struct et131x_adapter *etdev);
101 static int nic_send_packet(struct et131x_adapter *etdev, struct tcb *tcb);
104 * et131x_tx_dma_memory_alloc
105 * @adapter: pointer to our private adapter structure
107 * Returns 0 on success and errno on failure (as defined in errno.h).
109 * Allocates memory that will be visible both to the device and to the CPU.
110 * The OS will pass us packets, pointers to which we will insert in the Tx
111 * Descriptor queue. The device will read this queue to find the packets in
112 * memory. The device will update the "status" in memory each time it xmits a
115 int et131x_tx_dma_memory_alloc(struct et131x_adapter *adapter)
118 struct tx_ring *tx_ring = &adapter->tx_ring;
120 /* Allocate memory for the TCB's (Transmit Control Block) */
121 adapter->tx_ring.MpTcbMem = (struct tcb *)
122 kcalloc(NUM_TCB, sizeof(struct tcb), GFP_ATOMIC | GFP_DMA);
123 if (!adapter->tx_ring.MpTcbMem) {
124 dev_err(&adapter->pdev->dev, "Cannot alloc memory for TCBs\n");
128 /* Allocate enough memory for the Tx descriptor ring, and allocate
129 * some extra so that the ring can be aligned on a 4k boundary.
131 desc_size = (sizeof(struct tx_desc) * NUM_DESC_PER_RING_TX) + 4096 - 1;
132 tx_ring->tx_desc_ring =
133 (struct tx_desc *) pci_alloc_consistent(adapter->pdev, desc_size,
134 &tx_ring->tx_desc_ring_pa);
135 if (!adapter->tx_ring.tx_desc_ring) {
136 dev_err(&adapter->pdev->dev, "Cannot alloc memory for Tx Ring\n");
140 /* Save physical address
142 * NOTE: pci_alloc_consistent(), used above to alloc DMA regions,
143 * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
144 * are ever returned, make sure the high part is retrieved here before
145 * storing the adjusted address.
147 /* Allocate memory for the Tx status block */
148 tx_ring->pTxStatusVa = pci_alloc_consistent(adapter->pdev,
149 sizeof(TX_STATUS_BLOCK_t),
150 &tx_ring->pTxStatusPa);
151 if (!adapter->tx_ring.pTxStatusPa) {
152 dev_err(&adapter->pdev->dev,
153 "Cannot alloc memory for Tx status block\n");
157 /* Allocate memory for a dummy buffer */
158 tx_ring->pTxDummyBlkVa = pci_alloc_consistent(adapter->pdev,
160 &tx_ring->pTxDummyBlkPa);
161 if (!adapter->tx_ring.pTxDummyBlkPa) {
162 dev_err(&adapter->pdev->dev,
163 "Cannot alloc memory for Tx dummy buffer\n");
171 * et131x_tx_dma_memory_free - Free all memory allocated within this module
172 * @adapter: pointer to our private adapter structure
174 * Returns 0 on success and errno on failure (as defined in errno.h).
176 void et131x_tx_dma_memory_free(struct et131x_adapter *adapter)
180 if (adapter->tx_ring.tx_desc_ring) {
181 /* Free memory relating to Tx rings here */
182 desc_size = (sizeof(struct tx_desc) * NUM_DESC_PER_RING_TX)
184 pci_free_consistent(adapter->pdev,
186 adapter->tx_ring.tx_desc_ring,
187 adapter->tx_ring.tx_desc_ring_pa);
188 adapter->tx_ring.tx_desc_ring = NULL;
191 /* Free memory for the Tx status block */
192 if (adapter->tx_ring.pTxStatusVa) {
193 pci_free_consistent(adapter->pdev,
194 sizeof(TX_STATUS_BLOCK_t),
195 adapter->tx_ring.pTxStatusVa,
196 adapter->tx_ring.pTxStatusPa);
198 adapter->tx_ring.pTxStatusVa = NULL;
201 /* Free memory for the dummy buffer */
202 if (adapter->tx_ring.pTxDummyBlkVa) {
203 pci_free_consistent(adapter->pdev,
205 adapter->tx_ring.pTxDummyBlkVa,
206 adapter->tx_ring.pTxDummyBlkPa);
208 adapter->tx_ring.pTxDummyBlkVa = NULL;
211 /* Free the memory for the tcb structures */
212 kfree(adapter->tx_ring.MpTcbMem);
216 * ConfigTxDmaRegs - Set up the tx dma section of the JAGCore.
217 * @etdev: pointer to our private adapter structure
219 void ConfigTxDmaRegs(struct et131x_adapter *etdev)
221 struct _TXDMA_t __iomem *txdma = &etdev->regs->txdma;
223 /* Load the hardware with the start of the transmit descriptor ring. */
224 writel((u32) ((u64)etdev->tx_ring.tx_desc_ring_pa >> 32),
226 writel((u32) etdev->tx_ring.tx_desc_ring_pa,
229 /* Initialise the transmit DMA engine */
230 writel(NUM_DESC_PER_RING_TX - 1, &txdma->pr_num_des.value);
232 /* Load the completion writeback physical address */
233 writel((u32)((u64)etdev->tx_ring.pTxStatusPa >> 32),
234 &txdma->dma_wb_base_hi);
235 writel((u32)etdev->tx_ring.pTxStatusPa, &txdma->dma_wb_base_lo);
237 memset(etdev->tx_ring.pTxStatusVa, 0, sizeof(TX_STATUS_BLOCK_t));
239 writel(0, &txdma->service_request);
240 etdev->tx_ring.txDmaReadyToSend = 0;
244 * et131x_tx_dma_disable - Stop of Tx_DMA on the ET1310
245 * @etdev: pointer to our adapter structure
247 void et131x_tx_dma_disable(struct et131x_adapter *etdev)
249 /* Setup the tramsmit dma configuration register */
250 writel(ET_TXDMA_CSR_HALT|ET_TXDMA_SNGL_EPKT,
251 &etdev->regs->txdma.csr);
255 * et131x_tx_dma_enable - re-start of Tx_DMA on the ET1310.
256 * @etdev: pointer to our adapter structure
258 * Mainly used after a return to the D0 (full-power) state from a lower state.
260 void et131x_tx_dma_enable(struct et131x_adapter *etdev)
262 /* Setup the transmit dma configuration register for normal
265 writel(ET_TXDMA_SNGL_EPKT|(PARM_DMA_CACHE_DEF << ET_TXDMA_CACHE_SHIFT),
266 &etdev->regs->txdma.csr);
270 * et131x_init_send - Initialize send data structures
271 * @adapter: pointer to our private adapter structure
273 void et131x_init_send(struct et131x_adapter *adapter)
277 struct tx_ring *tx_ring;
279 /* Setup some convenience pointers */
280 tx_ring = &adapter->tx_ring;
281 tcb = adapter->tx_ring.MpTcbMem;
283 tx_ring->TCBReadyQueueHead = tcb;
285 /* Go through and set up each TCB */
286 for (ct = 0; ct < NUM_TCB; ct++) {
287 memset(tcb, 0, sizeof(struct tcb));
289 /* Set the link pointer in HW TCB to the next TCB in the
290 * chain. If this is the last TCB in the chain, also set the
293 if (ct < NUM_TCB - 1)
296 tx_ring->TCBReadyQueueTail = tcb;
302 /* Curr send queue should now be empty */
303 tx_ring->CurrSendHead = NULL;
304 tx_ring->CurrSendTail = NULL;
308 * et131x_send_packets - This function is called by the OS to send packets
309 * @skb: the packet(s) to send
310 * @netdev:device on which to TX the above packet(s)
312 * Return 0 in almost all cases; non-zero value in extreme hard failure only
314 int et131x_send_packets(struct sk_buff *skb, struct net_device *netdev)
317 struct et131x_adapter *etdev = NULL;
319 etdev = netdev_priv(netdev);
321 /* Send these packets
323 * NOTE: The Linux Tx entry point is only given one packet at a time
324 * to Tx, so the PacketCount and it's array used makes no sense here
327 /* TCB is not available */
328 if (etdev->tx_ring.nBusySend >= NUM_TCB) {
329 /* NOTE: If there's an error on send, no need to queue the
330 * packet under Linux; if we just send an error up to the
331 * netif layer, it will resend the skb to us.
335 /* We need to see if the link is up; if it's not, make the
336 * netif layer think we're good and drop the packet
338 if ((etdev->Flags & fMP_ADAPTER_FAIL_SEND_MASK) ||
339 !netif_carrier_ok(netdev)) {
340 dev_kfree_skb_any(skb);
343 etdev->net_stats.tx_dropped++;
345 status = et131x_send_packet(skb, etdev);
346 if (status != 0 && status != -ENOMEM) {
347 /* On any other error, make netif think we're
348 * OK and drop the packet
350 dev_kfree_skb_any(skb);
352 etdev->net_stats.tx_dropped++;
360 * et131x_send_packet - Do the work to send a packet
361 * @skb: the packet(s) to send
362 * @etdev: a pointer to the device's private adapter structure
364 * Return 0 in almost all cases; non-zero value in extreme hard failure only.
366 * Assumption: Send spinlock has been acquired
368 static int et131x_send_packet(struct sk_buff *skb,
369 struct et131x_adapter *etdev)
372 struct tcb *tcb = NULL;
376 /* All packets must have at least a MAC address and a protocol type */
377 if (skb->len < ETH_HLEN)
380 /* Get a TCB for this packet */
381 spin_lock_irqsave(&etdev->TCBReadyQLock, flags);
383 tcb = etdev->tx_ring.TCBReadyQueueHead;
386 spin_unlock_irqrestore(&etdev->TCBReadyQLock, flags);
390 etdev->tx_ring.TCBReadyQueueHead = tcb->Next;
392 if (etdev->tx_ring.TCBReadyQueueHead == NULL)
393 etdev->tx_ring.TCBReadyQueueTail = NULL;
395 spin_unlock_irqrestore(&etdev->TCBReadyQLock, flags);
397 tcb->PacketLength = skb->len;
400 if ((skb->data != NULL) && ((skb->len - skb->data_len) >= 6)) {
401 shbufva = (u16 *) skb->data;
403 if ((shbufva[0] == 0xffff) &&
404 (shbufva[1] == 0xffff) && (shbufva[2] == 0xffff)) {
405 tcb->Flags |= fMP_DEST_BROAD;
406 } else if ((shbufva[0] & 0x3) == 0x0001) {
407 tcb->Flags |= fMP_DEST_MULTI;
413 /* Call the NIC specific send handler. */
414 status = nic_send_packet(etdev, tcb);
417 spin_lock_irqsave(&etdev->TCBReadyQLock, flags);
419 if (etdev->tx_ring.TCBReadyQueueTail) {
420 etdev->tx_ring.TCBReadyQueueTail->Next = tcb;
422 /* Apparently ready Q is empty. */
423 etdev->tx_ring.TCBReadyQueueHead = tcb;
426 etdev->tx_ring.TCBReadyQueueTail = tcb;
427 spin_unlock_irqrestore(&etdev->TCBReadyQLock, flags);
430 WARN_ON(etdev->tx_ring.nBusySend > NUM_TCB);
435 * nic_send_packet - NIC specific send handler for version B silicon.
436 * @etdev: pointer to our adapter
437 * @tcb: pointer to struct tcb
439 * Returns 0 or errno.
441 static int nic_send_packet(struct et131x_adapter *etdev, struct tcb *tcb)
444 struct tx_desc desc[24]; /* 24 x 16 byte */
446 u32 thiscopy, remainder;
447 struct sk_buff *skb = tcb->Packet;
448 u32 nr_frags = skb_shinfo(skb)->nr_frags + 1;
449 struct skb_frag_struct *frags = &skb_shinfo(skb)->frags[0];
452 /* Part of the optimizations of this send routine restrict us to
453 * sending 24 fragments at a pass. In practice we should never see
454 * more than 5 fragments.
456 * NOTE: The older version of this function (below) can handle any
457 * number of fragments. If needed, we can call this function,
458 * although it is less efficient.
463 memset(desc, 0, sizeof(struct tx_desc) * (nr_frags + 1));
465 for (i = 0; i < nr_frags; i++) {
466 /* If there is something in this element, lets get a
467 * descriptor from the ring and get the necessary data
470 /* If the fragments are smaller than a standard MTU,
471 * then map them to a single descriptor in the Tx
472 * Desc ring. However, if they're larger, as is
473 * possible with support for jumbo packets, then
474 * split them each across 2 descriptors.
476 * This will work until we determine why the hardware
477 * doesn't seem to like large fragments.
479 if ((skb->len - skb->data_len) <= 1514) {
480 desc[frag].addr_hi = 0;
481 /* Low 16bits are length, high is vlan and
482 unused currently so zero */
483 desc[frag].len_vlan =
484 skb->len - skb->data_len;
486 /* NOTE: Here, the dma_addr_t returned from
487 * pci_map_single() is implicitly cast as a
488 * u32. Although dma_addr_t can be
489 * 64-bit, the address returned by
490 * pci_map_single() is always 32-bit
491 * addressable (as defined by the pci/dma
494 desc[frag++].addr_lo =
495 pci_map_single(etdev->pdev,
501 desc[frag].addr_hi = 0;
502 desc[frag].len_vlan =
503 (skb->len - skb->data_len) / 2;
505 /* NOTE: Here, the dma_addr_t returned from
506 * pci_map_single() is implicitly cast as a
507 * u32. Although dma_addr_t can be
508 * 64-bit, the address returned by
509 * pci_map_single() is always 32-bit
510 * addressable (as defined by the pci/dma
513 desc[frag++].addr_lo =
514 pci_map_single(etdev->pdev,
519 desc[frag].addr_hi = 0;
521 desc[frag].len_vlan =
522 (skb->len - skb->data_len) / 2;
524 /* NOTE: Here, the dma_addr_t returned from
525 * pci_map_single() is implicitly cast as a
526 * u32. Although dma_addr_t can be
527 * 64-bit, the address returned by
528 * pci_map_single() is always 32-bit
529 * addressable (as defined by the pci/dma
532 desc[frag++].addr_lo =
533 pci_map_single(etdev->pdev,
542 desc[frag].addr_hi = 0;
543 desc[frag].len_vlan =
546 /* NOTE: Here, the dma_addr_t returned from
547 * pci_map_page() is implicitly cast as a u32.
548 * Although dma_addr_t can be 64-bit, the address
549 * returned by pci_map_page() is always 32-bit
550 * addressable (as defined by the pci/dma subsystem)
552 desc[frag++].addr_lo =
553 pci_map_page(etdev->pdev,
555 frags[i - 1].page_offset,
564 if (etdev->linkspeed == TRUEPHY_SPEED_1000MBPS) {
565 if (++etdev->tx_ring.TxPacketsSinceLastinterrupt ==
566 PARM_TX_NUM_BUFS_DEF) {
567 /* Last element & Interrupt flag */
568 desc[frag - 1].flags = 0x5;
569 etdev->tx_ring.TxPacketsSinceLastinterrupt = 0;
570 } else { /* Last element */
571 desc[frag - 1].flags = 0x1;
574 desc[frag - 1].flags = 0x5;
576 desc[0].flags |= 2; /* First element flag */
578 tcb->WrIndexStart = etdev->tx_ring.txDmaReadyToSend;
579 tcb->PacketStaleCount = 0;
581 spin_lock_irqsave(&etdev->SendHWLock, flags);
583 thiscopy = NUM_DESC_PER_RING_TX -
584 INDEX10(etdev->tx_ring.txDmaReadyToSend);
586 if (thiscopy >= frag) {
590 remainder = frag - thiscopy;
593 memcpy(etdev->tx_ring.tx_desc_ring +
594 INDEX10(etdev->tx_ring.txDmaReadyToSend), desc,
595 sizeof(struct tx_desc) * thiscopy);
597 add_10bit(&etdev->tx_ring.txDmaReadyToSend, thiscopy);
599 if (INDEX10(etdev->tx_ring.txDmaReadyToSend)== 0 ||
600 INDEX10(etdev->tx_ring.txDmaReadyToSend) == NUM_DESC_PER_RING_TX) {
601 etdev->tx_ring.txDmaReadyToSend &= ~ET_DMA10_MASK;
602 etdev->tx_ring.txDmaReadyToSend ^= ET_DMA10_WRAP;
606 memcpy(etdev->tx_ring.tx_desc_ring,
608 sizeof(struct tx_desc) * remainder);
610 add_10bit(&etdev->tx_ring.txDmaReadyToSend, remainder);
613 if (INDEX10(etdev->tx_ring.txDmaReadyToSend) == 0) {
614 if (etdev->tx_ring.txDmaReadyToSend)
615 tcb->WrIndex = NUM_DESC_PER_RING_TX - 1;
617 tcb->WrIndex= ET_DMA10_WRAP | (NUM_DESC_PER_RING_TX - 1);
619 tcb->WrIndex = etdev->tx_ring.txDmaReadyToSend - 1;
621 spin_lock(&etdev->TCBSendQLock);
623 if (etdev->tx_ring.CurrSendTail)
624 etdev->tx_ring.CurrSendTail->Next = tcb;
626 etdev->tx_ring.CurrSendHead = tcb;
628 etdev->tx_ring.CurrSendTail = tcb;
630 WARN_ON(tcb->Next != NULL);
632 etdev->tx_ring.nBusySend++;
634 spin_unlock(&etdev->TCBSendQLock);
636 /* Write the new write pointer back to the device. */
637 writel(etdev->tx_ring.txDmaReadyToSend,
638 &etdev->regs->txdma.service_request);
640 /* For Gig only, we use Tx Interrupt coalescing. Enable the software
641 * timer to wake us up if this packet isn't followed by N more.
643 if (etdev->linkspeed == TRUEPHY_SPEED_1000MBPS) {
644 writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO,
645 &etdev->regs->global.watchdog_timer);
647 spin_unlock_irqrestore(&etdev->SendHWLock, flags);
654 * et131x_free_send_packet - Recycle a struct tcb
655 * @etdev: pointer to our adapter
656 * @tcb: pointer to struct tcb
658 * Complete the packet if necessary
659 * Assumption - Send spinlock has been acquired
661 inline void et131x_free_send_packet(struct et131x_adapter *etdev,
665 struct tx_desc *desc = NULL;
666 struct net_device_stats *stats = &etdev->net_stats;
668 if (tcb->Flags & fMP_DEST_BROAD)
669 atomic_inc(&etdev->Stats.brdcstxmt);
670 else if (tcb->Flags & fMP_DEST_MULTI)
671 atomic_inc(&etdev->Stats.multixmt);
673 atomic_inc(&etdev->Stats.unixmt);
676 stats->tx_bytes += tcb->Packet->len;
678 /* Iterate through the TX descriptors on the ring
679 * corresponding to this packet and umap the fragments
683 desc =(struct tx_desc *) (etdev->tx_ring.tx_desc_ring +
684 INDEX10(tcb->WrIndexStart));
686 pci_unmap_single(etdev->pdev,
688 desc->len_vlan, PCI_DMA_TODEVICE);
690 add_10bit(&tcb->WrIndexStart, 1);
691 if (INDEX10(tcb->WrIndexStart) >=
692 NUM_DESC_PER_RING_TX) {
693 tcb->WrIndexStart &= ~ET_DMA10_MASK;
694 tcb->WrIndexStart ^= ET_DMA10_WRAP;
696 } while (desc != (etdev->tx_ring.tx_desc_ring +
697 INDEX10(tcb->WrIndex)));
699 dev_kfree_skb_any(tcb->Packet);
702 memset(tcb, 0, sizeof(struct tcb));
704 /* Add the TCB to the Ready Q */
705 spin_lock_irqsave(&etdev->TCBReadyQLock, flags);
707 etdev->Stats.opackets++;
709 if (etdev->tx_ring.TCBReadyQueueTail)
710 etdev->tx_ring.TCBReadyQueueTail->Next = tcb;
712 /* Apparently ready Q is empty. */
713 etdev->tx_ring.TCBReadyQueueHead = tcb;
715 etdev->tx_ring.TCBReadyQueueTail = tcb;
717 spin_unlock_irqrestore(&etdev->TCBReadyQLock, flags);
718 WARN_ON(etdev->tx_ring.nBusySend < 0);
722 * et131x_free_busy_send_packets - Free and complete the stopped active sends
723 * @etdev: pointer to our adapter
725 * Assumption - Send spinlock has been acquired
727 void et131x_free_busy_send_packets(struct et131x_adapter *etdev)
733 /* Any packets being sent? Check the first TCB on the send list */
734 spin_lock_irqsave(&etdev->TCBSendQLock, flags);
736 tcb = etdev->tx_ring.CurrSendHead;
738 while ((tcb != NULL) && (freed < NUM_TCB)) {
739 struct tcb *pNext = tcb->Next;
741 etdev->tx_ring.CurrSendHead = pNext;
744 etdev->tx_ring.CurrSendTail = NULL;
746 etdev->tx_ring.nBusySend--;
748 spin_unlock_irqrestore(&etdev->TCBSendQLock, flags);
751 et131x_free_send_packet(etdev, tcb);
753 spin_lock_irqsave(&etdev->TCBSendQLock, flags);
755 tcb = etdev->tx_ring.CurrSendHead;
758 WARN_ON(freed == NUM_TCB);
760 spin_unlock_irqrestore(&etdev->TCBSendQLock, flags);
762 etdev->tx_ring.nBusySend = 0;
766 * et131x_handle_send_interrupt - Interrupt handler for sending processing
767 * @etdev: pointer to our adapter
769 * Re-claim the send resources, complete sends and get more to send from
770 * the send wait queue.
772 * Assumption - Send spinlock has been acquired
774 void et131x_handle_send_interrupt(struct et131x_adapter *etdev)
781 serviced = readl(&etdev->regs->txdma.NewServiceComplete);
782 index = INDEX10(serviced);
784 /* Has the ring wrapped? Process any descriptors that do not have
785 * the same "wrap" indicator as the current completion indicator
787 spin_lock_irqsave(&etdev->TCBSendQLock, flags);
789 tcb = etdev->tx_ring.CurrSendHead;
792 ((serviced ^ tcb->WrIndex) & ET_DMA10_WRAP) &&
793 index < INDEX10(tcb->WrIndex)) {
794 etdev->tx_ring.nBusySend--;
795 etdev->tx_ring.CurrSendHead = tcb->Next;
796 if (tcb->Next == NULL)
797 etdev->tx_ring.CurrSendTail = NULL;
799 spin_unlock_irqrestore(&etdev->TCBSendQLock, flags);
800 et131x_free_send_packet(etdev, tcb);
801 spin_lock_irqsave(&etdev->TCBSendQLock, flags);
803 /* Goto the next packet */
804 tcb = etdev->tx_ring.CurrSendHead;
807 !((serviced ^ tcb->WrIndex) & ET_DMA10_WRAP)
808 && index > (tcb->WrIndex & ET_DMA10_MASK)) {
809 etdev->tx_ring.nBusySend--;
810 etdev->tx_ring.CurrSendHead = tcb->Next;
811 if (tcb->Next == NULL)
812 etdev->tx_ring.CurrSendTail = NULL;
814 spin_unlock_irqrestore(&etdev->TCBSendQLock, flags);
815 et131x_free_send_packet(etdev, tcb);
816 spin_lock_irqsave(&etdev->TCBSendQLock, flags);
818 /* Goto the next packet */
819 tcb = etdev->tx_ring.CurrSendHead;
822 /* Wake up the queue when we hit a low-water mark */
823 if (etdev->tx_ring.nBusySend <= (NUM_TCB / 3))
824 netif_wake_queue(etdev->netdev);
826 spin_unlock_irqrestore(&etdev->TCBSendQLock, flags);