3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
5 * Copyright © 2005 Agere Systems Inc.
9 * Copyright (c) 2011 Mark Einon <mark.einon@gmail.com>
11 *------------------------------------------------------------------------------
15 * This software is provided subject to the following terms and conditions,
16 * which you should read carefully before using the software. Using this
17 * software indicates your acceptance of these terms and conditions. If you do
18 * not agree with these terms and conditions, do not use the software.
20 * Copyright © 2005 Agere Systems Inc.
21 * All rights reserved.
23 * Redistribution and use in source or binary forms, with or without
24 * modifications, are permitted provided that the following conditions are met:
26 * . Redistributions of source code must retain the above copyright notice, this
27 * list of conditions and the following Disclaimer as comments in the code as
28 * well as in the documentation and/or other materials provided with the
31 * . Redistributions in binary form must reproduce the above copyright notice,
32 * this list of conditions and the following Disclaimer in the documentation
33 * and/or other materials provided with the distribution.
35 * . Neither the name of Agere Systems Inc. nor the names of the contributors
36 * may be used to endorse or promote products derived from this software
37 * without specific prior written permission.
41 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
42 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
43 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
44 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
45 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
46 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
47 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
48 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
49 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
50 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
51 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
56 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
58 #include <linux/pci.h>
59 #include <linux/init.h>
60 #include <linux/module.h>
61 #include <linux/types.h>
62 #include <linux/kernel.h>
64 #include <linux/sched.h>
65 #include <linux/ptrace.h>
66 #include <linux/slab.h>
67 #include <linux/ctype.h>
68 #include <linux/string.h>
69 #include <linux/timer.h>
70 #include <linux/interrupt.h>
72 #include <linux/delay.h>
73 #include <linux/bitops.h>
76 #include <linux/netdevice.h>
77 #include <linux/etherdevice.h>
78 #include <linux/skbuff.h>
79 #include <linux/if_arp.h>
80 #include <linux/ioport.h>
81 #include <linux/crc32.h>
82 #include <linux/random.h>
83 #include <linux/phy.h>
87 MODULE_AUTHOR("Victor Soriano <vjsoriano@agere.com>");
88 MODULE_AUTHOR("Mark Einon <mark.einon@gmail.com>");
89 MODULE_LICENSE("Dual BSD/GPL");
90 MODULE_DESCRIPTION("10/100/1000 Base-T Ethernet Driver for the ET1310 by Agere Systems");
93 #define MAX_NUM_REGISTER_POLLS 1000
94 #define MAX_NUM_WRITE_RETRIES 2
97 #define COUNTER_WRAP_16_BIT 0x10000
98 #define COUNTER_WRAP_12_BIT 0x1000
101 #define INTERNAL_MEM_SIZE 0x400 /* 1024 of internal memory */
102 #define INTERNAL_MEM_RX_OFFSET 0x1FF /* 50% Tx, 50% Rx */
106 * For interrupts, normal running is:
107 * rxdma_xfr_done, phy_interrupt, mac_stat_interrupt,
108 * watchdog_interrupt & txdma_xfer_done
110 * In both cases, when flow control is enabled for either Tx or bi-direction,
111 * we additional enable rx_fbr0_low and rx_fbr1_low, so we know when the
112 * buffer rings are running low.
114 #define INT_MASK_DISABLE 0xffffffff
116 /* NOTE: Masking out MAC_STAT Interrupt for now...
117 * #define INT_MASK_ENABLE 0xfff6bf17
118 * #define INT_MASK_ENABLE_NO_FLOW 0xfff6bfd7
120 #define INT_MASK_ENABLE 0xfffebf17
121 #define INT_MASK_ENABLE_NO_FLOW 0xfffebfd7
123 /* General defines */
124 /* Packet and header sizes */
125 #define NIC_MIN_PACKET_SIZE 60
127 /* Multicast list size */
128 #define NIC_MAX_MCAST_LIST 128
130 /* Supported Filters */
131 #define ET131X_PACKET_TYPE_DIRECTED 0x0001
132 #define ET131X_PACKET_TYPE_MULTICAST 0x0002
133 #define ET131X_PACKET_TYPE_BROADCAST 0x0004
134 #define ET131X_PACKET_TYPE_PROMISCUOUS 0x0008
135 #define ET131X_PACKET_TYPE_ALL_MULTICAST 0x0010
138 #define ET131X_TX_TIMEOUT (1 * HZ)
139 #define NIC_SEND_HANG_THRESHOLD 0
142 #define fMP_DEST_MULTI 0x00000001
143 #define fMP_DEST_BROAD 0x00000002
145 /* MP_ADAPTER flags */
146 #define fMP_ADAPTER_RECV_LOOKASIDE 0x00000004
147 #define fMP_ADAPTER_INTERRUPT_IN_USE 0x00000008
149 /* MP_SHARED flags */
150 #define fMP_ADAPTER_LOWER_POWER 0x00200000
152 #define fMP_ADAPTER_NON_RECOVER_ERROR 0x00800000
153 #define fMP_ADAPTER_HARDWARE_ERROR 0x04000000
155 #define fMP_ADAPTER_FAIL_SEND_MASK 0x3ff00000
157 /* Some offsets in PCI config space that are actually used. */
158 #define ET1310_PCI_MAC_ADDRESS 0xA4
159 #define ET1310_PCI_EEPROM_STATUS 0xB2
160 #define ET1310_PCI_ACK_NACK 0xC0
161 #define ET1310_PCI_REPLAY 0xC2
162 #define ET1310_PCI_L0L1LATENCY 0xCF
164 /* PCI Product IDs */
165 #define ET131X_PCI_DEVICE_ID_GIG 0xED00 /* ET1310 1000 Base-T 8 */
166 #define ET131X_PCI_DEVICE_ID_FAST 0xED01 /* ET1310 100 Base-T */
168 /* Define order of magnitude converter */
169 #define NANO_IN_A_MICRO 1000
171 #define PARM_RX_NUM_BUFS_DEF 4
172 #define PARM_RX_TIME_INT_DEF 10
173 #define PARM_RX_MEM_END_DEF 0x2bc
174 #define PARM_TX_TIME_INT_DEF 40
175 #define PARM_TX_NUM_BUFS_DEF 4
176 #define PARM_DMA_CACHE_DEF 0
179 #define FBR_CHUNKS 32
180 #define MAX_DESC_PER_RING_RX 1024
182 /* number of RFDs - default and min */
183 #define RFD_LOW_WATER_MARK 40
184 #define NIC_DEFAULT_NUM_RFD 1024
187 #define NIC_MIN_NUM_RFD 64
188 #define NUM_PACKETS_HANDLED 256
190 #define ALCATEL_MULTICAST_PKT 0x01000000
191 #define ALCATEL_BROADCAST_PKT 0x02000000
193 /* typedefs for Free Buffer Descriptors */
197 u32 word2; /* Bits 10-31 reserved, 0-9 descriptor */
200 /* Packet Status Ring Descriptors
204 * top 16 bits are from the Alcatel Status Word as enumerated in
205 * PE-MCXMAC Data Sheet IPD DS54 0210-1 (also IPD-DS80 0205-2)
208 * 1: ipa IP checksum assist
209 * 2: ipp IP checksum pass
210 * 3: tcpa TCP checksum assist
211 * 4: tcpp TCP checksum pass
213 * 6: rxmac_error RXMAC Error Indicator
214 * 7: drop Drop packet
215 * 8: ft Frame Truncated
219 * 16: asw_prev_pkt_dropped e.g. IFG too small on previous
220 * 17: asw_RX_DV_event short receive event detected
221 * 18: asw_false_carrier_event bad carrier since last good packet
222 * 19: asw_code_err one or more nibbles signalled as errors
223 * 20: asw_CRC_err CRC error
224 * 21: asw_len_chk_err frame length field incorrect
225 * 22: asw_too_long frame length > 1518 bytes
226 * 23: asw_OK valid CRC + no code error
227 * 24: asw_multicast has a multicast address
228 * 25: asw_broadcast has a broadcast address
229 * 26: asw_dribble_nibble spurious bits after EOP
230 * 27: asw_control_frame is a control frame
231 * 28: asw_pause_frame is a pause frame
232 * 29: asw_unsupported_op unsupported OP code
233 * 30: asw_VLAN_tag VLAN tag detected
234 * 31: asw_long_evt Rx long event
237 * 0-15: length length in bytes
238 * 16-25: bi Buffer Index
239 * 26-27: ri Ring Index
243 struct pkt_stat_desc {
248 /* Typedefs for the RX DMA status word */
251 * rx status word 0 holds part of the status bits of the Rx DMA engine
252 * that get copied out to memory by the ET-1310. Word 0 is a 32 bit word
253 * which contains the Free Buffer ring 0 and 1 available offset.
255 * bit 0-9 FBR1 offset
256 * bit 10 Wrap flag for FBR1
257 * bit 16-25 FBR0 offset
258 * bit 26 Wrap flag for FBR0
262 * RXSTAT_WORD1_t structure holds part of the status bits of the Rx DMA engine
263 * that get copied out to memory by the ET-1310. Word 3 is a 32 bit word
264 * which contains the Packet Status Ring available offset.
267 * bit 16-27 PSRoffset
273 * struct rx_status_block is a structure representing the status of the Rx
274 * DMA engine it sits in free memory, and is pointed to by 0x101c / 0x1020
276 struct rx_status_block {
282 * Structure for look-up table holding free buffer ring pointers, addresses
286 void *virt[MAX_DESC_PER_RING_RX];
287 u32 bus_high[MAX_DESC_PER_RING_RX];
288 u32 bus_low[MAX_DESC_PER_RING_RX];
290 dma_addr_t ring_physaddr;
291 void *mem_virtaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
292 dma_addr_t mem_physaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
299 * struct rx_ring is the sructure representing the adaptor's local
300 * reference(s) to the rings
303 struct fbr_lookup *fbr[NUM_FBRS];
304 void *ps_ring_virtaddr;
305 dma_addr_t ps_ring_physaddr;
309 struct rx_status_block *rx_status_block;
310 dma_addr_t rx_status_bus;
313 struct list_head recv_list;
318 bool unfinished_receives;
320 /* lookaside lists */
321 struct kmem_cache *recv_lookaside;
326 * word 2 of the control bits in the Tx Descriptor ring for the ET-1310
328 * 0-15: length of packet
331 * 29-31: VLAN priority
333 * word 3 of the control bits in the Tx Descriptor ring for the ET-1310
335 * 0: last packet in the sequence
336 * 1: first packet in the sequence
337 * 2: interrupt the processor when this pkt sent
338 * 3: Control word - no packet data
339 * 4: Issue half-duplex backpressure : XON/XOFF
340 * 5: send pause frame
341 * 6: Tx frame has error
345 * 10: Packet is a Huge packet
346 * 11: append VLAN tag
347 * 12: IP checksum assist
348 * 13: TCP checksum assist
349 * 14: UDP checksum assist
352 /* struct tx_desc represents each descriptor on the ring */
356 u32 len_vlan; /* control words how to xmit the */
357 u32 flags; /* data (detailed above) */
361 * The status of the Tx DMA engine it sits in free memory, and is pointed to
362 * by 0x101c / 0x1020. This is a DMA10 type
365 /* TCB (Transmit Control Block: Host Side) */
367 struct tcb *next; /* Next entry in ring */
368 u32 flags; /* Our flags for the packet */
369 u32 count; /* Used to spot stuck/lost packets */
370 u32 stale; /* Used to spot stuck/lost packets */
371 struct sk_buff *skb; /* Network skb we are tied to */
372 u32 index; /* Ring indexes */
376 /* Structure representing our local reference(s) to the ring */
378 /* TCB (Transmit Control Block) memory and lists */
379 struct tcb *tcb_ring;
381 /* List of TCBs that are ready to be used */
382 struct tcb *tcb_qhead;
383 struct tcb *tcb_qtail;
385 /* list of TCBs that are currently being sent. NOTE that access to all
386 * three of these (including used) are controlled via the
387 * TCBSendQLock. This lock should be secured prior to incementing /
388 * decrementing used, or any queue manipulation on send_head /
391 struct tcb *send_head;
392 struct tcb *send_tail;
395 /* The actual descriptor ring */
396 struct tx_desc *tx_desc_ring;
397 dma_addr_t tx_desc_ring_pa;
399 /* send_idx indicates where we last wrote to in the descriptor ring. */
402 /* The location of the write-back status block */
404 dma_addr_t tx_status_pa;
406 /* Packets since the last IRQ: used for interrupt coalescing */
411 * Do not change these values: if changed, then change also in respective
412 * TXdma and Rxdma engines
414 #define NUM_DESC_PER_RING_TX 512 /* TX Do not change these values */
418 * These values are all superseded by registry entries to facilitate tuning.
419 * Once the desired performance has been achieved, the optimal registry values
420 * should be re-populated to these #defines:
422 #define TX_ERROR_PERIOD 1000
424 #define LO_MARK_PERCENT_FOR_PSR 15
425 #define LO_MARK_PERCENT_FOR_RX 15
427 /* RFD (Receive Frame Descriptor) */
429 struct list_head list_node;
431 u32 len; /* total size of receive frame */
438 #define FLOW_TXONLY 1
439 #define FLOW_RXONLY 2
442 /* Struct to define some device statistics */
446 * NOTE: atomic_t types are only guaranteed to store 24-bits; if we
447 * MUST have 32, then we'll need another way to perform atomic
450 u32 unicast_pkts_rcvd;
451 atomic_t unicast_pkts_xmtd;
452 u32 multicast_pkts_rcvd;
453 atomic_t multicast_pkts_xmtd;
454 u32 broadcast_pkts_rcvd;
455 atomic_t broadcast_pkts_xmtd;
456 u32 rcvd_pkts_dropped;
462 u32 tx_excessive_collisions;
463 u32 tx_first_collisions;
464 u32 tx_late_collisions;
474 u32 rx_code_violations;
477 u32 synchronous_iterations;
478 u32 interrupt_status;
481 /* The private adapter structure */
482 struct et131x_adapter {
483 struct net_device *netdev;
484 struct pci_dev *pdev;
485 struct mii_bus *mii_bus;
486 struct phy_device *phydev;
487 struct work_struct task;
489 /* Flags that indicate current state of the adapter */
492 /* local link state, to determine if a state change has occurred */
496 u8 rom_addr[ETH_ALEN];
504 spinlock_t tcb_send_qlock;
505 spinlock_t tcb_ready_qlock;
506 spinlock_t send_hw_lock;
509 spinlock_t rcv_pend_lock;
514 /* Packet Filter and look ahead size */
518 u32 multicast_addr_count;
519 u8 multicast_list[NIC_MAX_MCAST_LIST][ETH_ALEN];
521 /* Pointer to the device's PCI register space */
522 struct address_map __iomem *regs;
524 /* Registry parameters */
525 u8 wanted_flow; /* Flow we want for 802.3x flow control */
526 u32 registry_jumbo_packet; /* Max supported ethernet packet size */
528 /* Derived from the registry: */
529 u8 flowcontrol; /* flow control validated by the far-end */
531 /* Minimize init-time */
532 struct timer_list error_timer;
534 /* variable putting the phy into coma mode when boot up with no cable
535 * plugged in after 5 seconds
539 /* Next two used to save power information at power down. This
540 * information will be used during power up to set up parts of Power
541 * Management in JAGCore
546 /* Tx Memory Variables */
547 struct tx_ring tx_ring;
549 /* Rx Memory Variables */
550 struct rx_ring rx_ring;
553 struct ce_stats stats;
555 struct net_device_stats net_stats;
558 static int eeprom_wait_ready(struct pci_dev *pdev, u32 *status)
564 * 1. Check LBCIF Status Register for bits 6 & 3:2 all equal to 0 and
565 * bits 7,1:0 both equal to 1, at least once after reset.
566 * Subsequent operations need only to check that bits 1:0 are equal
567 * to 1 prior to starting a single byte read/write
570 for (i = 0; i < MAX_NUM_REGISTER_POLLS; i++) {
571 /* Read registers grouped in DWORD1 */
572 if (pci_read_config_dword(pdev, LBCIF_DWORD1_GROUP, ®))
575 /* I2C idle and Phy Queue Avail both true */
576 if ((reg & 0x3000) == 0x3000) {
587 * eeprom_write - Write a byte to the ET1310's EEPROM
588 * @adapter: pointer to our private adapter structure
589 * @addr: the address to write
590 * @data: the value to write
592 * Returns 1 for a successful write.
594 static int eeprom_write(struct et131x_adapter *adapter, u32 addr, u8 data)
596 struct pci_dev *pdev = adapter->pdev;
606 * For an EEPROM, an I2C single byte write is defined as a START
607 * condition followed by the device address, EEPROM address, one byte
608 * of data and a STOP condition. The STOP condition will trigger the
609 * EEPROM's internally timed write cycle to the nonvolatile memory.
610 * All inputs are disabled during this write cycle and the EEPROM will
611 * not respond to any access until the internal write is complete.
614 err = eeprom_wait_ready(pdev, NULL);
619 * 2. Write to the LBCIF Control Register: bit 7=1, bit 6=1, bit 3=0,
620 * and bits 1:0 both =0. Bit 5 should be set according to the
621 * type of EEPROM being accessed (1=two byte addressing, 0=one
624 if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
625 LBCIF_CONTROL_LBCIF_ENABLE | LBCIF_CONTROL_I2C_WRITE))
630 /* Prepare EEPROM address for Step 3 */
632 for (retries = 0; retries < MAX_NUM_WRITE_RETRIES; retries++) {
633 /* Write the address to the LBCIF Address Register */
634 if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER, addr))
637 * Write the data to the LBCIF Data Register (the I2C write
640 if (pci_write_config_byte(pdev, LBCIF_DATA_REGISTER, data))
643 * Monitor bit 1:0 of the LBCIF Status Register. When bits
644 * 1:0 are both equal to 1, the I2C write has completed and the
645 * internal write cycle of the EEPROM is about to start.
646 * (bits 1:0 = 01 is a legal state while waiting from both
647 * equal to 1, but bits 1:0 = 10 is invalid and implies that
648 * something is broken).
650 err = eeprom_wait_ready(pdev, &status);
655 * Check bit 3 of the LBCIF Status Register. If equal to 1,
656 * an error has occurred.Don't break here if we are revision
657 * 1, this is so we do a blind write for load bug.
659 if ((status & LBCIF_STATUS_GENERAL_ERROR)
660 && adapter->pdev->revision == 0)
664 * Check bit 2 of the LBCIF Status Register. If equal to 1 an
665 * ACK error has occurred on the address phase of the write.
666 * This could be due to an actual hardware failure or the
667 * EEPROM may still be in its internal write cycle from a
668 * previous write. This write operation was ignored and must be
671 if (status & LBCIF_STATUS_ACK_ERROR) {
673 * This could be due to an actual hardware failure
674 * or the EEPROM may still be in its internal write
675 * cycle from a previous write. This write operation
676 * was ignored and must be repeated later.
687 * Set bit 6 of the LBCIF Control Register = 0.
692 if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
693 LBCIF_CONTROL_LBCIF_ENABLE))
696 /* Do read until internal ACK_ERROR goes away meaning write
700 pci_write_config_dword(pdev,
701 LBCIF_ADDRESS_REGISTER,
704 pci_read_config_dword(pdev,
705 LBCIF_DATA_REGISTER, &val);
706 } while ((val & 0x00010000) == 0);
707 } while (val & 0x00040000);
709 if ((val & 0xFF00) != 0xC000 || index == 10000)
713 return writeok ? 0 : -EIO;
717 * eeprom_read - Read a byte from the ET1310's EEPROM
718 * @adapter: pointer to our private adapter structure
719 * @addr: the address from which to read
720 * @pdata: a pointer to a byte in which to store the value of the read
721 * @eeprom_id: the ID of the EEPROM
722 * @addrmode: how the EEPROM is to be accessed
724 * Returns 1 for a successful read
726 static int eeprom_read(struct et131x_adapter *adapter, u32 addr, u8 *pdata)
728 struct pci_dev *pdev = adapter->pdev;
733 * A single byte read is similar to the single byte write, with the
734 * exception of the data flow:
737 err = eeprom_wait_ready(pdev, NULL);
741 * Write to the LBCIF Control Register: bit 7=1, bit 6=0, bit 3=0,
742 * and bits 1:0 both =0. Bit 5 should be set according to the type
743 * of EEPROM being accessed (1=two byte addressing, 0=one byte
746 if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
747 LBCIF_CONTROL_LBCIF_ENABLE))
750 * Write the address to the LBCIF Address Register (I2C read will
753 if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER, addr))
756 * Monitor bit 0 of the LBCIF Status Register. When = 1, I2C read
757 * is complete. (if bit 1 =1 and bit 0 stays = 0, a hardware failure
760 err = eeprom_wait_ready(pdev, &status);
764 * Regardless of error status, read data byte from LBCIF Data
769 * Check bit 2 of the LBCIF Status Register. If = 1,
770 * then an error has occurred.
772 return (status & LBCIF_STATUS_ACK_ERROR) ? -EIO : 0;
775 static int et131x_init_eeprom(struct et131x_adapter *adapter)
777 struct pci_dev *pdev = adapter->pdev;
780 /* We first need to check the EEPROM Status code located at offset
781 * 0xB2 of config space
783 pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS,
786 /* THIS IS A WORKAROUND:
787 * I need to call this function twice to get my card in a
788 * LG M1 Express Dual running. I tried also a msleep before this
789 * function, because I thought there could be some time condidions
790 * but it didn't work. Call the whole function twice also work.
792 if (pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS, &eestatus)) {
794 "Could not read PCI config space for EEPROM Status\n");
798 /* Determine if the error(s) we care about are present. If they are
799 * present we need to fail.
801 if (eestatus & 0x4C) {
802 int write_failed = 0;
803 if (pdev->revision == 0x01) {
805 static const u8 eedata[4] = { 0xFE, 0x13, 0x10, 0xFF };
807 /* Re-write the first 4 bytes if we have an eeprom
808 * present and the revision id is 1, this fixes the
809 * corruption seen with 1310 B Silicon
811 for (i = 0; i < 3; i++)
812 if (eeprom_write(adapter, i, eedata[i]) < 0)
815 if (pdev->revision != 0x01 || write_failed) {
817 "Fatal EEPROM Status Error - 0x%04x\n", eestatus);
819 /* This error could mean that there was an error
820 * reading the eeprom or that the eeprom doesn't exist.
821 * We will treat each case the same and not try to
822 * gather additional information that normally would
823 * come from the eeprom, like MAC Address
825 adapter->has_eeprom = 0;
829 adapter->has_eeprom = 1;
831 /* Read the EEPROM for information regarding LED behavior. Refer to
832 * ET1310_phy.c, et131x_xcvr_init(), for its use.
834 eeprom_read(adapter, 0x70, &adapter->eeprom_data[0]);
835 eeprom_read(adapter, 0x71, &adapter->eeprom_data[1]);
837 if (adapter->eeprom_data[0] != 0xcd)
838 /* Disable all optional features */
839 adapter->eeprom_data[1] = 0x00;
845 * et131x_rx_dma_enable - re-start of Rx_DMA on the ET1310.
846 * @adapter: pointer to our adapter structure
848 static void et131x_rx_dma_enable(struct et131x_adapter *adapter)
850 /* Setup the receive dma configuration register for normal operation */
851 u32 csr = 0x2000; /* FBR1 enable */
853 if (adapter->rx_ring.fbr[1]->buffsize == 4096)
855 else if (adapter->rx_ring.fbr[1]->buffsize == 8192)
857 else if (adapter->rx_ring.fbr[1]->buffsize == 16384)
860 csr |= 0x0400; /* FBR0 enable */
861 if (adapter->rx_ring.fbr[0]->buffsize == 256)
863 else if (adapter->rx_ring.fbr[0]->buffsize == 512)
865 else if (adapter->rx_ring.fbr[0]->buffsize == 1024)
867 writel(csr, &adapter->regs->rxdma.csr);
869 csr = readl(&adapter->regs->rxdma.csr);
870 if (csr & 0x00020000) {
872 csr = readl(&adapter->regs->rxdma.csr);
873 if (csr & 0x00020000) {
874 dev_err(&adapter->pdev->dev,
875 "RX Dma failed to exit halt state. CSR 0x%08x\n",
882 * et131x_rx_dma_disable - Stop of Rx_DMA on the ET1310
883 * @adapter: pointer to our adapter structure
885 static void et131x_rx_dma_disable(struct et131x_adapter *adapter)
888 /* Setup the receive dma configuration register */
889 writel(0x00002001, &adapter->regs->rxdma.csr);
890 csr = readl(&adapter->regs->rxdma.csr);
891 if ((csr & 0x00020000) == 0) { /* Check halt status (bit 17) */
893 csr = readl(&adapter->regs->rxdma.csr);
894 if ((csr & 0x00020000) == 0)
895 dev_err(&adapter->pdev->dev,
896 "RX Dma failed to enter halt state. CSR 0x%08x\n",
902 * et131x_tx_dma_enable - re-start of Tx_DMA on the ET1310.
903 * @adapter: pointer to our adapter structure
905 * Mainly used after a return to the D0 (full-power) state from a lower state.
907 static void et131x_tx_dma_enable(struct et131x_adapter *adapter)
909 /* Setup the transmit dma configuration register for normal
912 writel(ET_TXDMA_SNGL_EPKT|(PARM_DMA_CACHE_DEF << ET_TXDMA_CACHE_SHIFT),
913 &adapter->regs->txdma.csr);
916 static inline void add_10bit(u32 *v, int n)
918 *v = INDEX10(*v + n) | (*v & ET_DMA10_WRAP);
921 static inline void add_12bit(u32 *v, int n)
923 *v = INDEX12(*v + n) | (*v & ET_DMA12_WRAP);
927 * et1310_config_mac_regs1 - Initialize the first part of MAC regs
928 * @adapter: pointer to our adapter structure
930 static void et1310_config_mac_regs1(struct et131x_adapter *adapter)
932 struct mac_regs __iomem *macregs = &adapter->regs->mac;
937 /* First we need to reset everything. Write to MAC configuration
938 * register 1 to perform reset.
940 writel(0xC00F0000, ¯egs->cfg1);
942 /* Next lets configure the MAC Inter-packet gap register */
943 ipg = 0x38005860; /* IPG1 0x38 IPG2 0x58 B2B 0x60 */
944 ipg |= 0x50 << 8; /* ifg enforce 0x50 */
945 writel(ipg, ¯egs->ipg);
947 /* Next lets configure the MAC Half Duplex register */
948 /* BEB trunc 0xA, Ex Defer, Rexmit 0xF Coll 0x37 */
949 writel(0x00A1F037, ¯egs->hfdp);
951 /* Next lets configure the MAC Interface Control register */
952 writel(0, ¯egs->if_ctrl);
954 /* Let's move on to setting up the mii management configuration */
955 writel(0x07, ¯egs->mii_mgmt_cfg); /* Clock reset 0x7 */
957 /* Next lets configure the MAC Station Address register. These
958 * values are read from the EEPROM during initialization and stored
959 * in the adapter structure. We write what is stored in the adapter
960 * structure to the MAC Station Address registers high and low. This
961 * station address is used for generating and checking pause control
964 station2 = (adapter->addr[1] << ET_MAC_STATION_ADDR2_OC2_SHIFT) |
965 (adapter->addr[0] << ET_MAC_STATION_ADDR2_OC1_SHIFT);
966 station1 = (adapter->addr[5] << ET_MAC_STATION_ADDR1_OC6_SHIFT) |
967 (adapter->addr[4] << ET_MAC_STATION_ADDR1_OC5_SHIFT) |
968 (adapter->addr[3] << ET_MAC_STATION_ADDR1_OC4_SHIFT) |
970 writel(station1, ¯egs->station_addr_1);
971 writel(station2, ¯egs->station_addr_2);
973 /* Max ethernet packet in bytes that will be passed by the mac without
974 * being truncated. Allow the MAC to pass 4 more than our max packet
975 * size. This is 4 for the Ethernet CRC.
977 * Packets larger than (registry_jumbo_packet) that do not contain a
978 * VLAN ID will be dropped by the Rx function.
980 writel(adapter->registry_jumbo_packet + 4, ¯egs->max_fm_len);
982 /* clear out MAC config reset */
983 writel(0, ¯egs->cfg1);
987 * et1310_config_mac_regs2 - Initialize the second part of MAC regs
988 * @adapter: pointer to our adapter structure
990 static void et1310_config_mac_regs2(struct et131x_adapter *adapter)
993 struct mac_regs __iomem *mac = &adapter->regs->mac;
994 struct phy_device *phydev = adapter->phydev;
1000 ctl = readl(&adapter->regs->txmac.ctl);
1001 cfg1 = readl(&mac->cfg1);
1002 cfg2 = readl(&mac->cfg2);
1003 ifctrl = readl(&mac->if_ctrl);
1005 /* Set up the if mode bits */
1007 if (phydev && phydev->speed == SPEED_1000) {
1010 ifctrl &= ~(1 << 24);
1013 ifctrl |= (1 << 24);
1016 /* We need to enable Rx/Tx */
1017 cfg1 |= CFG1_RX_ENABLE | CFG1_TX_ENABLE | CFG1_TX_FLOW;
1018 /* Initialize loop back to off */
1019 cfg1 &= ~(CFG1_LOOPBACK | CFG1_RX_FLOW);
1020 if (adapter->flowcontrol == FLOW_RXONLY ||
1021 adapter->flowcontrol == FLOW_BOTH)
1022 cfg1 |= CFG1_RX_FLOW;
1023 writel(cfg1, &mac->cfg1);
1025 /* Now we need to initialize the MAC Configuration 2 register */
1026 /* preamble 7, check length, huge frame off, pad crc, crc enable
1031 /* Turn on duplex if needed */
1032 if (phydev && phydev->duplex == DUPLEX_FULL)
1035 ifctrl &= ~(1 << 26);
1036 if (phydev && phydev->duplex == DUPLEX_HALF)
1037 ifctrl |= (1<<26); /* Enable ghd */
1039 writel(ifctrl, &mac->if_ctrl);
1040 writel(cfg2, &mac->cfg2);
1045 cfg1 = readl(&mac->cfg1);
1046 } while ((cfg1 & CFG1_WAIT) != CFG1_WAIT && delay < 100);
1049 dev_warn(&adapter->pdev->dev,
1050 "Syncd bits did not respond correctly cfg1 word 0x%08x\n",
1055 ctl |= 0x09; /* TX mac enable, FC disable */
1056 writel(ctl, &adapter->regs->txmac.ctl);
1058 /* Ready to start the RXDMA/TXDMA engine */
1059 if (adapter->flags & fMP_ADAPTER_LOWER_POWER) {
1060 et131x_rx_dma_enable(adapter);
1061 et131x_tx_dma_enable(adapter);
1066 * et1310_in_phy_coma - check if the device is in phy coma
1067 * @adapter: pointer to our adapter structure
1069 * Returns 0 if the device is not in phy coma, 1 if it is in phy coma
1071 static int et1310_in_phy_coma(struct et131x_adapter *adapter)
1075 pmcsr = readl(&adapter->regs->global.pm_csr);
1077 return ET_PM_PHY_SW_COMA & pmcsr ? 1 : 0;
1080 static void et1310_setup_device_for_multicast(struct et131x_adapter *adapter)
1082 struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac;
1089 /* If ET131X_PACKET_TYPE_MULTICAST is specified, then we provision
1090 * the multi-cast LIST. If it is NOT specified, (and "ALL" is not
1091 * specified) then we should pass NO multi-cast addresses to the
1094 if (adapter->packet_filter & ET131X_PACKET_TYPE_MULTICAST) {
1097 /* Loop through our multicast array and set up the device */
1098 for (i = 0; i < adapter->multicast_addr_count; i++) {
1101 result = ether_crc(6, adapter->multicast_list[i]);
1103 result = (result & 0x3F800000) >> 23;
1106 hash1 |= (1 << result);
1107 } else if ((31 < result) && (result < 64)) {
1109 hash2 |= (1 << result);
1110 } else if ((63 < result) && (result < 96)) {
1112 hash3 |= (1 << result);
1115 hash4 |= (1 << result);
1120 /* Write out the new hash to the device */
1121 pm_csr = readl(&adapter->regs->global.pm_csr);
1122 if (!et1310_in_phy_coma(adapter)) {
1123 writel(hash1, &rxmac->multi_hash1);
1124 writel(hash2, &rxmac->multi_hash2);
1125 writel(hash3, &rxmac->multi_hash3);
1126 writel(hash4, &rxmac->multi_hash4);
1130 static void et1310_setup_device_for_unicast(struct et131x_adapter *adapter)
1132 struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac;
1138 /* Set up unicast packet filter reg 3 to be the first two octets of
1139 * the MAC address for both address
1141 * Set up unicast packet filter reg 2 to be the octets 2 - 5 of the
1142 * MAC address for second address
1144 * Set up unicast packet filter reg 3 to be the octets 2 - 5 of the
1145 * MAC address for first address
1147 uni_pf3 = (adapter->addr[0] << ET_UNI_PF_ADDR2_1_SHIFT) |
1148 (adapter->addr[1] << ET_UNI_PF_ADDR2_2_SHIFT) |
1149 (adapter->addr[0] << ET_UNI_PF_ADDR1_1_SHIFT) |
1152 uni_pf2 = (adapter->addr[2] << ET_UNI_PF_ADDR2_3_SHIFT) |
1153 (adapter->addr[3] << ET_UNI_PF_ADDR2_4_SHIFT) |
1154 (adapter->addr[4] << ET_UNI_PF_ADDR2_5_SHIFT) |
1157 uni_pf1 = (adapter->addr[2] << ET_UNI_PF_ADDR1_3_SHIFT) |
1158 (adapter->addr[3] << ET_UNI_PF_ADDR1_4_SHIFT) |
1159 (adapter->addr[4] << ET_UNI_PF_ADDR1_5_SHIFT) |
1162 pm_csr = readl(&adapter->regs->global.pm_csr);
1163 if (!et1310_in_phy_coma(adapter)) {
1164 writel(uni_pf1, &rxmac->uni_pf_addr1);
1165 writel(uni_pf2, &rxmac->uni_pf_addr2);
1166 writel(uni_pf3, &rxmac->uni_pf_addr3);
1170 static void et1310_config_rxmac_regs(struct et131x_adapter *adapter)
1172 struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac;
1173 struct phy_device *phydev = adapter->phydev;
1178 /* Disable the MAC while it is being configured (also disable WOL) */
1179 writel(0x8, &rxmac->ctrl);
1181 /* Initialize WOL to disabled. */
1182 writel(0, &rxmac->crc0);
1183 writel(0, &rxmac->crc12);
1184 writel(0, &rxmac->crc34);
1186 /* We need to set the WOL mask0 - mask4 next. We initialize it to
1187 * its default Values of 0x00000000 because there are not WOL masks
1190 writel(0, &rxmac->mask0_word0);
1191 writel(0, &rxmac->mask0_word1);
1192 writel(0, &rxmac->mask0_word2);
1193 writel(0, &rxmac->mask0_word3);
1195 writel(0, &rxmac->mask1_word0);
1196 writel(0, &rxmac->mask1_word1);
1197 writel(0, &rxmac->mask1_word2);
1198 writel(0, &rxmac->mask1_word3);
1200 writel(0, &rxmac->mask2_word0);
1201 writel(0, &rxmac->mask2_word1);
1202 writel(0, &rxmac->mask2_word2);
1203 writel(0, &rxmac->mask2_word3);
1205 writel(0, &rxmac->mask3_word0);
1206 writel(0, &rxmac->mask3_word1);
1207 writel(0, &rxmac->mask3_word2);
1208 writel(0, &rxmac->mask3_word3);
1210 writel(0, &rxmac->mask4_word0);
1211 writel(0, &rxmac->mask4_word1);
1212 writel(0, &rxmac->mask4_word2);
1213 writel(0, &rxmac->mask4_word3);
1215 /* Lets setup the WOL Source Address */
1216 sa_lo = (adapter->addr[2] << ET_WOL_LO_SA3_SHIFT) |
1217 (adapter->addr[3] << ET_WOL_LO_SA4_SHIFT) |
1218 (adapter->addr[4] << ET_WOL_LO_SA5_SHIFT) |
1220 writel(sa_lo, &rxmac->sa_lo);
1222 sa_hi = (u32) (adapter->addr[0] << ET_WOL_HI_SA1_SHIFT) |
1224 writel(sa_hi, &rxmac->sa_hi);
1226 /* Disable all Packet Filtering */
1227 writel(0, &rxmac->pf_ctrl);
1229 /* Let's initialize the Unicast Packet filtering address */
1230 if (adapter->packet_filter & ET131X_PACKET_TYPE_DIRECTED) {
1231 et1310_setup_device_for_unicast(adapter);
1232 pf_ctrl |= 4; /* Unicast filter */
1234 writel(0, &rxmac->uni_pf_addr1);
1235 writel(0, &rxmac->uni_pf_addr2);
1236 writel(0, &rxmac->uni_pf_addr3);
1239 /* Let's initialize the Multicast hash */
1240 if (!(adapter->packet_filter & ET131X_PACKET_TYPE_ALL_MULTICAST)) {
1241 pf_ctrl |= 2; /* Multicast filter */
1242 et1310_setup_device_for_multicast(adapter);
1245 /* Runt packet filtering. Didn't work in version A silicon. */
1246 pf_ctrl |= (NIC_MIN_PACKET_SIZE + 4) << 16;
1247 pf_ctrl |= 8; /* Fragment filter */
1249 if (adapter->registry_jumbo_packet > 8192)
1250 /* In order to transmit jumbo packets greater than 8k, the
1251 * FIFO between RxMAC and RxDMA needs to be reduced in size
1252 * to (16k - Jumbo packet size). In order to implement this,
1253 * we must use "cut through" mode in the RxMAC, which chops
1254 * packets down into segments which are (max_size * 16). In
1255 * this case we selected 256 bytes, since this is the size of
1256 * the PCI-Express TLP's that the 1310 uses.
1258 * seg_en on, fc_en off, size 0x10
1260 writel(0x41, &rxmac->mcif_ctrl_max_seg);
1262 writel(0, &rxmac->mcif_ctrl_max_seg);
1264 /* Initialize the MCIF water marks */
1265 writel(0, &rxmac->mcif_water_mark);
1267 /* Initialize the MIF control */
1268 writel(0, &rxmac->mif_ctrl);
1270 /* Initialize the Space Available Register */
1271 writel(0, &rxmac->space_avail);
1273 /* Initialize the the mif_ctrl register
1274 * bit 3: Receive code error. One or more nibbles were signaled as
1275 * errors during the reception of the packet. Clear this
1276 * bit in Gigabit, set it in 100Mbit. This was derived
1277 * experimentally at UNH.
1278 * bit 4: Receive CRC error. The packet's CRC did not match the
1279 * internally generated CRC.
1280 * bit 5: Receive length check error. Indicates that frame length
1281 * field value in the packet does not match the actual data
1282 * byte length and is not a type field.
1283 * bit 16: Receive frame truncated.
1284 * bit 17: Drop packet enable
1286 if (phydev && phydev->speed == SPEED_100)
1287 writel(0x30038, &rxmac->mif_ctrl);
1289 writel(0x30030, &rxmac->mif_ctrl);
1291 /* Finally we initialize RxMac to be enabled & WOL disabled. Packet
1292 * filter is always enabled since it is where the runt packets are
1293 * supposed to be dropped. For version A silicon, runt packet
1294 * dropping doesn't work, so it is disabled in the pf_ctrl register,
1295 * but we still leave the packet filter on.
1297 writel(pf_ctrl, &rxmac->pf_ctrl);
1298 writel(0x9, &rxmac->ctrl);
1301 static void et1310_config_txmac_regs(struct et131x_adapter *adapter)
1303 struct txmac_regs __iomem *txmac = &adapter->regs->txmac;
1305 /* We need to update the Control Frame Parameters
1306 * cfpt - control frame pause timer set to 64 (0x40)
1307 * cfep - control frame extended pause timer set to 0x0
1309 if (adapter->flowcontrol == FLOW_NONE)
1310 writel(0, &txmac->cf_param);
1312 writel(0x40, &txmac->cf_param);
1315 static void et1310_config_macstat_regs(struct et131x_adapter *adapter)
1317 struct macstat_regs __iomem *macstat =
1318 &adapter->regs->macstat;
1320 /* Next we need to initialize all the macstat registers to zero on
1323 writel(0, &macstat->txrx_0_64_byte_frames);
1324 writel(0, &macstat->txrx_65_127_byte_frames);
1325 writel(0, &macstat->txrx_128_255_byte_frames);
1326 writel(0, &macstat->txrx_256_511_byte_frames);
1327 writel(0, &macstat->txrx_512_1023_byte_frames);
1328 writel(0, &macstat->txrx_1024_1518_byte_frames);
1329 writel(0, &macstat->txrx_1519_1522_gvln_frames);
1331 writel(0, &macstat->rx_bytes);
1332 writel(0, &macstat->rx_packets);
1333 writel(0, &macstat->rx_fcs_errs);
1334 writel(0, &macstat->rx_multicast_packets);
1335 writel(0, &macstat->rx_broadcast_packets);
1336 writel(0, &macstat->rx_control_frames);
1337 writel(0, &macstat->rx_pause_frames);
1338 writel(0, &macstat->rx_unknown_opcodes);
1339 writel(0, &macstat->rx_align_errs);
1340 writel(0, &macstat->rx_frame_len_errs);
1341 writel(0, &macstat->rx_code_errs);
1342 writel(0, &macstat->rx_carrier_sense_errs);
1343 writel(0, &macstat->rx_undersize_packets);
1344 writel(0, &macstat->rx_oversize_packets);
1345 writel(0, &macstat->rx_fragment_packets);
1346 writel(0, &macstat->rx_jabbers);
1347 writel(0, &macstat->rx_drops);
1349 writel(0, &macstat->tx_bytes);
1350 writel(0, &macstat->tx_packets);
1351 writel(0, &macstat->tx_multicast_packets);
1352 writel(0, &macstat->tx_broadcast_packets);
1353 writel(0, &macstat->tx_pause_frames);
1354 writel(0, &macstat->tx_deferred);
1355 writel(0, &macstat->tx_excessive_deferred);
1356 writel(0, &macstat->tx_single_collisions);
1357 writel(0, &macstat->tx_multiple_collisions);
1358 writel(0, &macstat->tx_late_collisions);
1359 writel(0, &macstat->tx_excessive_collisions);
1360 writel(0, &macstat->tx_total_collisions);
1361 writel(0, &macstat->tx_pause_honored_frames);
1362 writel(0, &macstat->tx_drops);
1363 writel(0, &macstat->tx_jabbers);
1364 writel(0, &macstat->tx_fcs_errs);
1365 writel(0, &macstat->tx_control_frames);
1366 writel(0, &macstat->tx_oversize_frames);
1367 writel(0, &macstat->tx_undersize_frames);
1368 writel(0, &macstat->tx_fragments);
1369 writel(0, &macstat->carry_reg1);
1370 writel(0, &macstat->carry_reg2);
1372 /* Unmask any counters that we want to track the overflow of.
1373 * Initially this will be all counters. It may become clear later
1374 * that we do not need to track all counters.
1376 writel(0xFFFFBE32, &macstat->carry_reg1_mask);
1377 writel(0xFFFE7E8B, &macstat->carry_reg2_mask);
1381 * et131x_phy_mii_read - Read from the PHY through the MII Interface on the MAC
1382 * @adapter: pointer to our private adapter structure
1383 * @addr: the address of the transceiver
1384 * @reg: the register to read
1385 * @value: pointer to a 16-bit value in which the value will be stored
1387 * Returns 0 on success, errno on failure (as defined in errno.h)
1389 static int et131x_phy_mii_read(struct et131x_adapter *adapter, u8 addr,
1392 struct mac_regs __iomem *mac = &adapter->regs->mac;
1399 /* Save a local copy of the registers we are dealing with so we can
1402 mii_addr = readl(&mac->mii_mgmt_addr);
1403 mii_cmd = readl(&mac->mii_mgmt_cmd);
1405 /* Stop the current operation */
1406 writel(0, &mac->mii_mgmt_cmd);
1408 /* Set up the register we need to read from on the correct PHY */
1409 writel(MII_ADDR(addr, reg), &mac->mii_mgmt_addr);
1411 writel(0x1, &mac->mii_mgmt_cmd);
1416 mii_indicator = readl(&mac->mii_mgmt_indicator);
1417 } while ((mii_indicator & MGMT_WAIT) && delay < 50);
1419 /* If we hit the max delay, we could not read the register */
1421 dev_warn(&adapter->pdev->dev,
1422 "reg 0x%08x could not be read\n", reg);
1423 dev_warn(&adapter->pdev->dev, "status is 0x%08x\n",
1429 /* If we hit here we were able to read the register and we need to
1430 * return the value to the caller */
1431 *value = readl(&mac->mii_mgmt_stat) & 0xFFFF;
1433 /* Stop the read operation */
1434 writel(0, &mac->mii_mgmt_cmd);
1436 /* set the registers we touched back to the state at which we entered
1439 writel(mii_addr, &mac->mii_mgmt_addr);
1440 writel(mii_cmd, &mac->mii_mgmt_cmd);
1445 static int et131x_mii_read(struct et131x_adapter *adapter, u8 reg, u16 *value)
1447 struct phy_device *phydev = adapter->phydev;
1452 return et131x_phy_mii_read(adapter, phydev->addr, reg, value);
1456 * et131x_mii_write - Write to a PHY register through the MII interface of the MAC
1457 * @adapter: pointer to our private adapter structure
1458 * @reg: the register to read
1459 * @value: 16-bit value to write
1461 * FIXME: one caller in netdev still
1463 * Return 0 on success, errno on failure (as defined in errno.h)
1465 static int et131x_mii_write(struct et131x_adapter *adapter, u8 reg, u16 value)
1467 struct mac_regs __iomem *mac = &adapter->regs->mac;
1468 struct phy_device *phydev = adapter->phydev;
1479 addr = phydev->addr;
1481 /* Save a local copy of the registers we are dealing with so we can
1484 mii_addr = readl(&mac->mii_mgmt_addr);
1485 mii_cmd = readl(&mac->mii_mgmt_cmd);
1487 /* Stop the current operation */
1488 writel(0, &mac->mii_mgmt_cmd);
1490 /* Set up the register we need to write to on the correct PHY */
1491 writel(MII_ADDR(addr, reg), &mac->mii_mgmt_addr);
1493 /* Add the value to write to the registers to the mac */
1494 writel(value, &mac->mii_mgmt_ctrl);
1499 mii_indicator = readl(&mac->mii_mgmt_indicator);
1500 } while ((mii_indicator & MGMT_BUSY) && delay < 100);
1502 /* If we hit the max delay, we could not write the register */
1506 dev_warn(&adapter->pdev->dev,
1507 "reg 0x%08x could not be written", reg);
1508 dev_warn(&adapter->pdev->dev, "status is 0x%08x\n",
1510 dev_warn(&adapter->pdev->dev, "command is 0x%08x\n",
1511 readl(&mac->mii_mgmt_cmd));
1513 et131x_mii_read(adapter, reg, &tmp);
1517 /* Stop the write operation */
1518 writel(0, &mac->mii_mgmt_cmd);
1521 * set the registers we touched back to the state at which we entered
1524 writel(mii_addr, &mac->mii_mgmt_addr);
1525 writel(mii_cmd, &mac->mii_mgmt_cmd);
1530 /* Still used from _mac for BIT_READ */
1531 static void et1310_phy_access_mii_bit(struct et131x_adapter *adapter,
1532 u16 action, u16 regnum, u16 bitnum,
1536 u16 mask = 0x0001 << bitnum;
1538 /* Read the requested register */
1539 et131x_mii_read(adapter, regnum, ®);
1542 case TRUEPHY_BIT_READ:
1543 *value = (reg & mask) >> bitnum;
1546 case TRUEPHY_BIT_SET:
1547 et131x_mii_write(adapter, regnum, reg | mask);
1550 case TRUEPHY_BIT_CLEAR:
1551 et131x_mii_write(adapter, regnum, reg & ~mask);
1559 static void et1310_config_flow_control(struct et131x_adapter *adapter)
1561 struct phy_device *phydev = adapter->phydev;
1563 if (phydev->duplex == DUPLEX_HALF) {
1564 adapter->flowcontrol = FLOW_NONE;
1566 char remote_pause, remote_async_pause;
1568 et1310_phy_access_mii_bit(adapter,
1569 TRUEPHY_BIT_READ, 5, 10, &remote_pause);
1570 et1310_phy_access_mii_bit(adapter,
1571 TRUEPHY_BIT_READ, 5, 11,
1572 &remote_async_pause);
1574 if ((remote_pause == TRUEPHY_BIT_SET) &&
1575 (remote_async_pause == TRUEPHY_BIT_SET)) {
1576 adapter->flowcontrol = adapter->wanted_flow;
1577 } else if ((remote_pause == TRUEPHY_BIT_SET) &&
1578 (remote_async_pause == TRUEPHY_BIT_CLEAR)) {
1579 if (adapter->wanted_flow == FLOW_BOTH)
1580 adapter->flowcontrol = FLOW_BOTH;
1582 adapter->flowcontrol = FLOW_NONE;
1583 } else if ((remote_pause == TRUEPHY_BIT_CLEAR) &&
1584 (remote_async_pause == TRUEPHY_BIT_CLEAR)) {
1585 adapter->flowcontrol = FLOW_NONE;
1586 } else {/* if (remote_pause == TRUEPHY_CLEAR_BIT &&
1587 remote_async_pause == TRUEPHY_SET_BIT) */
1588 if (adapter->wanted_flow == FLOW_BOTH)
1589 adapter->flowcontrol = FLOW_RXONLY;
1591 adapter->flowcontrol = FLOW_NONE;
1597 * et1310_update_macstat_host_counters - Update the local copy of the statistics
1598 * @adapter: pointer to the adapter structure
1600 static void et1310_update_macstat_host_counters(struct et131x_adapter *adapter)
1602 struct ce_stats *stats = &adapter->stats;
1603 struct macstat_regs __iomem *macstat =
1604 &adapter->regs->macstat;
1606 stats->tx_collisions += readl(&macstat->tx_total_collisions);
1607 stats->tx_first_collisions += readl(&macstat->tx_single_collisions);
1608 stats->tx_deferred += readl(&macstat->tx_deferred);
1609 stats->tx_excessive_collisions +=
1610 readl(&macstat->tx_multiple_collisions);
1611 stats->tx_late_collisions += readl(&macstat->tx_late_collisions);
1612 stats->tx_underflows += readl(&macstat->tx_undersize_frames);
1613 stats->tx_max_pkt_errs += readl(&macstat->tx_oversize_frames);
1615 stats->rx_align_errs += readl(&macstat->rx_align_errs);
1616 stats->rx_crc_errs += readl(&macstat->rx_code_errs);
1617 stats->rcvd_pkts_dropped += readl(&macstat->rx_drops);
1618 stats->rx_overflows += readl(&macstat->rx_oversize_packets);
1619 stats->rx_code_violations += readl(&macstat->rx_fcs_errs);
1620 stats->rx_length_errs += readl(&macstat->rx_frame_len_errs);
1621 stats->rx_other_errs += readl(&macstat->rx_fragment_packets);
1625 * et1310_handle_macstat_interrupt
1626 * @adapter: pointer to the adapter structure
1628 * One of the MACSTAT counters has wrapped. Update the local copy of
1629 * the statistics held in the adapter structure, checking the "wrap"
1630 * bit for each counter.
1632 static void et1310_handle_macstat_interrupt(struct et131x_adapter *adapter)
1637 /* Read the interrupt bits from the register(s). These are Clear On
1640 carry_reg1 = readl(&adapter->regs->macstat.carry_reg1);
1641 carry_reg2 = readl(&adapter->regs->macstat.carry_reg2);
1643 writel(carry_reg1, &adapter->regs->macstat.carry_reg1);
1644 writel(carry_reg2, &adapter->regs->macstat.carry_reg2);
1646 /* We need to do update the host copy of all the MAC_STAT counters.
1647 * For each counter, check it's overflow bit. If the overflow bit is
1648 * set, then increment the host version of the count by one complete
1649 * revolution of the counter. This routine is called when the counter
1650 * block indicates that one of the counters has wrapped.
1652 if (carry_reg1 & (1 << 14))
1653 adapter->stats.rx_code_violations += COUNTER_WRAP_16_BIT;
1654 if (carry_reg1 & (1 << 8))
1655 adapter->stats.rx_align_errs += COUNTER_WRAP_12_BIT;
1656 if (carry_reg1 & (1 << 7))
1657 adapter->stats.rx_length_errs += COUNTER_WRAP_16_BIT;
1658 if (carry_reg1 & (1 << 2))
1659 adapter->stats.rx_other_errs += COUNTER_WRAP_16_BIT;
1660 if (carry_reg1 & (1 << 6))
1661 adapter->stats.rx_crc_errs += COUNTER_WRAP_16_BIT;
1662 if (carry_reg1 & (1 << 3))
1663 adapter->stats.rx_overflows += COUNTER_WRAP_16_BIT;
1664 if (carry_reg1 & (1 << 0))
1665 adapter->stats.rcvd_pkts_dropped += COUNTER_WRAP_16_BIT;
1666 if (carry_reg2 & (1 << 16))
1667 adapter->stats.tx_max_pkt_errs += COUNTER_WRAP_12_BIT;
1668 if (carry_reg2 & (1 << 15))
1669 adapter->stats.tx_underflows += COUNTER_WRAP_12_BIT;
1670 if (carry_reg2 & (1 << 6))
1671 adapter->stats.tx_first_collisions += COUNTER_WRAP_12_BIT;
1672 if (carry_reg2 & (1 << 8))
1673 adapter->stats.tx_deferred += COUNTER_WRAP_12_BIT;
1674 if (carry_reg2 & (1 << 5))
1675 adapter->stats.tx_excessive_collisions += COUNTER_WRAP_12_BIT;
1676 if (carry_reg2 & (1 << 4))
1677 adapter->stats.tx_late_collisions += COUNTER_WRAP_12_BIT;
1678 if (carry_reg2 & (1 << 2))
1679 adapter->stats.tx_collisions += COUNTER_WRAP_12_BIT;
1682 static int et131x_mdio_read(struct mii_bus *bus, int phy_addr, int reg)
1684 struct net_device *netdev = bus->priv;
1685 struct et131x_adapter *adapter = netdev_priv(netdev);
1689 ret = et131x_phy_mii_read(adapter, phy_addr, reg, &value);
1697 static int et131x_mdio_write(struct mii_bus *bus, int phy_addr,
1700 struct net_device *netdev = bus->priv;
1701 struct et131x_adapter *adapter = netdev_priv(netdev);
1703 return et131x_mii_write(adapter, reg, value);
1706 static int et131x_mdio_reset(struct mii_bus *bus)
1708 struct net_device *netdev = bus->priv;
1709 struct et131x_adapter *adapter = netdev_priv(netdev);
1711 et131x_mii_write(adapter, MII_BMCR, BMCR_RESET);
1717 * et1310_phy_power_down - PHY power control
1718 * @adapter: device to control
1719 * @down: true for off/false for back on
1721 * one hundred, ten, one thousand megs
1722 * How would you like to have your LAN accessed
1723 * Can't you see that this code processed
1724 * Phy power, phy power..
1726 static void et1310_phy_power_down(struct et131x_adapter *adapter, bool down)
1730 et131x_mii_read(adapter, MII_BMCR, &data);
1731 data &= ~BMCR_PDOWN;
1734 et131x_mii_write(adapter, MII_BMCR, data);
1738 * et131x_xcvr_init - Init the phy if we are setting it into force mode
1739 * @adapter: pointer to our private adapter structure
1742 static void et131x_xcvr_init(struct et131x_adapter *adapter)
1746 /* Set the LED behavior such that LED 1 indicates speed (off =
1747 * 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates
1748 * link and activity (on for link, blink off for activity).
1750 * NOTE: Some customizations have been added here for specific
1751 * vendors; The LED behavior is now determined by vendor data in the
1752 * EEPROM. However, the above description is the default.
1754 if ((adapter->eeprom_data[1] & 0x4) == 0) {
1755 et131x_mii_read(adapter, PHY_LED_2, &lcr2);
1757 lcr2 &= (ET_LED2_LED_100TX | ET_LED2_LED_1000T);
1758 lcr2 |= (LED_VAL_LINKON_ACTIVE << LED_LINK_SHIFT);
1760 if ((adapter->eeprom_data[1] & 0x8) == 0)
1761 lcr2 |= (LED_VAL_1000BT_100BTX << LED_TXRX_SHIFT);
1763 lcr2 |= (LED_VAL_LINKON << LED_TXRX_SHIFT);
1765 et131x_mii_write(adapter, PHY_LED_2, lcr2);
1770 * et131x_configure_global_regs - configure JAGCore global regs
1771 * @adapter: pointer to our adapter structure
1773 * Used to configure the global registers on the JAGCore
1775 static void et131x_configure_global_regs(struct et131x_adapter *adapter)
1777 struct global_regs __iomem *regs = &adapter->regs->global;
1779 writel(0, ®s->rxq_start_addr);
1780 writel(INTERNAL_MEM_SIZE - 1, ®s->txq_end_addr);
1782 if (adapter->registry_jumbo_packet < 2048) {
1783 /* Tx / RxDMA and Tx/Rx MAC interfaces have a 1k word
1784 * block of RAM that the driver can split between Tx
1785 * and Rx as it desires. Our default is to split it
1788 writel(PARM_RX_MEM_END_DEF, ®s->rxq_end_addr);
1789 writel(PARM_RX_MEM_END_DEF + 1, ®s->txq_start_addr);
1790 } else if (adapter->registry_jumbo_packet < 8192) {
1791 /* For jumbo packets > 2k but < 8k, split 50-50. */
1792 writel(INTERNAL_MEM_RX_OFFSET, ®s->rxq_end_addr);
1793 writel(INTERNAL_MEM_RX_OFFSET + 1, ®s->txq_start_addr);
1795 /* 9216 is the only packet size greater than 8k that
1796 * is available. The Tx buffer has to be big enough
1797 * for one whole packet on the Tx side. We'll make
1798 * the Tx 9408, and give the rest to Rx
1800 writel(0x01b3, ®s->rxq_end_addr);
1801 writel(0x01b4, ®s->txq_start_addr);
1804 /* Initialize the loopback register. Disable all loopbacks. */
1805 writel(0, ®s->loopback);
1808 writel(0, ®s->msi_config);
1810 /* By default, disable the watchdog timer. It will be enabled when
1811 * a packet is queued.
1813 writel(0, ®s->watchdog_timer);
1817 * et131x_config_rx_dma_regs - Start of Rx_DMA init sequence
1818 * @adapter: pointer to our adapter structure
1820 static void et131x_config_rx_dma_regs(struct et131x_adapter *adapter)
1822 struct rxdma_regs __iomem *rx_dma = &adapter->regs->rxdma;
1823 struct rx_ring *rx_local = &adapter->rx_ring;
1824 struct fbr_desc *fbr_entry;
1827 unsigned long flags;
1830 /* Halt RXDMA to perform the reconfigure. */
1831 et131x_rx_dma_disable(adapter);
1833 /* Load the completion writeback physical address */
1834 writel(upper_32_bits(rx_local->rx_status_bus), &rx_dma->dma_wb_base_hi);
1835 writel(lower_32_bits(rx_local->rx_status_bus), &rx_dma->dma_wb_base_lo);
1837 memset(rx_local->rx_status_block, 0, sizeof(struct rx_status_block));
1839 /* Set the address and parameters of the packet status ring into the
1842 writel(upper_32_bits(rx_local->ps_ring_physaddr), &rx_dma->psr_base_hi);
1843 writel(lower_32_bits(rx_local->ps_ring_physaddr), &rx_dma->psr_base_lo);
1844 writel(rx_local->psr_num_entries - 1, &rx_dma->psr_num_des);
1845 writel(0, &rx_dma->psr_full_offset);
1847 psr_num_des = readl(&rx_dma->psr_num_des) & 0xFFF;
1848 writel((psr_num_des * LO_MARK_PERCENT_FOR_PSR) / 100,
1849 &rx_dma->psr_min_des);
1851 spin_lock_irqsave(&adapter->rcv_lock, flags);
1853 /* These local variables track the PSR in the adapter structure */
1854 rx_local->local_psr_full = 0;
1856 for (id = 0; id < NUM_FBRS; id++) {
1864 num_des = &rx_dma->fbr0_num_des;
1865 full_offset = &rx_dma->fbr0_full_offset;
1866 min_des = &rx_dma->fbr0_min_des;
1867 base_hi = &rx_dma->fbr0_base_hi;
1868 base_lo = &rx_dma->fbr0_base_lo;
1870 num_des = &rx_dma->fbr1_num_des;
1871 full_offset = &rx_dma->fbr1_full_offset;
1872 min_des = &rx_dma->fbr1_min_des;
1873 base_hi = &rx_dma->fbr1_base_hi;
1874 base_lo = &rx_dma->fbr1_base_lo;
1877 /* Now's the best time to initialize FBR contents */
1878 fbr_entry = (struct fbr_desc *) rx_local->fbr[id]->ring_virtaddr;
1879 for (entry = 0; entry < rx_local->fbr[id]->num_entries; entry++) {
1880 fbr_entry->addr_hi = rx_local->fbr[id]->bus_high[entry];
1881 fbr_entry->addr_lo = rx_local->fbr[id]->bus_low[entry];
1882 fbr_entry->word2 = entry;
1886 /* Set the address and parameters of Free buffer ring 1 and 0
1887 * into the 1310's registers
1889 writel(upper_32_bits(rx_local->fbr[id]->ring_physaddr), base_hi);
1890 writel(lower_32_bits(rx_local->fbr[id]->ring_physaddr), base_lo);
1891 writel(rx_local->fbr[id]->num_entries - 1, num_des);
1892 writel(ET_DMA10_WRAP, full_offset);
1894 /* This variable tracks the free buffer ring 1 full position,
1895 * so it has to match the above.
1897 rx_local->fbr[id]->local_full = ET_DMA10_WRAP;
1898 writel(((rx_local->fbr[id]->num_entries *
1899 LO_MARK_PERCENT_FOR_RX) / 100) - 1,
1903 /* Program the number of packets we will receive before generating an
1905 * For version B silicon, this value gets updated once autoneg is
1908 writel(PARM_RX_NUM_BUFS_DEF, &rx_dma->num_pkt_done);
1910 /* The "time_done" is not working correctly to coalesce interrupts
1911 * after a given time period, but rather is giving us an interrupt
1912 * regardless of whether we have received packets.
1913 * This value gets updated once autoneg is complete.
1915 writel(PARM_RX_TIME_INT_DEF, &rx_dma->max_pkt_time);
1917 spin_unlock_irqrestore(&adapter->rcv_lock, flags);
1921 * et131x_config_tx_dma_regs - Set up the tx dma section of the JAGCore.
1922 * @adapter: pointer to our private adapter structure
1924 * Configure the transmit engine with the ring buffers we have created
1925 * and prepare it for use.
1927 static void et131x_config_tx_dma_regs(struct et131x_adapter *adapter)
1929 struct txdma_regs __iomem *txdma = &adapter->regs->txdma;
1931 /* Load the hardware with the start of the transmit descriptor ring. */
1932 writel(upper_32_bits(adapter->tx_ring.tx_desc_ring_pa),
1933 &txdma->pr_base_hi);
1934 writel(lower_32_bits(adapter->tx_ring.tx_desc_ring_pa),
1935 &txdma->pr_base_lo);
1937 /* Initialise the transmit DMA engine */
1938 writel(NUM_DESC_PER_RING_TX - 1, &txdma->pr_num_des);
1940 /* Load the completion writeback physical address */
1941 writel(upper_32_bits(adapter->tx_ring.tx_status_pa),
1942 &txdma->dma_wb_base_hi);
1943 writel(lower_32_bits(adapter->tx_ring.tx_status_pa),
1944 &txdma->dma_wb_base_lo);
1946 *adapter->tx_ring.tx_status = 0;
1948 writel(0, &txdma->service_request);
1949 adapter->tx_ring.send_idx = 0;
1953 * et131x_adapter_setup - Set the adapter up as per cassini+ documentation
1954 * @adapter: pointer to our private adapter structure
1956 * Returns 0 on success, errno on failure (as defined in errno.h)
1958 static void et131x_adapter_setup(struct et131x_adapter *adapter)
1960 /* Configure the JAGCore */
1961 et131x_configure_global_regs(adapter);
1963 et1310_config_mac_regs1(adapter);
1965 /* Configure the MMC registers */
1966 /* All we need to do is initialize the Memory Control Register */
1967 writel(ET_MMC_ENABLE, &adapter->regs->mmc.mmc_ctrl);
1969 et1310_config_rxmac_regs(adapter);
1970 et1310_config_txmac_regs(adapter);
1972 et131x_config_rx_dma_regs(adapter);
1973 et131x_config_tx_dma_regs(adapter);
1975 et1310_config_macstat_regs(adapter);
1977 et1310_phy_power_down(adapter, 0);
1978 et131x_xcvr_init(adapter);
1982 * et131x_soft_reset - Issue a soft reset to the hardware, complete for ET1310
1983 * @adapter: pointer to our private adapter structure
1985 static void et131x_soft_reset(struct et131x_adapter *adapter)
1987 /* Disable MAC Core */
1988 writel(0xc00f0000, &adapter->regs->mac.cfg1);
1990 /* Set everything to a reset value */
1991 writel(0x7F, &adapter->regs->global.sw_reset);
1992 writel(0x000f0000, &adapter->regs->mac.cfg1);
1993 writel(0x00000000, &adapter->regs->mac.cfg1);
1997 * et131x_enable_interrupts - enable interrupt
1998 * @adapter: et131x device
2000 * Enable the appropriate interrupts on the ET131x according to our
2003 static void et131x_enable_interrupts(struct et131x_adapter *adapter)
2007 /* Enable all global interrupts */
2008 if (adapter->flowcontrol == FLOW_TXONLY ||
2009 adapter->flowcontrol == FLOW_BOTH)
2010 mask = INT_MASK_ENABLE;
2012 mask = INT_MASK_ENABLE_NO_FLOW;
2014 writel(mask, &adapter->regs->global.int_mask);
2018 * et131x_disable_interrupts - interrupt disable
2019 * @adapter: et131x device
2021 * Block all interrupts from the et131x device at the device itself
2023 static void et131x_disable_interrupts(struct et131x_adapter *adapter)
2025 /* Disable all global interrupts */
2026 writel(INT_MASK_DISABLE, &adapter->regs->global.int_mask);
2030 * et131x_tx_dma_disable - Stop of Tx_DMA on the ET1310
2031 * @adapter: pointer to our adapter structure
2033 static void et131x_tx_dma_disable(struct et131x_adapter *adapter)
2035 /* Setup the tramsmit dma configuration register */
2036 writel(ET_TXDMA_CSR_HALT|ET_TXDMA_SNGL_EPKT,
2037 &adapter->regs->txdma.csr);
2041 * et131x_enable_txrx - Enable tx/rx queues
2042 * @netdev: device to be enabled
2044 static void et131x_enable_txrx(struct net_device *netdev)
2046 struct et131x_adapter *adapter = netdev_priv(netdev);
2048 /* Enable the Tx and Rx DMA engines (if not already enabled) */
2049 et131x_rx_dma_enable(adapter);
2050 et131x_tx_dma_enable(adapter);
2052 /* Enable device interrupts */
2053 if (adapter->flags & fMP_ADAPTER_INTERRUPT_IN_USE)
2054 et131x_enable_interrupts(adapter);
2056 /* We're ready to move some data, so start the queue */
2057 netif_start_queue(netdev);
2061 * et131x_disable_txrx - Disable tx/rx queues
2062 * @netdev: device to be disabled
2064 static void et131x_disable_txrx(struct net_device *netdev)
2066 struct et131x_adapter *adapter = netdev_priv(netdev);
2068 /* First thing is to stop the queue */
2069 netif_stop_queue(netdev);
2071 /* Stop the Tx and Rx DMA engines */
2072 et131x_rx_dma_disable(adapter);
2073 et131x_tx_dma_disable(adapter);
2075 /* Disable device interrupts */
2076 et131x_disable_interrupts(adapter);
2080 * et131x_init_send - Initialize send data structures
2081 * @adapter: pointer to our private adapter structure
2083 static void et131x_init_send(struct et131x_adapter *adapter)
2087 struct tx_ring *tx_ring;
2089 /* Setup some convenience pointers */
2090 tx_ring = &adapter->tx_ring;
2091 tcb = adapter->tx_ring.tcb_ring;
2093 tx_ring->tcb_qhead = tcb;
2095 memset(tcb, 0, sizeof(struct tcb) * NUM_TCB);
2097 /* Go through and set up each TCB */
2098 for (ct = 0; ct++ < NUM_TCB; tcb++)
2099 /* Set the link pointer in HW TCB to the next TCB in the
2102 tcb->next = tcb + 1;
2104 /* Set the tail pointer */
2106 tx_ring->tcb_qtail = tcb;
2108 /* Curr send queue should now be empty */
2109 tx_ring->send_head = NULL;
2110 tx_ring->send_tail = NULL;
2114 * et1310_enable_phy_coma - called when network cable is unplugged
2115 * @adapter: pointer to our adapter structure
2117 * driver receive an phy status change interrupt while in D0 and check that
2118 * phy_status is down.
2120 * -- gate off JAGCore;
2121 * -- set gigE PHY in Coma mode
2122 * -- wake on phy_interrupt; Perform software reset JAGCore,
2123 * re-initialize jagcore and gigE PHY
2125 * Add D0-ASPM-PhyLinkDown Support:
2126 * -- while in D0, when there is a phy_interrupt indicating phy link
2127 * down status, call the MPSetPhyComa routine to enter this active
2128 * state power saving mode
2129 * -- while in D0-ASPM-PhyLinkDown mode, when there is a phy_interrupt
2130 * indicating linkup status, call the MPDisablePhyComa routine to
2131 * restore JAGCore and gigE PHY
2133 static void et1310_enable_phy_coma(struct et131x_adapter *adapter)
2135 unsigned long flags;
2138 pmcsr = readl(&adapter->regs->global.pm_csr);
2140 /* Save the GbE PHY speed and duplex modes. Need to restore this
2141 * when cable is plugged back in
2144 * TODO - when PM is re-enabled, check if we need to
2145 * perform a similar task as this -
2146 * adapter->pdown_speed = adapter->ai_force_speed;
2147 * adapter->pdown_duplex = adapter->ai_force_duplex;
2150 /* Stop sending packets. */
2151 spin_lock_irqsave(&adapter->send_hw_lock, flags);
2152 adapter->flags |= fMP_ADAPTER_LOWER_POWER;
2153 spin_unlock_irqrestore(&adapter->send_hw_lock, flags);
2155 /* Wait for outstanding Receive packets */
2157 et131x_disable_txrx(adapter->netdev);
2159 /* Gate off JAGCore 3 clock domains */
2160 pmcsr &= ~ET_PMCSR_INIT;
2161 writel(pmcsr, &adapter->regs->global.pm_csr);
2163 /* Program gigE PHY in to Coma mode */
2164 pmcsr |= ET_PM_PHY_SW_COMA;
2165 writel(pmcsr, &adapter->regs->global.pm_csr);
2169 * et1310_disable_phy_coma - Disable the Phy Coma Mode
2170 * @adapter: pointer to our adapter structure
2172 static void et1310_disable_phy_coma(struct et131x_adapter *adapter)
2176 pmcsr = readl(&adapter->regs->global.pm_csr);
2178 /* Disable phy_sw_coma register and re-enable JAGCore clocks */
2179 pmcsr |= ET_PMCSR_INIT;
2180 pmcsr &= ~ET_PM_PHY_SW_COMA;
2181 writel(pmcsr, &adapter->regs->global.pm_csr);
2183 /* Restore the GbE PHY speed and duplex modes;
2184 * Reset JAGCore; re-configure and initialize JAGCore and gigE PHY
2186 /* TODO - when PM is re-enabled, check if we need to
2187 * perform a similar task as this -
2188 * adapter->ai_force_speed = adapter->pdown_speed;
2189 * adapter->ai_force_duplex = adapter->pdown_duplex;
2192 /* Re-initialize the send structures */
2193 et131x_init_send(adapter);
2195 /* Bring the device back to the state it was during init prior to
2196 * autonegotiation being complete. This way, when we get the auto-neg
2197 * complete interrupt, we can complete init by calling ConfigMacREGS2.
2199 et131x_soft_reset(adapter);
2201 /* setup et1310 as per the documentation ?? */
2202 et131x_adapter_setup(adapter);
2204 /* Allow Tx to restart */
2205 adapter->flags &= ~fMP_ADAPTER_LOWER_POWER;
2207 et131x_enable_txrx(adapter->netdev);
2210 static inline u32 bump_free_buff_ring(u32 *free_buff_ring, u32 limit)
2212 u32 tmp_free_buff_ring = *free_buff_ring;
2213 tmp_free_buff_ring++;
2214 /* This works for all cases where limit < 1024. The 1023 case
2215 works because 1023++ is 1024 which means the if condition is not
2216 taken but the carry of the bit into the wrap bit toggles the wrap
2218 if ((tmp_free_buff_ring & ET_DMA10_MASK) > limit) {
2219 tmp_free_buff_ring &= ~ET_DMA10_MASK;
2220 tmp_free_buff_ring ^= ET_DMA10_WRAP;
2222 /* For the 1023 case */
2223 tmp_free_buff_ring &= (ET_DMA10_MASK|ET_DMA10_WRAP);
2224 *free_buff_ring = tmp_free_buff_ring;
2225 return tmp_free_buff_ring;
2229 * et131x_rx_dma_memory_alloc
2230 * @adapter: pointer to our private adapter structure
2232 * Returns 0 on success and errno on failure (as defined in errno.h)
2234 * Allocates Free buffer ring 1 for sure, free buffer ring 0 if required,
2235 * and the Packet Status Ring.
2237 static int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
2242 u32 pktstat_ringsize;
2244 struct rx_ring *rx_ring;
2246 /* Setup some convenience pointers */
2247 rx_ring = &adapter->rx_ring;
2249 /* Alloc memory for the lookup table */
2250 rx_ring->fbr[0] = kmalloc(sizeof(struct fbr_lookup), GFP_KERNEL);
2251 rx_ring->fbr[1] = kmalloc(sizeof(struct fbr_lookup), GFP_KERNEL);
2253 /* The first thing we will do is configure the sizes of the buffer
2254 * rings. These will change based on jumbo packet support. Larger
2255 * jumbo packets increases the size of each entry in FBR0, and the
2256 * number of entries in FBR0, while at the same time decreasing the
2257 * number of entries in FBR1.
2259 * FBR1 holds "large" frames, FBR0 holds "small" frames. If FBR1
2260 * entries are huge in order to accommodate a "jumbo" frame, then it
2261 * will have less entries. Conversely, FBR1 will now be relied upon
2262 * to carry more "normal" frames, thus it's entry size also increases
2263 * and the number of entries goes up too (since it now carries
2264 * "small" + "regular" packets.
2266 * In this scheme, we try to maintain 512 entries between the two
2267 * rings. Also, FBR1 remains a constant size - when it's size doubles
2268 * the number of entries halves. FBR0 increases in size, however.
2271 if (adapter->registry_jumbo_packet < 2048) {
2272 rx_ring->fbr[0]->buffsize = 256;
2273 rx_ring->fbr[0]->num_entries = 512;
2274 rx_ring->fbr[1]->buffsize = 2048;
2275 rx_ring->fbr[1]->num_entries = 512;
2276 } else if (adapter->registry_jumbo_packet < 4096) {
2277 rx_ring->fbr[0]->buffsize = 512;
2278 rx_ring->fbr[0]->num_entries = 1024;
2279 rx_ring->fbr[1]->buffsize = 4096;
2280 rx_ring->fbr[1]->num_entries = 512;
2282 rx_ring->fbr[0]->buffsize = 1024;
2283 rx_ring->fbr[0]->num_entries = 768;
2284 rx_ring->fbr[1]->buffsize = 16384;
2285 rx_ring->fbr[1]->num_entries = 128;
2288 adapter->rx_ring.psr_num_entries =
2289 adapter->rx_ring.fbr[0]->num_entries +
2290 adapter->rx_ring.fbr[1]->num_entries;
2292 for (id = 0; id < NUM_FBRS; id++) {
2293 /* Allocate an area of memory for Free Buffer Ring */
2294 bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr[id]->num_entries);
2295 rx_ring->fbr[id]->ring_virtaddr =
2296 dma_alloc_coherent(&adapter->pdev->dev,
2298 &rx_ring->fbr[id]->ring_physaddr,
2300 if (!rx_ring->fbr[id]->ring_virtaddr) {
2301 dev_err(&adapter->pdev->dev,
2302 "Cannot alloc memory for Free Buffer Ring %d\n", id);
2307 for (id = 0; id < NUM_FBRS; id++) {
2308 fbr_chunksize = (FBR_CHUNKS * rx_ring->fbr[id]->buffsize);
2310 for (i = 0; i < (rx_ring->fbr[id]->num_entries / FBR_CHUNKS); i++) {
2311 dma_addr_t fbr_tmp_physaddr;
2313 rx_ring->fbr[id]->mem_virtaddrs[i] = dma_alloc_coherent(
2314 &adapter->pdev->dev, fbr_chunksize,
2315 &rx_ring->fbr[id]->mem_physaddrs[i],
2318 if (!rx_ring->fbr[id]->mem_virtaddrs[i]) {
2319 dev_err(&adapter->pdev->dev,
2320 "Could not alloc memory\n");
2324 /* See NOTE in "Save Physical Address" comment above */
2325 fbr_tmp_physaddr = rx_ring->fbr[id]->mem_physaddrs[i];
2327 for (j = 0; j < FBR_CHUNKS; j++) {
2328 u32 index = (i * FBR_CHUNKS) + j;
2330 /* Save the Virtual address of this index for
2331 * quick access later
2333 rx_ring->fbr[id]->virt[index] =
2334 (u8 *) rx_ring->fbr[id]->mem_virtaddrs[i] +
2335 (j * rx_ring->fbr[id]->buffsize);
2337 /* now store the physical address in the
2338 * descriptor so the device can access it
2340 rx_ring->fbr[id]->bus_high[index] =
2341 upper_32_bits(fbr_tmp_physaddr);
2342 rx_ring->fbr[id]->bus_low[index] =
2343 lower_32_bits(fbr_tmp_physaddr);
2345 fbr_tmp_physaddr += rx_ring->fbr[id]->buffsize;
2350 /* Allocate an area of memory for FIFO of Packet Status ring entries */
2352 sizeof(struct pkt_stat_desc) * adapter->rx_ring.psr_num_entries;
2354 rx_ring->ps_ring_virtaddr = dma_alloc_coherent(&adapter->pdev->dev,
2356 &rx_ring->ps_ring_physaddr,
2359 if (!rx_ring->ps_ring_virtaddr) {
2360 dev_err(&adapter->pdev->dev,
2361 "Cannot alloc memory for Packet Status Ring\n");
2364 pr_info("Packet Status Ring %llx\n",
2365 (unsigned long long) rx_ring->ps_ring_physaddr);
2368 * NOTE : dma_alloc_coherent(), used above to alloc DMA regions,
2369 * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
2370 * are ever returned, make sure the high part is retrieved here before
2371 * storing the adjusted address.
2374 /* Allocate an area of memory for writeback of status information */
2375 rx_ring->rx_status_block = dma_alloc_coherent(&adapter->pdev->dev,
2376 sizeof(struct rx_status_block),
2377 &rx_ring->rx_status_bus,
2379 if (!rx_ring->rx_status_block) {
2380 dev_err(&adapter->pdev->dev,
2381 "Cannot alloc memory for Status Block\n");
2384 rx_ring->num_rfd = NIC_DEFAULT_NUM_RFD;
2385 pr_info("PRS %llx\n", (unsigned long long)rx_ring->rx_status_bus);
2388 * kmem_cache_create initializes a lookaside list. After successful
2389 * creation, nonpaged fixed-size blocks can be allocated from and
2390 * freed to the lookaside list.
2391 * RFDs will be allocated from this pool.
2393 rx_ring->recv_lookaside = kmem_cache_create(adapter->netdev->name,
2400 adapter->flags |= fMP_ADAPTER_RECV_LOOKASIDE;
2402 /* The RFDs are going to be put on lists later on, so initialize the
2405 INIT_LIST_HEAD(&rx_ring->recv_list);
2410 * et131x_rx_dma_memory_free - Free all memory allocated within this module.
2411 * @adapter: pointer to our private adapter structure
2413 static void et131x_rx_dma_memory_free(struct et131x_adapter *adapter)
2418 u32 pktstat_ringsize;
2420 struct rx_ring *rx_ring;
2422 /* Setup some convenience pointers */
2423 rx_ring = &adapter->rx_ring;
2425 /* Free RFDs and associated packet descriptors */
2426 WARN_ON(rx_ring->num_ready_recv != rx_ring->num_rfd);
2428 while (!list_empty(&rx_ring->recv_list)) {
2429 rfd = (struct rfd *) list_entry(rx_ring->recv_list.next,
2430 struct rfd, list_node);
2432 list_del(&rfd->list_node);
2434 kmem_cache_free(adapter->rx_ring.recv_lookaside, rfd);
2437 /* Free Free Buffer Rings */
2438 for (id = 0; id < NUM_FBRS; id++) {
2439 if (!rx_ring->fbr[id]->ring_virtaddr)
2442 /* First the packet memory */
2444 index < (rx_ring->fbr[id]->num_entries / FBR_CHUNKS);
2446 if (rx_ring->fbr[id]->mem_virtaddrs[index]) {
2447 bufsize = rx_ring->fbr[id]->buffsize * FBR_CHUNKS;
2449 dma_free_coherent(&adapter->pdev->dev,
2451 rx_ring->fbr[id]->mem_virtaddrs[index],
2452 rx_ring->fbr[id]->mem_physaddrs[index]);
2454 rx_ring->fbr[id]->mem_virtaddrs[index] = NULL;
2459 sizeof(struct fbr_desc) * rx_ring->fbr[id]->num_entries;
2461 dma_free_coherent(&adapter->pdev->dev, bufsize,
2462 rx_ring->fbr[id]->ring_virtaddr,
2463 rx_ring->fbr[id]->ring_physaddr);
2465 rx_ring->fbr[id]->ring_virtaddr = NULL;
2468 /* Free Packet Status Ring */
2469 if (rx_ring->ps_ring_virtaddr) {
2470 pktstat_ringsize = sizeof(struct pkt_stat_desc) *
2471 adapter->rx_ring.psr_num_entries;
2473 dma_free_coherent(&adapter->pdev->dev, pktstat_ringsize,
2474 rx_ring->ps_ring_virtaddr,
2475 rx_ring->ps_ring_physaddr);
2477 rx_ring->ps_ring_virtaddr = NULL;
2480 /* Free area of memory for the writeback of status information */
2481 if (rx_ring->rx_status_block) {
2482 dma_free_coherent(&adapter->pdev->dev,
2483 sizeof(struct rx_status_block),
2484 rx_ring->rx_status_block, rx_ring->rx_status_bus);
2485 rx_ring->rx_status_block = NULL;
2488 /* Destroy the lookaside (RFD) pool */
2489 if (adapter->flags & fMP_ADAPTER_RECV_LOOKASIDE) {
2490 kmem_cache_destroy(rx_ring->recv_lookaside);
2491 adapter->flags &= ~fMP_ADAPTER_RECV_LOOKASIDE;
2494 /* Free the FBR Lookup Table */
2495 kfree(rx_ring->fbr[0]);
2496 kfree(rx_ring->fbr[1]);
2498 /* Reset Counters */
2499 rx_ring->num_ready_recv = 0;
2503 * et131x_init_recv - Initialize receive data structures.
2504 * @adapter: pointer to our private adapter structure
2506 * Returns 0 on success and errno on failure (as defined in errno.h)
2508 static int et131x_init_recv(struct et131x_adapter *adapter)
2510 int status = -ENOMEM;
2511 struct rfd *rfd = NULL;
2514 struct rx_ring *rx_ring;
2516 /* Setup some convenience pointers */
2517 rx_ring = &adapter->rx_ring;
2519 /* Setup each RFD */
2520 for (rfdct = 0; rfdct < rx_ring->num_rfd; rfdct++) {
2521 rfd = kmem_cache_alloc(rx_ring->recv_lookaside,
2522 GFP_ATOMIC | GFP_DMA);
2525 dev_err(&adapter->pdev->dev,
2526 "Couldn't alloc RFD out of kmem_cache\n");
2533 /* Add this RFD to the recv_list */
2534 list_add_tail(&rfd->list_node, &rx_ring->recv_list);
2536 /* Increment both the available RFD's, and the total RFD's. */
2537 rx_ring->num_ready_recv++;
2541 if (numrfd > NIC_MIN_NUM_RFD)
2544 rx_ring->num_rfd = numrfd;
2547 kmem_cache_free(rx_ring->recv_lookaside, rfd);
2548 dev_err(&adapter->pdev->dev,
2549 "Allocation problems in et131x_init_recv\n");
2555 * et131x_set_rx_dma_timer - Set the heartbeat timer according to line rate.
2556 * @adapter: pointer to our adapter structure
2558 static void et131x_set_rx_dma_timer(struct et131x_adapter *adapter)
2560 struct phy_device *phydev = adapter->phydev;
2565 /* For version B silicon, we do not use the RxDMA timer for 10 and 100
2566 * Mbits/s line rates. We do not enable and RxDMA interrupt coalescing.
2568 if ((phydev->speed == SPEED_100) || (phydev->speed == SPEED_10)) {
2569 writel(0, &adapter->regs->rxdma.max_pkt_time);
2570 writel(1, &adapter->regs->rxdma.num_pkt_done);
2575 * NICReturnRFD - Recycle a RFD and put it back onto the receive list
2576 * @adapter: pointer to our adapter
2577 * @rfd: pointer to the RFD
2579 static void nic_return_rfd(struct et131x_adapter *adapter, struct rfd *rfd)
2581 struct rx_ring *rx_local = &adapter->rx_ring;
2582 struct rxdma_regs __iomem *rx_dma = &adapter->regs->rxdma;
2583 u16 buff_index = rfd->bufferindex;
2584 u8 ring_index = rfd->ringindex;
2585 unsigned long flags;
2587 /* We don't use any of the OOB data besides status. Otherwise, we
2588 * need to clean up OOB data
2590 if (buff_index < rx_local->fbr[ring_index]->num_entries) {
2592 struct fbr_desc *next;
2594 spin_lock_irqsave(&adapter->fbr_lock, flags);
2596 if (ring_index == 0)
2597 offset = &rx_dma->fbr0_full_offset;
2599 offset = &rx_dma->fbr1_full_offset;
2601 next = (struct fbr_desc *) (rx_local->fbr[ring_index]->ring_virtaddr) +
2602 INDEX10(rx_local->fbr[ring_index]->local_full);
2604 /* Handle the Free Buffer Ring advancement here. Write
2605 * the PA / Buffer Index for the returned buffer into
2606 * the oldest (next to be freed)FBR entry
2608 next->addr_hi = rx_local->fbr[ring_index]->bus_high[buff_index];
2609 next->addr_lo = rx_local->fbr[ring_index]->bus_low[buff_index];
2610 next->word2 = buff_index;
2612 writel(bump_free_buff_ring(&rx_local->fbr[ring_index]->local_full,
2613 rx_local->fbr[ring_index]->num_entries - 1),
2616 spin_unlock_irqrestore(&adapter->fbr_lock, flags);
2618 dev_err(&adapter->pdev->dev,
2619 "%s illegal Buffer Index returned\n", __func__);
2622 /* The processing on this RFD is done, so put it back on the tail of
2625 spin_lock_irqsave(&adapter->rcv_lock, flags);
2626 list_add_tail(&rfd->list_node, &rx_local->recv_list);
2627 rx_local->num_ready_recv++;
2628 spin_unlock_irqrestore(&adapter->rcv_lock, flags);
2630 WARN_ON(rx_local->num_ready_recv > rx_local->num_rfd);
2634 * nic_rx_pkts - Checks the hardware for available packets
2635 * @adapter: pointer to our adapter
2637 * Returns rfd, a pointer to our MPRFD.
2639 * Checks the hardware for available packets, using completion ring
2640 * If packets are available, it gets an RFD from the recv_list, attaches
2641 * the packet to it, puts the RFD in the RecvPendList, and also returns
2642 * the pointer to the RFD.
2644 static struct rfd *nic_rx_pkts(struct et131x_adapter *adapter)
2646 struct rx_ring *rx_local = &adapter->rx_ring;
2647 struct rx_status_block *status;
2648 struct pkt_stat_desc *psr;
2652 unsigned long flags;
2653 struct list_head *element;
2659 struct sk_buff *skb;
2661 /* RX Status block is written by the DMA engine prior to every
2662 * interrupt. It contains the next to be used entry in the Packet
2663 * Status Ring, and also the two Free Buffer rings.
2665 status = rx_local->rx_status_block;
2666 word1 = status->word1 >> 16; /* Get the useful bits */
2668 /* Check the PSR and wrap bits do not match */
2669 if ((word1 & 0x1FFF) == (rx_local->local_psr_full & 0x1FFF))
2670 return NULL; /* Looks like this ring is not updated yet */
2672 /* The packet status ring indicates that data is available. */
2673 psr = (struct pkt_stat_desc *) (rx_local->ps_ring_virtaddr) +
2674 (rx_local->local_psr_full & 0xFFF);
2676 /* Grab any information that is required once the PSR is advanced,
2677 * since we can no longer rely on the memory being accurate
2679 len = psr->word1 & 0xFFFF;
2680 ring_index = (psr->word1 >> 26) & 0x03;
2681 buff_index = (psr->word1 >> 16) & 0x3FF;
2684 /* Indicate that we have used this PSR entry. */
2686 add_12bit(&rx_local->local_psr_full, 1);
2688 (rx_local->local_psr_full & 0xFFF) > rx_local->psr_num_entries - 1) {
2689 /* Clear psr full and toggle the wrap bit */
2690 rx_local->local_psr_full &= ~0xFFF;
2691 rx_local->local_psr_full ^= 0x1000;
2694 writel(rx_local->local_psr_full, &adapter->regs->rxdma.psr_full_offset);
2696 if (ring_index > 1 ||
2697 buff_index > rx_local->fbr[ring_index]->num_entries - 1) {
2698 /* Illegal buffer or ring index cannot be used by S/W*/
2699 dev_err(&adapter->pdev->dev,
2700 "NICRxPkts PSR Entry %d indicates length of %d and/or bad bi(%d)\n",
2701 rx_local->local_psr_full & 0xFFF, len, buff_index);
2705 /* Get and fill the RFD. */
2706 spin_lock_irqsave(&adapter->rcv_lock, flags);
2708 element = rx_local->recv_list.next;
2709 rfd = (struct rfd *) list_entry(element, struct rfd, list_node);
2712 spin_unlock_irqrestore(&adapter->rcv_lock, flags);
2716 list_del(&rfd->list_node);
2717 rx_local->num_ready_recv--;
2719 spin_unlock_irqrestore(&adapter->rcv_lock, flags);
2721 rfd->bufferindex = buff_index;
2722 rfd->ringindex = ring_index;
2724 /* In V1 silicon, there is a bug which screws up filtering of runt
2725 * packets. Therefore runt packet filtering is disabled in the MAC and
2726 * the packets are dropped here. They are also counted here.
2728 if (len < (NIC_MIN_PACKET_SIZE + 4)) {
2729 adapter->stats.rx_other_errs++;
2738 /* Determine if this is a multicast packet coming in */
2739 if ((word0 & ALCATEL_MULTICAST_PKT) &&
2740 !(word0 & ALCATEL_BROADCAST_PKT)) {
2741 /* Promiscuous mode and Multicast mode are not mutually
2742 * exclusive as was first thought. I guess Promiscuous is just
2743 * considered a super-set of the other filters. Generally filter
2744 * is 0x2b when in promiscuous mode.
2746 if ((adapter->packet_filter & ET131X_PACKET_TYPE_MULTICAST)
2747 && !(adapter->packet_filter & ET131X_PACKET_TYPE_PROMISCUOUS)
2748 && !(adapter->packet_filter &
2749 ET131X_PACKET_TYPE_ALL_MULTICAST)) {
2750 buf = rx_local->fbr[ring_index]->virt[buff_index];
2752 /* Loop through our list to see if the destination
2753 * address of this packet matches one in our list.
2755 for (i = 0; i < adapter->multicast_addr_count; i++) {
2756 if (buf[0] == adapter->multicast_list[i][0]
2757 && buf[1] == adapter->multicast_list[i][1]
2758 && buf[2] == adapter->multicast_list[i][2]
2759 && buf[3] == adapter->multicast_list[i][3]
2760 && buf[4] == adapter->multicast_list[i][4]
2761 && buf[5] == adapter->multicast_list[i][5]) {
2766 /* If our index is equal to the number of Multicast
2767 * address we have, then this means we did not find this
2768 * packet's matching address in our list. Set the len to
2769 * zero, so we free our RFD when we return from this
2772 if (i == adapter->multicast_addr_count)
2777 adapter->stats.multicast_pkts_rcvd++;
2778 } else if (word0 & ALCATEL_BROADCAST_PKT) {
2779 adapter->stats.broadcast_pkts_rcvd++;
2781 /* Not sure what this counter measures in promiscuous mode.
2782 * Perhaps we should check the MAC address to see if it is
2783 * directed to us in promiscuous mode.
2785 adapter->stats.unicast_pkts_rcvd++;
2795 skb = dev_alloc_skb(rfd->len + 2);
2797 dev_err(&adapter->pdev->dev, "Couldn't alloc an SKB for Rx\n");
2801 adapter->net_stats.rx_bytes += rfd->len;
2803 memcpy(skb_put(skb, rfd->len),
2804 rx_local->fbr[ring_index]->virt[buff_index],
2807 skb->dev = adapter->netdev;
2808 skb->protocol = eth_type_trans(skb, adapter->netdev);
2809 skb->ip_summed = CHECKSUM_NONE;
2813 nic_return_rfd(adapter, rfd);
2818 * et131x_handle_recv_interrupt - Interrupt handler for receive processing
2819 * @adapter: pointer to our adapter
2821 * Assumption, Rcv spinlock has been acquired.
2823 static void et131x_handle_recv_interrupt(struct et131x_adapter *adapter)
2825 struct rfd *rfd = NULL;
2829 /* Process up to available RFD's */
2830 while (count < NUM_PACKETS_HANDLED) {
2831 if (list_empty(&adapter->rx_ring.recv_list)) {
2832 WARN_ON(adapter->rx_ring.num_ready_recv != 0);
2837 rfd = nic_rx_pkts(adapter);
2842 /* Do not receive any packets until a filter has been set.
2843 * Do not receive any packets until we have link.
2844 * If length is zero, return the RFD in order to advance the
2847 if (!adapter->packet_filter ||
2848 !netif_carrier_ok(adapter->netdev) ||
2852 /* Increment the number of packets we received */
2853 adapter->net_stats.rx_packets++;
2855 /* Set the status on the packet, either resources or success */
2856 if (adapter->rx_ring.num_ready_recv < RFD_LOW_WATER_MARK) {
2857 dev_warn(&adapter->pdev->dev,
2858 "RFD's are running out\n");
2863 if (count == NUM_PACKETS_HANDLED || !done) {
2864 adapter->rx_ring.unfinished_receives = true;
2865 writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO,
2866 &adapter->regs->global.watchdog_timer);
2868 /* Watchdog timer will disable itself if appropriate. */
2869 adapter->rx_ring.unfinished_receives = false;
2873 * et131x_tx_dma_memory_alloc
2874 * @adapter: pointer to our private adapter structure
2876 * Returns 0 on success and errno on failure (as defined in errno.h).
2878 * Allocates memory that will be visible both to the device and to the CPU.
2879 * The OS will pass us packets, pointers to which we will insert in the Tx
2880 * Descriptor queue. The device will read this queue to find the packets in
2881 * memory. The device will update the "status" in memory each time it xmits a
2884 static int et131x_tx_dma_memory_alloc(struct et131x_adapter *adapter)
2887 struct tx_ring *tx_ring = &adapter->tx_ring;
2889 /* Allocate memory for the TCB's (Transmit Control Block) */
2890 adapter->tx_ring.tcb_ring =
2891 kcalloc(NUM_TCB, sizeof(struct tcb), GFP_ATOMIC | GFP_DMA);
2892 if (!adapter->tx_ring.tcb_ring) {
2893 dev_err(&adapter->pdev->dev, "Cannot alloc memory for TCBs\n");
2897 desc_size = (sizeof(struct tx_desc) * NUM_DESC_PER_RING_TX);
2898 tx_ring->tx_desc_ring =
2899 (struct tx_desc *) dma_alloc_coherent(&adapter->pdev->dev,
2901 &tx_ring->tx_desc_ring_pa,
2903 if (!adapter->tx_ring.tx_desc_ring) {
2904 dev_err(&adapter->pdev->dev,
2905 "Cannot alloc memory for Tx Ring\n");
2909 /* Save physical address
2911 * NOTE: dma_alloc_coherent(), used above to alloc DMA regions,
2912 * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
2913 * are ever returned, make sure the high part is retrieved here before
2914 * storing the adjusted address.
2916 /* Allocate memory for the Tx status block */
2917 tx_ring->tx_status = dma_alloc_coherent(&adapter->pdev->dev,
2919 &tx_ring->tx_status_pa,
2921 if (!adapter->tx_ring.tx_status_pa) {
2922 dev_err(&adapter->pdev->dev,
2923 "Cannot alloc memory for Tx status block\n");
2930 * et131x_tx_dma_memory_free - Free all memory allocated within this module
2931 * @adapter: pointer to our private adapter structure
2933 * Returns 0 on success and errno on failure (as defined in errno.h).
2935 static void et131x_tx_dma_memory_free(struct et131x_adapter *adapter)
2939 if (adapter->tx_ring.tx_desc_ring) {
2940 /* Free memory relating to Tx rings here */
2941 desc_size = (sizeof(struct tx_desc) * NUM_DESC_PER_RING_TX);
2942 dma_free_coherent(&adapter->pdev->dev,
2944 adapter->tx_ring.tx_desc_ring,
2945 adapter->tx_ring.tx_desc_ring_pa);
2946 adapter->tx_ring.tx_desc_ring = NULL;
2949 /* Free memory for the Tx status block */
2950 if (adapter->tx_ring.tx_status) {
2951 dma_free_coherent(&adapter->pdev->dev,
2953 adapter->tx_ring.tx_status,
2954 adapter->tx_ring.tx_status_pa);
2956 adapter->tx_ring.tx_status = NULL;
2958 /* Free the memory for the tcb structures */
2959 kfree(adapter->tx_ring.tcb_ring);
2963 * nic_send_packet - NIC specific send handler for version B silicon.
2964 * @adapter: pointer to our adapter
2965 * @tcb: pointer to struct tcb
2967 * Returns 0 or errno.
2969 static int nic_send_packet(struct et131x_adapter *adapter, struct tcb *tcb)
2972 struct tx_desc desc[24]; /* 24 x 16 byte */
2974 u32 thiscopy, remainder;
2975 struct sk_buff *skb = tcb->skb;
2976 u32 nr_frags = skb_shinfo(skb)->nr_frags + 1;
2977 struct skb_frag_struct *frags = &skb_shinfo(skb)->frags[0];
2978 unsigned long flags;
2979 struct phy_device *phydev = adapter->phydev;
2980 dma_addr_t dma_addr;
2982 /* Part of the optimizations of this send routine restrict us to
2983 * sending 24 fragments at a pass. In practice we should never see
2984 * more than 5 fragments.
2986 * NOTE: The older version of this function (below) can handle any
2987 * number of fragments. If needed, we can call this function,
2988 * although it is less efficient.
2993 memset(desc, 0, sizeof(struct tx_desc) * (nr_frags + 1));
2995 for (i = 0; i < nr_frags; i++) {
2996 /* If there is something in this element, lets get a
2997 * descriptor from the ring and get the necessary data
3000 /* If the fragments are smaller than a standard MTU,
3001 * then map them to a single descriptor in the Tx
3002 * Desc ring. However, if they're larger, as is
3003 * possible with support for jumbo packets, then
3004 * split them each across 2 descriptors.
3006 * This will work until we determine why the hardware
3007 * doesn't seem to like large fragments.
3009 if (skb_headlen(skb) <= 1514) {
3010 /* Low 16bits are length, high is vlan and
3011 unused currently so zero */
3012 desc[frag].len_vlan = skb_headlen(skb);
3013 dma_addr = dma_map_single(&adapter->pdev->dev,
3017 desc[frag].addr_lo = lower_32_bits(dma_addr);
3018 desc[frag].addr_hi = upper_32_bits(dma_addr);
3021 desc[frag].len_vlan = skb_headlen(skb) / 2;
3022 dma_addr = dma_map_single(&adapter->pdev->dev,
3024 (skb_headlen(skb) / 2),
3026 desc[frag].addr_lo = lower_32_bits(dma_addr);
3027 desc[frag].addr_hi = upper_32_bits(dma_addr);
3030 desc[frag].len_vlan = skb_headlen(skb) / 2;
3031 dma_addr = dma_map_single(&adapter->pdev->dev,
3033 (skb_headlen(skb) / 2),
3034 (skb_headlen(skb) / 2),
3036 desc[frag].addr_lo = lower_32_bits(dma_addr);
3037 desc[frag].addr_hi = upper_32_bits(dma_addr);
3041 desc[frag].len_vlan = frags[i - 1].size;
3042 dma_addr = skb_frag_dma_map(&adapter->pdev->dev,
3047 desc[frag].addr_lo = lower_32_bits(dma_addr);
3048 desc[frag].addr_hi = upper_32_bits(dma_addr);
3053 if (phydev && phydev->speed == SPEED_1000) {
3054 if (++adapter->tx_ring.since_irq == PARM_TX_NUM_BUFS_DEF) {
3055 /* Last element & Interrupt flag */
3056 desc[frag - 1].flags = 0x5;
3057 adapter->tx_ring.since_irq = 0;
3058 } else { /* Last element */
3059 desc[frag - 1].flags = 0x1;
3062 desc[frag - 1].flags = 0x5;
3064 desc[0].flags |= 2; /* First element flag */
3066 tcb->index_start = adapter->tx_ring.send_idx;
3069 spin_lock_irqsave(&adapter->send_hw_lock, flags);
3071 thiscopy = NUM_DESC_PER_RING_TX -
3072 INDEX10(adapter->tx_ring.send_idx);
3074 if (thiscopy >= frag) {
3078 remainder = frag - thiscopy;
3081 memcpy(adapter->tx_ring.tx_desc_ring +
3082 INDEX10(adapter->tx_ring.send_idx), desc,
3083 sizeof(struct tx_desc) * thiscopy);
3085 add_10bit(&adapter->tx_ring.send_idx, thiscopy);
3087 if (INDEX10(adapter->tx_ring.send_idx) == 0 ||
3088 INDEX10(adapter->tx_ring.send_idx) == NUM_DESC_PER_RING_TX) {
3089 adapter->tx_ring.send_idx &= ~ET_DMA10_MASK;
3090 adapter->tx_ring.send_idx ^= ET_DMA10_WRAP;
3094 memcpy(adapter->tx_ring.tx_desc_ring,
3096 sizeof(struct tx_desc) * remainder);
3098 add_10bit(&adapter->tx_ring.send_idx, remainder);
3101 if (INDEX10(adapter->tx_ring.send_idx) == 0) {
3102 if (adapter->tx_ring.send_idx)
3103 tcb->index = NUM_DESC_PER_RING_TX - 1;
3105 tcb->index = ET_DMA10_WRAP|(NUM_DESC_PER_RING_TX - 1);
3107 tcb->index = adapter->tx_ring.send_idx - 1;
3109 spin_lock(&adapter->tcb_send_qlock);
3111 if (adapter->tx_ring.send_tail)
3112 adapter->tx_ring.send_tail->next = tcb;
3114 adapter->tx_ring.send_head = tcb;
3116 adapter->tx_ring.send_tail = tcb;
3118 WARN_ON(tcb->next != NULL);
3120 adapter->tx_ring.used++;
3122 spin_unlock(&adapter->tcb_send_qlock);
3124 /* Write the new write pointer back to the device. */
3125 writel(adapter->tx_ring.send_idx,
3126 &adapter->regs->txdma.service_request);
3128 /* For Gig only, we use Tx Interrupt coalescing. Enable the software
3129 * timer to wake us up if this packet isn't followed by N more.
3131 if (phydev && phydev->speed == SPEED_1000) {
3132 writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO,
3133 &adapter->regs->global.watchdog_timer);
3135 spin_unlock_irqrestore(&adapter->send_hw_lock, flags);
3141 * send_packet - Do the work to send a packet
3142 * @skb: the packet(s) to send
3143 * @adapter: a pointer to the device's private adapter structure
3145 * Return 0 in almost all cases; non-zero value in extreme hard failure only.
3147 * Assumption: Send spinlock has been acquired
3149 static int send_packet(struct sk_buff *skb, struct et131x_adapter *adapter)
3152 struct tcb *tcb = NULL;
3154 unsigned long flags;
3156 /* All packets must have at least a MAC address and a protocol type */
3157 if (skb->len < ETH_HLEN)
3160 /* Get a TCB for this packet */
3161 spin_lock_irqsave(&adapter->tcb_ready_qlock, flags);
3163 tcb = adapter->tx_ring.tcb_qhead;
3166 spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
3170 adapter->tx_ring.tcb_qhead = tcb->next;
3172 if (adapter->tx_ring.tcb_qhead == NULL)
3173 adapter->tx_ring.tcb_qtail = NULL;
3175 spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
3179 if (skb->data != NULL && skb_headlen(skb) >= 6) {
3180 shbufva = (u16 *) skb->data;
3182 if ((shbufva[0] == 0xffff) &&
3183 (shbufva[1] == 0xffff) && (shbufva[2] == 0xffff)) {
3184 tcb->flags |= fMP_DEST_BROAD;
3185 } else if ((shbufva[0] & 0x3) == 0x0001) {
3186 tcb->flags |= fMP_DEST_MULTI;
3192 /* Call the NIC specific send handler. */
3193 status = nic_send_packet(adapter, tcb);
3196 spin_lock_irqsave(&adapter->tcb_ready_qlock, flags);
3198 if (adapter->tx_ring.tcb_qtail)
3199 adapter->tx_ring.tcb_qtail->next = tcb;
3201 /* Apparently ready Q is empty. */
3202 adapter->tx_ring.tcb_qhead = tcb;
3204 adapter->tx_ring.tcb_qtail = tcb;
3205 spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
3208 WARN_ON(adapter->tx_ring.used > NUM_TCB);
3213 * et131x_send_packets - This function is called by the OS to send packets
3214 * @skb: the packet(s) to send
3215 * @netdev:device on which to TX the above packet(s)
3217 * Return 0 in almost all cases; non-zero value in extreme hard failure only
3219 static int et131x_send_packets(struct sk_buff *skb, struct net_device *netdev)
3222 struct et131x_adapter *adapter = netdev_priv(netdev);
3224 /* Send these packets
3226 * NOTE: The Linux Tx entry point is only given one packet at a time
3227 * to Tx, so the PacketCount and it's array used makes no sense here
3230 /* TCB is not available */
3231 if (adapter->tx_ring.used >= NUM_TCB) {
3232 /* NOTE: If there's an error on send, no need to queue the
3233 * packet under Linux; if we just send an error up to the
3234 * netif layer, it will resend the skb to us.
3238 /* We need to see if the link is up; if it's not, make the
3239 * netif layer think we're good and drop the packet
3241 if ((adapter->flags & fMP_ADAPTER_FAIL_SEND_MASK) ||
3242 !netif_carrier_ok(netdev)) {
3243 dev_kfree_skb_any(skb);
3246 adapter->net_stats.tx_dropped++;
3248 status = send_packet(skb, adapter);
3249 if (status != 0 && status != -ENOMEM) {
3250 /* On any other error, make netif think we're
3251 * OK and drop the packet
3253 dev_kfree_skb_any(skb);
3255 adapter->net_stats.tx_dropped++;
3263 * free_send_packet - Recycle a struct tcb
3264 * @adapter: pointer to our adapter
3265 * @tcb: pointer to struct tcb
3267 * Complete the packet if necessary
3268 * Assumption - Send spinlock has been acquired
3270 static inline void free_send_packet(struct et131x_adapter *adapter,
3273 unsigned long flags;
3274 struct tx_desc *desc = NULL;
3275 struct net_device_stats *stats = &adapter->net_stats;
3278 if (tcb->flags & fMP_DEST_BROAD)
3279 atomic_inc(&adapter->stats.broadcast_pkts_xmtd);
3280 else if (tcb->flags & fMP_DEST_MULTI)
3281 atomic_inc(&adapter->stats.multicast_pkts_xmtd);
3283 atomic_inc(&adapter->stats.unicast_pkts_xmtd);
3286 stats->tx_bytes += tcb->skb->len;
3288 /* Iterate through the TX descriptors on the ring
3289 * corresponding to this packet and umap the fragments
3293 desc = (struct tx_desc *)
3294 (adapter->tx_ring.tx_desc_ring +
3295 INDEX10(tcb->index_start));
3297 dma_addr = desc->addr_lo;
3298 dma_addr |= (u64)desc->addr_hi << 32;
3300 dma_unmap_single(&adapter->pdev->dev,
3302 desc->len_vlan, DMA_TO_DEVICE);
3304 add_10bit(&tcb->index_start, 1);
3305 if (INDEX10(tcb->index_start) >=
3306 NUM_DESC_PER_RING_TX) {
3307 tcb->index_start &= ~ET_DMA10_MASK;
3308 tcb->index_start ^= ET_DMA10_WRAP;
3310 } while (desc != (adapter->tx_ring.tx_desc_ring +
3311 INDEX10(tcb->index)));
3313 dev_kfree_skb_any(tcb->skb);
3316 memset(tcb, 0, sizeof(struct tcb));
3318 /* Add the TCB to the Ready Q */
3319 spin_lock_irqsave(&adapter->tcb_ready_qlock, flags);
3321 adapter->net_stats.tx_packets++;
3323 if (adapter->tx_ring.tcb_qtail)
3324 adapter->tx_ring.tcb_qtail->next = tcb;
3326 /* Apparently ready Q is empty. */
3327 adapter->tx_ring.tcb_qhead = tcb;
3329 adapter->tx_ring.tcb_qtail = tcb;
3331 spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
3332 WARN_ON(adapter->tx_ring.used < 0);
3336 * et131x_free_busy_send_packets - Free and complete the stopped active sends
3337 * @adapter: pointer to our adapter
3339 * Assumption - Send spinlock has been acquired
3341 static void et131x_free_busy_send_packets(struct et131x_adapter *adapter)
3344 unsigned long flags;
3347 /* Any packets being sent? Check the first TCB on the send list */
3348 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3350 tcb = adapter->tx_ring.send_head;
3352 while (tcb != NULL && freed < NUM_TCB) {
3353 struct tcb *next = tcb->next;
3355 adapter->tx_ring.send_head = next;
3358 adapter->tx_ring.send_tail = NULL;
3360 adapter->tx_ring.used--;
3362 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3365 free_send_packet(adapter, tcb);
3367 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3369 tcb = adapter->tx_ring.send_head;
3372 WARN_ON(freed == NUM_TCB);
3374 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3376 adapter->tx_ring.used = 0;
3380 * et131x_handle_send_interrupt - Interrupt handler for sending processing
3381 * @adapter: pointer to our adapter
3383 * Re-claim the send resources, complete sends and get more to send from
3384 * the send wait queue.
3386 * Assumption - Send spinlock has been acquired
3388 static void et131x_handle_send_interrupt(struct et131x_adapter *adapter)
3390 unsigned long flags;
3395 serviced = readl(&adapter->regs->txdma.new_service_complete);
3396 index = INDEX10(serviced);
3398 /* Has the ring wrapped? Process any descriptors that do not have
3399 * the same "wrap" indicator as the current completion indicator
3401 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3403 tcb = adapter->tx_ring.send_head;
3406 ((serviced ^ tcb->index) & ET_DMA10_WRAP) &&
3407 index < INDEX10(tcb->index)) {
3408 adapter->tx_ring.used--;
3409 adapter->tx_ring.send_head = tcb->next;
3410 if (tcb->next == NULL)
3411 adapter->tx_ring.send_tail = NULL;
3413 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3414 free_send_packet(adapter, tcb);
3415 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3417 /* Goto the next packet */
3418 tcb = adapter->tx_ring.send_head;
3421 !((serviced ^ tcb->index) & ET_DMA10_WRAP)
3422 && index > (tcb->index & ET_DMA10_MASK)) {
3423 adapter->tx_ring.used--;
3424 adapter->tx_ring.send_head = tcb->next;
3425 if (tcb->next == NULL)
3426 adapter->tx_ring.send_tail = NULL;
3428 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3429 free_send_packet(adapter, tcb);
3430 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3432 /* Goto the next packet */
3433 tcb = adapter->tx_ring.send_head;
3436 /* Wake up the queue when we hit a low-water mark */
3437 if (adapter->tx_ring.used <= NUM_TCB / 3)
3438 netif_wake_queue(adapter->netdev);
3440 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3443 static int et131x_get_settings(struct net_device *netdev,
3444 struct ethtool_cmd *cmd)
3446 struct et131x_adapter *adapter = netdev_priv(netdev);
3448 return phy_ethtool_gset(adapter->phydev, cmd);
3451 static int et131x_set_settings(struct net_device *netdev,
3452 struct ethtool_cmd *cmd)
3454 struct et131x_adapter *adapter = netdev_priv(netdev);
3456 return phy_ethtool_sset(adapter->phydev, cmd);
3459 static int et131x_get_regs_len(struct net_device *netdev)
3461 #define ET131X_REGS_LEN 256
3462 return ET131X_REGS_LEN * sizeof(u32);
3465 static void et131x_get_regs(struct net_device *netdev,
3466 struct ethtool_regs *regs, void *regs_data)
3468 struct et131x_adapter *adapter = netdev_priv(netdev);
3469 struct address_map __iomem *aregs = adapter->regs;
3470 u32 *regs_buff = regs_data;
3473 memset(regs_data, 0, et131x_get_regs_len(netdev));
3475 regs->version = (1 << 24) | (adapter->pdev->revision << 16) |
3476 adapter->pdev->device;
3479 et131x_mii_read(adapter, MII_BMCR, (u16 *)®s_buff[num++]);
3480 et131x_mii_read(adapter, MII_BMSR, (u16 *)®s_buff[num++]);
3481 et131x_mii_read(adapter, MII_PHYSID1, (u16 *)®s_buff[num++]);
3482 et131x_mii_read(adapter, MII_PHYSID2, (u16 *)®s_buff[num++]);
3483 et131x_mii_read(adapter, MII_ADVERTISE, (u16 *)®s_buff[num++]);
3484 et131x_mii_read(adapter, MII_LPA, (u16 *)®s_buff[num++]);
3485 et131x_mii_read(adapter, MII_EXPANSION, (u16 *)®s_buff[num++]);
3486 /* Autoneg next page transmit reg */
3487 et131x_mii_read(adapter, 0x07, (u16 *)®s_buff[num++]);
3488 /* Link partner next page reg */
3489 et131x_mii_read(adapter, 0x08, (u16 *)®s_buff[num++]);
3490 et131x_mii_read(adapter, MII_CTRL1000, (u16 *)®s_buff[num++]);
3491 et131x_mii_read(adapter, MII_STAT1000, (u16 *)®s_buff[num++]);
3492 et131x_mii_read(adapter, 0x0b, (u16 *)®s_buff[num++]);
3493 et131x_mii_read(adapter, 0x0c, (u16 *)®s_buff[num++]);
3494 et131x_mii_read(adapter, MII_MMD_CTRL, (u16 *)®s_buff[num++]);
3495 et131x_mii_read(adapter, MII_MMD_DATA, (u16 *)®s_buff[num++]);
3496 et131x_mii_read(adapter, MII_ESTATUS, (u16 *)®s_buff[num++]);
3498 et131x_mii_read(adapter, PHY_INDEX_REG, (u16 *)®s_buff[num++]);
3499 et131x_mii_read(adapter, PHY_DATA_REG, (u16 *)®s_buff[num++]);
3500 et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG,
3501 (u16 *)®s_buff[num++]);
3502 et131x_mii_read(adapter, PHY_LOOPBACK_CONTROL,
3503 (u16 *)®s_buff[num++]);
3504 et131x_mii_read(adapter, PHY_LOOPBACK_CONTROL+1,
3505 (u16 *)®s_buff[num++]);
3507 et131x_mii_read(adapter, PHY_REGISTER_MGMT_CONTROL,
3508 (u16 *)®s_buff[num++]);
3509 et131x_mii_read(adapter, PHY_CONFIG, (u16 *)®s_buff[num++]);
3510 et131x_mii_read(adapter, PHY_PHY_CONTROL, (u16 *)®s_buff[num++]);
3511 et131x_mii_read(adapter, PHY_INTERRUPT_MASK, (u16 *)®s_buff[num++]);
3512 et131x_mii_read(adapter, PHY_INTERRUPT_STATUS,
3513 (u16 *)®s_buff[num++]);
3514 et131x_mii_read(adapter, PHY_PHY_STATUS, (u16 *)®s_buff[num++]);
3515 et131x_mii_read(adapter, PHY_LED_1, (u16 *)®s_buff[num++]);
3516 et131x_mii_read(adapter, PHY_LED_2, (u16 *)®s_buff[num++]);
3519 regs_buff[num++] = readl(&aregs->global.txq_start_addr);
3520 regs_buff[num++] = readl(&aregs->global.txq_end_addr);
3521 regs_buff[num++] = readl(&aregs->global.rxq_start_addr);
3522 regs_buff[num++] = readl(&aregs->global.rxq_end_addr);
3523 regs_buff[num++] = readl(&aregs->global.pm_csr);
3524 regs_buff[num++] = adapter->stats.interrupt_status;
3525 regs_buff[num++] = readl(&aregs->global.int_mask);
3526 regs_buff[num++] = readl(&aregs->global.int_alias_clr_en);
3527 regs_buff[num++] = readl(&aregs->global.int_status_alias);
3528 regs_buff[num++] = readl(&aregs->global.sw_reset);
3529 regs_buff[num++] = readl(&aregs->global.slv_timer);
3530 regs_buff[num++] = readl(&aregs->global.msi_config);
3531 regs_buff[num++] = readl(&aregs->global.loopback);
3532 regs_buff[num++] = readl(&aregs->global.watchdog_timer);
3535 regs_buff[num++] = readl(&aregs->txdma.csr);
3536 regs_buff[num++] = readl(&aregs->txdma.pr_base_hi);
3537 regs_buff[num++] = readl(&aregs->txdma.pr_base_lo);
3538 regs_buff[num++] = readl(&aregs->txdma.pr_num_des);
3539 regs_buff[num++] = readl(&aregs->txdma.txq_wr_addr);
3540 regs_buff[num++] = readl(&aregs->txdma.txq_wr_addr_ext);
3541 regs_buff[num++] = readl(&aregs->txdma.txq_rd_addr);
3542 regs_buff[num++] = readl(&aregs->txdma.dma_wb_base_hi);
3543 regs_buff[num++] = readl(&aregs->txdma.dma_wb_base_lo);
3544 regs_buff[num++] = readl(&aregs->txdma.service_request);
3545 regs_buff[num++] = readl(&aregs->txdma.service_complete);
3546 regs_buff[num++] = readl(&aregs->txdma.cache_rd_index);
3547 regs_buff[num++] = readl(&aregs->txdma.cache_wr_index);
3548 regs_buff[num++] = readl(&aregs->txdma.tx_dma_error);
3549 regs_buff[num++] = readl(&aregs->txdma.desc_abort_cnt);
3550 regs_buff[num++] = readl(&aregs->txdma.payload_abort_cnt);
3551 regs_buff[num++] = readl(&aregs->txdma.writeback_abort_cnt);
3552 regs_buff[num++] = readl(&aregs->txdma.desc_timeout_cnt);
3553 regs_buff[num++] = readl(&aregs->txdma.payload_timeout_cnt);
3554 regs_buff[num++] = readl(&aregs->txdma.writeback_timeout_cnt);
3555 regs_buff[num++] = readl(&aregs->txdma.desc_error_cnt);
3556 regs_buff[num++] = readl(&aregs->txdma.payload_error_cnt);
3557 regs_buff[num++] = readl(&aregs->txdma.writeback_error_cnt);
3558 regs_buff[num++] = readl(&aregs->txdma.dropped_tlp_cnt);
3559 regs_buff[num++] = readl(&aregs->txdma.new_service_complete);
3560 regs_buff[num++] = readl(&aregs->txdma.ethernet_packet_cnt);
3563 regs_buff[num++] = readl(&aregs->rxdma.csr);
3564 regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_hi);
3565 regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_lo);
3566 regs_buff[num++] = readl(&aregs->rxdma.num_pkt_done);
3567 regs_buff[num++] = readl(&aregs->rxdma.max_pkt_time);
3568 regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr);
3569 regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr_ext);
3570 regs_buff[num++] = readl(&aregs->rxdma.rxq_wr_addr);
3571 regs_buff[num++] = readl(&aregs->rxdma.psr_base_hi);
3572 regs_buff[num++] = readl(&aregs->rxdma.psr_base_lo);
3573 regs_buff[num++] = readl(&aregs->rxdma.psr_num_des);
3574 regs_buff[num++] = readl(&aregs->rxdma.psr_avail_offset);
3575 regs_buff[num++] = readl(&aregs->rxdma.psr_full_offset);
3576 regs_buff[num++] = readl(&aregs->rxdma.psr_access_index);
3577 regs_buff[num++] = readl(&aregs->rxdma.psr_min_des);
3578 regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_lo);
3579 regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_hi);
3580 regs_buff[num++] = readl(&aregs->rxdma.fbr0_num_des);
3581 regs_buff[num++] = readl(&aregs->rxdma.fbr0_avail_offset);
3582 regs_buff[num++] = readl(&aregs->rxdma.fbr0_full_offset);
3583 regs_buff[num++] = readl(&aregs->rxdma.fbr0_rd_index);
3584 regs_buff[num++] = readl(&aregs->rxdma.fbr0_min_des);
3585 regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_lo);
3586 regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_hi);
3587 regs_buff[num++] = readl(&aregs->rxdma.fbr1_num_des);
3588 regs_buff[num++] = readl(&aregs->rxdma.fbr1_avail_offset);
3589 regs_buff[num++] = readl(&aregs->rxdma.fbr1_full_offset);
3590 regs_buff[num++] = readl(&aregs->rxdma.fbr1_rd_index);
3591 regs_buff[num++] = readl(&aregs->rxdma.fbr1_min_des);
3594 #define ET131X_DRVINFO_LEN 32 /* value from ethtool.h */
3595 static void et131x_get_drvinfo(struct net_device *netdev,
3596 struct ethtool_drvinfo *info)
3598 struct et131x_adapter *adapter = netdev_priv(netdev);
3600 strncpy(info->driver, DRIVER_NAME, ET131X_DRVINFO_LEN);
3601 strncpy(info->version, DRIVER_VERSION, ET131X_DRVINFO_LEN);
3602 strncpy(info->bus_info, pci_name(adapter->pdev), ET131X_DRVINFO_LEN);
3605 static struct ethtool_ops et131x_ethtool_ops = {
3606 .get_settings = et131x_get_settings,
3607 .set_settings = et131x_set_settings,
3608 .get_drvinfo = et131x_get_drvinfo,
3609 .get_regs_len = et131x_get_regs_len,
3610 .get_regs = et131x_get_regs,
3611 .get_link = ethtool_op_get_link,
3614 * et131x_hwaddr_init - set up the MAC Address on the ET1310
3615 * @adapter: pointer to our private adapter structure
3617 static void et131x_hwaddr_init(struct et131x_adapter *adapter)
3619 /* If have our default mac from init and no mac address from
3620 * EEPROM then we need to generate the last octet and set it on the
3623 if (is_zero_ether_addr(adapter->rom_addr)) {
3625 * We need to randomly generate the last octet so we
3626 * decrease our chances of setting the mac address to
3627 * same as another one of our cards in the system
3629 get_random_bytes(&adapter->addr[5], 1);
3631 * We have the default value in the register we are
3632 * working with so we need to copy the current
3633 * address into the permanent address
3635 memcpy(adapter->rom_addr,
3636 adapter->addr, ETH_ALEN);
3638 /* We do not have an override address, so set the
3639 * current address to the permanent address and add
3642 memcpy(adapter->addr,
3643 adapter->rom_addr, ETH_ALEN);
3648 * et131x_pci_init - initial PCI setup
3649 * @adapter: pointer to our private adapter structure
3650 * @pdev: our PCI device
3652 * Perform the initial setup of PCI registers and if possible initialise
3653 * the MAC address. At this point the I/O registers have yet to be mapped
3655 static int et131x_pci_init(struct et131x_adapter *adapter,
3656 struct pci_dev *pdev)
3661 rc = et131x_init_eeprom(adapter);
3665 if (!pci_is_pcie(pdev)) {
3666 dev_err(&pdev->dev, "Missing PCIe capabilities\n");
3670 /* Let's set up the PORT LOGIC Register. First we need to know what
3671 * the max_payload_size is
3673 if (pcie_capability_read_word(pdev, PCI_EXP_DEVCAP, &max_payload)) {
3675 "Could not read PCI config space for Max Payload Size\n");
3679 /* Program the Ack/Nak latency and replay timers */
3680 max_payload &= 0x07;
3682 if (max_payload < 2) {
3683 static const u16 acknak[2] = { 0x76, 0xD0 };
3684 static const u16 replay[2] = { 0x1E0, 0x2ED };
3686 if (pci_write_config_word(pdev, ET1310_PCI_ACK_NACK,
3687 acknak[max_payload])) {
3689 "Could not write PCI config space for ACK/NAK\n");
3692 if (pci_write_config_word(pdev, ET1310_PCI_REPLAY,
3693 replay[max_payload])) {
3695 "Could not write PCI config space for Replay Timer\n");
3700 /* l0s and l1 latency timers. We are using default values.
3701 * Representing 001 for L0s and 010 for L1
3703 if (pci_write_config_byte(pdev, ET1310_PCI_L0L1LATENCY, 0x11)) {
3705 "Could not write PCI config space for Latency Timers\n");
3709 /* Change the max read size to 2k */
3710 if (pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
3711 PCI_EXP_DEVCTL_READRQ, 0x4 << 12)) {
3713 "Couldn't change PCI config space for Max read size\n");
3717 /* Get MAC address from config space if an eeprom exists, otherwise
3718 * the MAC address there will not be valid
3720 if (!adapter->has_eeprom) {
3721 et131x_hwaddr_init(adapter);
3725 for (i = 0; i < ETH_ALEN; i++) {
3726 if (pci_read_config_byte(pdev, ET1310_PCI_MAC_ADDRESS + i,
3727 adapter->rom_addr + i)) {
3728 dev_err(&pdev->dev, "Could not read PCI config space for MAC address\n");
3732 memcpy(adapter->addr, adapter->rom_addr, ETH_ALEN);
3741 * et131x_error_timer_handler
3742 * @data: timer-specific variable; here a pointer to our adapter structure
3744 * The routine called when the error timer expires, to track the number of
3747 static void et131x_error_timer_handler(unsigned long data)
3749 struct et131x_adapter *adapter = (struct et131x_adapter *) data;
3750 struct phy_device *phydev = adapter->phydev;
3752 if (et1310_in_phy_coma(adapter)) {
3753 /* Bring the device immediately out of coma, to
3754 * prevent it from sleeping indefinitely, this
3755 * mechanism could be improved! */
3756 et1310_disable_phy_coma(adapter);
3757 adapter->boot_coma = 20;
3759 et1310_update_macstat_host_counters(adapter);
3762 if (!phydev->link && adapter->boot_coma < 11)
3763 adapter->boot_coma++;
3765 if (adapter->boot_coma == 10) {
3766 if (!phydev->link) {
3767 if (!et1310_in_phy_coma(adapter)) {
3768 /* NOTE - This was originally a 'sync with
3769 * interrupt'. How to do that under Linux?
3771 et131x_enable_interrupts(adapter);
3772 et1310_enable_phy_coma(adapter);
3777 /* This is a periodic timer, so reschedule */
3778 mod_timer(&adapter->error_timer, jiffies + TX_ERROR_PERIOD * HZ / 1000);
3782 * et131x_adapter_memory_alloc
3783 * @adapter: pointer to our private adapter structure
3785 * Returns 0 on success, errno on failure (as defined in errno.h).
3787 * Allocate all the memory blocks for send, receive and others.
3789 static int et131x_adapter_memory_alloc(struct et131x_adapter *adapter)
3793 /* Allocate memory for the Tx Ring */
3794 status = et131x_tx_dma_memory_alloc(adapter);
3796 dev_err(&adapter->pdev->dev,
3797 "et131x_tx_dma_memory_alloc FAILED\n");
3800 /* Receive buffer memory allocation */
3801 status = et131x_rx_dma_memory_alloc(adapter);
3803 dev_err(&adapter->pdev->dev,
3804 "et131x_rx_dma_memory_alloc FAILED\n");
3805 et131x_tx_dma_memory_free(adapter);
3809 /* Init receive data structures */
3810 status = et131x_init_recv(adapter);
3812 dev_err(&adapter->pdev->dev,
3813 "et131x_init_recv FAILED\n");
3814 et131x_tx_dma_memory_free(adapter);
3815 et131x_rx_dma_memory_free(adapter);
3821 * et131x_adapter_memory_free - Free all memory allocated for use by Tx & Rx
3822 * @adapter: pointer to our private adapter structure
3824 static void et131x_adapter_memory_free(struct et131x_adapter *adapter)
3826 /* Free DMA memory */
3827 et131x_tx_dma_memory_free(adapter);
3828 et131x_rx_dma_memory_free(adapter);
3831 static void et131x_adjust_link(struct net_device *netdev)
3833 struct et131x_adapter *adapter = netdev_priv(netdev);
3834 struct phy_device *phydev = adapter->phydev;
3836 if (netif_carrier_ok(netdev)) {
3837 adapter->boot_coma = 20;
3839 if (phydev && phydev->speed == SPEED_10) {
3841 * NOTE - Is there a way to query this without
3843 * && TRU_QueryCoreType(adapter->hTruePhy, 0)==
3844 * EMI_TRUEPHY_A13O) {
3848 et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG,
3850 et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG,
3852 et131x_mii_write(adapter, PHY_INDEX_REG,
3853 register18 | 0x8402);
3854 et131x_mii_write(adapter, PHY_DATA_REG,
3856 et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG,
3860 et1310_config_flow_control(adapter);
3862 if (phydev && phydev->speed == SPEED_1000 &&
3863 adapter->registry_jumbo_packet > 2048) {
3866 et131x_mii_read(adapter, PHY_CONFIG, ®);
3867 reg &= ~ET_PHY_CONFIG_TX_FIFO_DEPTH;
3868 reg |= ET_PHY_CONFIG_FIFO_DEPTH_32;
3869 et131x_mii_write(adapter, PHY_CONFIG, reg);
3872 et131x_set_rx_dma_timer(adapter);
3873 et1310_config_mac_regs2(adapter);
3876 if (phydev && phydev->link != adapter->link) {
3878 * Check to see if we are in coma mode and if
3879 * so, disable it because we will not be able
3880 * to read PHY values until we are out.
3882 if (et1310_in_phy_coma(adapter))
3883 et1310_disable_phy_coma(adapter);
3886 adapter->boot_coma = 20;
3888 dev_warn(&adapter->pdev->dev,
3889 "Link down - cable problem ?\n");
3890 adapter->boot_coma = 0;
3892 if (phydev->speed == SPEED_10) {
3893 /* NOTE - Is there a way to query this without
3895 * && TRU_QueryCoreType(adapter->hTruePhy, 0) ==
3900 et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG,
3902 et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG,
3904 et131x_mii_write(adapter, PHY_INDEX_REG,
3905 register18 | 0x8402);
3906 et131x_mii_write(adapter, PHY_DATA_REG,
3908 et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG,
3912 /* Free the packets being actively sent & stopped */
3913 et131x_free_busy_send_packets(adapter);
3915 /* Re-initialize the send structures */
3916 et131x_init_send(adapter);
3919 * Bring the device back to the state it was during
3920 * init prior to autonegotiation being complete. This
3921 * way, when we get the auto-neg complete interrupt,
3922 * we can complete init by calling config_mac_regs2.
3924 et131x_soft_reset(adapter);
3926 /* Setup ET1310 as per the documentation */
3927 et131x_adapter_setup(adapter);
3929 /* perform reset of tx/rx */
3930 et131x_disable_txrx(netdev);
3931 et131x_enable_txrx(netdev);
3934 adapter->link = phydev->link;
3936 phy_print_status(phydev);
3940 static int et131x_mii_probe(struct net_device *netdev)
3942 struct et131x_adapter *adapter = netdev_priv(netdev);
3943 struct phy_device *phydev = NULL;
3945 phydev = phy_find_first(adapter->mii_bus);
3947 dev_err(&adapter->pdev->dev, "no PHY found\n");
3951 phydev = phy_connect(netdev, dev_name(&phydev->dev),
3952 &et131x_adjust_link, 0, PHY_INTERFACE_MODE_MII);
3954 if (IS_ERR(phydev)) {
3955 dev_err(&adapter->pdev->dev, "Could not attach to PHY\n");
3956 return PTR_ERR(phydev);
3959 phydev->supported &= (SUPPORTED_10baseT_Half
3960 | SUPPORTED_10baseT_Full
3961 | SUPPORTED_100baseT_Half
3962 | SUPPORTED_100baseT_Full
3967 if (adapter->pdev->device != ET131X_PCI_DEVICE_ID_FAST)
3968 phydev->supported |= SUPPORTED_1000baseT_Full;
3970 phydev->advertising = phydev->supported;
3971 adapter->phydev = phydev;
3973 dev_info(&adapter->pdev->dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
3974 phydev->drv->name, dev_name(&phydev->dev));
3980 * et131x_adapter_init
3981 * @adapter: pointer to the private adapter struct
3982 * @pdev: pointer to the PCI device
3984 * Initialize the data structures for the et131x_adapter object and link
3985 * them together with the platform provided device structures.
3987 static struct et131x_adapter *et131x_adapter_init(struct net_device *netdev,
3988 struct pci_dev *pdev)
3990 static const u8 default_mac[] = { 0x00, 0x05, 0x3d, 0x00, 0x02, 0x00 };
3992 struct et131x_adapter *adapter;
3994 /* Allocate private adapter struct and copy in relevant information */
3995 adapter = netdev_priv(netdev);
3996 adapter->pdev = pci_dev_get(pdev);
3997 adapter->netdev = netdev;
3999 /* Initialize spinlocks here */
4000 spin_lock_init(&adapter->lock);
4001 spin_lock_init(&adapter->tcb_send_qlock);
4002 spin_lock_init(&adapter->tcb_ready_qlock);
4003 spin_lock_init(&adapter->send_hw_lock);
4004 spin_lock_init(&adapter->rcv_lock);
4005 spin_lock_init(&adapter->rcv_pend_lock);
4006 spin_lock_init(&adapter->fbr_lock);
4007 spin_lock_init(&adapter->phy_lock);
4009 adapter->registry_jumbo_packet = 1514; /* 1514-9216 */
4011 /* Set the MAC address to a default */
4012 memcpy(adapter->addr, default_mac, ETH_ALEN);
4019 * @pdev: a pointer to the device's pci_dev structure
4021 * Registered in the pci_driver structure, this function is called when the
4022 * PCI subsystem detects that a PCI device which matches the information
4023 * contained in the pci_device_id table has been removed.
4025 static void et131x_pci_remove(struct pci_dev *pdev)
4027 struct net_device *netdev = pci_get_drvdata(pdev);
4028 struct et131x_adapter *adapter = netdev_priv(netdev);
4030 unregister_netdev(netdev);
4031 phy_disconnect(adapter->phydev);
4032 mdiobus_unregister(adapter->mii_bus);
4033 kfree(adapter->mii_bus->irq);
4034 mdiobus_free(adapter->mii_bus);
4036 et131x_adapter_memory_free(adapter);
4037 iounmap(adapter->regs);
4040 free_netdev(netdev);
4041 pci_release_regions(pdev);
4042 pci_disable_device(pdev);
4046 * et131x_up - Bring up a device for use.
4047 * @netdev: device to be opened
4049 static void et131x_up(struct net_device *netdev)
4051 struct et131x_adapter *adapter = netdev_priv(netdev);
4053 et131x_enable_txrx(netdev);
4054 phy_start(adapter->phydev);
4058 * et131x_down - Bring down the device
4059 * @netdev: device to be brought down
4061 static void et131x_down(struct net_device *netdev)
4063 struct et131x_adapter *adapter = netdev_priv(netdev);
4065 /* Save the timestamp for the TX watchdog, prevent a timeout */
4066 netdev->trans_start = jiffies;
4068 phy_stop(adapter->phydev);
4069 et131x_disable_txrx(netdev);
4072 #ifdef CONFIG_PM_SLEEP
4073 static int et131x_suspend(struct device *dev)
4075 struct pci_dev *pdev = to_pci_dev(dev);
4076 struct net_device *netdev = pci_get_drvdata(pdev);
4078 if (netif_running(netdev)) {
4079 netif_device_detach(netdev);
4080 et131x_down(netdev);
4081 pci_save_state(pdev);
4087 static int et131x_resume(struct device *dev)
4089 struct pci_dev *pdev = to_pci_dev(dev);
4090 struct net_device *netdev = pci_get_drvdata(pdev);
4092 if (netif_running(netdev)) {
4093 pci_restore_state(pdev);
4095 netif_device_attach(netdev);
4101 static SIMPLE_DEV_PM_OPS(et131x_pm_ops, et131x_suspend, et131x_resume);
4102 #define ET131X_PM_OPS (&et131x_pm_ops)
4104 #define ET131X_PM_OPS NULL
4108 * et131x_isr - The Interrupt Service Routine for the driver.
4109 * @irq: the IRQ on which the interrupt was received.
4110 * @dev_id: device-specific info (here a pointer to a net_device struct)
4112 * Returns a value indicating if the interrupt was handled.
4114 irqreturn_t et131x_isr(int irq, void *dev_id)
4116 bool handled = true;
4117 struct net_device *netdev = (struct net_device *)dev_id;
4118 struct et131x_adapter *adapter = NULL;
4121 if (!netif_device_present(netdev)) {
4126 adapter = netdev_priv(netdev);
4128 /* If the adapter is in low power state, then it should not
4129 * recognize any interrupt
4132 /* Disable Device Interrupts */
4133 et131x_disable_interrupts(adapter);
4135 /* Get a copy of the value in the interrupt status register
4136 * so we can process the interrupting section
4138 status = readl(&adapter->regs->global.int_status);
4140 if (adapter->flowcontrol == FLOW_TXONLY ||
4141 adapter->flowcontrol == FLOW_BOTH) {
4142 status &= ~INT_MASK_ENABLE;
4144 status &= ~INT_MASK_ENABLE_NO_FLOW;
4147 /* Make sure this is our interrupt */
4150 et131x_enable_interrupts(adapter);
4154 /* This is our interrupt, so process accordingly */
4156 if (status & ET_INTR_WATCHDOG) {
4157 struct tcb *tcb = adapter->tx_ring.send_head;
4160 if (++tcb->stale > 1)
4161 status |= ET_INTR_TXDMA_ISR;
4163 if (adapter->rx_ring.unfinished_receives)
4164 status |= ET_INTR_RXDMA_XFR_DONE;
4165 else if (tcb == NULL)
4166 writel(0, &adapter->regs->global.watchdog_timer);
4168 status &= ~ET_INTR_WATCHDOG;
4172 /* This interrupt has in some way been "handled" by
4173 * the ISR. Either it was a spurious Rx interrupt, or
4174 * it was a Tx interrupt that has been filtered by
4177 et131x_enable_interrupts(adapter);
4181 /* We need to save the interrupt status value for use in our
4182 * DPC. We will clear the software copy of that in that
4185 adapter->stats.interrupt_status = status;
4187 /* Schedule the ISR handler as a bottom-half task in the
4188 * kernel's tq_immediate queue, and mark the queue for
4191 schedule_work(&adapter->task);
4193 return IRQ_RETVAL(handled);
4197 * et131x_isr_handler - The ISR handler
4198 * @p_adapter, a pointer to the device's private adapter structure
4200 * scheduled to run in a deferred context by the ISR. This is where the ISR's
4201 * work actually gets done.
4203 static void et131x_isr_handler(struct work_struct *work)
4205 struct et131x_adapter *adapter =
4206 container_of(work, struct et131x_adapter, task);
4207 u32 status = adapter->stats.interrupt_status;
4208 struct address_map __iomem *iomem = adapter->regs;
4211 * These first two are by far the most common. Once handled, we clear
4212 * their two bits in the status word. If the word is now zero, we
4215 /* Handle all the completed Transmit interrupts */
4216 if (status & ET_INTR_TXDMA_ISR)
4217 et131x_handle_send_interrupt(adapter);
4219 /* Handle all the completed Receives interrupts */
4220 if (status & ET_INTR_RXDMA_XFR_DONE)
4221 et131x_handle_recv_interrupt(adapter);
4223 status &= 0xffffffd7;
4228 /* Handle the TXDMA Error interrupt */
4229 if (status & ET_INTR_TXDMA_ERR) {
4232 /* Following read also clears the register (COR) */
4233 txdma_err = readl(&iomem->txdma.tx_dma_error);
4235 dev_warn(&adapter->pdev->dev,
4236 "TXDMA_ERR interrupt, error = %d\n",
4240 /* Handle Free Buffer Ring 0 and 1 Low interrupt */
4241 if (status & (ET_INTR_RXDMA_FB_R0_LOW | ET_INTR_RXDMA_FB_R1_LOW)) {
4243 * This indicates the number of unused buffers in RXDMA free
4244 * buffer ring 0 is <= the limit you programmed. Free buffer
4245 * resources need to be returned. Free buffers are consumed as
4246 * packets are passed from the network to the host. The host
4247 * becomes aware of the packets from the contents of the packet
4248 * status ring. This ring is queried when the packet done
4249 * interrupt occurs. Packets are then passed to the OS. When
4250 * the OS is done with the packets the resources can be
4251 * returned to the ET1310 for re-use. This interrupt is one
4252 * method of returning resources.
4256 * If the user has flow control on, then we will
4257 * send a pause packet, otherwise just exit
4259 if (adapter->flowcontrol == FLOW_TXONLY ||
4260 adapter->flowcontrol == FLOW_BOTH) {
4264 * Tell the device to send a pause packet via the back
4265 * pressure register (bp req and bp xon/xoff)
4267 pm_csr = readl(&iomem->global.pm_csr);
4268 if (!et1310_in_phy_coma(adapter))
4269 writel(3, &iomem->txmac.bp_ctrl);
4273 /* Handle Packet Status Ring Low Interrupt */
4274 if (status & ET_INTR_RXDMA_STAT_LOW) {
4276 * Same idea as with the two Free Buffer Rings. Packets going
4277 * from the network to the host each consume a free buffer
4278 * resource and a packet status resource. These resoures are
4279 * passed to the OS. When the OS is done with the resources,
4280 * they need to be returned to the ET1310. This is one method
4281 * of returning the resources.
4285 /* Handle RXDMA Error Interrupt */
4286 if (status & ET_INTR_RXDMA_ERR) {
4288 * The rxdma_error interrupt is sent when a time-out on a
4289 * request issued by the JAGCore has occurred or a completion is
4290 * returned with an un-successful status. In both cases the
4291 * request is considered complete. The JAGCore will
4292 * automatically re-try the request in question. Normally
4293 * information on events like these are sent to the host using
4294 * the "Advanced Error Reporting" capability. This interrupt is
4295 * another way of getting similar information. The only thing
4296 * required is to clear the interrupt by reading the ISR in the
4297 * global resources. The JAGCore will do a re-try on the
4298 * request. Normally you should never see this interrupt. If
4299 * you start to see this interrupt occurring frequently then
4300 * something bad has occurred. A reset might be the thing to do.
4304 dev_warn(&adapter->pdev->dev,
4305 "RxDMA_ERR interrupt, error %x\n",
4306 readl(&iomem->txmac.tx_test));
4309 /* Handle the Wake on LAN Event */
4310 if (status & ET_INTR_WOL) {
4312 * This is a secondary interrupt for wake on LAN. The driver
4313 * should never see this, if it does, something serious is
4314 * wrong. We will TRAP the message when we are in DBG mode,
4315 * otherwise we will ignore it.
4317 dev_err(&adapter->pdev->dev, "WAKE_ON_LAN interrupt\n");
4320 /* Let's move on to the TxMac */
4321 if (status & ET_INTR_TXMAC) {
4322 u32 err = readl(&iomem->txmac.err);
4325 * When any of the errors occur and TXMAC generates an
4326 * interrupt to report these errors, it usually means that
4327 * TXMAC has detected an error in the data stream retrieved
4328 * from the on-chip Tx Q. All of these errors are catastrophic
4329 * and TXMAC won't be able to recover data when these errors
4330 * occur. In a nutshell, the whole Tx path will have to be reset
4331 * and re-configured afterwards.
4333 dev_warn(&adapter->pdev->dev,
4334 "TXMAC interrupt, error 0x%08x\n",
4338 * If we are debugging, we want to see this error, otherwise we
4339 * just want the device to be reset and continue
4343 /* Handle RXMAC Interrupt */
4344 if (status & ET_INTR_RXMAC) {
4346 * These interrupts are catastrophic to the device, what we need
4347 * to do is disable the interrupts and set the flag to cause us
4348 * to reset so we can solve this issue.
4350 /* MP_SET_FLAG( adapter, fMP_ADAPTER_HARDWARE_ERROR); */
4352 dev_warn(&adapter->pdev->dev,
4353 "RXMAC interrupt, error 0x%08x. Requesting reset\n",
4354 readl(&iomem->rxmac.err_reg));
4356 dev_warn(&adapter->pdev->dev,
4357 "Enable 0x%08x, Diag 0x%08x\n",
4358 readl(&iomem->rxmac.ctrl),
4359 readl(&iomem->rxmac.rxq_diag));
4362 * If we are debugging, we want to see this error, otherwise we
4363 * just want the device to be reset and continue
4367 /* Handle MAC_STAT Interrupt */
4368 if (status & ET_INTR_MAC_STAT) {
4370 * This means at least one of the un-masked counters in the
4371 * MAC_STAT block has rolled over. Use this to maintain the top,
4372 * software managed bits of the counter(s).
4374 et1310_handle_macstat_interrupt(adapter);
4377 /* Handle SLV Timeout Interrupt */
4378 if (status & ET_INTR_SLV_TIMEOUT) {
4380 * This means a timeout has occurred on a read or write request
4381 * to one of the JAGCore registers. The Global Resources block
4382 * has terminated the request and on a read request, returned a
4383 * "fake" value. The most likely reasons are: Bad Address or the
4384 * addressed module is in a power-down state and can't respond.
4388 et131x_enable_interrupts(adapter);
4392 * et131x_stats - Return the current device statistics.
4393 * @netdev: device whose stats are being queried
4395 * Returns 0 on success, errno on failure (as defined in errno.h)
4397 static struct net_device_stats *et131x_stats(struct net_device *netdev)
4399 struct et131x_adapter *adapter = netdev_priv(netdev);
4400 struct net_device_stats *stats = &adapter->net_stats;
4401 struct ce_stats *devstat = &adapter->stats;
4403 stats->rx_errors = devstat->rx_length_errs +
4404 devstat->rx_align_errs +
4405 devstat->rx_crc_errs +
4406 devstat->rx_code_violations +
4407 devstat->rx_other_errs;
4408 stats->tx_errors = devstat->tx_max_pkt_errs;
4409 stats->multicast = devstat->multicast_pkts_rcvd;
4410 stats->collisions = devstat->tx_collisions;
4412 stats->rx_length_errors = devstat->rx_length_errs;
4413 stats->rx_over_errors = devstat->rx_overflows;
4414 stats->rx_crc_errors = devstat->rx_crc_errs;
4416 /* NOTE: These stats don't have corresponding values in CE_STATS,
4417 * so we're going to have to update these directly from within the
4420 /* stats->rx_bytes = 20; devstat->; */
4421 /* stats->tx_bytes = 20; devstat->; */
4422 /* stats->rx_dropped = devstat->; */
4423 /* stats->tx_dropped = devstat->; */
4425 /* NOTE: Not used, can't find analogous statistics */
4426 /* stats->rx_frame_errors = devstat->; */
4427 /* stats->rx_fifo_errors = devstat->; */
4428 /* stats->rx_missed_errors = devstat->; */
4430 /* stats->tx_aborted_errors = devstat->; */
4431 /* stats->tx_carrier_errors = devstat->; */
4432 /* stats->tx_fifo_errors = devstat->; */
4433 /* stats->tx_heartbeat_errors = devstat->; */
4434 /* stats->tx_window_errors = devstat->; */
4439 * et131x_open - Open the device for use.
4440 * @netdev: device to be opened
4442 * Returns 0 on success, errno on failure (as defined in errno.h)
4444 static int et131x_open(struct net_device *netdev)
4446 struct et131x_adapter *adapter = netdev_priv(netdev);
4447 struct pci_dev *pdev = adapter->pdev;
4448 unsigned int irq = pdev->irq;
4451 /* Start the timer to track NIC errors */
4452 init_timer(&adapter->error_timer);
4453 adapter->error_timer.expires = jiffies + TX_ERROR_PERIOD * HZ / 1000;
4454 adapter->error_timer.function = et131x_error_timer_handler;
4455 adapter->error_timer.data = (unsigned long)adapter;
4456 add_timer(&adapter->error_timer);
4458 result = request_irq(irq, et131x_isr,
4459 IRQF_SHARED, netdev->name, netdev);
4461 dev_err(&pdev->dev, "could not register IRQ %d\n", irq);
4465 adapter->flags |= fMP_ADAPTER_INTERRUPT_IN_USE;
4473 * et131x_close - Close the device
4474 * @netdev: device to be closed
4476 * Returns 0 on success, errno on failure (as defined in errno.h)
4478 static int et131x_close(struct net_device *netdev)
4480 struct et131x_adapter *adapter = netdev_priv(netdev);
4482 et131x_down(netdev);
4484 adapter->flags &= ~fMP_ADAPTER_INTERRUPT_IN_USE;
4485 free_irq(adapter->pdev->irq, netdev);
4487 /* Stop the error timer */
4488 return del_timer_sync(&adapter->error_timer);
4492 * et131x_ioctl - The I/O Control handler for the driver
4493 * @netdev: device on which the control request is being made
4494 * @reqbuf: a pointer to the IOCTL request buffer
4495 * @cmd: the IOCTL command code
4497 * Returns 0 on success, errno on failure (as defined in errno.h)
4499 static int et131x_ioctl(struct net_device *netdev, struct ifreq *reqbuf,
4502 struct et131x_adapter *adapter = netdev_priv(netdev);
4504 if (!adapter->phydev)
4507 return phy_mii_ioctl(adapter->phydev, reqbuf, cmd);
4511 * et131x_set_packet_filter - Configures the Rx Packet filtering on the device
4512 * @adapter: pointer to our private adapter structure
4514 * FIXME: lot of dups with MAC code
4516 * Returns 0 on success, errno on failure
4518 static int et131x_set_packet_filter(struct et131x_adapter *adapter)
4520 int filter = adapter->packet_filter;
4525 ctrl = readl(&adapter->regs->rxmac.ctrl);
4526 pf_ctrl = readl(&adapter->regs->rxmac.pf_ctrl);
4528 /* Default to disabled packet filtering. Enable it in the individual
4529 * case statements that require the device to filter something
4533 /* Set us to be in promiscuous mode so we receive everything, this
4534 * is also true when we get a packet filter of 0
4536 if ((filter & ET131X_PACKET_TYPE_PROMISCUOUS) || filter == 0)
4537 pf_ctrl &= ~7; /* Clear filter bits */
4540 * Set us up with Multicast packet filtering. Three cases are
4541 * possible - (1) we have a multi-cast list, (2) we receive ALL
4542 * multicast entries or (3) we receive none.
4544 if (filter & ET131X_PACKET_TYPE_ALL_MULTICAST)
4545 pf_ctrl &= ~2; /* Multicast filter bit */
4547 et1310_setup_device_for_multicast(adapter);
4552 /* Set us up with Unicast packet filtering */
4553 if (filter & ET131X_PACKET_TYPE_DIRECTED) {
4554 et1310_setup_device_for_unicast(adapter);
4559 /* Set us up with Broadcast packet filtering */
4560 if (filter & ET131X_PACKET_TYPE_BROADCAST) {
4561 pf_ctrl |= 1; /* Broadcast filter bit */
4566 /* Setup the receive mac configuration registers - Packet
4567 * Filter control + the enable / disable for packet filter
4568 * in the control reg.
4570 writel(pf_ctrl, &adapter->regs->rxmac.pf_ctrl);
4571 writel(ctrl, &adapter->regs->rxmac.ctrl);
4577 * et131x_multicast - The handler to configure multicasting on the interface
4578 * @netdev: a pointer to a net_device struct representing the device
4580 static void et131x_multicast(struct net_device *netdev)
4582 struct et131x_adapter *adapter = netdev_priv(netdev);
4584 unsigned long flags;
4585 struct netdev_hw_addr *ha;
4588 spin_lock_irqsave(&adapter->lock, flags);
4590 /* Before we modify the platform-independent filter flags, store them
4591 * locally. This allows us to determine if anything's changed and if
4592 * we even need to bother the hardware
4594 packet_filter = adapter->packet_filter;
4596 /* Clear the 'multicast' flag locally; because we only have a single
4597 * flag to check multicast, and multiple multicast addresses can be
4598 * set, this is the easiest way to determine if more than one
4599 * multicast address is being set.
4601 packet_filter &= ~ET131X_PACKET_TYPE_MULTICAST;
4603 /* Check the net_device flags and set the device independent flags
4607 if (netdev->flags & IFF_PROMISC)
4608 adapter->packet_filter |= ET131X_PACKET_TYPE_PROMISCUOUS;
4610 adapter->packet_filter &= ~ET131X_PACKET_TYPE_PROMISCUOUS;
4612 if (netdev->flags & IFF_ALLMULTI)
4613 adapter->packet_filter |= ET131X_PACKET_TYPE_ALL_MULTICAST;
4615 if (netdev_mc_count(netdev) > NIC_MAX_MCAST_LIST)
4616 adapter->packet_filter |= ET131X_PACKET_TYPE_ALL_MULTICAST;
4618 if (netdev_mc_count(netdev) < 1) {
4619 adapter->packet_filter &= ~ET131X_PACKET_TYPE_ALL_MULTICAST;
4620 adapter->packet_filter &= ~ET131X_PACKET_TYPE_MULTICAST;
4622 adapter->packet_filter |= ET131X_PACKET_TYPE_MULTICAST;
4624 /* Set values in the private adapter struct */
4626 netdev_for_each_mc_addr(ha, netdev) {
4627 if (i == NIC_MAX_MCAST_LIST)
4629 memcpy(adapter->multicast_list[i++], ha->addr, ETH_ALEN);
4631 adapter->multicast_addr_count = i;
4633 /* Are the new flags different from the previous ones? If not, then no
4634 * action is required
4636 * NOTE - This block will always update the multicast_list with the
4637 * hardware, even if the addresses aren't the same.
4639 if (packet_filter != adapter->packet_filter) {
4640 /* Call the device's filter function */
4641 et131x_set_packet_filter(adapter);
4643 spin_unlock_irqrestore(&adapter->lock, flags);
4647 * et131x_tx - The handler to tx a packet on the device
4648 * @skb: data to be Tx'd
4649 * @netdev: device on which data is to be Tx'd
4651 * Returns 0 on success, errno on failure (as defined in errno.h)
4653 static int et131x_tx(struct sk_buff *skb, struct net_device *netdev)
4656 struct et131x_adapter *adapter = netdev_priv(netdev);
4658 /* stop the queue if it's getting full */
4659 if (adapter->tx_ring.used >= NUM_TCB - 1 &&
4660 !netif_queue_stopped(netdev))
4661 netif_stop_queue(netdev);
4663 /* Save the timestamp for the TX timeout watchdog */
4664 netdev->trans_start = jiffies;
4666 /* Call the device-specific data Tx routine */
4667 status = et131x_send_packets(skb, netdev);
4669 /* Check status and manage the netif queue if necessary */
4671 if (status == -ENOMEM)
4672 status = NETDEV_TX_BUSY;
4674 status = NETDEV_TX_OK;
4680 * et131x_tx_timeout - Timeout handler
4681 * @netdev: a pointer to a net_device struct representing the device
4683 * The handler called when a Tx request times out. The timeout period is
4684 * specified by the 'tx_timeo" element in the net_device structure (see
4685 * et131x_alloc_device() to see how this value is set).
4687 static void et131x_tx_timeout(struct net_device *netdev)
4689 struct et131x_adapter *adapter = netdev_priv(netdev);
4691 unsigned long flags;
4693 /* If the device is closed, ignore the timeout */
4694 if (~(adapter->flags & fMP_ADAPTER_INTERRUPT_IN_USE))
4697 /* Any nonrecoverable hardware error?
4698 * Checks adapter->flags for any failure in phy reading
4700 if (adapter->flags & fMP_ADAPTER_NON_RECOVER_ERROR)
4703 /* Hardware failure? */
4704 if (adapter->flags & fMP_ADAPTER_HARDWARE_ERROR) {
4705 dev_err(&adapter->pdev->dev, "hardware error - reset\n");
4709 /* Is send stuck? */
4710 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
4712 tcb = adapter->tx_ring.send_head;
4717 if (tcb->count > NIC_SEND_HANG_THRESHOLD) {
4718 spin_unlock_irqrestore(&adapter->tcb_send_qlock,
4721 dev_warn(&adapter->pdev->dev,
4722 "Send stuck - reset. tcb->WrIndex %x, flags 0x%08x\n",
4726 adapter->net_stats.tx_errors++;
4728 /* perform reset of tx/rx */
4729 et131x_disable_txrx(netdev);
4730 et131x_enable_txrx(netdev);
4735 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
4739 * et131x_change_mtu - The handler called to change the MTU for the device
4740 * @netdev: device whose MTU is to be changed
4741 * @new_mtu: the desired MTU
4743 * Returns 0 on success, errno on failure (as defined in errno.h)
4745 static int et131x_change_mtu(struct net_device *netdev, int new_mtu)
4748 struct et131x_adapter *adapter = netdev_priv(netdev);
4750 /* Make sure the requested MTU is valid */
4751 if (new_mtu < 64 || new_mtu > 9216)
4754 et131x_disable_txrx(netdev);
4755 et131x_handle_send_interrupt(adapter);
4756 et131x_handle_recv_interrupt(adapter);
4758 /* Set the new MTU */
4759 netdev->mtu = new_mtu;
4761 /* Free Rx DMA memory */
4762 et131x_adapter_memory_free(adapter);
4764 /* Set the config parameter for Jumbo Packet support */
4765 adapter->registry_jumbo_packet = new_mtu + 14;
4766 et131x_soft_reset(adapter);
4768 /* Alloc and init Rx DMA memory */
4769 result = et131x_adapter_memory_alloc(adapter);
4771 dev_warn(&adapter->pdev->dev,
4772 "Change MTU failed; couldn't re-alloc DMA memory\n");
4776 et131x_init_send(adapter);
4778 et131x_hwaddr_init(adapter);
4779 memcpy(netdev->dev_addr, adapter->addr, ETH_ALEN);
4781 /* Init the device with the new settings */
4782 et131x_adapter_setup(adapter);
4784 et131x_enable_txrx(netdev);
4790 * et131x_set_mac_addr - handler to change the MAC address for the device
4791 * @netdev: device whose MAC is to be changed
4792 * @new_mac: the desired MAC address
4794 * Returns 0 on success, errno on failure (as defined in errno.h)
4796 * IMPLEMENTED BY : blux http://berndlux.de 22.01.2007 21:14
4798 static int et131x_set_mac_addr(struct net_device *netdev, void *new_mac)
4801 struct et131x_adapter *adapter = netdev_priv(netdev);
4802 struct sockaddr *address = new_mac;
4806 if (adapter == NULL)
4809 /* Make sure the requested MAC is valid */
4810 if (!is_valid_ether_addr(address->sa_data))
4811 return -EADDRNOTAVAIL;
4813 et131x_disable_txrx(netdev);
4814 et131x_handle_send_interrupt(adapter);
4815 et131x_handle_recv_interrupt(adapter);
4817 /* Set the new MAC */
4818 /* netdev->set_mac_address = &new_mac; */
4820 memcpy(netdev->dev_addr, address->sa_data, netdev->addr_len);
4822 netdev_info(netdev, "Setting MAC address to %pM\n",
4825 /* Free Rx DMA memory */
4826 et131x_adapter_memory_free(adapter);
4828 et131x_soft_reset(adapter);
4830 /* Alloc and init Rx DMA memory */
4831 result = et131x_adapter_memory_alloc(adapter);
4833 dev_err(&adapter->pdev->dev,
4834 "Change MAC failed; couldn't re-alloc DMA memory\n");
4838 et131x_init_send(adapter);
4840 et131x_hwaddr_init(adapter);
4842 /* Init the device with the new settings */
4843 et131x_adapter_setup(adapter);
4845 et131x_enable_txrx(netdev);
4850 static const struct net_device_ops et131x_netdev_ops = {
4851 .ndo_open = et131x_open,
4852 .ndo_stop = et131x_close,
4853 .ndo_start_xmit = et131x_tx,
4854 .ndo_set_rx_mode = et131x_multicast,
4855 .ndo_tx_timeout = et131x_tx_timeout,
4856 .ndo_change_mtu = et131x_change_mtu,
4857 .ndo_set_mac_address = et131x_set_mac_addr,
4858 .ndo_validate_addr = eth_validate_addr,
4859 .ndo_get_stats = et131x_stats,
4860 .ndo_do_ioctl = et131x_ioctl,
4864 * et131x_pci_setup - Perform device initialization
4865 * @pdev: a pointer to the device's pci_dev structure
4866 * @ent: this device's entry in the pci_device_id table
4868 * Returns 0 on success, errno on failure (as defined in errno.h)
4870 * Registered in the pci_driver structure, this function is called when the
4871 * PCI subsystem finds a new PCI device which matches the information
4872 * contained in the pci_device_id table. This routine is the equivalent to
4873 * a device insertion routine.
4875 static int et131x_pci_setup(struct pci_dev *pdev,
4876 const struct pci_device_id *ent)
4878 struct net_device *netdev;
4879 struct et131x_adapter *adapter;
4883 rc = pci_enable_device(pdev);
4885 dev_err(&pdev->dev, "pci_enable_device() failed\n");
4889 /* Perform some basic PCI checks */
4890 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
4891 dev_err(&pdev->dev, "Can't find PCI device's base address\n");
4896 rc = pci_request_regions(pdev, DRIVER_NAME);
4898 dev_err(&pdev->dev, "Can't get PCI resources\n");
4902 pci_set_master(pdev);
4904 /* Check the DMA addressing support of this device */
4905 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
4906 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
4909 "Unable to obtain 64 bit DMA for consistent allocations\n");
4910 goto err_release_res;
4912 } else if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
4913 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
4916 "Unable to obtain 32 bit DMA for consistent allocations\n");
4917 goto err_release_res;
4920 dev_err(&pdev->dev, "No usable DMA addressing method\n");
4922 goto err_release_res;
4925 /* Allocate netdev and private adapter structs */
4926 netdev = alloc_etherdev(sizeof(struct et131x_adapter));
4928 dev_err(&pdev->dev, "Couldn't alloc netdev struct\n");
4930 goto err_release_res;
4933 netdev->watchdog_timeo = ET131X_TX_TIMEOUT;
4934 netdev->netdev_ops = &et131x_netdev_ops;
4936 SET_NETDEV_DEV(netdev, &pdev->dev);
4937 SET_ETHTOOL_OPS(netdev, &et131x_ethtool_ops);
4939 adapter = et131x_adapter_init(netdev, pdev);
4941 rc = et131x_pci_init(adapter, pdev);
4945 /* Map the bus-relative registers to system virtual memory */
4946 adapter->regs = pci_ioremap_bar(pdev, 0);
4947 if (!adapter->regs) {
4948 dev_err(&pdev->dev, "Cannot map device registers\n");
4953 /* If Phy COMA mode was enabled when we went down, disable it here. */
4954 writel(ET_PMCSR_INIT, &adapter->regs->global.pm_csr);
4956 /* Issue a global reset to the et1310 */
4957 et131x_soft_reset(adapter);
4959 /* Disable all interrupts (paranoid) */
4960 et131x_disable_interrupts(adapter);
4962 /* Allocate DMA memory */
4963 rc = et131x_adapter_memory_alloc(adapter);
4965 dev_err(&pdev->dev, "Could not alloc adapater memory (DMA)\n");
4969 /* Init send data structures */
4970 et131x_init_send(adapter);
4972 /* Set up the task structure for the ISR's deferred handler */
4973 INIT_WORK(&adapter->task, et131x_isr_handler);
4975 /* Copy address into the net_device struct */
4976 memcpy(netdev->dev_addr, adapter->addr, ETH_ALEN);
4978 /* Init variable for counting how long we do not have link status */
4979 adapter->boot_coma = 0;
4980 et1310_disable_phy_coma(adapter);
4984 /* Setup the mii_bus struct */
4985 adapter->mii_bus = mdiobus_alloc();
4986 if (!adapter->mii_bus) {
4987 dev_err(&pdev->dev, "Alloc of mii_bus struct failed\n");
4991 adapter->mii_bus->name = "et131x_eth_mii";
4992 snprintf(adapter->mii_bus->id, MII_BUS_ID_SIZE, "%x",
4993 (adapter->pdev->bus->number << 8) | adapter->pdev->devfn);
4994 adapter->mii_bus->priv = netdev;
4995 adapter->mii_bus->read = et131x_mdio_read;
4996 adapter->mii_bus->write = et131x_mdio_write;
4997 adapter->mii_bus->reset = et131x_mdio_reset;
4998 adapter->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
4999 if (!adapter->mii_bus->irq) {
5000 dev_err(&pdev->dev, "mii_bus irq allocation failed\n");
5004 for (ii = 0; ii < PHY_MAX_ADDR; ii++)
5005 adapter->mii_bus->irq[ii] = PHY_POLL;
5007 rc = mdiobus_register(adapter->mii_bus);
5009 dev_err(&pdev->dev, "failed to register MII bus\n");
5010 goto err_mdio_free_irq;
5013 rc = et131x_mii_probe(netdev);
5015 dev_err(&pdev->dev, "failed to probe MII bus\n");
5016 goto err_mdio_unregister;
5019 /* Setup et1310 as per the documentation */
5020 et131x_adapter_setup(adapter);
5022 /* We can enable interrupts now
5024 * NOTE - Because registration of interrupt handler is done in the
5025 * device's open(), defer enabling device interrupts to that
5029 /* Register the net_device struct with the Linux network layer */
5030 rc = register_netdev(netdev);
5032 dev_err(&pdev->dev, "register_netdev() failed\n");
5033 goto err_phy_disconnect;
5036 /* Register the net_device struct with the PCI subsystem. Save a copy
5037 * of the PCI config space for this device now that the device has
5038 * been initialized, just in case it needs to be quickly restored.
5040 pci_set_drvdata(pdev, netdev);
5045 phy_disconnect(adapter->phydev);
5046 err_mdio_unregister:
5047 mdiobus_unregister(adapter->mii_bus);
5049 kfree(adapter->mii_bus->irq);
5051 mdiobus_free(adapter->mii_bus);
5053 et131x_adapter_memory_free(adapter);
5055 iounmap(adapter->regs);
5058 free_netdev(netdev);
5060 pci_release_regions(pdev);
5062 pci_disable_device(pdev);
5066 static DEFINE_PCI_DEVICE_TABLE(et131x_pci_table) = {
5067 { PCI_VDEVICE(ATT, ET131X_PCI_DEVICE_ID_GIG), 0UL},
5068 { PCI_VDEVICE(ATT, ET131X_PCI_DEVICE_ID_FAST), 0UL},
5071 MODULE_DEVICE_TABLE(pci, et131x_pci_table);
5073 static struct pci_driver et131x_driver = {
5074 .name = DRIVER_NAME,
5075 .id_table = et131x_pci_table,
5076 .probe = et131x_pci_setup,
5077 .remove = et131x_pci_remove,
5078 .driver.pm = ET131X_PM_OPS,
5081 module_pci_driver(et131x_driver);