3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
5 * Copyright © 2005 Agere Systems Inc.
9 * Copyright (c) 2011 Mark Einon <mark.einon@gmail.com>
11 *------------------------------------------------------------------------------
15 * This software is provided subject to the following terms and conditions,
16 * which you should read carefully before using the software. Using this
17 * software indicates your acceptance of these terms and conditions. If you do
18 * not agree with these terms and conditions, do not use the software.
20 * Copyright © 2005 Agere Systems Inc.
21 * All rights reserved.
23 * Redistribution and use in source or binary forms, with or without
24 * modifications, are permitted provided that the following conditions are met:
26 * . Redistributions of source code must retain the above copyright notice, this
27 * list of conditions and the following Disclaimer as comments in the code as
28 * well as in the documentation and/or other materials provided with the
31 * . Redistributions in binary form must reproduce the above copyright notice,
32 * this list of conditions and the following Disclaimer in the documentation
33 * and/or other materials provided with the distribution.
35 * . Neither the name of Agere Systems Inc. nor the names of the contributors
36 * may be used to endorse or promote products derived from this software
37 * without specific prior written permission.
41 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
42 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
43 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
44 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
45 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
46 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
47 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
48 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
49 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
50 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
51 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
56 #include "et131x_defs.h"
58 #include <linux/pci.h>
59 #include <linux/init.h>
60 #include <linux/module.h>
61 #include <linux/types.h>
62 #include <linux/kernel.h>
64 #include <linux/sched.h>
65 #include <linux/ptrace.h>
66 #include <linux/slab.h>
67 #include <linux/ctype.h>
68 #include <linux/string.h>
69 #include <linux/timer.h>
70 #include <linux/interrupt.h>
72 #include <linux/delay.h>
73 #include <linux/bitops.h>
75 #include <asm/system.h>
77 #include <linux/netdevice.h>
78 #include <linux/etherdevice.h>
79 #include <linux/skbuff.h>
80 #include <linux/if_arp.h>
81 #include <linux/ioport.h>
82 #include <linux/crc32.h>
83 #include <linux/random.h>
84 #include <linux/phy.h>
86 #include "et1310_phy.h"
87 #include "et131x_adapter.h"
88 #include "et1310_address_map.h"
89 #include "et1310_tx.h"
90 #include "et1310_rx.h"
93 MODULE_AUTHOR("Victor Soriano <vjsoriano@agere.com>");
94 MODULE_AUTHOR("Mark Einon <mark.einon@gmail.com>");
95 MODULE_LICENSE("Dual BSD/GPL");
96 MODULE_DESCRIPTION("10/100/1000 Base-T Ethernet Driver "
97 "for the ET1310 by Agere Systems");
99 /* EEPROM functions */
101 static int eeprom_wait_ready(struct pci_dev *pdev, u32 *status)
107 * 1. Check LBCIF Status Register for bits 6 & 3:2 all equal to 0 and
108 * bits 7,1:0 both equal to 1, at least once after reset.
109 * Subsequent operations need only to check that bits 1:0 are equal
110 * to 1 prior to starting a single byte read/write
113 for (i = 0; i < MAX_NUM_REGISTER_POLLS; i++) {
114 /* Read registers grouped in DWORD1 */
115 if (pci_read_config_dword(pdev, LBCIF_DWORD1_GROUP, ®))
118 /* I2C idle and Phy Queue Avail both true */
119 if ((reg & 0x3000) == 0x3000) {
130 * eeprom_write - Write a byte to the ET1310's EEPROM
131 * @adapter: pointer to our private adapter structure
132 * @addr: the address to write
133 * @data: the value to write
135 * Returns 1 for a successful write.
137 static int eeprom_write(struct et131x_adapter *adapter, u32 addr, u8 data)
139 struct pci_dev *pdev = adapter->pdev;
149 * For an EEPROM, an I2C single byte write is defined as a START
150 * condition followed by the device address, EEPROM address, one byte
151 * of data and a STOP condition. The STOP condition will trigger the
152 * EEPROM's internally timed write cycle to the nonvolatile memory.
153 * All inputs are disabled during this write cycle and the EEPROM will
154 * not respond to any access until the internal write is complete.
157 err = eeprom_wait_ready(pdev, NULL);
162 * 2. Write to the LBCIF Control Register: bit 7=1, bit 6=1, bit 3=0,
163 * and bits 1:0 both =0. Bit 5 should be set according to the
164 * type of EEPROM being accessed (1=two byte addressing, 0=one
167 if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
168 LBCIF_CONTROL_LBCIF_ENABLE | LBCIF_CONTROL_I2C_WRITE))
173 /* Prepare EEPROM address for Step 3 */
175 for (retries = 0; retries < MAX_NUM_WRITE_RETRIES; retries++) {
176 /* Write the address to the LBCIF Address Register */
177 if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER, addr))
180 * Write the data to the LBCIF Data Register (the I2C write
183 if (pci_write_config_byte(pdev, LBCIF_DATA_REGISTER, data))
186 * Monitor bit 1:0 of the LBCIF Status Register. When bits
187 * 1:0 are both equal to 1, the I2C write has completed and the
188 * internal write cycle of the EEPROM is about to start.
189 * (bits 1:0 = 01 is a legal state while waiting from both
190 * equal to 1, but bits 1:0 = 10 is invalid and implies that
191 * something is broken).
193 err = eeprom_wait_ready(pdev, &status);
198 * Check bit 3 of the LBCIF Status Register. If equal to 1,
199 * an error has occurred.Don't break here if we are revision
200 * 1, this is so we do a blind write for load bug.
202 if ((status & LBCIF_STATUS_GENERAL_ERROR)
203 && adapter->pdev->revision == 0)
207 * Check bit 2 of the LBCIF Status Register. If equal to 1 an
208 * ACK error has occurred on the address phase of the write.
209 * This could be due to an actual hardware failure or the
210 * EEPROM may still be in its internal write cycle from a
211 * previous write. This write operation was ignored and must be
214 if (status & LBCIF_STATUS_ACK_ERROR) {
216 * This could be due to an actual hardware failure
217 * or the EEPROM may still be in its internal write
218 * cycle from a previous write. This write operation
219 * was ignored and must be repeated later.
230 * Set bit 6 of the LBCIF Control Register = 0.
235 if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
236 LBCIF_CONTROL_LBCIF_ENABLE))
239 /* Do read until internal ACK_ERROR goes away meaning write
243 pci_write_config_dword(pdev,
244 LBCIF_ADDRESS_REGISTER,
247 pci_read_config_dword(pdev,
248 LBCIF_DATA_REGISTER, &val);
249 } while ((val & 0x00010000) == 0);
250 } while (val & 0x00040000);
252 if ((val & 0xFF00) != 0xC000 || index == 10000)
256 return writeok ? 0 : -EIO;
260 * eeprom_read - Read a byte from the ET1310's EEPROM
261 * @adapter: pointer to our private adapter structure
262 * @addr: the address from which to read
263 * @pdata: a pointer to a byte in which to store the value of the read
264 * @eeprom_id: the ID of the EEPROM
265 * @addrmode: how the EEPROM is to be accessed
267 * Returns 1 for a successful read
269 static int eeprom_read(struct et131x_adapter *adapter, u32 addr, u8 *pdata)
271 struct pci_dev *pdev = adapter->pdev;
276 * A single byte read is similar to the single byte write, with the
277 * exception of the data flow:
280 err = eeprom_wait_ready(pdev, NULL);
284 * Write to the LBCIF Control Register: bit 7=1, bit 6=0, bit 3=0,
285 * and bits 1:0 both =0. Bit 5 should be set according to the type
286 * of EEPROM being accessed (1=two byte addressing, 0=one byte
289 if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
290 LBCIF_CONTROL_LBCIF_ENABLE))
293 * Write the address to the LBCIF Address Register (I2C read will
296 if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER, addr))
299 * Monitor bit 0 of the LBCIF Status Register. When = 1, I2C read
300 * is complete. (if bit 1 =1 and bit 0 stays = 0, a hardware failure
303 err = eeprom_wait_ready(pdev, &status);
307 * Regardless of error status, read data byte from LBCIF Data
312 * Check bit 2 of the LBCIF Status Register. If = 1,
313 * then an error has occurred.
315 return (status & LBCIF_STATUS_ACK_ERROR) ? -EIO : 0;
318 int et131x_init_eeprom(struct et131x_adapter *adapter)
320 struct pci_dev *pdev = adapter->pdev;
323 /* We first need to check the EEPROM Status code located at offset
324 * 0xB2 of config space
326 pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS,
329 /* THIS IS A WORKAROUND:
330 * I need to call this function twice to get my card in a
331 * LG M1 Express Dual running. I tried also a msleep before this
332 * function, because I thougth there could be some time condidions
333 * but it didn't work. Call the whole function twice also work.
335 if (pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS, &eestatus)) {
337 "Could not read PCI config space for EEPROM Status\n");
341 /* Determine if the error(s) we care about are present. If they are
342 * present we need to fail.
344 if (eestatus & 0x4C) {
345 int write_failed = 0;
346 if (pdev->revision == 0x01) {
348 static const u8 eedata[4] = { 0xFE, 0x13, 0x10, 0xFF };
350 /* Re-write the first 4 bytes if we have an eeprom
351 * present and the revision id is 1, this fixes the
352 * corruption seen with 1310 B Silicon
354 for (i = 0; i < 3; i++)
355 if (eeprom_write(adapter, i, eedata[i]) < 0)
358 if (pdev->revision != 0x01 || write_failed) {
360 "Fatal EEPROM Status Error - 0x%04x\n", eestatus);
362 /* This error could mean that there was an error
363 * reading the eeprom or that the eeprom doesn't exist.
364 * We will treat each case the same and not try to
365 * gather additional information that normally would
366 * come from the eeprom, like MAC Address
368 adapter->has_eeprom = 0;
372 adapter->has_eeprom = 1;
374 /* Read the EEPROM for information regarding LED behavior. Refer to
375 * ET1310_phy.c, et131x_xcvr_init(), for its use.
377 eeprom_read(adapter, 0x70, &adapter->eeprom_data[0]);
378 eeprom_read(adapter, 0x71, &adapter->eeprom_data[1]);
380 if (adapter->eeprom_data[0] != 0xcd)
381 /* Disable all optional features */
382 adapter->eeprom_data[1] = 0x00;
390 * et1310_config_mac_regs1 - Initialize the first part of MAC regs
391 * @adapter: pointer to our adapter structure
393 void et1310_config_mac_regs1(struct et131x_adapter *adapter)
395 struct mac_regs __iomem *macregs = &adapter->regs->mac;
400 /* First we need to reset everything. Write to MAC configuration
401 * register 1 to perform reset.
403 writel(0xC00F0000, ¯egs->cfg1);
405 /* Next lets configure the MAC Inter-packet gap register */
406 ipg = 0x38005860; /* IPG1 0x38 IPG2 0x58 B2B 0x60 */
407 ipg |= 0x50 << 8; /* ifg enforce 0x50 */
408 writel(ipg, ¯egs->ipg);
410 /* Next lets configure the MAC Half Duplex register */
411 /* BEB trunc 0xA, Ex Defer, Rexmit 0xF Coll 0x37 */
412 writel(0x00A1F037, ¯egs->hfdp);
414 /* Next lets configure the MAC Interface Control register */
415 writel(0, ¯egs->if_ctrl);
417 /* Let's move on to setting up the mii management configuration */
418 writel(0x07, ¯egs->mii_mgmt_cfg); /* Clock reset 0x7 */
420 /* Next lets configure the MAC Station Address register. These
421 * values are read from the EEPROM during initialization and stored
422 * in the adapter structure. We write what is stored in the adapter
423 * structure to the MAC Station Address registers high and low. This
424 * station address is used for generating and checking pause control
427 station2 = (adapter->addr[1] << ET_MAC_STATION_ADDR2_OC2_SHIFT) |
428 (adapter->addr[0] << ET_MAC_STATION_ADDR2_OC1_SHIFT);
429 station1 = (adapter->addr[5] << ET_MAC_STATION_ADDR1_OC6_SHIFT) |
430 (adapter->addr[4] << ET_MAC_STATION_ADDR1_OC5_SHIFT) |
431 (adapter->addr[3] << ET_MAC_STATION_ADDR1_OC4_SHIFT) |
433 writel(station1, ¯egs->station_addr_1);
434 writel(station2, ¯egs->station_addr_2);
436 /* Max ethernet packet in bytes that will passed by the mac without
437 * being truncated. Allow the MAC to pass 4 more than our max packet
438 * size. This is 4 for the Ethernet CRC.
440 * Packets larger than (registry_jumbo_packet) that do not contain a
441 * VLAN ID will be dropped by the Rx function.
443 writel(adapter->registry_jumbo_packet + 4, ¯egs->max_fm_len);
445 /* clear out MAC config reset */
446 writel(0, ¯egs->cfg1);
450 * et1310_config_mac_regs2 - Initialize the second part of MAC regs
451 * @adapter: pointer to our adapter structure
453 void et1310_config_mac_regs2(struct et131x_adapter *adapter)
456 struct mac_regs __iomem *mac = &adapter->regs->mac;
457 struct phy_device *phydev = adapter->phydev;
463 ctl = readl(&adapter->regs->txmac.ctl);
464 cfg1 = readl(&mac->cfg1);
465 cfg2 = readl(&mac->cfg2);
466 ifctrl = readl(&mac->if_ctrl);
468 /* Set up the if mode bits */
470 if (phydev && phydev->speed == SPEED_1000) {
473 ifctrl &= ~(1 << 24);
479 /* We need to enable Rx/Tx */
480 cfg1 |= CFG1_RX_ENABLE | CFG1_TX_ENABLE | CFG1_TX_FLOW;
481 /* Initialize loop back to off */
482 cfg1 &= ~(CFG1_LOOPBACK | CFG1_RX_FLOW);
483 if (adapter->flowcontrol == FLOW_RXONLY ||
484 adapter->flowcontrol == FLOW_BOTH)
485 cfg1 |= CFG1_RX_FLOW;
486 writel(cfg1, &mac->cfg1);
488 /* Now we need to initialize the MAC Configuration 2 register */
489 /* preamble 7, check length, huge frame off, pad crc, crc enable
494 /* Turn on duplex if needed */
495 if (phydev && phydev->duplex == DUPLEX_FULL)
498 ifctrl &= ~(1 << 26);
499 if (phydev && phydev->duplex == DUPLEX_HALF)
500 ifctrl |= (1<<26); /* Enable ghd */
502 writel(ifctrl, &mac->if_ctrl);
503 writel(cfg2, &mac->cfg2);
508 cfg1 = readl(&mac->cfg1);
509 } while ((cfg1 & CFG1_WAIT) != CFG1_WAIT && delay < 100);
512 dev_warn(&adapter->pdev->dev,
513 "Syncd bits did not respond correctly cfg1 word 0x%08x\n",
518 ctl |= 0x09; /* TX mac enable, FC disable */
519 writel(ctl, &adapter->regs->txmac.ctl);
521 /* Ready to start the RXDMA/TXDMA engine */
522 if (adapter->flags & fMP_ADAPTER_LOWER_POWER) {
523 et131x_rx_dma_enable(adapter);
524 et131x_tx_dma_enable(adapter);
528 void et1310_config_rxmac_regs(struct et131x_adapter *adapter)
530 struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac;
531 struct phy_device *phydev = adapter->phydev;
536 /* Disable the MAC while it is being configured (also disable WOL) */
537 writel(0x8, &rxmac->ctrl);
539 /* Initialize WOL to disabled. */
540 writel(0, &rxmac->crc0);
541 writel(0, &rxmac->crc12);
542 writel(0, &rxmac->crc34);
544 /* We need to set the WOL mask0 - mask4 next. We initialize it to
545 * its default Values of 0x00000000 because there are not WOL masks
548 writel(0, &rxmac->mask0_word0);
549 writel(0, &rxmac->mask0_word1);
550 writel(0, &rxmac->mask0_word2);
551 writel(0, &rxmac->mask0_word3);
553 writel(0, &rxmac->mask1_word0);
554 writel(0, &rxmac->mask1_word1);
555 writel(0, &rxmac->mask1_word2);
556 writel(0, &rxmac->mask1_word3);
558 writel(0, &rxmac->mask2_word0);
559 writel(0, &rxmac->mask2_word1);
560 writel(0, &rxmac->mask2_word2);
561 writel(0, &rxmac->mask2_word3);
563 writel(0, &rxmac->mask3_word0);
564 writel(0, &rxmac->mask3_word1);
565 writel(0, &rxmac->mask3_word2);
566 writel(0, &rxmac->mask3_word3);
568 writel(0, &rxmac->mask4_word0);
569 writel(0, &rxmac->mask4_word1);
570 writel(0, &rxmac->mask4_word2);
571 writel(0, &rxmac->mask4_word3);
573 /* Lets setup the WOL Source Address */
574 sa_lo = (adapter->addr[2] << ET_WOL_LO_SA3_SHIFT) |
575 (adapter->addr[3] << ET_WOL_LO_SA4_SHIFT) |
576 (adapter->addr[4] << ET_WOL_LO_SA5_SHIFT) |
578 writel(sa_lo, &rxmac->sa_lo);
580 sa_hi = (u32) (adapter->addr[0] << ET_WOL_HI_SA1_SHIFT) |
582 writel(sa_hi, &rxmac->sa_hi);
584 /* Disable all Packet Filtering */
585 writel(0, &rxmac->pf_ctrl);
587 /* Let's initialize the Unicast Packet filtering address */
588 if (adapter->packet_filter & ET131X_PACKET_TYPE_DIRECTED) {
589 et1310_setup_device_for_unicast(adapter);
590 pf_ctrl |= 4; /* Unicast filter */
592 writel(0, &rxmac->uni_pf_addr1);
593 writel(0, &rxmac->uni_pf_addr2);
594 writel(0, &rxmac->uni_pf_addr3);
597 /* Let's initialize the Multicast hash */
598 if (!(adapter->packet_filter & ET131X_PACKET_TYPE_ALL_MULTICAST)) {
599 pf_ctrl |= 2; /* Multicast filter */
600 et1310_setup_device_for_multicast(adapter);
603 /* Runt packet filtering. Didn't work in version A silicon. */
604 pf_ctrl |= (NIC_MIN_PACKET_SIZE + 4) << 16;
605 pf_ctrl |= 8; /* Fragment filter */
607 if (adapter->registry_jumbo_packet > 8192)
608 /* In order to transmit jumbo packets greater than 8k, the
609 * FIFO between RxMAC and RxDMA needs to be reduced in size
610 * to (16k - Jumbo packet size). In order to implement this,
611 * we must use "cut through" mode in the RxMAC, which chops
612 * packets down into segments which are (max_size * 16). In
613 * this case we selected 256 bytes, since this is the size of
614 * the PCI-Express TLP's that the 1310 uses.
616 * seg_en on, fc_en off, size 0x10
618 writel(0x41, &rxmac->mcif_ctrl_max_seg);
620 writel(0, &rxmac->mcif_ctrl_max_seg);
622 /* Initialize the MCIF water marks */
623 writel(0, &rxmac->mcif_water_mark);
625 /* Initialize the MIF control */
626 writel(0, &rxmac->mif_ctrl);
628 /* Initialize the Space Available Register */
629 writel(0, &rxmac->space_avail);
631 /* Initialize the the mif_ctrl register
632 * bit 3: Receive code error. One or more nibbles were signaled as
633 * errors during the reception of the packet. Clear this
634 * bit in Gigabit, set it in 100Mbit. This was derived
635 * experimentally at UNH.
636 * bit 4: Receive CRC error. The packet's CRC did not match the
637 * internally generated CRC.
638 * bit 5: Receive length check error. Indicates that frame length
639 * field value in the packet does not match the actual data
640 * byte length and is not a type field.
641 * bit 16: Receive frame truncated.
642 * bit 17: Drop packet enable
644 if (phydev && phydev->speed == SPEED_100)
645 writel(0x30038, &rxmac->mif_ctrl);
647 writel(0x30030, &rxmac->mif_ctrl);
649 /* Finally we initialize RxMac to be enabled & WOL disabled. Packet
650 * filter is always enabled since it is where the runt packets are
651 * supposed to be dropped. For version A silicon, runt packet
652 * dropping doesn't work, so it is disabled in the pf_ctrl register,
653 * but we still leave the packet filter on.
655 writel(pf_ctrl, &rxmac->pf_ctrl);
656 writel(0x9, &rxmac->ctrl);
659 void et1310_config_txmac_regs(struct et131x_adapter *adapter)
661 struct txmac_regs __iomem *txmac = &adapter->regs->txmac;
663 /* We need to update the Control Frame Parameters
664 * cfpt - control frame pause timer set to 64 (0x40)
665 * cfep - control frame extended pause timer set to 0x0
667 if (adapter->flowcontrol == FLOW_NONE)
668 writel(0, &txmac->cf_param);
670 writel(0x40, &txmac->cf_param);
673 void et1310_config_macstat_regs(struct et131x_adapter *adapter)
675 struct macstat_regs __iomem *macstat =
676 &adapter->regs->macstat;
678 /* Next we need to initialize all the macstat registers to zero on
681 writel(0, &macstat->txrx_0_64_byte_frames);
682 writel(0, &macstat->txrx_65_127_byte_frames);
683 writel(0, &macstat->txrx_128_255_byte_frames);
684 writel(0, &macstat->txrx_256_511_byte_frames);
685 writel(0, &macstat->txrx_512_1023_byte_frames);
686 writel(0, &macstat->txrx_1024_1518_byte_frames);
687 writel(0, &macstat->txrx_1519_1522_gvln_frames);
689 writel(0, &macstat->rx_bytes);
690 writel(0, &macstat->rx_packets);
691 writel(0, &macstat->rx_fcs_errs);
692 writel(0, &macstat->rx_multicast_packets);
693 writel(0, &macstat->rx_broadcast_packets);
694 writel(0, &macstat->rx_control_frames);
695 writel(0, &macstat->rx_pause_frames);
696 writel(0, &macstat->rx_unknown_opcodes);
697 writel(0, &macstat->rx_align_errs);
698 writel(0, &macstat->rx_frame_len_errs);
699 writel(0, &macstat->rx_code_errs);
700 writel(0, &macstat->rx_carrier_sense_errs);
701 writel(0, &macstat->rx_undersize_packets);
702 writel(0, &macstat->rx_oversize_packets);
703 writel(0, &macstat->rx_fragment_packets);
704 writel(0, &macstat->rx_jabbers);
705 writel(0, &macstat->rx_drops);
707 writel(0, &macstat->tx_bytes);
708 writel(0, &macstat->tx_packets);
709 writel(0, &macstat->tx_multicast_packets);
710 writel(0, &macstat->tx_broadcast_packets);
711 writel(0, &macstat->tx_pause_frames);
712 writel(0, &macstat->tx_deferred);
713 writel(0, &macstat->tx_excessive_deferred);
714 writel(0, &macstat->tx_single_collisions);
715 writel(0, &macstat->tx_multiple_collisions);
716 writel(0, &macstat->tx_late_collisions);
717 writel(0, &macstat->tx_excessive_collisions);
718 writel(0, &macstat->tx_total_collisions);
719 writel(0, &macstat->tx_pause_honored_frames);
720 writel(0, &macstat->tx_drops);
721 writel(0, &macstat->tx_jabbers);
722 writel(0, &macstat->tx_fcs_errs);
723 writel(0, &macstat->tx_control_frames);
724 writel(0, &macstat->tx_oversize_frames);
725 writel(0, &macstat->tx_undersize_frames);
726 writel(0, &macstat->tx_fragments);
727 writel(0, &macstat->carry_reg1);
728 writel(0, &macstat->carry_reg2);
730 /* Unmask any counters that we want to track the overflow of.
731 * Initially this will be all counters. It may become clear later
732 * that we do not need to track all counters.
734 writel(0xFFFFBE32, &macstat->carry_reg1_mask);
735 writel(0xFFFE7E8B, &macstat->carry_reg2_mask);
738 void et1310_config_flow_control(struct et131x_adapter *adapter)
740 struct phy_device *phydev = adapter->phydev;
742 if (phydev->duplex == DUPLEX_HALF) {
743 adapter->flowcontrol = FLOW_NONE;
745 char remote_pause, remote_async_pause;
747 et1310_phy_access_mii_bit(adapter,
748 TRUEPHY_BIT_READ, 5, 10, &remote_pause);
749 et1310_phy_access_mii_bit(adapter,
750 TRUEPHY_BIT_READ, 5, 11,
751 &remote_async_pause);
753 if ((remote_pause == TRUEPHY_BIT_SET) &&
754 (remote_async_pause == TRUEPHY_BIT_SET)) {
755 adapter->flowcontrol = adapter->wanted_flow;
756 } else if ((remote_pause == TRUEPHY_BIT_SET) &&
757 (remote_async_pause == TRUEPHY_BIT_CLEAR)) {
758 if (adapter->wanted_flow == FLOW_BOTH)
759 adapter->flowcontrol = FLOW_BOTH;
761 adapter->flowcontrol = FLOW_NONE;
762 } else if ((remote_pause == TRUEPHY_BIT_CLEAR) &&
763 (remote_async_pause == TRUEPHY_BIT_CLEAR)) {
764 adapter->flowcontrol = FLOW_NONE;
765 } else {/* if (remote_pause == TRUEPHY_CLEAR_BIT &&
766 remote_async_pause == TRUEPHY_SET_BIT) */
767 if (adapter->wanted_flow == FLOW_BOTH)
768 adapter->flowcontrol = FLOW_RXONLY;
770 adapter->flowcontrol = FLOW_NONE;
776 * et1310_update_macstat_host_counters - Update the local copy of the statistics
777 * @adapter: pointer to the adapter structure
779 void et1310_update_macstat_host_counters(struct et131x_adapter *adapter)
781 struct ce_stats *stats = &adapter->stats;
782 struct macstat_regs __iomem *macstat =
783 &adapter->regs->macstat;
785 stats->tx_collisions += readl(&macstat->tx_total_collisions);
786 stats->tx_first_collisions += readl(&macstat->tx_single_collisions);
787 stats->tx_deferred += readl(&macstat->tx_deferred);
788 stats->tx_excessive_collisions +=
789 readl(&macstat->tx_multiple_collisions);
790 stats->tx_late_collisions += readl(&macstat->tx_late_collisions);
791 stats->tx_underflows += readl(&macstat->tx_undersize_frames);
792 stats->tx_max_pkt_errs += readl(&macstat->tx_oversize_frames);
794 stats->rx_align_errs += readl(&macstat->rx_align_errs);
795 stats->rx_crc_errs += readl(&macstat->rx_code_errs);
796 stats->rcvd_pkts_dropped += readl(&macstat->rx_drops);
797 stats->rx_overflows += readl(&macstat->rx_oversize_packets);
798 stats->rx_code_violations += readl(&macstat->rx_fcs_errs);
799 stats->rx_length_errs += readl(&macstat->rx_frame_len_errs);
800 stats->rx_other_errs += readl(&macstat->rx_fragment_packets);
804 * et1310_handle_macstat_interrupt
805 * @adapter: pointer to the adapter structure
807 * One of the MACSTAT counters has wrapped. Update the local copy of
808 * the statistics held in the adapter structure, checking the "wrap"
809 * bit for each counter.
811 void et1310_handle_macstat_interrupt(struct et131x_adapter *adapter)
816 /* Read the interrupt bits from the register(s). These are Clear On
819 carry_reg1 = readl(&adapter->regs->macstat.carry_reg1);
820 carry_reg2 = readl(&adapter->regs->macstat.carry_reg2);
822 writel(carry_reg1, &adapter->regs->macstat.carry_reg1);
823 writel(carry_reg2, &adapter->regs->macstat.carry_reg2);
825 /* We need to do update the host copy of all the MAC_STAT counters.
826 * For each counter, check it's overflow bit. If the overflow bit is
827 * set, then increment the host version of the count by one complete
828 * revolution of the counter. This routine is called when the counter
829 * block indicates that one of the counters has wrapped.
831 if (carry_reg1 & (1 << 14))
832 adapter->stats.rx_code_violations += COUNTER_WRAP_16_BIT;
833 if (carry_reg1 & (1 << 8))
834 adapter->stats.rx_align_errs += COUNTER_WRAP_12_BIT;
835 if (carry_reg1 & (1 << 7))
836 adapter->stats.rx_length_errs += COUNTER_WRAP_16_BIT;
837 if (carry_reg1 & (1 << 2))
838 adapter->stats.rx_other_errs += COUNTER_WRAP_16_BIT;
839 if (carry_reg1 & (1 << 6))
840 adapter->stats.rx_crc_errs += COUNTER_WRAP_16_BIT;
841 if (carry_reg1 & (1 << 3))
842 adapter->stats.rx_overflows += COUNTER_WRAP_16_BIT;
843 if (carry_reg1 & (1 << 0))
844 adapter->stats.rcvd_pkts_dropped += COUNTER_WRAP_16_BIT;
845 if (carry_reg2 & (1 << 16))
846 adapter->stats.tx_max_pkt_errs += COUNTER_WRAP_12_BIT;
847 if (carry_reg2 & (1 << 15))
848 adapter->stats.tx_underflows += COUNTER_WRAP_12_BIT;
849 if (carry_reg2 & (1 << 6))
850 adapter->stats.tx_first_collisions += COUNTER_WRAP_12_BIT;
851 if (carry_reg2 & (1 << 8))
852 adapter->stats.tx_deferred += COUNTER_WRAP_12_BIT;
853 if (carry_reg2 & (1 << 5))
854 adapter->stats.tx_excessive_collisions += COUNTER_WRAP_12_BIT;
855 if (carry_reg2 & (1 << 4))
856 adapter->stats.tx_late_collisions += COUNTER_WRAP_12_BIT;
857 if (carry_reg2 & (1 << 2))
858 adapter->stats.tx_collisions += COUNTER_WRAP_12_BIT;
861 void et1310_setup_device_for_multicast(struct et131x_adapter *adapter)
863 struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac;
872 /* If ET131X_PACKET_TYPE_MULTICAST is specified, then we provision
873 * the multi-cast LIST. If it is NOT specified, (and "ALL" is not
874 * specified) then we should pass NO multi-cast addresses to the
877 if (adapter->packet_filter & ET131X_PACKET_TYPE_MULTICAST) {
878 /* Loop through our multicast array and set up the device */
879 for (nIndex = 0; nIndex < adapter->multicast_addr_count;
881 result = ether_crc(6, adapter->multicast_list[nIndex]);
883 result = (result & 0x3F800000) >> 23;
886 hash1 |= (1 << result);
887 } else if ((31 < result) && (result < 64)) {
889 hash2 |= (1 << result);
890 } else if ((63 < result) && (result < 96)) {
892 hash3 |= (1 << result);
895 hash4 |= (1 << result);
900 /* Write out the new hash to the device */
901 pm_csr = readl(&adapter->regs->global.pm_csr);
902 if (!et1310_in_phy_coma(adapter)) {
903 writel(hash1, &rxmac->multi_hash1);
904 writel(hash2, &rxmac->multi_hash2);
905 writel(hash3, &rxmac->multi_hash3);
906 writel(hash4, &rxmac->multi_hash4);
910 void et1310_setup_device_for_unicast(struct et131x_adapter *adapter)
912 struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac;
918 /* Set up unicast packet filter reg 3 to be the first two octets of
919 * the MAC address for both address
921 * Set up unicast packet filter reg 2 to be the octets 2 - 5 of the
922 * MAC address for second address
924 * Set up unicast packet filter reg 3 to be the octets 2 - 5 of the
925 * MAC address for first address
927 uni_pf3 = (adapter->addr[0] << ET_UNI_PF_ADDR2_1_SHIFT) |
928 (adapter->addr[1] << ET_UNI_PF_ADDR2_2_SHIFT) |
929 (adapter->addr[0] << ET_UNI_PF_ADDR1_1_SHIFT) |
932 uni_pf2 = (adapter->addr[2] << ET_UNI_PF_ADDR2_3_SHIFT) |
933 (adapter->addr[3] << ET_UNI_PF_ADDR2_4_SHIFT) |
934 (adapter->addr[4] << ET_UNI_PF_ADDR2_5_SHIFT) |
937 uni_pf1 = (adapter->addr[2] << ET_UNI_PF_ADDR1_3_SHIFT) |
938 (adapter->addr[3] << ET_UNI_PF_ADDR1_4_SHIFT) |
939 (adapter->addr[4] << ET_UNI_PF_ADDR1_5_SHIFT) |
942 pm_csr = readl(&adapter->regs->global.pm_csr);
943 if (!et1310_in_phy_coma(adapter)) {
944 writel(uni_pf1, &rxmac->uni_pf_addr1);
945 writel(uni_pf2, &rxmac->uni_pf_addr2);
946 writel(uni_pf3, &rxmac->uni_pf_addr3);
952 int et131x_mdio_read(struct mii_bus *bus, int phy_addr, int reg)
954 struct net_device *netdev = bus->priv;
955 struct et131x_adapter *adapter = netdev_priv(netdev);
959 ret = et131x_phy_mii_read(adapter, phy_addr, reg, &value);
967 int et131x_mdio_write(struct mii_bus *bus, int phy_addr, int reg, u16 value)
969 struct net_device *netdev = bus->priv;
970 struct et131x_adapter *adapter = netdev_priv(netdev);
972 return et131x_mii_write(adapter, reg, value);
975 int et131x_mdio_reset(struct mii_bus *bus)
977 struct net_device *netdev = bus->priv;
978 struct et131x_adapter *adapter = netdev_priv(netdev);
980 et131x_mii_write(adapter, MII_BMCR, BMCR_RESET);
985 int et131x_mii_read(struct et131x_adapter *adapter, u8 reg, u16 *value)
987 struct phy_device *phydev = adapter->phydev;
992 return et131x_phy_mii_read(adapter, phydev->addr, reg, value);
996 * et131x_phy_mii_read - Read from the PHY through the MII Interface on the MAC
997 * @adapter: pointer to our private adapter structure
998 * @addr: the address of the transceiver
999 * @reg: the register to read
1000 * @value: pointer to a 16-bit value in which the value will be stored
1002 * Returns 0 on success, errno on failure (as defined in errno.h)
1004 int et131x_phy_mii_read(struct et131x_adapter *adapter, u8 addr,
1007 struct mac_regs __iomem *mac = &adapter->regs->mac;
1014 /* Save a local copy of the registers we are dealing with so we can
1017 mii_addr = readl(&mac->mii_mgmt_addr);
1018 mii_cmd = readl(&mac->mii_mgmt_cmd);
1020 /* Stop the current operation */
1021 writel(0, &mac->mii_mgmt_cmd);
1023 /* Set up the register we need to read from on the correct PHY */
1024 writel(MII_ADDR(addr, reg), &mac->mii_mgmt_addr);
1026 writel(0x1, &mac->mii_mgmt_cmd);
1031 mii_indicator = readl(&mac->mii_mgmt_indicator);
1032 } while ((mii_indicator & MGMT_WAIT) && delay < 50);
1034 /* If we hit the max delay, we could not read the register */
1036 dev_warn(&adapter->pdev->dev,
1037 "reg 0x%08x could not be read\n", reg);
1038 dev_warn(&adapter->pdev->dev, "status is 0x%08x\n",
1044 /* If we hit here we were able to read the register and we need to
1045 * return the value to the caller */
1046 *value = readl(&mac->mii_mgmt_stat) & 0xFFFF;
1048 /* Stop the read operation */
1049 writel(0, &mac->mii_mgmt_cmd);
1051 /* set the registers we touched back to the state at which we entered
1054 writel(mii_addr, &mac->mii_mgmt_addr);
1055 writel(mii_cmd, &mac->mii_mgmt_cmd);
1061 * et131x_mii_write - Write to a PHY register through the MII interface of the MAC
1062 * @adapter: pointer to our private adapter structure
1063 * @reg: the register to read
1064 * @value: 16-bit value to write
1066 * FIXME: one caller in netdev still
1068 * Return 0 on success, errno on failure (as defined in errno.h)
1070 int et131x_mii_write(struct et131x_adapter *adapter, u8 reg, u16 value)
1072 struct mac_regs __iomem *mac = &adapter->regs->mac;
1073 struct phy_device *phydev = adapter->phydev;
1084 addr = phydev->addr;
1086 /* Save a local copy of the registers we are dealing with so we can
1089 mii_addr = readl(&mac->mii_mgmt_addr);
1090 mii_cmd = readl(&mac->mii_mgmt_cmd);
1092 /* Stop the current operation */
1093 writel(0, &mac->mii_mgmt_cmd);
1095 /* Set up the register we need to write to on the correct PHY */
1096 writel(MII_ADDR(addr, reg), &mac->mii_mgmt_addr);
1098 /* Add the value to write to the registers to the mac */
1099 writel(value, &mac->mii_mgmt_ctrl);
1104 mii_indicator = readl(&mac->mii_mgmt_indicator);
1105 } while ((mii_indicator & MGMT_BUSY) && delay < 100);
1107 /* If we hit the max delay, we could not write the register */
1111 dev_warn(&adapter->pdev->dev,
1112 "reg 0x%08x could not be written", reg);
1113 dev_warn(&adapter->pdev->dev, "status is 0x%08x\n",
1115 dev_warn(&adapter->pdev->dev, "command is 0x%08x\n",
1116 readl(&mac->mii_mgmt_cmd));
1118 et131x_mii_read(adapter, reg, &tmp);
1122 /* Stop the write operation */
1123 writel(0, &mac->mii_mgmt_cmd);
1126 * set the registers we touched back to the state at which we entered
1129 writel(mii_addr, &mac->mii_mgmt_addr);
1130 writel(mii_cmd, &mac->mii_mgmt_cmd);
1136 * et1310_phy_power_down - PHY power control
1137 * @adapter: device to control
1138 * @down: true for off/false for back on
1140 * one hundred, ten, one thousand megs
1141 * How would you like to have your LAN accessed
1142 * Can't you see that this code processed
1143 * Phy power, phy power..
1145 void et1310_phy_power_down(struct et131x_adapter *adapter, bool down)
1149 et131x_mii_read(adapter, MII_BMCR, &data);
1150 data &= ~BMCR_PDOWN;
1153 et131x_mii_write(adapter, MII_BMCR, data);
1156 /* Still used from _mac for BIT_READ */
1157 void et1310_phy_access_mii_bit(struct et131x_adapter *adapter, u16 action,
1158 u16 regnum, u16 bitnum, u8 *value)
1161 u16 mask = 0x0001 << bitnum;
1163 /* Read the requested register */
1164 et131x_mii_read(adapter, regnum, ®);
1167 case TRUEPHY_BIT_READ:
1168 *value = (reg & mask) >> bitnum;
1171 case TRUEPHY_BIT_SET:
1172 et131x_mii_write(adapter, regnum, reg | mask);
1175 case TRUEPHY_BIT_CLEAR:
1176 et131x_mii_write(adapter, regnum, reg & ~mask);
1185 * et131x_xcvr_init - Init the phy if we are setting it into force mode
1186 * @adapter: pointer to our private adapter structure
1189 void et131x_xcvr_init(struct et131x_adapter *adapter)
1195 et131x_mii_read(adapter, PHY_INTERRUPT_STATUS, &isr);
1196 et131x_mii_read(adapter, PHY_INTERRUPT_MASK, &imr);
1198 /* Set the link status interrupt only. Bad behavior when link status
1199 * and auto neg are set, we run into a nested interrupt problem
1201 imr |= (ET_PHY_INT_MASK_AUTONEGSTAT &
1202 ET_PHY_INT_MASK_LINKSTAT &
1203 ET_PHY_INT_MASK_ENABLE);
1205 et131x_mii_write(adapter, PHY_INTERRUPT_MASK, imr);
1207 /* Set the LED behavior such that LED 1 indicates speed (off =
1208 * 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates
1209 * link and activity (on for link, blink off for activity).
1211 * NOTE: Some customizations have been added here for specific
1212 * vendors; The LED behavior is now determined by vendor data in the
1213 * EEPROM. However, the above description is the default.
1215 if ((adapter->eeprom_data[1] & 0x4) == 0) {
1216 et131x_mii_read(adapter, PHY_LED_2, &lcr2);
1218 lcr2 &= (ET_LED2_LED_100TX & ET_LED2_LED_1000T);
1219 lcr2 |= (LED_VAL_LINKON_ACTIVE << LED_LINK_SHIFT);
1221 if ((adapter->eeprom_data[1] & 0x8) == 0)
1222 lcr2 |= (LED_VAL_1000BT_100BTX << LED_TXRX_SHIFT);
1224 lcr2 |= (LED_VAL_LINKON << LED_TXRX_SHIFT);
1226 et131x_mii_write(adapter, PHY_LED_2, lcr2);
1233 * et1310_in_phy_coma - check if the device is in phy coma
1234 * @adapter: pointer to our adapter structure
1236 * Returns 0 if the device is not in phy coma, 1 if it is in phy coma
1238 int et1310_in_phy_coma(struct et131x_adapter *adapter)
1242 pmcsr = readl(&adapter->regs->global.pm_csr);
1244 return ET_PM_PHY_SW_COMA & pmcsr ? 1 : 0;
1248 * et1310_enable_phy_coma - called when network cable is unplugged
1249 * @adapter: pointer to our adapter structure
1251 * driver receive an phy status change interrupt while in D0 and check that
1252 * phy_status is down.
1254 * -- gate off JAGCore;
1255 * -- set gigE PHY in Coma mode
1256 * -- wake on phy_interrupt; Perform software reset JAGCore,
1257 * re-initialize jagcore and gigE PHY
1259 * Add D0-ASPM-PhyLinkDown Support:
1260 * -- while in D0, when there is a phy_interrupt indicating phy link
1261 * down status, call the MPSetPhyComa routine to enter this active
1262 * state power saving mode
1263 * -- while in D0-ASPM-PhyLinkDown mode, when there is a phy_interrupt
1264 * indicating linkup status, call the MPDisablePhyComa routine to
1265 * restore JAGCore and gigE PHY
1267 void et1310_enable_phy_coma(struct et131x_adapter *adapter)
1269 unsigned long flags;
1272 pmcsr = readl(&adapter->regs->global.pm_csr);
1274 /* Save the GbE PHY speed and duplex modes. Need to restore this
1275 * when cable is plugged back in
1278 * TODO - when PM is re-enabled, check if we need to
1279 * perform a similar task as this -
1280 * adapter->pdown_speed = adapter->ai_force_speed;
1281 * adapter->pdown_duplex = adapter->ai_force_duplex;
1284 /* Stop sending packets. */
1285 spin_lock_irqsave(&adapter->send_hw_lock, flags);
1286 adapter->flags |= fMP_ADAPTER_LOWER_POWER;
1287 spin_unlock_irqrestore(&adapter->send_hw_lock, flags);
1289 /* Wait for outstanding Receive packets */
1291 et131x_disable_txrx(adapter->netdev);
1293 /* Gate off JAGCore 3 clock domains */
1294 pmcsr &= ~ET_PMCSR_INIT;
1295 writel(pmcsr, &adapter->regs->global.pm_csr);
1297 /* Program gigE PHY in to Coma mode */
1298 pmcsr |= ET_PM_PHY_SW_COMA;
1299 writel(pmcsr, &adapter->regs->global.pm_csr);
1303 * et1310_disable_phy_coma - Disable the Phy Coma Mode
1304 * @adapter: pointer to our adapter structure
1306 void et1310_disable_phy_coma(struct et131x_adapter *adapter)
1310 pmcsr = readl(&adapter->regs->global.pm_csr);
1312 /* Disable phy_sw_coma register and re-enable JAGCore clocks */
1313 pmcsr |= ET_PMCSR_INIT;
1314 pmcsr &= ~ET_PM_PHY_SW_COMA;
1315 writel(pmcsr, &adapter->regs->global.pm_csr);
1317 /* Restore the GbE PHY speed and duplex modes;
1318 * Reset JAGCore; re-configure and initialize JAGCore and gigE PHY
1320 /* TODO - when PM is re-enabled, check if we need to
1321 * perform a similar task as this -
1322 * adapter->ai_force_speed = adapter->pdown_speed;
1323 * adapter->ai_force_duplex = adapter->pdown_duplex;
1326 /* Re-initialize the send structures */
1327 et131x_init_send(adapter);
1329 /* Reset the RFD list and re-start RU */
1330 et131x_reset_recv(adapter);
1332 /* Bring the device back to the state it was during init prior to
1333 * autonegotiation being complete. This way, when we get the auto-neg
1334 * complete interrupt, we can complete init by calling ConfigMacREGS2.
1336 et131x_soft_reset(adapter);
1338 /* setup et1310 as per the documentation ?? */
1339 et131x_adapter_setup(adapter);
1341 /* Allow Tx to restart */
1342 adapter->flags &= ~fMP_ADAPTER_LOWER_POWER;
1344 et131x_enable_txrx(adapter->netdev);
1349 static inline u32 bump_free_buff_ring(u32 *free_buff_ring, u32 limit)
1351 u32 tmp_free_buff_ring = *free_buff_ring;
1352 tmp_free_buff_ring++;
1353 /* This works for all cases where limit < 1024. The 1023 case
1354 works because 1023++ is 1024 which means the if condition is not
1355 taken but the carry of the bit into the wrap bit toggles the wrap
1357 if ((tmp_free_buff_ring & ET_DMA10_MASK) > limit) {
1358 tmp_free_buff_ring &= ~ET_DMA10_MASK;
1359 tmp_free_buff_ring ^= ET_DMA10_WRAP;
1361 /* For the 1023 case */
1362 tmp_free_buff_ring &= (ET_DMA10_MASK|ET_DMA10_WRAP);
1363 *free_buff_ring = tmp_free_buff_ring;
1364 return tmp_free_buff_ring;
1368 * et131x_rx_dma_memory_alloc
1369 * @adapter: pointer to our private adapter structure
1371 * Returns 0 on success and errno on failure (as defined in errno.h)
1373 * Allocates Free buffer ring 1 for sure, free buffer ring 0 if required,
1374 * and the Packet Status Ring.
1376 int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
1380 u32 pktstat_ringsize, fbr_chunksize;
1381 struct rx_ring *rx_ring;
1383 /* Setup some convenience pointers */
1384 rx_ring = &adapter->rx_ring;
1386 /* Alloc memory for the lookup table */
1388 rx_ring->fbr[0] = kmalloc(sizeof(struct fbr_lookup), GFP_KERNEL);
1390 rx_ring->fbr[1] = kmalloc(sizeof(struct fbr_lookup), GFP_KERNEL);
1392 /* The first thing we will do is configure the sizes of the buffer
1393 * rings. These will change based on jumbo packet support. Larger
1394 * jumbo packets increases the size of each entry in FBR0, and the
1395 * number of entries in FBR0, while at the same time decreasing the
1396 * number of entries in FBR1.
1398 * FBR1 holds "large" frames, FBR0 holds "small" frames. If FBR1
1399 * entries are huge in order to accommodate a "jumbo" frame, then it
1400 * will have less entries. Conversely, FBR1 will now be relied upon
1401 * to carry more "normal" frames, thus it's entry size also increases
1402 * and the number of entries goes up too (since it now carries
1403 * "small" + "regular" packets.
1405 * In this scheme, we try to maintain 512 entries between the two
1406 * rings. Also, FBR1 remains a constant size - when it's size doubles
1407 * the number of entries halves. FBR0 increases in size, however.
1410 if (adapter->registry_jumbo_packet < 2048) {
1412 rx_ring->fbr0_buffsize = 256;
1413 rx_ring->fbr0_num_entries = 512;
1415 rx_ring->fbr1_buffsize = 2048;
1416 rx_ring->fbr1_num_entries = 512;
1417 } else if (adapter->registry_jumbo_packet < 4096) {
1419 rx_ring->fbr0_buffsize = 512;
1420 rx_ring->fbr0_num_entries = 1024;
1422 rx_ring->fbr1_buffsize = 4096;
1423 rx_ring->fbr1_num_entries = 512;
1426 rx_ring->fbr0_buffsize = 1024;
1427 rx_ring->fbr0_num_entries = 768;
1429 rx_ring->fbr1_buffsize = 16384;
1430 rx_ring->fbr1_num_entries = 128;
1434 adapter->rx_ring.psr_num_entries = adapter->rx_ring.fbr0_num_entries +
1435 adapter->rx_ring.fbr1_num_entries;
1437 adapter->rx_ring.psr_num_entries = adapter->rx_ring.fbr1_num_entries;
1440 /* Allocate an area of memory for Free Buffer Ring 1 */
1441 bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr1_num_entries) + 0xfff;
1442 rx_ring->fbr1_ring_virtaddr = pci_alloc_consistent(adapter->pdev,
1444 &rx_ring->fbr1_ring_physaddr);
1445 if (!rx_ring->fbr1_ring_virtaddr) {
1446 dev_err(&adapter->pdev->dev,
1447 "Cannot alloc memory for Free Buffer Ring 1\n");
1451 /* Save physical address
1453 * NOTE: pci_alloc_consistent(), used above to alloc DMA regions,
1454 * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
1455 * are ever returned, make sure the high part is retrieved here
1456 * before storing the adjusted address.
1458 rx_ring->fbr1_real_physaddr = rx_ring->fbr1_ring_physaddr;
1460 /* Align Free Buffer Ring 1 on a 4K boundary */
1461 et131x_align_allocated_memory(adapter,
1462 &rx_ring->fbr1_real_physaddr,
1463 &rx_ring->fbr1_offset, 0x0FFF);
1465 rx_ring->fbr1_ring_virtaddr =
1466 (void *)((u8 *) rx_ring->fbr1_ring_virtaddr +
1467 rx_ring->fbr1_offset);
1470 /* Allocate an area of memory for Free Buffer Ring 0 */
1471 bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr0_num_entries) + 0xfff;
1472 rx_ring->fbr0_ring_virtaddr = pci_alloc_consistent(adapter->pdev,
1474 &rx_ring->fbr0_ring_physaddr);
1475 if (!rx_ring->fbr0_ring_virtaddr) {
1476 dev_err(&adapter->pdev->dev,
1477 "Cannot alloc memory for Free Buffer Ring 0\n");
1481 /* Save physical address
1483 * NOTE: pci_alloc_consistent(), used above to alloc DMA regions,
1484 * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
1485 * are ever returned, make sure the high part is retrieved here before
1486 * storing the adjusted address.
1488 rx_ring->fbr0_real_physaddr = rx_ring->fbr0_ring_physaddr;
1490 /* Align Free Buffer Ring 0 on a 4K boundary */
1491 et131x_align_allocated_memory(adapter,
1492 &rx_ring->fbr0_real_physaddr,
1493 &rx_ring->fbr0_offset, 0x0FFF);
1495 rx_ring->fbr0_ring_virtaddr =
1496 (void *)((u8 *) rx_ring->fbr0_ring_virtaddr +
1497 rx_ring->fbr0_offset);
1499 for (i = 0; i < (rx_ring->fbr1_num_entries / FBR_CHUNKS); i++) {
1501 u64 fbr1_tmp_physaddr;
1504 /* This code allocates an area of memory big enough for N
1505 * free buffers + (buffer_size - 1) so that the buffers can
1506 * be aligned on 4k boundaries. If each buffer were aligned
1507 * to a buffer_size boundary, the effect would be to double
1508 * the size of FBR0. By allocating N buffers at once, we
1509 * reduce this overhead.
1511 if (rx_ring->fbr1_buffsize > 4096)
1514 fbr1_align = rx_ring->fbr1_buffsize;
1517 (FBR_CHUNKS * rx_ring->fbr1_buffsize) + fbr1_align - 1;
1518 rx_ring->fbr1_mem_virtaddrs[i] =
1519 pci_alloc_consistent(adapter->pdev, fbr_chunksize,
1520 &rx_ring->fbr1_mem_physaddrs[i]);
1522 if (!rx_ring->fbr1_mem_virtaddrs[i]) {
1523 dev_err(&adapter->pdev->dev,
1524 "Could not alloc memory\n");
1528 /* See NOTE in "Save Physical Address" comment above */
1529 fbr1_tmp_physaddr = rx_ring->fbr1_mem_physaddrs[i];
1531 et131x_align_allocated_memory(adapter,
1533 &fbr1_offset, (fbr1_align - 1));
1535 for (j = 0; j < FBR_CHUNKS; j++) {
1536 u32 index = (i * FBR_CHUNKS) + j;
1538 /* Save the Virtual address of this index for quick
1541 rx_ring->fbr[1]->virt[index] =
1542 (u8 *) rx_ring->fbr1_mem_virtaddrs[i] +
1543 (j * rx_ring->fbr1_buffsize) + fbr1_offset;
1545 /* now store the physical address in the descriptor
1546 * so the device can access it
1548 rx_ring->fbr[1]->bus_high[index] =
1549 (u32) (fbr1_tmp_physaddr >> 32);
1550 rx_ring->fbr[1]->bus_low[index] =
1551 (u32) fbr1_tmp_physaddr;
1553 fbr1_tmp_physaddr += rx_ring->fbr1_buffsize;
1555 rx_ring->fbr[1]->buffer1[index] =
1556 rx_ring->fbr[1]->virt[index];
1557 rx_ring->fbr[1]->buffer2[index] =
1558 rx_ring->fbr[1]->virt[index] - 4;
1563 /* Same for FBR0 (if in use) */
1564 for (i = 0; i < (rx_ring->fbr0_num_entries / FBR_CHUNKS); i++) {
1566 u64 fbr0_tmp_physaddr;
1569 ((FBR_CHUNKS + 1) * rx_ring->fbr0_buffsize) - 1;
1570 rx_ring->fbr0_mem_virtaddrs[i] =
1571 pci_alloc_consistent(adapter->pdev, fbr_chunksize,
1572 &rx_ring->fbr0_mem_physaddrs[i]);
1574 if (!rx_ring->fbr0_mem_virtaddrs[i]) {
1575 dev_err(&adapter->pdev->dev,
1576 "Could not alloc memory\n");
1580 /* See NOTE in "Save Physical Address" comment above */
1581 fbr0_tmp_physaddr = rx_ring->fbr0_mem_physaddrs[i];
1583 et131x_align_allocated_memory(adapter,
1586 rx_ring->fbr0_buffsize - 1);
1588 for (j = 0; j < FBR_CHUNKS; j++) {
1589 u32 index = (i * FBR_CHUNKS) + j;
1591 rx_ring->fbr[0]->virt[index] =
1592 (u8 *) rx_ring->fbr0_mem_virtaddrs[i] +
1593 (j * rx_ring->fbr0_buffsize) + fbr0_offset;
1595 rx_ring->fbr[0]->bus_high[index] =
1596 (u32) (fbr0_tmp_physaddr >> 32);
1597 rx_ring->fbr[0]->bus_low[index] =
1598 (u32) fbr0_tmp_physaddr;
1600 fbr0_tmp_physaddr += rx_ring->fbr0_buffsize;
1602 rx_ring->fbr[0]->buffer1[index] =
1603 rx_ring->fbr[0]->virt[index];
1604 rx_ring->fbr[0]->buffer2[index] =
1605 rx_ring->fbr[0]->virt[index] - 4;
1610 /* Allocate an area of memory for FIFO of Packet Status ring entries */
1612 sizeof(struct pkt_stat_desc) * adapter->rx_ring.psr_num_entries;
1614 rx_ring->ps_ring_virtaddr = pci_alloc_consistent(adapter->pdev,
1616 &rx_ring->ps_ring_physaddr);
1618 if (!rx_ring->ps_ring_virtaddr) {
1619 dev_err(&adapter->pdev->dev,
1620 "Cannot alloc memory for Packet Status Ring\n");
1623 printk(KERN_INFO "Packet Status Ring %lx\n",
1624 (unsigned long) rx_ring->ps_ring_physaddr);
1627 * NOTE : pci_alloc_consistent(), used above to alloc DMA regions,
1628 * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
1629 * are ever returned, make sure the high part is retrieved here before
1630 * storing the adjusted address.
1633 /* Allocate an area of memory for writeback of status information */
1634 rx_ring->rx_status_block = pci_alloc_consistent(adapter->pdev,
1635 sizeof(struct rx_status_block),
1636 &rx_ring->rx_status_bus);
1637 if (!rx_ring->rx_status_block) {
1638 dev_err(&adapter->pdev->dev,
1639 "Cannot alloc memory for Status Block\n");
1642 rx_ring->num_rfd = NIC_DEFAULT_NUM_RFD;
1643 printk(KERN_INFO "PRS %lx\n", (unsigned long)rx_ring->rx_status_bus);
1646 * pci_pool_create initializes a lookaside list. After successful
1647 * creation, nonpaged fixed-size blocks can be allocated from and
1648 * freed to the lookaside list.
1649 * RFDs will be allocated from this pool.
1651 rx_ring->recv_lookaside = kmem_cache_create(adapter->netdev->name,
1658 adapter->flags |= fMP_ADAPTER_RECV_LOOKASIDE;
1660 /* The RFDs are going to be put on lists later on, so initialize the
1663 INIT_LIST_HEAD(&rx_ring->recv_list);
1668 * et131x_rx_dma_memory_free - Free all memory allocated within this module.
1669 * @adapter: pointer to our private adapter structure
1671 void et131x_rx_dma_memory_free(struct et131x_adapter *adapter)
1675 u32 pktstat_ringsize;
1677 struct rx_ring *rx_ring;
1679 /* Setup some convenience pointers */
1680 rx_ring = &adapter->rx_ring;
1682 /* Free RFDs and associated packet descriptors */
1683 WARN_ON(rx_ring->num_ready_recv != rx_ring->num_rfd);
1685 while (!list_empty(&rx_ring->recv_list)) {
1686 rfd = (struct rfd *) list_entry(rx_ring->recv_list.next,
1687 struct rfd, list_node);
1689 list_del(&rfd->list_node);
1691 kmem_cache_free(adapter->rx_ring.recv_lookaside, rfd);
1694 /* Free Free Buffer Ring 1 */
1695 if (rx_ring->fbr1_ring_virtaddr) {
1696 /* First the packet memory */
1697 for (index = 0; index <
1698 (rx_ring->fbr1_num_entries / FBR_CHUNKS); index++) {
1699 if (rx_ring->fbr1_mem_virtaddrs[index]) {
1702 if (rx_ring->fbr1_buffsize > 4096)
1705 fbr1_align = rx_ring->fbr1_buffsize;
1708 (rx_ring->fbr1_buffsize * FBR_CHUNKS) +
1711 pci_free_consistent(adapter->pdev,
1713 rx_ring->fbr1_mem_virtaddrs[index],
1714 rx_ring->fbr1_mem_physaddrs[index]);
1716 rx_ring->fbr1_mem_virtaddrs[index] = NULL;
1720 /* Now the FIFO itself */
1721 rx_ring->fbr1_ring_virtaddr = (void *)((u8 *)
1722 rx_ring->fbr1_ring_virtaddr - rx_ring->fbr1_offset);
1724 bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr1_num_entries)
1727 pci_free_consistent(adapter->pdev, bufsize,
1728 rx_ring->fbr1_ring_virtaddr,
1729 rx_ring->fbr1_ring_physaddr);
1731 rx_ring->fbr1_ring_virtaddr = NULL;
1735 /* Now the same for Free Buffer Ring 0 */
1736 if (rx_ring->fbr0_ring_virtaddr) {
1737 /* First the packet memory */
1738 for (index = 0; index <
1739 (rx_ring->fbr0_num_entries / FBR_CHUNKS); index++) {
1740 if (rx_ring->fbr0_mem_virtaddrs[index]) {
1742 (rx_ring->fbr0_buffsize *
1743 (FBR_CHUNKS + 1)) - 1;
1745 pci_free_consistent(adapter->pdev,
1747 rx_ring->fbr0_mem_virtaddrs[index],
1748 rx_ring->fbr0_mem_physaddrs[index]);
1750 rx_ring->fbr0_mem_virtaddrs[index] = NULL;
1754 /* Now the FIFO itself */
1755 rx_ring->fbr0_ring_virtaddr = (void *)((u8 *)
1756 rx_ring->fbr0_ring_virtaddr - rx_ring->fbr0_offset);
1758 bufsize = (sizeof(struct fbr_desc) * rx_ring->fbr0_num_entries)
1761 pci_free_consistent(adapter->pdev,
1763 rx_ring->fbr0_ring_virtaddr,
1764 rx_ring->fbr0_ring_physaddr);
1766 rx_ring->fbr0_ring_virtaddr = NULL;
1770 /* Free Packet Status Ring */
1771 if (rx_ring->ps_ring_virtaddr) {
1773 sizeof(struct pkt_stat_desc) *
1774 adapter->rx_ring.psr_num_entries;
1776 pci_free_consistent(adapter->pdev, pktstat_ringsize,
1777 rx_ring->ps_ring_virtaddr,
1778 rx_ring->ps_ring_physaddr);
1780 rx_ring->ps_ring_virtaddr = NULL;
1783 /* Free area of memory for the writeback of status information */
1784 if (rx_ring->rx_status_block) {
1785 pci_free_consistent(adapter->pdev,
1786 sizeof(struct rx_status_block),
1787 rx_ring->rx_status_block, rx_ring->rx_status_bus);
1788 rx_ring->rx_status_block = NULL;
1791 /* Free receive buffer pool */
1793 /* Free receive packet pool */
1795 /* Destroy the lookaside (RFD) pool */
1796 if (adapter->flags & fMP_ADAPTER_RECV_LOOKASIDE) {
1797 kmem_cache_destroy(rx_ring->recv_lookaside);
1798 adapter->flags &= ~fMP_ADAPTER_RECV_LOOKASIDE;
1801 /* Free the FBR Lookup Table */
1803 kfree(rx_ring->fbr[0]);
1806 kfree(rx_ring->fbr[1]);
1808 /* Reset Counters */
1809 rx_ring->num_ready_recv = 0;
1813 * et131x_init_recv - Initialize receive data structures.
1814 * @adapter: pointer to our private adapter structure
1816 * Returns 0 on success and errno on failure (as defined in errno.h)
1818 int et131x_init_recv(struct et131x_adapter *adapter)
1820 int status = -ENOMEM;
1821 struct rfd *rfd = NULL;
1824 struct rx_ring *rx_ring;
1826 /* Setup some convenience pointers */
1827 rx_ring = &adapter->rx_ring;
1829 /* Setup each RFD */
1830 for (rfdct = 0; rfdct < rx_ring->num_rfd; rfdct++) {
1831 rfd = kmem_cache_alloc(rx_ring->recv_lookaside,
1832 GFP_ATOMIC | GFP_DMA);
1835 dev_err(&adapter->pdev->dev,
1836 "Couldn't alloc RFD out of kmem_cache\n");
1843 /* Add this RFD to the recv_list */
1844 list_add_tail(&rfd->list_node, &rx_ring->recv_list);
1846 /* Increment both the available RFD's, and the total RFD's. */
1847 rx_ring->num_ready_recv++;
1851 if (numrfd > NIC_MIN_NUM_RFD)
1854 rx_ring->num_rfd = numrfd;
1857 kmem_cache_free(rx_ring->recv_lookaside, rfd);
1858 dev_err(&adapter->pdev->dev,
1859 "Allocation problems in et131x_init_recv\n");
1865 * et131x_config_rx_dma_regs - Start of Rx_DMA init sequence
1866 * @adapter: pointer to our adapter structure
1868 void et131x_config_rx_dma_regs(struct et131x_adapter *adapter)
1870 struct rxdma_regs __iomem *rx_dma = &adapter->regs->rxdma;
1871 struct rx_ring *rx_local = &adapter->rx_ring;
1872 struct fbr_desc *fbr_entry;
1875 unsigned long flags;
1877 /* Halt RXDMA to perform the reconfigure. */
1878 et131x_rx_dma_disable(adapter);
1880 /* Load the completion writeback physical address
1882 * NOTE : pci_alloc_consistent(), used above to alloc DMA regions,
1883 * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
1884 * are ever returned, make sure the high part is retrieved here
1885 * before storing the adjusted address.
1887 writel((u32) ((u64)rx_local->rx_status_bus >> 32),
1888 &rx_dma->dma_wb_base_hi);
1889 writel((u32) rx_local->rx_status_bus, &rx_dma->dma_wb_base_lo);
1891 memset(rx_local->rx_status_block, 0, sizeof(struct rx_status_block));
1893 /* Set the address and parameters of the packet status ring into the
1896 writel((u32) ((u64)rx_local->ps_ring_physaddr >> 32),
1897 &rx_dma->psr_base_hi);
1898 writel((u32) rx_local->ps_ring_physaddr, &rx_dma->psr_base_lo);
1899 writel(rx_local->psr_num_entries - 1, &rx_dma->psr_num_des);
1900 writel(0, &rx_dma->psr_full_offset);
1902 psr_num_des = readl(&rx_dma->psr_num_des) & 0xFFF;
1903 writel((psr_num_des * LO_MARK_PERCENT_FOR_PSR) / 100,
1904 &rx_dma->psr_min_des);
1906 spin_lock_irqsave(&adapter->rcv_lock, flags);
1908 /* These local variables track the PSR in the adapter structure */
1909 rx_local->local_psr_full = 0;
1911 /* Now's the best time to initialize FBR1 contents */
1912 fbr_entry = (struct fbr_desc *) rx_local->fbr1_ring_virtaddr;
1913 for (entry = 0; entry < rx_local->fbr1_num_entries; entry++) {
1914 fbr_entry->addr_hi = rx_local->fbr[1]->bus_high[entry];
1915 fbr_entry->addr_lo = rx_local->fbr[1]->bus_low[entry];
1916 fbr_entry->word2 = entry;
1920 /* Set the address and parameters of Free buffer ring 1 (and 0 if
1921 * required) into the 1310's registers
1923 writel((u32) (rx_local->fbr1_real_physaddr >> 32),
1924 &rx_dma->fbr1_base_hi);
1925 writel((u32) rx_local->fbr1_real_physaddr, &rx_dma->fbr1_base_lo);
1926 writel(rx_local->fbr1_num_entries - 1, &rx_dma->fbr1_num_des);
1927 writel(ET_DMA10_WRAP, &rx_dma->fbr1_full_offset);
1929 /* This variable tracks the free buffer ring 1 full position, so it
1930 * has to match the above.
1932 rx_local->local_fbr1_full = ET_DMA10_WRAP;
1934 ((rx_local->fbr1_num_entries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,
1935 &rx_dma->fbr1_min_des);
1938 /* Now's the best time to initialize FBR0 contents */
1939 fbr_entry = (struct fbr_desc *) rx_local->fbr0_ring_virtaddr;
1940 for (entry = 0; entry < rx_local->fbr0_num_entries; entry++) {
1941 fbr_entry->addr_hi = rx_local->fbr[0]->bus_high[entry];
1942 fbr_entry->addr_lo = rx_local->fbr[0]->bus_low[entry];
1943 fbr_entry->word2 = entry;
1947 writel((u32) (rx_local->fbr0_real_physaddr >> 32),
1948 &rx_dma->fbr0_base_hi);
1949 writel((u32) rx_local->fbr0_real_physaddr, &rx_dma->fbr0_base_lo);
1950 writel(rx_local->fbr0_num_entries - 1, &rx_dma->fbr0_num_des);
1951 writel(ET_DMA10_WRAP, &rx_dma->fbr0_full_offset);
1953 /* This variable tracks the free buffer ring 0 full position, so it
1954 * has to match the above.
1956 rx_local->local_fbr0_full = ET_DMA10_WRAP;
1958 ((rx_local->fbr0_num_entries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,
1959 &rx_dma->fbr0_min_des);
1962 /* Program the number of packets we will receive before generating an
1964 * For version B silicon, this value gets updated once autoneg is
1967 writel(PARM_RX_NUM_BUFS_DEF, &rx_dma->num_pkt_done);
1969 /* The "time_done" is not working correctly to coalesce interrupts
1970 * after a given time period, but rather is giving us an interrupt
1971 * regardless of whether we have received packets.
1972 * This value gets updated once autoneg is complete.
1974 writel(PARM_RX_TIME_INT_DEF, &rx_dma->max_pkt_time);
1976 spin_unlock_irqrestore(&adapter->rcv_lock, flags);
1980 * et131x_set_rx_dma_timer - Set the heartbeat timer according to line rate.
1981 * @adapter: pointer to our adapter structure
1983 void et131x_set_rx_dma_timer(struct et131x_adapter *adapter)
1985 struct phy_device *phydev = adapter->phydev;
1990 /* For version B silicon, we do not use the RxDMA timer for 10 and 100
1991 * Mbits/s line rates. We do not enable and RxDMA interrupt coalescing.
1993 if ((phydev->speed == SPEED_100) || (phydev->speed == SPEED_10)) {
1994 writel(0, &adapter->regs->rxdma.max_pkt_time);
1995 writel(1, &adapter->regs->rxdma.num_pkt_done);
2000 * NICReturnRFD - Recycle a RFD and put it back onto the receive list
2001 * @adapter: pointer to our adapter
2002 * @rfd: pointer to the RFD
2004 static void nic_return_rfd(struct et131x_adapter *adapter, struct rfd *rfd)
2006 struct rx_ring *rx_local = &adapter->rx_ring;
2007 struct rxdma_regs __iomem *rx_dma = &adapter->regs->rxdma;
2008 u16 buff_index = rfd->bufferindex;
2009 u8 ring_index = rfd->ringindex;
2010 unsigned long flags;
2012 /* We don't use any of the OOB data besides status. Otherwise, we
2013 * need to clean up OOB data
2017 (ring_index == 0 && buff_index < rx_local->fbr0_num_entries) ||
2019 (ring_index == 1 && buff_index < rx_local->fbr1_num_entries)) {
2020 spin_lock_irqsave(&adapter->fbr_lock, flags);
2022 if (ring_index == 1) {
2023 struct fbr_desc *next =
2024 (struct fbr_desc *) (rx_local->fbr1_ring_virtaddr) +
2025 INDEX10(rx_local->local_fbr1_full);
2027 /* Handle the Free Buffer Ring advancement here. Write
2028 * the PA / Buffer Index for the returned buffer into
2029 * the oldest (next to be freed)FBR entry
2031 next->addr_hi = rx_local->fbr[1]->bus_high[buff_index];
2032 next->addr_lo = rx_local->fbr[1]->bus_low[buff_index];
2033 next->word2 = buff_index;
2035 writel(bump_free_buff_ring(&rx_local->local_fbr1_full,
2036 rx_local->fbr1_num_entries - 1),
2037 &rx_dma->fbr1_full_offset);
2041 struct fbr_desc *next = (struct fbr_desc *)
2042 rx_local->fbr0_ring_virtaddr +
2043 INDEX10(rx_local->local_fbr0_full);
2045 /* Handle the Free Buffer Ring advancement here. Write
2046 * the PA / Buffer Index for the returned buffer into
2047 * the oldest (next to be freed) FBR entry
2049 next->addr_hi = rx_local->fbr[0]->bus_high[buff_index];
2050 next->addr_lo = rx_local->fbr[0]->bus_low[buff_index];
2051 next->word2 = buff_index;
2053 writel(bump_free_buff_ring(&rx_local->local_fbr0_full,
2054 rx_local->fbr0_num_entries - 1),
2055 &rx_dma->fbr0_full_offset);
2058 spin_unlock_irqrestore(&adapter->fbr_lock, flags);
2060 dev_err(&adapter->pdev->dev,
2061 "%s illegal Buffer Index returned\n", __func__);
2064 /* The processing on this RFD is done, so put it back on the tail of
2067 spin_lock_irqsave(&adapter->rcv_lock, flags);
2068 list_add_tail(&rfd->list_node, &rx_local->recv_list);
2069 rx_local->num_ready_recv++;
2070 spin_unlock_irqrestore(&adapter->rcv_lock, flags);
2072 WARN_ON(rx_local->num_ready_recv > rx_local->num_rfd);
2076 * et131x_rx_dma_disable - Stop of Rx_DMA on the ET1310
2077 * @adapter: pointer to our adapter structure
2079 void et131x_rx_dma_disable(struct et131x_adapter *adapter)
2082 /* Setup the receive dma configuration register */
2083 writel(0x00002001, &adapter->regs->rxdma.csr);
2084 csr = readl(&adapter->regs->rxdma.csr);
2085 if ((csr & 0x00020000) == 0) { /* Check halt status (bit 17) */
2087 csr = readl(&adapter->regs->rxdma.csr);
2088 if ((csr & 0x00020000) == 0)
2089 dev_err(&adapter->pdev->dev,
2090 "RX Dma failed to enter halt state. CSR 0x%08x\n",
2096 * et131x_rx_dma_enable - re-start of Rx_DMA on the ET1310.
2097 * @adapter: pointer to our adapter structure
2099 void et131x_rx_dma_enable(struct et131x_adapter *adapter)
2101 /* Setup the receive dma configuration register for normal operation */
2102 u32 csr = 0x2000; /* FBR1 enable */
2104 if (adapter->rx_ring.fbr1_buffsize == 4096)
2106 else if (adapter->rx_ring.fbr1_buffsize == 8192)
2108 else if (adapter->rx_ring.fbr1_buffsize == 16384)
2111 csr |= 0x0400; /* FBR0 enable */
2112 if (adapter->rx_ring.fbr0_buffsize == 256)
2114 else if (adapter->rx_ring.fbr0_buffsize == 512)
2116 else if (adapter->rx_ring.fbr0_buffsize == 1024)
2119 writel(csr, &adapter->regs->rxdma.csr);
2121 csr = readl(&adapter->regs->rxdma.csr);
2122 if ((csr & 0x00020000) != 0) {
2124 csr = readl(&adapter->regs->rxdma.csr);
2125 if ((csr & 0x00020000) != 0) {
2126 dev_err(&adapter->pdev->dev,
2127 "RX Dma failed to exit halt state. CSR 0x%08x\n",
2134 * nic_rx_pkts - Checks the hardware for available packets
2135 * @adapter: pointer to our adapter
2137 * Returns rfd, a pointer to our MPRFD.
2139 * Checks the hardware for available packets, using completion ring
2140 * If packets are available, it gets an RFD from the recv_list, attaches
2141 * the packet to it, puts the RFD in the RecvPendList, and also returns
2142 * the pointer to the RFD.
2144 static struct rfd *nic_rx_pkts(struct et131x_adapter *adapter)
2146 struct rx_ring *rx_local = &adapter->rx_ring;
2147 struct rx_status_block *status;
2148 struct pkt_stat_desc *psr;
2152 unsigned long flags;
2153 struct list_head *element;
2160 /* RX Status block is written by the DMA engine prior to every
2161 * interrupt. It contains the next to be used entry in the Packet
2162 * Status Ring, and also the two Free Buffer rings.
2164 status = rx_local->rx_status_block;
2165 word1 = status->word1 >> 16; /* Get the useful bits */
2167 /* Check the PSR and wrap bits do not match */
2168 if ((word1 & 0x1FFF) == (rx_local->local_psr_full & 0x1FFF))
2169 /* Looks like this ring is not updated yet */
2172 /* The packet status ring indicates that data is available. */
2173 psr = (struct pkt_stat_desc *) (rx_local->ps_ring_virtaddr) +
2174 (rx_local->local_psr_full & 0xFFF);
2176 /* Grab any information that is required once the PSR is
2177 * advanced, since we can no longer rely on the memory being
2180 len = psr->word1 & 0xFFFF;
2181 ring_index = (psr->word1 >> 26) & 0x03;
2182 buff_index = (psr->word1 >> 16) & 0x3FF;
2185 /* Indicate that we have used this PSR entry. */
2187 add_12bit(&rx_local->local_psr_full, 1);
2189 (rx_local->local_psr_full & 0xFFF) > rx_local->psr_num_entries - 1) {
2190 /* Clear psr full and toggle the wrap bit */
2191 rx_local->local_psr_full &= ~0xFFF;
2192 rx_local->local_psr_full ^= 0x1000;
2195 writel(rx_local->local_psr_full,
2196 &adapter->regs->rxdma.psr_full_offset);
2199 if (ring_index != 1)
2204 if (ring_index > 1 ||
2206 buff_index > rx_local->fbr0_num_entries - 1) ||
2208 buff_index > rx_local->fbr1_num_entries - 1))
2210 if (ring_index != 1 || buff_index > rx_local->fbr1_num_entries - 1)
2213 /* Illegal buffer or ring index cannot be used by S/W*/
2214 dev_err(&adapter->pdev->dev,
2215 "NICRxPkts PSR Entry %d indicates "
2216 "length of %d and/or bad bi(%d)\n",
2217 rx_local->local_psr_full & 0xFFF,
2222 /* Get and fill the RFD. */
2223 spin_lock_irqsave(&adapter->rcv_lock, flags);
2226 element = rx_local->recv_list.next;
2227 rfd = (struct rfd *) list_entry(element, struct rfd, list_node);
2230 spin_unlock_irqrestore(&adapter->rcv_lock, flags);
2234 list_del(&rfd->list_node);
2235 rx_local->num_ready_recv--;
2237 spin_unlock_irqrestore(&adapter->rcv_lock, flags);
2239 rfd->bufferindex = buff_index;
2240 rfd->ringindex = ring_index;
2242 /* In V1 silicon, there is a bug which screws up filtering of
2243 * runt packets. Therefore runt packet filtering is disabled
2244 * in the MAC and the packets are dropped here. They are
2245 * also counted here.
2247 if (len < (NIC_MIN_PACKET_SIZE + 4)) {
2248 adapter->stats.rx_other_errs++;
2253 /* Determine if this is a multicast packet coming in */
2254 if ((word0 & ALCATEL_MULTICAST_PKT) &&
2255 !(word0 & ALCATEL_BROADCAST_PKT)) {
2256 /* Promiscuous mode and Multicast mode are
2257 * not mutually exclusive as was first
2258 * thought. I guess Promiscuous is just
2259 * considered a super-set of the other
2260 * filters. Generally filter is 0x2b when in
2263 if ((adapter->packet_filter &
2264 ET131X_PACKET_TYPE_MULTICAST)
2265 && !(adapter->packet_filter &
2266 ET131X_PACKET_TYPE_PROMISCUOUS)
2267 && !(adapter->packet_filter &
2268 ET131X_PACKET_TYPE_ALL_MULTICAST)) {
2269 buf = rx_local->fbr[ring_index]->
2272 /* Loop through our list to see if the
2273 * destination address of this packet
2274 * matches one in our list.
2276 for (i = 0; i < adapter->multicast_addr_count;
2279 adapter->multicast_list[i][0]
2281 adapter->multicast_list[i][1]
2283 adapter->multicast_list[i][2]
2285 adapter->multicast_list[i][3]
2287 adapter->multicast_list[i][4]
2289 adapter->multicast_list[i][5]) {
2294 /* If our index is equal to the number
2295 * of Multicast address we have, then
2296 * this means we did not find this
2297 * packet's matching address in our
2298 * list. Set the len to zero,
2299 * so we free our RFD when we return
2300 * from this function.
2302 if (i == adapter->multicast_addr_count)
2307 adapter->stats.multicast_pkts_rcvd++;
2308 } else if (word0 & ALCATEL_BROADCAST_PKT)
2309 adapter->stats.broadcast_pkts_rcvd++;
2311 /* Not sure what this counter measures in
2312 * promiscuous mode. Perhaps we should check
2313 * the MAC address to see if it is directed
2314 * to us in promiscuous mode.
2316 adapter->stats.unicast_pkts_rcvd++;
2320 struct sk_buff *skb = NULL;
2322 /*rfd->len = len - 4; */
2325 skb = dev_alloc_skb(rfd->len + 2);
2327 dev_err(&adapter->pdev->dev,
2328 "Couldn't alloc an SKB for Rx\n");
2332 adapter->net_stats.rx_bytes += rfd->len;
2334 memcpy(skb_put(skb, rfd->len),
2335 rx_local->fbr[ring_index]->virt[buff_index],
2338 skb->dev = adapter->netdev;
2339 skb->protocol = eth_type_trans(skb, adapter->netdev);
2340 skb->ip_summed = CHECKSUM_NONE;
2347 nic_return_rfd(adapter, rfd);
2352 * et131x_reset_recv - Reset the receive list
2353 * @adapter: pointer to our adapter
2355 * Assumption, Rcv spinlock has been acquired.
2357 void et131x_reset_recv(struct et131x_adapter *adapter)
2359 WARN_ON(list_empty(&adapter->rx_ring.recv_list));
2363 * et131x_handle_recv_interrupt - Interrupt handler for receive processing
2364 * @adapter: pointer to our adapter
2366 * Assumption, Rcv spinlock has been acquired.
2368 void et131x_handle_recv_interrupt(struct et131x_adapter *adapter)
2370 struct rfd *rfd = NULL;
2374 /* Process up to available RFD's */
2375 while (count < NUM_PACKETS_HANDLED) {
2376 if (list_empty(&adapter->rx_ring.recv_list)) {
2377 WARN_ON(adapter->rx_ring.num_ready_recv != 0);
2382 rfd = nic_rx_pkts(adapter);
2387 /* Do not receive any packets until a filter has been set.
2388 * Do not receive any packets until we have link.
2389 * If length is zero, return the RFD in order to advance the
2392 if (!adapter->packet_filter ||
2393 !netif_carrier_ok(adapter->netdev) ||
2397 /* Increment the number of packets we received */
2398 adapter->net_stats.rx_packets++;
2400 /* Set the status on the packet, either resources or success */
2401 if (adapter->rx_ring.num_ready_recv < RFD_LOW_WATER_MARK) {
2402 dev_warn(&adapter->pdev->dev,
2403 "RFD's are running out\n");
2408 if (count == NUM_PACKETS_HANDLED || !done) {
2409 adapter->rx_ring.unfinished_receives = true;
2410 writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO,
2411 &adapter->regs->global.watchdog_timer);
2413 /* Watchdog timer will disable itself if appropriate. */
2414 adapter->rx_ring.unfinished_receives = false;
2420 * et131x_tx_dma_memory_alloc
2421 * @adapter: pointer to our private adapter structure
2423 * Returns 0 on success and errno on failure (as defined in errno.h).
2425 * Allocates memory that will be visible both to the device and to the CPU.
2426 * The OS will pass us packets, pointers to which we will insert in the Tx
2427 * Descriptor queue. The device will read this queue to find the packets in
2428 * memory. The device will update the "status" in memory each time it xmits a
2431 int et131x_tx_dma_memory_alloc(struct et131x_adapter *adapter)
2434 struct tx_ring *tx_ring = &adapter->tx_ring;
2436 /* Allocate memory for the TCB's (Transmit Control Block) */
2437 adapter->tx_ring.tcb_ring =
2438 kcalloc(NUM_TCB, sizeof(struct tcb), GFP_ATOMIC | GFP_DMA);
2439 if (!adapter->tx_ring.tcb_ring) {
2440 dev_err(&adapter->pdev->dev, "Cannot alloc memory for TCBs\n");
2444 /* Allocate enough memory for the Tx descriptor ring, and allocate
2445 * some extra so that the ring can be aligned on a 4k boundary.
2447 desc_size = (sizeof(struct tx_desc) * NUM_DESC_PER_RING_TX) + 4096 - 1;
2448 tx_ring->tx_desc_ring =
2449 (struct tx_desc *) pci_alloc_consistent(adapter->pdev, desc_size,
2450 &tx_ring->tx_desc_ring_pa);
2451 if (!adapter->tx_ring.tx_desc_ring) {
2452 dev_err(&adapter->pdev->dev,
2453 "Cannot alloc memory for Tx Ring\n");
2457 /* Save physical address
2459 * NOTE: pci_alloc_consistent(), used above to alloc DMA regions,
2460 * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
2461 * are ever returned, make sure the high part is retrieved here before
2462 * storing the adjusted address.
2464 /* Allocate memory for the Tx status block */
2465 tx_ring->tx_status = pci_alloc_consistent(adapter->pdev,
2467 &tx_ring->tx_status_pa);
2468 if (!adapter->tx_ring.tx_status_pa) {
2469 dev_err(&adapter->pdev->dev,
2470 "Cannot alloc memory for Tx status block\n");
2477 * et131x_tx_dma_memory_free - Free all memory allocated within this module
2478 * @adapter: pointer to our private adapter structure
2480 * Returns 0 on success and errno on failure (as defined in errno.h).
2482 void et131x_tx_dma_memory_free(struct et131x_adapter *adapter)
2486 if (adapter->tx_ring.tx_desc_ring) {
2487 /* Free memory relating to Tx rings here */
2488 desc_size = (sizeof(struct tx_desc) * NUM_DESC_PER_RING_TX)
2490 pci_free_consistent(adapter->pdev,
2492 adapter->tx_ring.tx_desc_ring,
2493 adapter->tx_ring.tx_desc_ring_pa);
2494 adapter->tx_ring.tx_desc_ring = NULL;
2497 /* Free memory for the Tx status block */
2498 if (adapter->tx_ring.tx_status) {
2499 pci_free_consistent(adapter->pdev,
2501 adapter->tx_ring.tx_status,
2502 adapter->tx_ring.tx_status_pa);
2504 adapter->tx_ring.tx_status = NULL;
2506 /* Free the memory for the tcb structures */
2507 kfree(adapter->tx_ring.tcb_ring);
2511 * et131x_config_tx_dma_regs - Set up the tx dma section of the JAGCore.
2512 * @adapter: pointer to our private adapter structure
2514 * Configure the transmit engine with the ring buffers we have created
2515 * and prepare it for use.
2517 void et131x_config_tx_dma_regs(struct et131x_adapter *adapter)
2519 struct txdma_regs __iomem *txdma = &adapter->regs->txdma;
2521 /* Load the hardware with the start of the transmit descriptor ring. */
2522 writel((u32) ((u64)adapter->tx_ring.tx_desc_ring_pa >> 32),
2523 &txdma->pr_base_hi);
2524 writel((u32) adapter->tx_ring.tx_desc_ring_pa,
2525 &txdma->pr_base_lo);
2527 /* Initialise the transmit DMA engine */
2528 writel(NUM_DESC_PER_RING_TX - 1, &txdma->pr_num_des);
2530 /* Load the completion writeback physical address */
2531 writel((u32)((u64)adapter->tx_ring.tx_status_pa >> 32),
2532 &txdma->dma_wb_base_hi);
2533 writel((u32)adapter->tx_ring.tx_status_pa, &txdma->dma_wb_base_lo);
2535 *adapter->tx_ring.tx_status = 0;
2537 writel(0, &txdma->service_request);
2538 adapter->tx_ring.send_idx = 0;
2542 * et131x_tx_dma_disable - Stop of Tx_DMA on the ET1310
2543 * @adapter: pointer to our adapter structure
2545 void et131x_tx_dma_disable(struct et131x_adapter *adapter)
2547 /* Setup the tramsmit dma configuration register */
2548 writel(ET_TXDMA_CSR_HALT|ET_TXDMA_SNGL_EPKT,
2549 &adapter->regs->txdma.csr);
2553 * et131x_tx_dma_enable - re-start of Tx_DMA on the ET1310.
2554 * @adapter: pointer to our adapter structure
2556 * Mainly used after a return to the D0 (full-power) state from a lower state.
2558 void et131x_tx_dma_enable(struct et131x_adapter *adapter)
2560 /* Setup the transmit dma configuration register for normal
2563 writel(ET_TXDMA_SNGL_EPKT|(PARM_DMA_CACHE_DEF << ET_TXDMA_CACHE_SHIFT),
2564 &adapter->regs->txdma.csr);
2568 * et131x_init_send - Initialize send data structures
2569 * @adapter: pointer to our private adapter structure
2571 void et131x_init_send(struct et131x_adapter *adapter)
2575 struct tx_ring *tx_ring;
2577 /* Setup some convenience pointers */
2578 tx_ring = &adapter->tx_ring;
2579 tcb = adapter->tx_ring.tcb_ring;
2581 tx_ring->tcb_qhead = tcb;
2583 memset(tcb, 0, sizeof(struct tcb) * NUM_TCB);
2585 /* Go through and set up each TCB */
2586 for (ct = 0; ct++ < NUM_TCB; tcb++)
2587 /* Set the link pointer in HW TCB to the next TCB in the
2590 tcb->next = tcb + 1;
2592 /* Set the tail pointer */
2594 tx_ring->tcb_qtail = tcb;
2596 /* Curr send queue should now be empty */
2597 tx_ring->send_head = NULL;
2598 tx_ring->send_tail = NULL;
2602 * nic_send_packet - NIC specific send handler for version B silicon.
2603 * @adapter: pointer to our adapter
2604 * @tcb: pointer to struct tcb
2606 * Returns 0 or errno.
2608 static int nic_send_packet(struct et131x_adapter *adapter, struct tcb *tcb)
2611 struct tx_desc desc[24]; /* 24 x 16 byte */
2613 u32 thiscopy, remainder;
2614 struct sk_buff *skb = tcb->skb;
2615 u32 nr_frags = skb_shinfo(skb)->nr_frags + 1;
2616 struct skb_frag_struct *frags = &skb_shinfo(skb)->frags[0];
2617 unsigned long flags;
2618 struct phy_device *phydev = adapter->phydev;
2620 /* Part of the optimizations of this send routine restrict us to
2621 * sending 24 fragments at a pass. In practice we should never see
2622 * more than 5 fragments.
2624 * NOTE: The older version of this function (below) can handle any
2625 * number of fragments. If needed, we can call this function,
2626 * although it is less efficient.
2631 memset(desc, 0, sizeof(struct tx_desc) * (nr_frags + 1));
2633 for (i = 0; i < nr_frags; i++) {
2634 /* If there is something in this element, lets get a
2635 * descriptor from the ring and get the necessary data
2638 /* If the fragments are smaller than a standard MTU,
2639 * then map them to a single descriptor in the Tx
2640 * Desc ring. However, if they're larger, as is
2641 * possible with support for jumbo packets, then
2642 * split them each across 2 descriptors.
2644 * This will work until we determine why the hardware
2645 * doesn't seem to like large fragments.
2647 if ((skb->len - skb->data_len) <= 1514) {
2648 desc[frag].addr_hi = 0;
2649 /* Low 16bits are length, high is vlan and
2650 unused currently so zero */
2651 desc[frag].len_vlan =
2652 skb->len - skb->data_len;
2654 /* NOTE: Here, the dma_addr_t returned from
2655 * pci_map_single() is implicitly cast as a
2656 * u32. Although dma_addr_t can be
2657 * 64-bit, the address returned by
2658 * pci_map_single() is always 32-bit
2659 * addressable (as defined by the pci/dma
2662 desc[frag++].addr_lo =
2663 pci_map_single(adapter->pdev,
2669 desc[frag].addr_hi = 0;
2670 desc[frag].len_vlan =
2671 (skb->len - skb->data_len) / 2;
2673 /* NOTE: Here, the dma_addr_t returned from
2674 * pci_map_single() is implicitly cast as a
2675 * u32. Although dma_addr_t can be
2676 * 64-bit, the address returned by
2677 * pci_map_single() is always 32-bit
2678 * addressable (as defined by the pci/dma
2681 desc[frag++].addr_lo =
2682 pci_map_single(adapter->pdev,
2685 skb->data_len) / 2),
2687 desc[frag].addr_hi = 0;
2689 desc[frag].len_vlan =
2690 (skb->len - skb->data_len) / 2;
2692 /* NOTE: Here, the dma_addr_t returned from
2693 * pci_map_single() is implicitly cast as a
2694 * u32. Although dma_addr_t can be
2695 * 64-bit, the address returned by
2696 * pci_map_single() is always 32-bit
2697 * addressable (as defined by the pci/dma
2700 desc[frag++].addr_lo =
2701 pci_map_single(adapter->pdev,
2704 skb->data_len) / 2),
2706 skb->data_len) / 2),
2710 desc[frag].addr_hi = 0;
2711 desc[frag].len_vlan =
2714 /* NOTE: Here, the dma_addr_t returned from
2715 * pci_map_page() is implicitly cast as a u32.
2716 * Although dma_addr_t can be 64-bit, the address
2717 * returned by pci_map_page() is always 32-bit
2718 * addressable (as defined by the pci/dma subsystem)
2720 desc[frag++].addr_lo =
2721 pci_map_page(adapter->pdev,
2723 frags[i - 1].page_offset,
2732 if (phydev && phydev->speed == SPEED_1000) {
2733 if (++adapter->tx_ring.since_irq == PARM_TX_NUM_BUFS_DEF) {
2734 /* Last element & Interrupt flag */
2735 desc[frag - 1].flags = 0x5;
2736 adapter->tx_ring.since_irq = 0;
2737 } else { /* Last element */
2738 desc[frag - 1].flags = 0x1;
2741 desc[frag - 1].flags = 0x5;
2743 desc[0].flags |= 2; /* First element flag */
2745 tcb->index_start = adapter->tx_ring.send_idx;
2748 spin_lock_irqsave(&adapter->send_hw_lock, flags);
2750 thiscopy = NUM_DESC_PER_RING_TX -
2751 INDEX10(adapter->tx_ring.send_idx);
2753 if (thiscopy >= frag) {
2757 remainder = frag - thiscopy;
2760 memcpy(adapter->tx_ring.tx_desc_ring +
2761 INDEX10(adapter->tx_ring.send_idx), desc,
2762 sizeof(struct tx_desc) * thiscopy);
2764 add_10bit(&adapter->tx_ring.send_idx, thiscopy);
2766 if (INDEX10(adapter->tx_ring.send_idx) == 0 ||
2767 INDEX10(adapter->tx_ring.send_idx) == NUM_DESC_PER_RING_TX) {
2768 adapter->tx_ring.send_idx &= ~ET_DMA10_MASK;
2769 adapter->tx_ring.send_idx ^= ET_DMA10_WRAP;
2773 memcpy(adapter->tx_ring.tx_desc_ring,
2775 sizeof(struct tx_desc) * remainder);
2777 add_10bit(&adapter->tx_ring.send_idx, remainder);
2780 if (INDEX10(adapter->tx_ring.send_idx) == 0) {
2781 if (adapter->tx_ring.send_idx)
2782 tcb->index = NUM_DESC_PER_RING_TX - 1;
2784 tcb->index = ET_DMA10_WRAP|(NUM_DESC_PER_RING_TX - 1);
2786 tcb->index = adapter->tx_ring.send_idx - 1;
2788 spin_lock(&adapter->tcb_send_qlock);
2790 if (adapter->tx_ring.send_tail)
2791 adapter->tx_ring.send_tail->next = tcb;
2793 adapter->tx_ring.send_head = tcb;
2795 adapter->tx_ring.send_tail = tcb;
2797 WARN_ON(tcb->next != NULL);
2799 adapter->tx_ring.used++;
2801 spin_unlock(&adapter->tcb_send_qlock);
2803 /* Write the new write pointer back to the device. */
2804 writel(adapter->tx_ring.send_idx,
2805 &adapter->regs->txdma.service_request);
2807 /* For Gig only, we use Tx Interrupt coalescing. Enable the software
2808 * timer to wake us up if this packet isn't followed by N more.
2810 if (phydev && phydev->speed == SPEED_1000) {
2811 writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO,
2812 &adapter->regs->global.watchdog_timer);
2814 spin_unlock_irqrestore(&adapter->send_hw_lock, flags);
2820 * send_packet - Do the work to send a packet
2821 * @skb: the packet(s) to send
2822 * @adapter: a pointer to the device's private adapter structure
2824 * Return 0 in almost all cases; non-zero value in extreme hard failure only.
2826 * Assumption: Send spinlock has been acquired
2828 static int send_packet(struct sk_buff *skb, struct et131x_adapter *adapter)
2831 struct tcb *tcb = NULL;
2833 unsigned long flags;
2835 /* All packets must have at least a MAC address and a protocol type */
2836 if (skb->len < ETH_HLEN)
2839 /* Get a TCB for this packet */
2840 spin_lock_irqsave(&adapter->tcb_ready_qlock, flags);
2842 tcb = adapter->tx_ring.tcb_qhead;
2845 spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
2849 adapter->tx_ring.tcb_qhead = tcb->next;
2851 if (adapter->tx_ring.tcb_qhead == NULL)
2852 adapter->tx_ring.tcb_qtail = NULL;
2854 spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
2858 if (skb->data != NULL && skb->len - skb->data_len >= 6) {
2859 shbufva = (u16 *) skb->data;
2861 if ((shbufva[0] == 0xffff) &&
2862 (shbufva[1] == 0xffff) && (shbufva[2] == 0xffff)) {
2863 tcb->flags |= fMP_DEST_BROAD;
2864 } else if ((shbufva[0] & 0x3) == 0x0001) {
2865 tcb->flags |= fMP_DEST_MULTI;
2871 /* Call the NIC specific send handler. */
2872 status = nic_send_packet(adapter, tcb);
2875 spin_lock_irqsave(&adapter->tcb_ready_qlock, flags);
2877 if (adapter->tx_ring.tcb_qtail)
2878 adapter->tx_ring.tcb_qtail->next = tcb;
2880 /* Apparently ready Q is empty. */
2881 adapter->tx_ring.tcb_qhead = tcb;
2883 adapter->tx_ring.tcb_qtail = tcb;
2884 spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
2887 WARN_ON(adapter->tx_ring.used > NUM_TCB);
2892 * et131x_send_packets - This function is called by the OS to send packets
2893 * @skb: the packet(s) to send
2894 * @netdev:device on which to TX the above packet(s)
2896 * Return 0 in almost all cases; non-zero value in extreme hard failure only
2898 int et131x_send_packets(struct sk_buff *skb, struct net_device *netdev)
2901 struct et131x_adapter *adapter = NULL;
2903 adapter = netdev_priv(netdev);
2905 /* Send these packets
2907 * NOTE: The Linux Tx entry point is only given one packet at a time
2908 * to Tx, so the PacketCount and it's array used makes no sense here
2911 /* TCB is not available */
2912 if (adapter->tx_ring.used >= NUM_TCB) {
2913 /* NOTE: If there's an error on send, no need to queue the
2914 * packet under Linux; if we just send an error up to the
2915 * netif layer, it will resend the skb to us.
2919 /* We need to see if the link is up; if it's not, make the
2920 * netif layer think we're good and drop the packet
2922 if ((adapter->flags & fMP_ADAPTER_FAIL_SEND_MASK) ||
2923 !netif_carrier_ok(netdev)) {
2924 dev_kfree_skb_any(skb);
2927 adapter->net_stats.tx_dropped++;
2929 status = send_packet(skb, adapter);
2930 if (status != 0 && status != -ENOMEM) {
2931 /* On any other error, make netif think we're
2932 * OK and drop the packet
2934 dev_kfree_skb_any(skb);
2936 adapter->net_stats.tx_dropped++;
2944 * free_send_packet - Recycle a struct tcb
2945 * @adapter: pointer to our adapter
2946 * @tcb: pointer to struct tcb
2948 * Complete the packet if necessary
2949 * Assumption - Send spinlock has been acquired
2951 static inline void free_send_packet(struct et131x_adapter *adapter,
2954 unsigned long flags;
2955 struct tx_desc *desc = NULL;
2956 struct net_device_stats *stats = &adapter->net_stats;
2958 if (tcb->flags & fMP_DEST_BROAD)
2959 atomic_inc(&adapter->stats.broadcast_pkts_xmtd);
2960 else if (tcb->flags & fMP_DEST_MULTI)
2961 atomic_inc(&adapter->stats.multicast_pkts_xmtd);
2963 atomic_inc(&adapter->stats.unicast_pkts_xmtd);
2966 stats->tx_bytes += tcb->skb->len;
2968 /* Iterate through the TX descriptors on the ring
2969 * corresponding to this packet and umap the fragments
2973 desc = (struct tx_desc *)
2974 (adapter->tx_ring.tx_desc_ring +
2975 INDEX10(tcb->index_start));
2977 pci_unmap_single(adapter->pdev,
2979 desc->len_vlan, PCI_DMA_TODEVICE);
2981 add_10bit(&tcb->index_start, 1);
2982 if (INDEX10(tcb->index_start) >=
2983 NUM_DESC_PER_RING_TX) {
2984 tcb->index_start &= ~ET_DMA10_MASK;
2985 tcb->index_start ^= ET_DMA10_WRAP;
2987 } while (desc != (adapter->tx_ring.tx_desc_ring +
2988 INDEX10(tcb->index)));
2990 dev_kfree_skb_any(tcb->skb);
2993 memset(tcb, 0, sizeof(struct tcb));
2995 /* Add the TCB to the Ready Q */
2996 spin_lock_irqsave(&adapter->tcb_ready_qlock, flags);
2998 adapter->net_stats.tx_packets++;
3000 if (adapter->tx_ring.tcb_qtail)
3001 adapter->tx_ring.tcb_qtail->next = tcb;
3003 /* Apparently ready Q is empty. */
3004 adapter->tx_ring.tcb_qhead = tcb;
3006 adapter->tx_ring.tcb_qtail = tcb;
3008 spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
3009 WARN_ON(adapter->tx_ring.used < 0);
3013 * et131x_free_busy_send_packets - Free and complete the stopped active sends
3014 * @adapter: pointer to our adapter
3016 * Assumption - Send spinlock has been acquired
3018 void et131x_free_busy_send_packets(struct et131x_adapter *adapter)
3021 unsigned long flags;
3024 /* Any packets being sent? Check the first TCB on the send list */
3025 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3027 tcb = adapter->tx_ring.send_head;
3029 while (tcb != NULL && freed < NUM_TCB) {
3030 struct tcb *next = tcb->next;
3032 adapter->tx_ring.send_head = next;
3035 adapter->tx_ring.send_tail = NULL;
3037 adapter->tx_ring.used--;
3039 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3042 free_send_packet(adapter, tcb);
3044 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3046 tcb = adapter->tx_ring.send_head;
3049 WARN_ON(freed == NUM_TCB);
3051 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3053 adapter->tx_ring.used = 0;
3057 * et131x_handle_send_interrupt - Interrupt handler for sending processing
3058 * @adapter: pointer to our adapter
3060 * Re-claim the send resources, complete sends and get more to send from
3061 * the send wait queue.
3063 * Assumption - Send spinlock has been acquired
3065 void et131x_handle_send_interrupt(struct et131x_adapter *adapter)
3067 unsigned long flags;
3072 serviced = readl(&adapter->regs->txdma.new_service_complete);
3073 index = INDEX10(serviced);
3075 /* Has the ring wrapped? Process any descriptors that do not have
3076 * the same "wrap" indicator as the current completion indicator
3078 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3080 tcb = adapter->tx_ring.send_head;
3083 ((serviced ^ tcb->index) & ET_DMA10_WRAP) &&
3084 index < INDEX10(tcb->index)) {
3085 adapter->tx_ring.used--;
3086 adapter->tx_ring.send_head = tcb->next;
3087 if (tcb->next == NULL)
3088 adapter->tx_ring.send_tail = NULL;
3090 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3091 free_send_packet(adapter, tcb);
3092 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3094 /* Goto the next packet */
3095 tcb = adapter->tx_ring.send_head;
3098 !((serviced ^ tcb->index) & ET_DMA10_WRAP)
3099 && index > (tcb->index & ET_DMA10_MASK)) {
3100 adapter->tx_ring.used--;
3101 adapter->tx_ring.send_head = tcb->next;
3102 if (tcb->next == NULL)
3103 adapter->tx_ring.send_tail = NULL;
3105 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3106 free_send_packet(adapter, tcb);
3107 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3109 /* Goto the next packet */
3110 tcb = adapter->tx_ring.send_head;
3113 /* Wake up the queue when we hit a low-water mark */
3114 if (adapter->tx_ring.used <= NUM_TCB / 3)
3115 netif_wake_queue(adapter->netdev);
3117 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3120 /* ETHTOOL functions */
3122 static int et131x_get_settings(struct net_device *netdev,
3123 struct ethtool_cmd *cmd)
3125 struct et131x_adapter *adapter = netdev_priv(netdev);
3127 return phy_ethtool_gset(adapter->phydev, cmd);
3130 static int et131x_set_settings(struct net_device *netdev,
3131 struct ethtool_cmd *cmd)
3133 struct et131x_adapter *adapter = netdev_priv(netdev);
3135 return phy_ethtool_sset(adapter->phydev, cmd);
3138 static int et131x_get_regs_len(struct net_device *netdev)
3140 #define ET131X_REGS_LEN 256
3141 return ET131X_REGS_LEN * sizeof(u32);
3144 static void et131x_get_regs(struct net_device *netdev,
3145 struct ethtool_regs *regs, void *regs_data)
3147 struct et131x_adapter *adapter = netdev_priv(netdev);
3148 struct address_map __iomem *aregs = adapter->regs;
3149 u32 *regs_buff = regs_data;
3152 memset(regs_data, 0, et131x_get_regs_len(netdev));
3154 regs->version = (1 << 24) | (adapter->pdev->revision << 16) |
3155 adapter->pdev->device;
3158 et131x_mii_read(adapter, MII_BMCR, (u16 *)®s_buff[num++]);
3159 et131x_mii_read(adapter, MII_BMSR, (u16 *)®s_buff[num++]);
3160 et131x_mii_read(adapter, MII_PHYSID1, (u16 *)®s_buff[num++]);
3161 et131x_mii_read(adapter, MII_PHYSID2, (u16 *)®s_buff[num++]);
3162 et131x_mii_read(adapter, MII_ADVERTISE, (u16 *)®s_buff[num++]);
3163 et131x_mii_read(adapter, MII_LPA, (u16 *)®s_buff[num++]);
3164 et131x_mii_read(adapter, MII_EXPANSION, (u16 *)®s_buff[num++]);
3165 /* Autoneg next page transmit reg */
3166 et131x_mii_read(adapter, 0x07, (u16 *)®s_buff[num++]);
3167 /* Link partner next page reg */
3168 et131x_mii_read(adapter, 0x08, (u16 *)®s_buff[num++]);
3169 et131x_mii_read(adapter, MII_CTRL1000, (u16 *)®s_buff[num++]);
3170 et131x_mii_read(adapter, MII_STAT1000, (u16 *)®s_buff[num++]);
3171 et131x_mii_read(adapter, MII_ESTATUS, (u16 *)®s_buff[num++]);
3172 et131x_mii_read(adapter, PHY_INDEX_REG, (u16 *)®s_buff[num++]);
3173 et131x_mii_read(adapter, PHY_DATA_REG, (u16 *)®s_buff[num++]);
3174 et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG,
3175 (u16 *)®s_buff[num++]);
3176 et131x_mii_read(adapter, PHY_LOOPBACK_CONTROL,
3177 (u16 *)®s_buff[num++]);
3178 et131x_mii_read(adapter, PHY_LOOPBACK_CONTROL+1,
3179 (u16 *)®s_buff[num++]);
3180 et131x_mii_read(adapter, PHY_REGISTER_MGMT_CONTROL,
3181 (u16 *)®s_buff[num++]);
3182 et131x_mii_read(adapter, PHY_CONFIG, (u16 *)®s_buff[num++]);
3183 et131x_mii_read(adapter, PHY_PHY_CONTROL, (u16 *)®s_buff[num++]);
3184 et131x_mii_read(adapter, PHY_INTERRUPT_MASK, (u16 *)®s_buff[num++]);
3185 et131x_mii_read(adapter, PHY_INTERRUPT_STATUS,
3186 (u16 *)®s_buff[num++]);
3187 et131x_mii_read(adapter, PHY_PHY_STATUS, (u16 *)®s_buff[num++]);
3188 et131x_mii_read(adapter, PHY_LED_1, (u16 *)®s_buff[num++]);
3189 et131x_mii_read(adapter, PHY_LED_2, (u16 *)®s_buff[num++]);
3192 regs_buff[num++] = readl(&aregs->global.txq_start_addr);
3193 regs_buff[num++] = readl(&aregs->global.txq_end_addr);
3194 regs_buff[num++] = readl(&aregs->global.rxq_start_addr);
3195 regs_buff[num++] = readl(&aregs->global.rxq_end_addr);
3196 regs_buff[num++] = readl(&aregs->global.pm_csr);
3197 regs_buff[num++] = adapter->stats.interrupt_status;
3198 regs_buff[num++] = readl(&aregs->global.int_mask);
3199 regs_buff[num++] = readl(&aregs->global.int_alias_clr_en);
3200 regs_buff[num++] = readl(&aregs->global.int_status_alias);
3201 regs_buff[num++] = readl(&aregs->global.sw_reset);
3202 regs_buff[num++] = readl(&aregs->global.slv_timer);
3203 regs_buff[num++] = readl(&aregs->global.msi_config);
3204 regs_buff[num++] = readl(&aregs->global.loopback);
3205 regs_buff[num++] = readl(&aregs->global.watchdog_timer);
3208 regs_buff[num++] = readl(&aregs->txdma.csr);
3209 regs_buff[num++] = readl(&aregs->txdma.pr_base_hi);
3210 regs_buff[num++] = readl(&aregs->txdma.pr_base_lo);
3211 regs_buff[num++] = readl(&aregs->txdma.pr_num_des);
3212 regs_buff[num++] = readl(&aregs->txdma.txq_wr_addr);
3213 regs_buff[num++] = readl(&aregs->txdma.txq_wr_addr_ext);
3214 regs_buff[num++] = readl(&aregs->txdma.txq_rd_addr);
3215 regs_buff[num++] = readl(&aregs->txdma.dma_wb_base_hi);
3216 regs_buff[num++] = readl(&aregs->txdma.dma_wb_base_lo);
3217 regs_buff[num++] = readl(&aregs->txdma.service_request);
3218 regs_buff[num++] = readl(&aregs->txdma.service_complete);
3219 regs_buff[num++] = readl(&aregs->txdma.cache_rd_index);
3220 regs_buff[num++] = readl(&aregs->txdma.cache_wr_index);
3221 regs_buff[num++] = readl(&aregs->txdma.tx_dma_error);
3222 regs_buff[num++] = readl(&aregs->txdma.desc_abort_cnt);
3223 regs_buff[num++] = readl(&aregs->txdma.payload_abort_cnt);
3224 regs_buff[num++] = readl(&aregs->txdma.writeback_abort_cnt);
3225 regs_buff[num++] = readl(&aregs->txdma.desc_timeout_cnt);
3226 regs_buff[num++] = readl(&aregs->txdma.payload_timeout_cnt);
3227 regs_buff[num++] = readl(&aregs->txdma.writeback_timeout_cnt);
3228 regs_buff[num++] = readl(&aregs->txdma.desc_error_cnt);
3229 regs_buff[num++] = readl(&aregs->txdma.payload_error_cnt);
3230 regs_buff[num++] = readl(&aregs->txdma.writeback_error_cnt);
3231 regs_buff[num++] = readl(&aregs->txdma.dropped_tlp_cnt);
3232 regs_buff[num++] = readl(&aregs->txdma.new_service_complete);
3233 regs_buff[num++] = readl(&aregs->txdma.ethernet_packet_cnt);
3236 regs_buff[num++] = readl(&aregs->rxdma.csr);
3237 regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_hi);
3238 regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_lo);
3239 regs_buff[num++] = readl(&aregs->rxdma.num_pkt_done);
3240 regs_buff[num++] = readl(&aregs->rxdma.max_pkt_time);
3241 regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr);
3242 regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr_ext);
3243 regs_buff[num++] = readl(&aregs->rxdma.rxq_wr_addr);
3244 regs_buff[num++] = readl(&aregs->rxdma.psr_base_hi);
3245 regs_buff[num++] = readl(&aregs->rxdma.psr_base_lo);
3246 regs_buff[num++] = readl(&aregs->rxdma.psr_num_des);
3247 regs_buff[num++] = readl(&aregs->rxdma.psr_avail_offset);
3248 regs_buff[num++] = readl(&aregs->rxdma.psr_full_offset);
3249 regs_buff[num++] = readl(&aregs->rxdma.psr_access_index);
3250 regs_buff[num++] = readl(&aregs->rxdma.psr_min_des);
3251 regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_lo);
3252 regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_hi);
3253 regs_buff[num++] = readl(&aregs->rxdma.fbr0_num_des);
3254 regs_buff[num++] = readl(&aregs->rxdma.fbr0_avail_offset);
3255 regs_buff[num++] = readl(&aregs->rxdma.fbr0_full_offset);
3256 regs_buff[num++] = readl(&aregs->rxdma.fbr0_rd_index);
3257 regs_buff[num++] = readl(&aregs->rxdma.fbr0_min_des);
3258 regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_lo);
3259 regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_hi);
3260 regs_buff[num++] = readl(&aregs->rxdma.fbr1_num_des);
3261 regs_buff[num++] = readl(&aregs->rxdma.fbr1_avail_offset);
3262 regs_buff[num++] = readl(&aregs->rxdma.fbr1_full_offset);
3263 regs_buff[num++] = readl(&aregs->rxdma.fbr1_rd_index);
3264 regs_buff[num++] = readl(&aregs->rxdma.fbr1_min_des);
3267 #define ET131X_DRVINFO_LEN 32 /* value from ethtool.h */
3268 static void et131x_get_drvinfo(struct net_device *netdev,
3269 struct ethtool_drvinfo *info)
3271 struct et131x_adapter *adapter = netdev_priv(netdev);
3273 strncpy(info->driver, DRIVER_NAME, ET131X_DRVINFO_LEN);
3274 strncpy(info->version, DRIVER_VERSION, ET131X_DRVINFO_LEN);
3275 strncpy(info->bus_info, pci_name(adapter->pdev), ET131X_DRVINFO_LEN);
3278 static struct ethtool_ops et131x_ethtool_ops = {
3279 .get_settings = et131x_get_settings,
3280 .set_settings = et131x_set_settings,
3281 .get_drvinfo = et131x_get_drvinfo,
3282 .get_regs_len = et131x_get_regs_len,
3283 .get_regs = et131x_get_regs,
3284 .get_link = ethtool_op_get_link,
3287 void et131x_set_ethtool_ops(struct net_device *netdev)
3289 SET_ETHTOOL_OPS(netdev, &et131x_ethtool_ops);
3295 * et131x_hwaddr_init - set up the MAC Address on the ET1310
3296 * @adapter: pointer to our private adapter structure
3298 void et131x_hwaddr_init(struct et131x_adapter *adapter)
3300 /* If have our default mac from init and no mac address from
3301 * EEPROM then we need to generate the last octet and set it on the
3304 if (adapter->rom_addr[0] == 0x00 &&
3305 adapter->rom_addr[1] == 0x00 &&
3306 adapter->rom_addr[2] == 0x00 &&
3307 adapter->rom_addr[3] == 0x00 &&
3308 adapter->rom_addr[4] == 0x00 &&
3309 adapter->rom_addr[5] == 0x00) {
3311 * We need to randomly generate the last octet so we
3312 * decrease our chances of setting the mac address to
3313 * same as another one of our cards in the system
3315 get_random_bytes(&adapter->addr[5], 1);
3317 * We have the default value in the register we are
3318 * working with so we need to copy the current
3319 * address into the permanent address
3321 memcpy(adapter->rom_addr,
3322 adapter->addr, ETH_ALEN);
3324 /* We do not have an override address, so set the
3325 * current address to the permanent address and add
3328 memcpy(adapter->addr,
3329 adapter->rom_addr, ETH_ALEN);
3334 * et131x_pci_init - initial PCI setup
3335 * @adapter: pointer to our private adapter structure
3336 * @pdev: our PCI device
3338 * Perform the initial setup of PCI registers and if possible initialise
3339 * the MAC address. At this point the I/O registers have yet to be mapped
3341 static int et131x_pci_init(struct et131x_adapter *adapter,
3342 struct pci_dev *pdev)
3348 if (et131x_init_eeprom(adapter) < 0)
3351 /* Let's set up the PORT LOGIC Register. First we need to know what
3352 * the max_payload_size is
3354 if (pci_read_config_byte(pdev, ET1310_PCI_MAX_PYLD, &max_payload)) {
3356 "Could not read PCI config space for Max Payload Size\n");
3360 /* Program the Ack/Nak latency and replay timers */
3361 max_payload &= 0x07; /* Only the lower 3 bits are valid */
3363 if (max_payload < 2) {
3364 static const u16 acknak[2] = { 0x76, 0xD0 };
3365 static const u16 replay[2] = { 0x1E0, 0x2ED };
3367 if (pci_write_config_word(pdev, ET1310_PCI_ACK_NACK,
3368 acknak[max_payload])) {
3370 "Could not write PCI config space for ACK/NAK\n");
3373 if (pci_write_config_word(pdev, ET1310_PCI_REPLAY,
3374 replay[max_payload])) {
3376 "Could not write PCI config space for Replay Timer\n");
3381 /* l0s and l1 latency timers. We are using default values.
3382 * Representing 001 for L0s and 010 for L1
3384 if (pci_write_config_byte(pdev, ET1310_PCI_L0L1LATENCY, 0x11)) {
3386 "Could not write PCI config space for Latency Timers\n");
3390 /* Change the max read size to 2k */
3391 if (pci_read_config_byte(pdev, 0x51, &read_size_reg)) {
3393 "Could not read PCI config space for Max read size\n");
3397 read_size_reg &= 0x8f;
3398 read_size_reg |= 0x40;
3400 if (pci_write_config_byte(pdev, 0x51, read_size_reg)) {
3402 "Could not write PCI config space for Max read size\n");
3406 /* Get MAC address from config space if an eeprom exists, otherwise
3407 * the MAC address there will not be valid
3409 if (!adapter->has_eeprom) {
3410 et131x_hwaddr_init(adapter);
3414 for (i = 0; i < ETH_ALEN; i++) {
3415 if (pci_read_config_byte(pdev, ET1310_PCI_MAC_ADDRESS + i,
3416 adapter->rom_addr + i)) {
3417 dev_err(&pdev->dev, "Could not read PCI config space for MAC address\n");
3421 memcpy(adapter->addr, adapter->rom_addr, ETH_ALEN);
3426 * et131x_error_timer_handler
3427 * @data: timer-specific variable; here a pointer to our adapter structure
3429 * The routine called when the error timer expires, to track the number of
3432 void et131x_error_timer_handler(unsigned long data)
3434 struct et131x_adapter *adapter = (struct et131x_adapter *) data;
3435 struct phy_device *phydev = adapter->phydev;
3437 if (et1310_in_phy_coma(adapter)) {
3438 /* Bring the device immediately out of coma, to
3439 * prevent it from sleeping indefinitely, this
3440 * mechanism could be improved! */
3441 et1310_disable_phy_coma(adapter);
3442 adapter->boot_coma = 20;
3444 et1310_update_macstat_host_counters(adapter);
3447 if (!phydev->link && adapter->boot_coma < 11)
3448 adapter->boot_coma++;
3450 if (adapter->boot_coma == 10) {
3451 if (!phydev->link) {
3452 if (!et1310_in_phy_coma(adapter)) {
3453 /* NOTE - This was originally a 'sync with
3454 * interrupt'. How to do that under Linux?
3456 et131x_enable_interrupts(adapter);
3457 et1310_enable_phy_coma(adapter);
3462 /* This is a periodic timer, so reschedule */
3463 mod_timer(&adapter->error_timer, jiffies +
3464 TX_ERROR_PERIOD * HZ / 1000);
3468 * et131x_configure_global_regs - configure JAGCore global regs
3469 * @adapter: pointer to our adapter structure
3471 * Used to configure the global registers on the JAGCore
3473 void et131x_configure_global_regs(struct et131x_adapter *adapter)
3475 struct global_regs __iomem *regs = &adapter->regs->global;
3477 writel(0, ®s->rxq_start_addr);
3478 writel(INTERNAL_MEM_SIZE - 1, ®s->txq_end_addr);
3480 if (adapter->registry_jumbo_packet < 2048) {
3481 /* Tx / RxDMA and Tx/Rx MAC interfaces have a 1k word
3482 * block of RAM that the driver can split between Tx
3483 * and Rx as it desires. Our default is to split it
3486 writel(PARM_RX_MEM_END_DEF, ®s->rxq_end_addr);
3487 writel(PARM_RX_MEM_END_DEF + 1, ®s->txq_start_addr);
3488 } else if (adapter->registry_jumbo_packet < 8192) {
3489 /* For jumbo packets > 2k but < 8k, split 50-50. */
3490 writel(INTERNAL_MEM_RX_OFFSET, ®s->rxq_end_addr);
3491 writel(INTERNAL_MEM_RX_OFFSET + 1, ®s->txq_start_addr);
3493 /* 9216 is the only packet size greater than 8k that
3494 * is available. The Tx buffer has to be big enough
3495 * for one whole packet on the Tx side. We'll make
3496 * the Tx 9408, and give the rest to Rx
3498 writel(0x01b3, ®s->rxq_end_addr);
3499 writel(0x01b4, ®s->txq_start_addr);
3502 /* Initialize the loopback register. Disable all loopbacks. */
3503 writel(0, ®s->loopback);
3506 writel(0, ®s->msi_config);
3508 /* By default, disable the watchdog timer. It will be enabled when
3509 * a packet is queued.
3511 writel(0, ®s->watchdog_timer);
3515 * et131x_adapter_setup - Set the adapter up as per cassini+ documentation
3516 * @adapter: pointer to our private adapter structure
3518 * Returns 0 on success, errno on failure (as defined in errno.h)
3520 void et131x_adapter_setup(struct et131x_adapter *adapter)
3522 /* Configure the JAGCore */
3523 et131x_configure_global_regs(adapter);
3525 et1310_config_mac_regs1(adapter);
3527 /* Configure the MMC registers */
3528 /* All we need to do is initialize the Memory Control Register */
3529 writel(ET_MMC_ENABLE, &adapter->regs->mmc.mmc_ctrl);
3531 et1310_config_rxmac_regs(adapter);
3532 et1310_config_txmac_regs(adapter);
3534 et131x_config_rx_dma_regs(adapter);
3535 et131x_config_tx_dma_regs(adapter);
3537 et1310_config_macstat_regs(adapter);
3539 et1310_phy_power_down(adapter, 0);
3540 et131x_xcvr_init(adapter);
3544 * et131x_soft_reset - Issue a soft reset to the hardware, complete for ET1310
3545 * @adapter: pointer to our private adapter structure
3547 void et131x_soft_reset(struct et131x_adapter *adapter)
3549 /* Disable MAC Core */
3550 writel(0xc00f0000, &adapter->regs->mac.cfg1);
3552 /* Set everything to a reset value */
3553 writel(0x7F, &adapter->regs->global.sw_reset);
3554 writel(0x000f0000, &adapter->regs->mac.cfg1);
3555 writel(0x00000000, &adapter->regs->mac.cfg1);
3559 * et131x_align_allocated_memory - Align allocated memory on a given boundary
3560 * @adapter: pointer to our adapter structure
3561 * @phys_addr: pointer to Physical address
3562 * @offset: pointer to the offset variable
3563 * @mask: correct mask
3565 void et131x_align_allocated_memory(struct et131x_adapter *adapter,
3566 uint64_t *phys_addr,
3567 uint64_t *offset, uint64_t mask)
3573 new_addr = *phys_addr & ~mask;
3575 if (new_addr != *phys_addr) {
3576 /* Move to next aligned block */
3577 new_addr += mask + 1;
3578 /* Return offset for adjusting virt addr */
3579 *offset = new_addr - *phys_addr;
3580 /* Return new physical address */
3581 *phys_addr = new_addr;
3586 * et131x_adapter_memory_alloc
3587 * @adapter: pointer to our private adapter structure
3589 * Returns 0 on success, errno on failure (as defined in errno.h).
3591 * Allocate all the memory blocks for send, receive and others.
3593 int et131x_adapter_memory_alloc(struct et131x_adapter *adapter)
3597 /* Allocate memory for the Tx Ring */
3598 status = et131x_tx_dma_memory_alloc(adapter);
3600 dev_err(&adapter->pdev->dev,
3601 "et131x_tx_dma_memory_alloc FAILED\n");
3604 /* Receive buffer memory allocation */
3605 status = et131x_rx_dma_memory_alloc(adapter);
3607 dev_err(&adapter->pdev->dev,
3608 "et131x_rx_dma_memory_alloc FAILED\n");
3609 et131x_tx_dma_memory_free(adapter);
3613 /* Init receive data structures */
3614 status = et131x_init_recv(adapter);
3616 dev_err(&adapter->pdev->dev,
3617 "et131x_init_recv FAILED\n");
3618 et131x_tx_dma_memory_free(adapter);
3619 et131x_rx_dma_memory_free(adapter);
3625 * et131x_adapter_memory_free - Free all memory allocated for use by Tx & Rx
3626 * @adapter: pointer to our private adapter structure
3628 void et131x_adapter_memory_free(struct et131x_adapter *adapter)
3630 /* Free DMA memory */
3631 et131x_tx_dma_memory_free(adapter);
3632 et131x_rx_dma_memory_free(adapter);
3635 static void et131x_adjust_link(struct net_device *netdev)
3637 struct et131x_adapter *adapter = netdev_priv(netdev);
3638 struct phy_device *phydev = adapter->phydev;
3640 if (netif_carrier_ok(netdev)) {
3641 adapter->boot_coma = 20;
3643 if (phydev && phydev->speed == SPEED_10) {
3645 * NOTE - Is there a way to query this without
3647 * && TRU_QueryCoreType(adapter->hTruePhy, 0)==
3648 * EMI_TRUEPHY_A13O) {
3652 et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG,
3654 et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG,
3656 et131x_mii_write(adapter, PHY_INDEX_REG,
3657 register18 | 0x8402);
3658 et131x_mii_write(adapter, PHY_DATA_REG,
3660 et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG,
3664 et1310_config_flow_control(adapter);
3666 if (phydev && phydev->speed == SPEED_1000 &&
3667 adapter->registry_jumbo_packet > 2048) {
3670 et131x_mii_read(adapter, PHY_CONFIG, ®);
3671 reg &= ~ET_PHY_CONFIG_TX_FIFO_DEPTH;
3672 reg |= ET_PHY_CONFIG_FIFO_DEPTH_32;
3673 et131x_mii_write(adapter, PHY_CONFIG, reg);
3676 et131x_set_rx_dma_timer(adapter);
3677 et1310_config_mac_regs2(adapter);
3680 if (phydev && phydev->link != adapter->link) {
3682 * Check to see if we are in coma mode and if
3683 * so, disable it because we will not be able
3684 * to read PHY values until we are out.
3686 if (et1310_in_phy_coma(adapter))
3687 et1310_disable_phy_coma(adapter);
3690 adapter->boot_coma = 20;
3692 dev_warn(&adapter->pdev->dev,
3693 "Link down - cable problem ?\n");
3694 adapter->boot_coma = 0;
3696 if (phydev->speed == SPEED_10) {
3697 /* NOTE - Is there a way to query this without
3699 * && TRU_QueryCoreType(adapter->hTruePhy, 0) ==
3704 et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG,
3706 et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG,
3708 et131x_mii_write(adapter, PHY_INDEX_REG,
3709 register18 | 0x8402);
3710 et131x_mii_write(adapter, PHY_DATA_REG,
3712 et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG,
3716 /* Free the packets being actively sent & stopped */
3717 et131x_free_busy_send_packets(adapter);
3719 /* Re-initialize the send structures */
3720 et131x_init_send(adapter);
3722 /* Reset the RFD list and re-start RU */
3723 et131x_reset_recv(adapter);
3726 * Bring the device back to the state it was during
3727 * init prior to autonegotiation being complete. This
3728 * way, when we get the auto-neg complete interrupt,
3729 * we can complete init by calling config_mac_regs2.
3731 et131x_soft_reset(adapter);
3733 /* Setup ET1310 as per the documentation */
3734 et131x_adapter_setup(adapter);
3736 /* perform reset of tx/rx */
3737 et131x_disable_txrx(netdev);
3738 et131x_enable_txrx(netdev);
3741 adapter->link = phydev->link;
3743 phy_print_status(phydev);
3747 static int et131x_mii_probe(struct net_device *netdev)
3749 struct et131x_adapter *adapter = netdev_priv(netdev);
3750 struct phy_device *phydev = NULL;
3752 phydev = phy_find_first(adapter->mii_bus);
3754 dev_err(&adapter->pdev->dev, "no PHY found\n");
3758 phydev = phy_connect(netdev, dev_name(&phydev->dev),
3759 &et131x_adjust_link, 0, PHY_INTERFACE_MODE_MII);
3761 if (IS_ERR(phydev)) {
3762 dev_err(&adapter->pdev->dev, "Could not attach to PHY\n");
3763 return PTR_ERR(phydev);
3766 phydev->supported &= (SUPPORTED_10baseT_Half
3767 | SUPPORTED_10baseT_Full
3768 | SUPPORTED_100baseT_Half
3769 | SUPPORTED_100baseT_Full
3774 if (adapter->pdev->device != ET131X_PCI_DEVICE_ID_FAST)
3775 phydev->supported |= SUPPORTED_1000baseT_Full;
3777 phydev->advertising = phydev->supported;
3778 adapter->phydev = phydev;
3780 dev_info(&adapter->pdev->dev, "attached PHY driver [%s] "
3781 "(mii_bus:phy_addr=%s)\n",
3782 phydev->drv->name, dev_name(&phydev->dev));
3788 * et131x_adapter_init
3789 * @adapter: pointer to the private adapter struct
3790 * @pdev: pointer to the PCI device
3792 * Initialize the data structures for the et131x_adapter object and link
3793 * them together with the platform provided device structures.
3795 static struct et131x_adapter *et131x_adapter_init(struct net_device *netdev,
3796 struct pci_dev *pdev)
3798 static const u8 default_mac[] = { 0x00, 0x05, 0x3d, 0x00, 0x02, 0x00 };
3800 struct et131x_adapter *adapter;
3802 /* Allocate private adapter struct and copy in relevant information */
3803 adapter = netdev_priv(netdev);
3804 adapter->pdev = pci_dev_get(pdev);
3805 adapter->netdev = netdev;
3807 /* Do the same for the netdev struct */
3808 netdev->irq = pdev->irq;
3809 netdev->base_addr = pci_resource_start(pdev, 0);
3811 /* Initialize spinlocks here */
3812 spin_lock_init(&adapter->lock);
3813 spin_lock_init(&adapter->tcb_send_qlock);
3814 spin_lock_init(&adapter->tcb_ready_qlock);
3815 spin_lock_init(&adapter->send_hw_lock);
3816 spin_lock_init(&adapter->rcv_lock);
3817 spin_lock_init(&adapter->rcv_pend_lock);
3818 spin_lock_init(&adapter->fbr_lock);
3819 spin_lock_init(&adapter->phy_lock);
3821 adapter->registry_jumbo_packet = 1514; /* 1514-9216 */
3823 /* Set the MAC address to a default */
3824 memcpy(adapter->addr, default_mac, ETH_ALEN);
3830 * et131x_pci_setup - Perform device initialization
3831 * @pdev: a pointer to the device's pci_dev structure
3832 * @ent: this device's entry in the pci_device_id table
3834 * Returns 0 on success, errno on failure (as defined in errno.h)
3836 * Registered in the pci_driver structure, this function is called when the
3837 * PCI subsystem finds a new PCI device which matches the information
3838 * contained in the pci_device_id table. This routine is the equivalent to
3839 * a device insertion routine.
3841 static int __devinit et131x_pci_setup(struct pci_dev *pdev,
3842 const struct pci_device_id *ent)
3846 struct net_device *netdev;
3847 struct et131x_adapter *adapter;
3850 result = pci_enable_device(pdev);
3852 dev_err(&pdev->dev, "pci_enable_device() failed\n");
3856 /* Perform some basic PCI checks */
3857 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
3858 dev_err(&pdev->dev, "Can't find PCI device's base address\n");
3862 if (pci_request_regions(pdev, DRIVER_NAME)) {
3863 dev_err(&pdev->dev, "Can't get PCI resources\n");
3867 pci_set_master(pdev);
3869 /* Query PCI for Power Mgmt Capabilities
3871 * NOTE: Now reading PowerMgmt in another location; is this still
3874 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3877 "Cannot find Power Management capabilities\n");
3879 goto err_release_res;
3882 /* Check the DMA addressing support of this device */
3883 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
3884 result = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3887 "Unable to obtain 64 bit DMA for consistent allocations\n");
3888 goto err_release_res;
3890 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
3891 result = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3894 "Unable to obtain 32 bit DMA for consistent allocations\n");
3895 goto err_release_res;
3898 dev_err(&pdev->dev, "No usable DMA addressing method\n");
3900 goto err_release_res;
3903 /* Allocate netdev and private adapter structs */
3904 netdev = et131x_device_alloc();
3906 dev_err(&pdev->dev, "Couldn't alloc netdev struct\n");
3908 goto err_release_res;
3911 SET_NETDEV_DEV(netdev, &pdev->dev);
3912 et131x_set_ethtool_ops(netdev);
3914 adapter = et131x_adapter_init(netdev, pdev);
3916 /* Initialise the PCI setup for the device */
3917 et131x_pci_init(adapter, pdev);
3919 /* Map the bus-relative registers to system virtual memory */
3920 adapter->regs = pci_ioremap_bar(pdev, 0);
3921 if (!adapter->regs) {
3922 dev_err(&pdev->dev, "Cannot map device registers\n");
3927 /* If Phy COMA mode was enabled when we went down, disable it here. */
3928 writel(ET_PMCSR_INIT, &adapter->regs->global.pm_csr);
3930 /* Issue a global reset to the et1310 */
3931 et131x_soft_reset(adapter);
3933 /* Disable all interrupts (paranoid) */
3934 et131x_disable_interrupts(adapter);
3936 /* Allocate DMA memory */
3937 result = et131x_adapter_memory_alloc(adapter);
3939 dev_err(&pdev->dev, "Could not alloc adapater memory (DMA)\n");
3943 /* Init send data structures */
3944 et131x_init_send(adapter);
3946 /* Set up the task structure for the ISR's deferred handler */
3947 INIT_WORK(&adapter->task, et131x_isr_handler);
3949 /* Copy address into the net_device struct */
3950 memcpy(netdev->dev_addr, adapter->addr, ETH_ALEN);
3952 /* Init variable for counting how long we do not have link status */
3953 adapter->boot_coma = 0;
3954 et1310_disable_phy_coma(adapter);
3956 /* Setup the mii_bus struct */
3957 adapter->mii_bus = mdiobus_alloc();
3958 if (!adapter->mii_bus) {
3959 dev_err(&pdev->dev, "Alloc of mii_bus struct failed\n");
3963 adapter->mii_bus->name = "et131x_eth_mii";
3964 snprintf(adapter->mii_bus->id, MII_BUS_ID_SIZE, "%x",
3965 (adapter->pdev->bus->number << 8) | adapter->pdev->devfn);
3966 adapter->mii_bus->priv = netdev;
3967 adapter->mii_bus->read = et131x_mdio_read;
3968 adapter->mii_bus->write = et131x_mdio_write;
3969 adapter->mii_bus->reset = et131x_mdio_reset;
3970 adapter->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
3971 if (!adapter->mii_bus->irq) {
3972 dev_err(&pdev->dev, "mii_bus irq allocation failed\n");
3976 for (ii = 0; ii < PHY_MAX_ADDR; ii++)
3977 adapter->mii_bus->irq[ii] = PHY_POLL;
3979 if (mdiobus_register(adapter->mii_bus)) {
3980 dev_err(&pdev->dev, "failed to register MII bus\n");
3981 mdiobus_free(adapter->mii_bus);
3982 goto err_mdio_free_irq;
3985 if (et131x_mii_probe(netdev)) {
3986 dev_err(&pdev->dev, "failed to probe MII bus\n");
3987 goto err_mdio_unregister;
3990 /* Setup et1310 as per the documentation */
3991 et131x_adapter_setup(adapter);
3993 /* We can enable interrupts now
3995 * NOTE - Because registration of interrupt handler is done in the
3996 * device's open(), defer enabling device interrupts to that
4000 /* Register the net_device struct with the Linux network layer */
4001 result = register_netdev(netdev);
4003 dev_err(&pdev->dev, "register_netdev() failed\n");
4004 goto err_mdio_unregister;
4007 /* Register the net_device struct with the PCI subsystem. Save a copy
4008 * of the PCI config space for this device now that the device has
4009 * been initialized, just in case it needs to be quickly restored.
4011 pci_set_drvdata(pdev, netdev);
4012 pci_save_state(adapter->pdev);
4016 err_mdio_unregister:
4017 mdiobus_unregister(adapter->mii_bus);
4019 kfree(adapter->mii_bus->irq);
4021 mdiobus_free(adapter->mii_bus);
4023 et131x_adapter_memory_free(adapter);
4025 iounmap(adapter->regs);
4028 free_netdev(netdev);
4030 pci_release_regions(pdev);
4032 pci_disable_device(pdev);
4039 * @pdev: a pointer to the device's pci_dev structure
4041 * Registered in the pci_driver structure, this function is called when the
4042 * PCI subsystem detects that a PCI device which matches the information
4043 * contained in the pci_device_id table has been removed.
4045 static void __devexit et131x_pci_remove(struct pci_dev *pdev)
4047 struct net_device *netdev = pci_get_drvdata(pdev);
4048 struct et131x_adapter *adapter = netdev_priv(netdev);
4050 unregister_netdev(netdev);
4051 mdiobus_unregister(adapter->mii_bus);
4052 kfree(adapter->mii_bus->irq);
4053 mdiobus_free(adapter->mii_bus);
4055 et131x_adapter_memory_free(adapter);
4056 iounmap(adapter->regs);
4059 free_netdev(netdev);
4060 pci_release_regions(pdev);
4061 pci_disable_device(pdev);
4064 #ifdef CONFIG_PM_SLEEP
4065 static int et131x_suspend(struct device *dev)
4067 struct pci_dev *pdev = to_pci_dev(dev);
4068 struct net_device *netdev = pci_get_drvdata(pdev);
4070 if (netif_running(netdev)) {
4071 netif_device_detach(netdev);
4072 et131x_down(netdev);
4073 pci_save_state(pdev);
4079 static int et131x_resume(struct device *dev)
4081 struct pci_dev *pdev = to_pci_dev(dev);
4082 struct net_device *netdev = pci_get_drvdata(pdev);
4084 if (netif_running(netdev)) {
4085 pci_restore_state(pdev);
4087 netif_device_attach(netdev);
4093 static SIMPLE_DEV_PM_OPS(et131x_pm_ops, et131x_suspend, et131x_resume);
4094 #define ET131X_PM_OPS (&et131x_pm_ops)
4096 #define ET131X_PM_OPS NULL
4099 static struct pci_device_id et131x_pci_table[] __devinitdata = {
4100 {ET131X_PCI_VENDOR_ID, ET131X_PCI_DEVICE_ID_GIG, PCI_ANY_ID,
4101 PCI_ANY_ID, 0, 0, 0UL},
4102 {ET131X_PCI_VENDOR_ID, ET131X_PCI_DEVICE_ID_FAST, PCI_ANY_ID,
4103 PCI_ANY_ID, 0, 0, 0UL},
4107 MODULE_DEVICE_TABLE(pci, et131x_pci_table);
4109 static struct pci_driver et131x_driver = {
4110 .name = DRIVER_NAME,
4111 .id_table = et131x_pci_table,
4112 .probe = et131x_pci_setup,
4113 .remove = __devexit_p(et131x_pci_remove),
4114 .driver.pm = ET131X_PM_OPS,
4118 * et131x_init_module - The "main" entry point called on driver initialization
4120 * Returns 0 on success, errno on failure (as defined in errno.h)
4122 static int __init et131x_init_module(void)
4124 return pci_register_driver(&et131x_driver);
4128 * et131x_cleanup_module - The entry point called on driver cleanup
4130 static void __exit et131x_cleanup_module(void)
4132 pci_unregister_driver(&et131x_driver);
4135 module_init(et131x_init_module);
4136 module_exit(et131x_cleanup_module);
4141 * et131x_enable_interrupts - enable interrupt
4142 * @adapter: et131x device
4144 * Enable the appropriate interrupts on the ET131x according to our
4147 void et131x_enable_interrupts(struct et131x_adapter *adapter)
4151 /* Enable all global interrupts */
4152 if (adapter->flowcontrol == FLOW_TXONLY ||
4153 adapter->flowcontrol == FLOW_BOTH)
4154 mask = INT_MASK_ENABLE;
4156 mask = INT_MASK_ENABLE_NO_FLOW;
4158 writel(mask, &adapter->regs->global.int_mask);
4162 * et131x_disable_interrupts - interrupt disable
4163 * @adapter: et131x device
4165 * Block all interrupts from the et131x device at the device itself
4167 void et131x_disable_interrupts(struct et131x_adapter *adapter)
4169 /* Disable all global interrupts */
4170 writel(INT_MASK_DISABLE, &adapter->regs->global.int_mask);
4175 * et131x_isr - The Interrupt Service Routine for the driver.
4176 * @irq: the IRQ on which the interrupt was received.
4177 * @dev_id: device-specific info (here a pointer to a net_device struct)
4179 * Returns a value indicating if the interrupt was handled.
4181 irqreturn_t et131x_isr(int irq, void *dev_id)
4183 bool handled = true;
4184 struct net_device *netdev = (struct net_device *)dev_id;
4185 struct et131x_adapter *adapter = NULL;
4188 if (!netif_device_present(netdev)) {
4193 adapter = netdev_priv(netdev);
4195 /* If the adapter is in low power state, then it should not
4196 * recognize any interrupt
4199 /* Disable Device Interrupts */
4200 et131x_disable_interrupts(adapter);
4202 /* Get a copy of the value in the interrupt status register
4203 * so we can process the interrupting section
4205 status = readl(&adapter->regs->global.int_status);
4207 if (adapter->flowcontrol == FLOW_TXONLY ||
4208 adapter->flowcontrol == FLOW_BOTH) {
4209 status &= ~INT_MASK_ENABLE;
4211 status &= ~INT_MASK_ENABLE_NO_FLOW;
4214 /* Make sure this is our interrupt */
4217 et131x_enable_interrupts(adapter);
4221 /* This is our interrupt, so process accordingly */
4223 if (status & ET_INTR_WATCHDOG) {
4224 struct tcb *tcb = adapter->tx_ring.send_head;
4227 if (++tcb->stale > 1)
4228 status |= ET_INTR_TXDMA_ISR;
4230 if (adapter->rx_ring.unfinished_receives)
4231 status |= ET_INTR_RXDMA_XFR_DONE;
4232 else if (tcb == NULL)
4233 writel(0, &adapter->regs->global.watchdog_timer);
4235 status &= ~ET_INTR_WATCHDOG;
4239 /* This interrupt has in some way been "handled" by
4240 * the ISR. Either it was a spurious Rx interrupt, or
4241 * it was a Tx interrupt that has been filtered by
4244 et131x_enable_interrupts(adapter);
4248 /* We need to save the interrupt status value for use in our
4249 * DPC. We will clear the software copy of that in that
4252 adapter->stats.interrupt_status = status;
4254 /* Schedule the ISR handler as a bottom-half task in the
4255 * kernel's tq_immediate queue, and mark the queue for
4258 schedule_work(&adapter->task);
4260 return IRQ_RETVAL(handled);
4264 * et131x_isr_handler - The ISR handler
4265 * @p_adapter, a pointer to the device's private adapter structure
4267 * scheduled to run in a deferred context by the ISR. This is where the ISR's
4268 * work actually gets done.
4270 void et131x_isr_handler(struct work_struct *work)
4272 struct et131x_adapter *adapter =
4273 container_of(work, struct et131x_adapter, task);
4274 u32 status = adapter->stats.interrupt_status;
4275 struct address_map __iomem *iomem = adapter->regs;
4278 * These first two are by far the most common. Once handled, we clear
4279 * their two bits in the status word. If the word is now zero, we
4282 /* Handle all the completed Transmit interrupts */
4283 if (status & ET_INTR_TXDMA_ISR)
4284 et131x_handle_send_interrupt(adapter);
4286 /* Handle all the completed Receives interrupts */
4287 if (status & ET_INTR_RXDMA_XFR_DONE)
4288 et131x_handle_recv_interrupt(adapter);
4290 status &= 0xffffffd7;
4293 /* Handle the TXDMA Error interrupt */
4294 if (status & ET_INTR_TXDMA_ERR) {
4297 /* Following read also clears the register (COR) */
4298 txdma_err = readl(&iomem->txdma.tx_dma_error);
4300 dev_warn(&adapter->pdev->dev,
4301 "TXDMA_ERR interrupt, error = %d\n",
4305 /* Handle Free Buffer Ring 0 and 1 Low interrupt */
4307 (ET_INTR_RXDMA_FB_R0_LOW | ET_INTR_RXDMA_FB_R1_LOW)) {
4309 * This indicates the number of unused buffers in
4310 * RXDMA free buffer ring 0 is <= the limit you
4311 * programmed. Free buffer resources need to be
4312 * returned. Free buffers are consumed as packets
4313 * are passed from the network to the host. The host
4314 * becomes aware of the packets from the contents of
4315 * the packet status ring. This ring is queried when
4316 * the packet done interrupt occurs. Packets are then
4317 * passed to the OS. When the OS is done with the
4318 * packets the resources can be returned to the
4319 * ET1310 for re-use. This interrupt is one method of
4320 * returning resources.
4323 /* If the user has flow control on, then we will
4324 * send a pause packet, otherwise just exit
4326 if (adapter->flowcontrol == FLOW_TXONLY ||
4327 adapter->flowcontrol == FLOW_BOTH) {
4330 /* Tell the device to send a pause packet via
4331 * the back pressure register (bp req and
4334 pm_csr = readl(&iomem->global.pm_csr);
4335 if (!et1310_in_phy_coma(adapter))
4336 writel(3, &iomem->txmac.bp_ctrl);
4340 /* Handle Packet Status Ring Low Interrupt */
4341 if (status & ET_INTR_RXDMA_STAT_LOW) {
4344 * Same idea as with the two Free Buffer Rings.
4345 * Packets going from the network to the host each
4346 * consume a free buffer resource and a packet status
4347 * resource. These resoures are passed to the OS.
4348 * When the OS is done with the resources, they need
4349 * to be returned to the ET1310. This is one method
4350 * of returning the resources.
4354 /* Handle RXDMA Error Interrupt */
4355 if (status & ET_INTR_RXDMA_ERR) {
4357 * The rxdma_error interrupt is sent when a time-out
4358 * on a request issued by the JAGCore has occurred or
4359 * a completion is returned with an un-successful
4360 * status. In both cases the request is considered
4361 * complete. The JAGCore will automatically re-try the
4362 * request in question. Normally information on events
4363 * like these are sent to the host using the "Advanced
4364 * Error Reporting" capability. This interrupt is
4365 * another way of getting similar information. The
4366 * only thing required is to clear the interrupt by
4367 * reading the ISR in the global resources. The
4368 * JAGCore will do a re-try on the request. Normally
4369 * you should never see this interrupt. If you start
4370 * to see this interrupt occurring frequently then
4371 * something bad has occurred. A reset might be the
4376 dev_warn(&adapter->pdev->dev,
4377 "RxDMA_ERR interrupt, error %x\n",
4378 readl(&iomem->txmac.tx_test));
4381 /* Handle the Wake on LAN Event */
4382 if (status & ET_INTR_WOL) {
4384 * This is a secondary interrupt for wake on LAN.
4385 * The driver should never see this, if it does,
4386 * something serious is wrong. We will TRAP the
4387 * message when we are in DBG mode, otherwise we
4390 dev_err(&adapter->pdev->dev, "WAKE_ON_LAN interrupt\n");
4393 /* Let's move on to the TxMac */
4394 if (status & ET_INTR_TXMAC) {
4395 u32 err = readl(&iomem->txmac.err);
4398 * When any of the errors occur and TXMAC generates
4399 * an interrupt to report these errors, it usually
4400 * means that TXMAC has detected an error in the data
4401 * stream retrieved from the on-chip Tx Q. All of
4402 * these errors are catastrophic and TXMAC won't be
4403 * able to recover data when these errors occur. In
4404 * a nutshell, the whole Tx path will have to be reset
4405 * and re-configured afterwards.
4407 dev_warn(&adapter->pdev->dev,
4408 "TXMAC interrupt, error 0x%08x\n",
4411 /* If we are debugging, we want to see this error,
4412 * otherwise we just want the device to be reset and
4417 /* Handle RXMAC Interrupt */
4418 if (status & ET_INTR_RXMAC) {
4420 * These interrupts are catastrophic to the device,
4421 * what we need to do is disable the interrupts and
4422 * set the flag to cause us to reset so we can solve
4425 /* MP_SET_FLAG( adapter,
4426 fMP_ADAPTER_HARDWARE_ERROR); */
4428 dev_warn(&adapter->pdev->dev,
4429 "RXMAC interrupt, error 0x%08x. Requesting reset\n",
4430 readl(&iomem->rxmac.err_reg));
4432 dev_warn(&adapter->pdev->dev,
4433 "Enable 0x%08x, Diag 0x%08x\n",
4434 readl(&iomem->rxmac.ctrl),
4435 readl(&iomem->rxmac.rxq_diag));
4438 * If we are debugging, we want to see this error,
4439 * otherwise we just want the device to be reset and
4444 /* Handle MAC_STAT Interrupt */
4445 if (status & ET_INTR_MAC_STAT) {
4447 * This means at least one of the un-masked counters
4448 * in the MAC_STAT block has rolled over. Use this
4449 * to maintain the top, software managed bits of the
4452 et1310_handle_macstat_interrupt(adapter);
4455 /* Handle SLV Timeout Interrupt */
4456 if (status & ET_INTR_SLV_TIMEOUT) {
4458 * This means a timeout has occurred on a read or
4459 * write request to one of the JAGCore registers. The
4460 * Global Resources block has terminated the request
4461 * and on a read request, returned a "fake" value.
4462 * The most likely reasons are: Bad Address or the
4463 * addressed module is in a power-down state and
4468 et131x_enable_interrupts(adapter);
4471 /* NETDEV functions */
4474 * et131x_stats - Return the current device statistics.
4475 * @netdev: device whose stats are being queried
4477 * Returns 0 on success, errno on failure (as defined in errno.h)
4479 static struct net_device_stats *et131x_stats(struct net_device *netdev)
4481 struct et131x_adapter *adapter = netdev_priv(netdev);
4482 struct net_device_stats *stats = &adapter->net_stats;
4483 struct ce_stats *devstat = &adapter->stats;
4485 stats->rx_errors = devstat->rx_length_errs +
4486 devstat->rx_align_errs +
4487 devstat->rx_crc_errs +
4488 devstat->rx_code_violations +
4489 devstat->rx_other_errs;
4490 stats->tx_errors = devstat->tx_max_pkt_errs;
4491 stats->multicast = devstat->multicast_pkts_rcvd;
4492 stats->collisions = devstat->tx_collisions;
4494 stats->rx_length_errors = devstat->rx_length_errs;
4495 stats->rx_over_errors = devstat->rx_overflows;
4496 stats->rx_crc_errors = devstat->rx_crc_errs;
4498 /* NOTE: These stats don't have corresponding values in CE_STATS,
4499 * so we're going to have to update these directly from within the
4502 /* stats->rx_bytes = 20; devstat->; */
4503 /* stats->tx_bytes = 20; devstat->; */
4504 /* stats->rx_dropped = devstat->; */
4505 /* stats->tx_dropped = devstat->; */
4507 /* NOTE: Not used, can't find analogous statistics */
4508 /* stats->rx_frame_errors = devstat->; */
4509 /* stats->rx_fifo_errors = devstat->; */
4510 /* stats->rx_missed_errors = devstat->; */
4512 /* stats->tx_aborted_errors = devstat->; */
4513 /* stats->tx_carrier_errors = devstat->; */
4514 /* stats->tx_fifo_errors = devstat->; */
4515 /* stats->tx_heartbeat_errors = devstat->; */
4516 /* stats->tx_window_errors = devstat->; */
4521 * et131x_enable_txrx - Enable tx/rx queues
4522 * @netdev: device to be enabled
4524 void et131x_enable_txrx(struct net_device *netdev)
4526 struct et131x_adapter *adapter = netdev_priv(netdev);
4528 /* Enable the Tx and Rx DMA engines (if not already enabled) */
4529 et131x_rx_dma_enable(adapter);
4530 et131x_tx_dma_enable(adapter);
4532 /* Enable device interrupts */
4533 if (adapter->flags & fMP_ADAPTER_INTERRUPT_IN_USE)
4534 et131x_enable_interrupts(adapter);
4536 /* We're ready to move some data, so start the queue */
4537 netif_start_queue(netdev);
4541 * et131x_disable_txrx - Disable tx/rx queues
4542 * @netdev: device to be disabled
4544 void et131x_disable_txrx(struct net_device *netdev)
4546 struct et131x_adapter *adapter = netdev_priv(netdev);
4548 /* First thing is to stop the queue */
4549 netif_stop_queue(netdev);
4551 /* Stop the Tx and Rx DMA engines */
4552 et131x_rx_dma_disable(adapter);
4553 et131x_tx_dma_disable(adapter);
4555 /* Disable device interrupts */
4556 et131x_disable_interrupts(adapter);
4560 * et131x_up - Bring up a device for use.
4561 * @netdev: device to be opened
4563 void et131x_up(struct net_device *netdev)
4565 struct et131x_adapter *adapter = netdev_priv(netdev);
4567 et131x_enable_txrx(netdev);
4568 phy_start(adapter->phydev);
4572 * et131x_open - Open the device for use.
4573 * @netdev: device to be opened
4575 * Returns 0 on success, errno on failure (as defined in errno.h)
4577 int et131x_open(struct net_device *netdev)
4580 struct et131x_adapter *adapter = netdev_priv(netdev);
4582 /* Start the timer to track NIC errors */
4583 init_timer(&adapter->error_timer);
4584 adapter->error_timer.expires = jiffies + TX_ERROR_PERIOD * HZ / 1000;
4585 adapter->error_timer.function = et131x_error_timer_handler;
4586 adapter->error_timer.data = (unsigned long)adapter;
4587 add_timer(&adapter->error_timer);
4589 /* Register our IRQ */
4590 result = request_irq(netdev->irq, et131x_isr, IRQF_SHARED,
4591 netdev->name, netdev);
4593 dev_err(&adapter->pdev->dev, "could not register IRQ %d\n",
4598 adapter->flags |= fMP_ADAPTER_INTERRUPT_IN_USE;
4606 * et131x_down - Bring down the device
4607 * @netdev: device to be broght down
4609 void et131x_down(struct net_device *netdev)
4611 struct et131x_adapter *adapter = netdev_priv(netdev);
4613 /* Save the timestamp for the TX watchdog, prevent a timeout */
4614 netdev->trans_start = jiffies;
4616 phy_stop(adapter->phydev);
4617 et131x_disable_txrx(netdev);
4621 * et131x_close - Close the device
4622 * @netdev: device to be closed
4624 * Returns 0 on success, errno on failure (as defined in errno.h)
4626 int et131x_close(struct net_device *netdev)
4628 struct et131x_adapter *adapter = netdev_priv(netdev);
4630 et131x_down(netdev);
4632 adapter->flags &= ~fMP_ADAPTER_INTERRUPT_IN_USE;
4633 free_irq(netdev->irq, netdev);
4635 /* Stop the error timer */
4636 return del_timer_sync(&adapter->error_timer);
4640 * et131x_ioctl - The I/O Control handler for the driver
4641 * @netdev: device on which the control request is being made
4642 * @reqbuf: a pointer to the IOCTL request buffer
4643 * @cmd: the IOCTL command code
4645 * Returns 0 on success, errno on failure (as defined in errno.h)
4647 static int et131x_ioctl(struct net_device *netdev, struct ifreq *reqbuf, int cmd)
4649 struct et131x_adapter *adapter = netdev_priv(netdev);
4651 if (!adapter->phydev)
4654 return phy_mii_ioctl(adapter->phydev, reqbuf, cmd);
4658 * et131x_set_packet_filter - Configures the Rx Packet filtering on the device
4659 * @adapter: pointer to our private adapter structure
4661 * FIXME: lot of dups with MAC code
4663 * Returns 0 on success, errno on failure
4665 static int et131x_set_packet_filter(struct et131x_adapter *adapter)
4668 uint32_t filter = adapter->packet_filter;
4672 ctrl = readl(&adapter->regs->rxmac.ctrl);
4673 pf_ctrl = readl(&adapter->regs->rxmac.pf_ctrl);
4675 /* Default to disabled packet filtering. Enable it in the individual
4676 * case statements that require the device to filter something
4680 /* Set us to be in promiscuous mode so we receive everything, this
4681 * is also true when we get a packet filter of 0
4683 if ((filter & ET131X_PACKET_TYPE_PROMISCUOUS) || filter == 0)
4684 pf_ctrl &= ~7; /* Clear filter bits */
4687 * Set us up with Multicast packet filtering. Three cases are
4688 * possible - (1) we have a multi-cast list, (2) we receive ALL
4689 * multicast entries or (3) we receive none.
4691 if (filter & ET131X_PACKET_TYPE_ALL_MULTICAST)
4692 pf_ctrl &= ~2; /* Multicast filter bit */
4694 et1310_setup_device_for_multicast(adapter);
4699 /* Set us up with Unicast packet filtering */
4700 if (filter & ET131X_PACKET_TYPE_DIRECTED) {
4701 et1310_setup_device_for_unicast(adapter);
4706 /* Set us up with Broadcast packet filtering */
4707 if (filter & ET131X_PACKET_TYPE_BROADCAST) {
4708 pf_ctrl |= 1; /* Broadcast filter bit */
4713 /* Setup the receive mac configuration registers - Packet
4714 * Filter control + the enable / disable for packet filter
4715 * in the control reg.
4717 writel(pf_ctrl, &adapter->regs->rxmac.pf_ctrl);
4718 writel(ctrl, &adapter->regs->rxmac.ctrl);
4724 * et131x_multicast - The handler to configure multicasting on the interface
4725 * @netdev: a pointer to a net_device struct representing the device
4727 static void et131x_multicast(struct net_device *netdev)
4729 struct et131x_adapter *adapter = netdev_priv(netdev);
4730 uint32_t packet_filter = 0;
4731 unsigned long flags;
4732 struct netdev_hw_addr *ha;
4735 spin_lock_irqsave(&adapter->lock, flags);
4737 /* Before we modify the platform-independent filter flags, store them
4738 * locally. This allows us to determine if anything's changed and if
4739 * we even need to bother the hardware
4741 packet_filter = adapter->packet_filter;
4743 /* Clear the 'multicast' flag locally; because we only have a single
4744 * flag to check multicast, and multiple multicast addresses can be
4745 * set, this is the easiest way to determine if more than one
4746 * multicast address is being set.
4748 packet_filter &= ~ET131X_PACKET_TYPE_MULTICAST;
4750 /* Check the net_device flags and set the device independent flags
4754 if (netdev->flags & IFF_PROMISC)
4755 adapter->packet_filter |= ET131X_PACKET_TYPE_PROMISCUOUS;
4757 adapter->packet_filter &= ~ET131X_PACKET_TYPE_PROMISCUOUS;
4759 if (netdev->flags & IFF_ALLMULTI)
4760 adapter->packet_filter |= ET131X_PACKET_TYPE_ALL_MULTICAST;
4762 if (netdev_mc_count(netdev) > NIC_MAX_MCAST_LIST)
4763 adapter->packet_filter |= ET131X_PACKET_TYPE_ALL_MULTICAST;
4765 if (netdev_mc_count(netdev) < 1) {
4766 adapter->packet_filter &= ~ET131X_PACKET_TYPE_ALL_MULTICAST;
4767 adapter->packet_filter &= ~ET131X_PACKET_TYPE_MULTICAST;
4769 adapter->packet_filter |= ET131X_PACKET_TYPE_MULTICAST;
4771 /* Set values in the private adapter struct */
4773 netdev_for_each_mc_addr(ha, netdev) {
4774 if (i == NIC_MAX_MCAST_LIST)
4776 memcpy(adapter->multicast_list[i++], ha->addr, ETH_ALEN);
4778 adapter->multicast_addr_count = i;
4780 /* Are the new flags different from the previous ones? If not, then no
4781 * action is required
4783 * NOTE - This block will always update the multicast_list with the
4784 * hardware, even if the addresses aren't the same.
4786 if (packet_filter != adapter->packet_filter) {
4787 /* Call the device's filter function */
4788 et131x_set_packet_filter(adapter);
4790 spin_unlock_irqrestore(&adapter->lock, flags);
4794 * et131x_tx - The handler to tx a packet on the device
4795 * @skb: data to be Tx'd
4796 * @netdev: device on which data is to be Tx'd
4798 * Returns 0 on success, errno on failure (as defined in errno.h)
4800 static int et131x_tx(struct sk_buff *skb, struct net_device *netdev)
4804 /* Save the timestamp for the TX timeout watchdog */
4805 netdev->trans_start = jiffies;
4807 /* Call the device-specific data Tx routine */
4808 status = et131x_send_packets(skb, netdev);
4810 /* Check status and manage the netif queue if necessary */
4812 if (status == -ENOMEM) {
4813 /* Put the queue to sleep until resources are
4816 netif_stop_queue(netdev);
4817 status = NETDEV_TX_BUSY;
4819 status = NETDEV_TX_OK;
4826 * et131x_tx_timeout - Timeout handler
4827 * @netdev: a pointer to a net_device struct representing the device
4829 * The handler called when a Tx request times out. The timeout period is
4830 * specified by the 'tx_timeo" element in the net_device structure (see
4831 * et131x_alloc_device() to see how this value is set).
4833 static void et131x_tx_timeout(struct net_device *netdev)
4835 struct et131x_adapter *adapter = netdev_priv(netdev);
4837 unsigned long flags;
4839 /* If the device is closed, ignore the timeout */
4840 if (~(adapter->flags & fMP_ADAPTER_INTERRUPT_IN_USE))
4843 /* Any nonrecoverable hardware error?
4844 * Checks adapter->flags for any failure in phy reading
4846 if (adapter->flags & fMP_ADAPTER_NON_RECOVER_ERROR)
4849 /* Hardware failure? */
4850 if (adapter->flags & fMP_ADAPTER_HARDWARE_ERROR) {
4851 dev_err(&adapter->pdev->dev, "hardware error - reset\n");
4855 /* Is send stuck? */
4856 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
4858 tcb = adapter->tx_ring.send_head;
4863 if (tcb->count > NIC_SEND_HANG_THRESHOLD) {
4864 spin_unlock_irqrestore(&adapter->tcb_send_qlock,
4867 dev_warn(&adapter->pdev->dev,
4868 "Send stuck - reset. tcb->WrIndex %x, flags 0x%08x\n",
4872 adapter->net_stats.tx_errors++;
4874 /* perform reset of tx/rx */
4875 et131x_disable_txrx(netdev);
4876 et131x_enable_txrx(netdev);
4881 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
4885 * et131x_change_mtu - The handler called to change the MTU for the device
4886 * @netdev: device whose MTU is to be changed
4887 * @new_mtu: the desired MTU
4889 * Returns 0 on success, errno on failure (as defined in errno.h)
4891 static int et131x_change_mtu(struct net_device *netdev, int new_mtu)
4894 struct et131x_adapter *adapter = netdev_priv(netdev);
4896 /* Make sure the requested MTU is valid */
4897 if (new_mtu < 64 || new_mtu > 9216)
4900 et131x_disable_txrx(netdev);
4901 et131x_handle_send_interrupt(adapter);
4902 et131x_handle_recv_interrupt(adapter);
4904 /* Set the new MTU */
4905 netdev->mtu = new_mtu;
4907 /* Free Rx DMA memory */
4908 et131x_adapter_memory_free(adapter);
4910 /* Set the config parameter for Jumbo Packet support */
4911 adapter->registry_jumbo_packet = new_mtu + 14;
4912 et131x_soft_reset(adapter);
4914 /* Alloc and init Rx DMA memory */
4915 result = et131x_adapter_memory_alloc(adapter);
4917 dev_warn(&adapter->pdev->dev,
4918 "Change MTU failed; couldn't re-alloc DMA memory\n");
4922 et131x_init_send(adapter);
4924 et131x_hwaddr_init(adapter);
4925 memcpy(netdev->dev_addr, adapter->addr, ETH_ALEN);
4927 /* Init the device with the new settings */
4928 et131x_adapter_setup(adapter);
4930 et131x_enable_txrx(netdev);
4936 * et131x_set_mac_addr - handler to change the MAC address for the device
4937 * @netdev: device whose MAC is to be changed
4938 * @new_mac: the desired MAC address
4940 * Returns 0 on success, errno on failure (as defined in errno.h)
4942 * IMPLEMENTED BY : blux http://berndlux.de 22.01.2007 21:14
4944 static int et131x_set_mac_addr(struct net_device *netdev, void *new_mac)
4947 struct et131x_adapter *adapter = netdev_priv(netdev);
4948 struct sockaddr *address = new_mac;
4952 if (adapter == NULL)
4955 /* Make sure the requested MAC is valid */
4956 if (!is_valid_ether_addr(address->sa_data))
4959 et131x_disable_txrx(netdev);
4960 et131x_handle_send_interrupt(adapter);
4961 et131x_handle_recv_interrupt(adapter);
4963 /* Set the new MAC */
4964 /* netdev->set_mac_address = &new_mac; */
4966 memcpy(netdev->dev_addr, address->sa_data, netdev->addr_len);
4968 printk(KERN_INFO "%s: Setting MAC address to %pM\n",
4969 netdev->name, netdev->dev_addr);
4971 /* Free Rx DMA memory */
4972 et131x_adapter_memory_free(adapter);
4974 et131x_soft_reset(adapter);
4976 /* Alloc and init Rx DMA memory */
4977 result = et131x_adapter_memory_alloc(adapter);
4979 dev_err(&adapter->pdev->dev,
4980 "Change MAC failed; couldn't re-alloc DMA memory\n");
4984 et131x_init_send(adapter);
4986 et131x_hwaddr_init(adapter);
4988 /* Init the device with the new settings */
4989 et131x_adapter_setup(adapter);
4991 et131x_enable_txrx(netdev);
4996 static const struct net_device_ops et131x_netdev_ops = {
4997 .ndo_open = et131x_open,
4998 .ndo_stop = et131x_close,
4999 .ndo_start_xmit = et131x_tx,
5000 .ndo_set_multicast_list = et131x_multicast,
5001 .ndo_tx_timeout = et131x_tx_timeout,
5002 .ndo_change_mtu = et131x_change_mtu,
5003 .ndo_set_mac_address = et131x_set_mac_addr,
5004 .ndo_validate_addr = eth_validate_addr,
5005 .ndo_get_stats = et131x_stats,
5006 .ndo_do_ioctl = et131x_ioctl,
5010 * et131x_device_alloc
5012 * Returns pointer to the allocated and initialized net_device struct for
5015 * Create instances of net_device and wl_private for the new adapter and
5016 * register the device's entry points in the net_device structure.
5018 struct net_device *et131x_device_alloc(void)
5020 struct net_device *netdev;
5022 /* Alloc net_device and adapter structs */
5023 netdev = alloc_etherdev(sizeof(struct et131x_adapter));
5026 printk(KERN_ERR "et131x: Alloc of net_device struct failed\n");
5031 * Setup the function registration table (and other data) for a
5034 netdev->watchdog_timeo = ET131X_TX_TIMEOUT;
5035 netdev->netdev_ops = &et131x_netdev_ops;
5038 /* netdev->poll = &et131x_poll; */
5039 /* netdev->poll_controller = &et131x_poll_controller; */