drivers/staging/fbtft/fb_ra8875.c

   1 /******************************************************************************
   2
   3   ProjectName: FBTFT driver                       ***** *****
   4                for the RA8875 LCD Controller     *     *      ************
   5                                                 *   **   **   *           *
   6   Copyright © by Pf@nne & NOTRO                *   *   *   *   *   ****    *
   7                                                 *   *       *   *   *   *   *
   8   Last modification by:                        *   *       *   *   ****    *
   9   - Pf@nne (pf@nne-mail.de)                     *   *     *****           *
  10                                                  *   *        *   *******
  11                                                   *****      *   *
  12   Date    : 10.06.2014                                      *   *
  13   Version : V1.13                                          *****
  14   Revision : 5
  15
  16 *******************************************************************************
  17  * This program is free software; you can redistribute it and/or modify
  18  * it under the terms of the GNU General Public License as published by
  19  * the Free Software Foundation; either version 2 of the License, or
  20  * (at your option) any later version.
  21  *
  22  * This program is distributed in the hope that it will be useful,
  23  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  25  * GNU General Public License for more details.
  26  *
  27  * You should have received a copy of the GNU General Public License
  28  * along with this program; if not, write to the Free Software
  29  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  30  */
  31
  32 #include <linux/module.h>
  33 #include <linux/kernel.h>
  34 #include <linux/init.h>
  35 #include <linux/delay.h>
  36
  37 #include <linux/gpio.h>
  38 #include "fbtft.h"
  39
  40 #define DRVNAME "fb_ra8875"
  41
  42 static int write_spi(struct fbtft_par *par, void *buf, size_t len)
  43 {
  44         struct spi_transfer t = {
  45                 .tx_buf = buf,
  46                 .len = len,
  47                 .speed_hz = 1000000,
  48         };
  49         struct spi_message m;
  50
  51         fbtft_par_dbg_hex(DEBUG_WRITE, par, par->info->device, u8, buf, len,
  52                 "%s(len=%d): ", __func__, len);
  53
  54         if (!par->spi) {
  55                 dev_err(par->info->device,
  56                         "%s: par->spi is unexpectedly NULL\n", __func__);
  57                 return -1;
  58         }
  59
  60         spi_message_init(&m);
  61         if (par->txbuf.dma && buf == par->txbuf.buf) {
  62                 t.tx_dma = par->txbuf.dma;
  63                 m.is_dma_mapped = 1;
  64         }
  65         spi_message_add_tail(&t, &m);
  66         return spi_sync(par->spi, &m);
  67 }
  68
  69 static int init_display(struct fbtft_par *par)
  70 {
  71         gpio_set_value(par->gpio.dc, 1);
  72
  73         fbtft_par_dbg(DEBUG_INIT_DISPLAY, par,
  74                 "%s()\n", __func__);
  75         fbtft_par_dbg(DEBUG_INIT_DISPLAY, par,
  76                 "display size %dx%d\n",
  77                 par->info->var.xres,
  78                 par->info->var.yres);
  79
  80         par->fbtftops.reset(par);
  81
  82         if ((par->info->var.xres == 320) && (par->info->var.yres == 240)) {
  83                 /* PLL clock frequency */
  84                 write_reg(par, 0x88, 0x0A);
  85                 write_reg(par, 0x89, 0x02);
  86                 mdelay(10);
  87                 /* color deep / MCU Interface */
  88                 write_reg(par, 0x10, 0x0C);
  89                 /* pixel clock period  */
  90                 write_reg(par, 0x04, 0x03);
  91                 mdelay(1);
  92                 /* horizontal settings */
  93                 write_reg(par, 0x14, 0x27);
  94                 write_reg(par, 0x15, 0x00);
  95                 write_reg(par, 0x16, 0x05);
  96                 write_reg(par, 0x17, 0x04);
  97                 write_reg(par, 0x18, 0x03);
  98                 /* vertical settings */
  99                 write_reg(par, 0x19, 0xEF);
 100                 write_reg(par, 0x1A, 0x00);
 101                 write_reg(par, 0x1B, 0x05);
 102                 write_reg(par, 0x1C, 0x00);
 103                 write_reg(par, 0x1D, 0x0E);
 104                 write_reg(par, 0x1E, 0x00);
 105                 write_reg(par, 0x1F, 0x02);
 106         } else if ((par->info->var.xres == 480) &&
 107                    (par->info->var.yres == 272)) {
 108                 /* PLL clock frequency  */
 109                 write_reg(par, 0x88, 0x0A);
 110                 write_reg(par, 0x89, 0x02);
 111                 mdelay(10);
 112                 /* color deep / MCU Interface */
 113                 write_reg(par, 0x10, 0x0C);
 114                 /* pixel clock period  */
 115                 write_reg(par, 0x04, 0x82);
 116                 mdelay(1);
 117                 /* horizontal settings */
 118                 write_reg(par, 0x14, 0x3B);
 119                 write_reg(par, 0x15, 0x00);
 120                 write_reg(par, 0x16, 0x01);
 121                 write_reg(par, 0x17, 0x00);
 122                 write_reg(par, 0x18, 0x05);
 123                 /* vertical settings */
 124                 write_reg(par, 0x19, 0x0F);
 125                 write_reg(par, 0x1A, 0x01);
 126                 write_reg(par, 0x1B, 0x02);
 127                 write_reg(par, 0x1C, 0x00);
 128                 write_reg(par, 0x1D, 0x07);
 129                 write_reg(par, 0x1E, 0x00);
 130                 write_reg(par, 0x1F, 0x09);
 131         } else if ((par->info->var.xres == 640) &&
 132                    (par->info->var.yres == 480)) {
 133                 /* PLL clock frequency */
 134                 write_reg(par, 0x88, 0x0B);
 135                 write_reg(par, 0x89, 0x02);
 136                 mdelay(10);
 137                 /* color deep / MCU Interface */
 138                 write_reg(par, 0x10, 0x0C);
 139                 /* pixel clock period */
 140                 write_reg(par, 0x04, 0x01);
 141                 mdelay(1);
 142                 /* horizontal settings */
 143                 write_reg(par, 0x14, 0x4F);
 144                 write_reg(par, 0x15, 0x05);
 145                 write_reg(par, 0x16, 0x0F);
 146                 write_reg(par, 0x17, 0x01);
 147                 write_reg(par, 0x18, 0x00);
 148                 /* vertical settings */
 149                 write_reg(par, 0x19, 0xDF);
 150                 write_reg(par, 0x1A, 0x01);
 151                 write_reg(par, 0x1B, 0x0A);
 152                 write_reg(par, 0x1C, 0x00);
 153                 write_reg(par, 0x1D, 0x0E);
 154                 write_reg(par, 0x1E, 0x00);
 155                 write_reg(par, 0x1F, 0x01);
 156         } else if ((par->info->var.xres == 800) &&
 157                    (par->info->var.yres == 480)) {
 158                 /* PLL clock frequency */
 159                 write_reg(par, 0x88, 0x0B);
 160                 write_reg(par, 0x89, 0x02);
 161                 mdelay(10);
 162                 /* color deep / MCU Interface */
 163                 write_reg(par, 0x10, 0x0C);
 164                 /* pixel clock period */
 165                 write_reg(par, 0x04, 0x81);
 166                 mdelay(1);
 167                 /* horizontal settings */
 168                 write_reg(par, 0x14, 0x63);
 169                 write_reg(par, 0x15, 0x03);
 170                 write_reg(par, 0x16, 0x03);
 171                 write_reg(par, 0x17, 0x02);
 172                 write_reg(par, 0x18, 0x00);
 173                 /* vertical settings */
 174                 write_reg(par, 0x19, 0xDF);
 175                 write_reg(par, 0x1A, 0x01);
 176                 write_reg(par, 0x1B, 0x14);
 177                 write_reg(par, 0x1C, 0x00);
 178                 write_reg(par, 0x1D, 0x06);
 179                 write_reg(par, 0x1E, 0x00);
 180                 write_reg(par, 0x1F, 0x01);
 181         } else {
 182                 dev_err(par->info->device, "display size is not supported!!");
 183                 return -1;
 184         }
 185
 186         /* PWM clock */
 187         write_reg(par, 0x8a, 0x81);
 188         write_reg(par, 0x8b, 0xFF);
 189         mdelay(10);
 190
 191         /* Display ON */
 192         write_reg(par, 0x01, 0x80);
 193         mdelay(10);
 194
 195         return 0;
 196 }
 197
 198 static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
 199 {
 200         fbtft_par_dbg(DEBUG_SET_ADDR_WIN, par,
 201                 "%s(xs=%d, ys=%d, xe=%d, ye=%d)\n", __func__, xs, ys, xe, ye);
 202
 203         /* Set_Active_Window */
 204         write_reg(par, 0x30, xs & 0x00FF);
 205         write_reg(par, 0x31, (xs & 0xFF00) >> 8);
 206         write_reg(par, 0x32, ys & 0x00FF);
 207         write_reg(par, 0x33, (ys & 0xFF00) >> 8);
 208         write_reg(par, 0x34, (xs+xe) & 0x00FF);
 209         write_reg(par, 0x35, ((xs+xe) & 0xFF00) >> 8);
 210         write_reg(par, 0x36, (ys+ye) & 0x00FF);
 211         write_reg(par, 0x37, ((ys+ye) & 0xFF00) >> 8);
 212
 213         /* Set_Memory_Write_Cursor */
 214         write_reg(par, 0x46,  xs & 0xff);
 215         write_reg(par, 0x47, (xs >> 8) & 0x03);
 216         write_reg(par, 0x48,  ys & 0xff);
 217         write_reg(par, 0x49, (ys >> 8) & 0x01);
 218
 219         write_reg(par, 0x02);
 220 }
 221
 222 static void write_reg8_bus8(struct fbtft_par *par, int len, ...)
 223 {
 224         va_list args;
 225         int i, ret;
 226         u8 *buf = (u8 *)par->buf;
 227
 228         /* slow down spi-speed for writing registers */
 229         par->fbtftops.write = write_spi;
 230
 231         if (unlikely(par->debug & DEBUG_WRITE_REGISTER)) {
 232                 va_start(args, len);
 233                 for (i = 0; i < len; i++)
 234                         buf[i] = (u8)va_arg(args, unsigned int);
 235                 va_end(args);
 236                 fbtft_par_dbg_hex(DEBUG_WRITE_REGISTER, par, par->info->device,
 237                         u8, buf, len, "%s: ", __func__);
 238         }
 239
 240         va_start(args, len);
 241         *buf++ = 0x80;
 242         *buf = (u8)va_arg(args, unsigned int);
 243         ret = par->fbtftops.write(par, par->buf, 2);
 244         if (ret < 0) {
 245                 va_end(args);
 246                 dev_err(par->info->device, "write() failed and returned %dn",
 247                         ret);
 248                 return;
 249         }
 250         len--;
 251
 252         udelay(100);
 253
 254         if (len) {
 255                 buf = (u8 *)par->buf;
 256                 *buf++ = 0x00;
 257                 i = len;
 258                 while (i--)
 259                         *buf++ = (u8)va_arg(args, unsigned int);
 260
 261                 ret = par->fbtftops.write(par, par->buf, len + 1);
 262                 if (ret < 0) {
 263                         va_end(args);
 264                         dev_err(par->info->device,
 265                                 "write() failed and returned %dn", ret);
 266                         return;
 267                 }
 268         }
 269         va_end(args);
 270
 271         /* restore user spi-speed */
 272         par->fbtftops.write = fbtft_write_spi;
 273         udelay(100);
 274 }
 275
 276 static int write_vmem16_bus8(struct fbtft_par *par, size_t offset, size_t len)
 277 {
 278         u16 *vmem16;
 279         u16 *txbuf16 = (u16 *)par->txbuf.buf;
 280         size_t remain;
 281         size_t to_copy;
 282         size_t tx_array_size;
 283         int i;
 284         int ret = 0;
 285         size_t startbyte_size = 0;
 286
 287         fbtft_par_dbg(DEBUG_WRITE_VMEM, par, "%s(offset=%zu, len=%zu)\n",
 288                 __func__, offset, len);
 289
 290         remain = len / 2;
 291         vmem16 = (u16 *)(par->info->screen_base + offset);
 292         tx_array_size = par->txbuf.len / 2;
 293                 txbuf16 = (u16 *)(par->txbuf.buf + 1);
 294                 tx_array_size -= 2;
 295                 *(u8 *)(par->txbuf.buf) = 0x00;
 296                 startbyte_size = 1;
 297
 298         while (remain) {
 299                 to_copy = remain > tx_array_size ? tx_array_size : remain;
 300                 dev_dbg(par->info->device, "    to_copy=%zu, remain=%zu\n",
 301                         to_copy, remain - to_copy);
 302
 303                 for (i = 0; i < to_copy; i++)
 304                         txbuf16[i] = cpu_to_be16(vmem16[i]);
 305
 306                 vmem16 = vmem16 + to_copy;
 307                 ret = par->fbtftops.write(par, par->txbuf.buf,
 308                         startbyte_size + to_copy * 2);
 309                 if (ret < 0)
 310                         return ret;
 311                 remain -= to_copy;
 312         }
 313
 314         return ret;
 315 }
 316
 317 static struct fbtft_display display = {
 318         .regwidth = 8,
 319         .fbtftops = {
 320                 .init_display = init_display,
 321                 .set_addr_win = set_addr_win,
 322                 .write_register = write_reg8_bus8,
 323                 .write_vmem = write_vmem16_bus8,
 324                 .write = write_spi,
 325         },
 326 };
 327 FBTFT_REGISTER_DRIVER(DRVNAME, "raio,ra8875", &display);
 328
 329 MODULE_ALIAS("spi:" DRVNAME);
 330 MODULE_ALIAS("platform:" DRVNAME);
 331 MODULE_ALIAS("spi:ra8875");
 332 MODULE_ALIAS("platform:ra8875");
 333
 334 MODULE_DESCRIPTION("FB driver for the RA8875 LCD Controller");
 335 MODULE_AUTHOR("Pf@nne");
 336 MODULE_LICENSE("GPL");