2 * AD9832 SPI DDS driver
4 * Copyright 2011 Analog Devices Inc.
6 * Licensed under the GPL-2.
9 #include <linux/device.h>
10 #include <linux/kernel.h>
11 #include <linux/slab.h>
12 #include <linux/sysfs.h>
13 #include <linux/spi/spi.h>
14 #include <linux/regulator/consumer.h>
15 #include <linux/err.h>
16 #include <linux/module.h>
17 #include <asm/div64.h>
25 static unsigned long ad9832_calc_freqreg(unsigned long mclk, unsigned long fout)
27 unsigned long long freqreg = (u64) fout *
28 (u64) ((u64) 1L << AD9832_FREQ_BITS);
29 do_div(freqreg, mclk);
33 static int ad9832_write_frequency(struct ad9832_state *st,
34 unsigned addr, unsigned long fout)
38 if (fout > (st->mclk / 2))
41 regval = ad9832_calc_freqreg(st->mclk, fout);
43 st->freq_data[0] = cpu_to_be16((AD9832_CMD_FRE8BITSW << CMD_SHIFT) |
45 ((regval >> 24) & 0xFF));
46 st->freq_data[1] = cpu_to_be16((AD9832_CMD_FRE16BITSW << CMD_SHIFT) |
47 ((addr - 1) << ADD_SHIFT) |
48 ((regval >> 16) & 0xFF));
49 st->freq_data[2] = cpu_to_be16((AD9832_CMD_FRE8BITSW << CMD_SHIFT) |
50 ((addr - 2) << ADD_SHIFT) |
51 ((regval >> 8) & 0xFF));
52 st->freq_data[3] = cpu_to_be16((AD9832_CMD_FRE16BITSW << CMD_SHIFT) |
53 ((addr - 3) << ADD_SHIFT) |
54 ((regval >> 0) & 0xFF));
56 return spi_sync(st->spi, &st->freq_msg);
59 static int ad9832_write_phase(struct ad9832_state *st,
60 unsigned long addr, unsigned long phase)
62 if (phase > (1 << AD9832_PHASE_BITS))
65 st->phase_data[0] = cpu_to_be16((AD9832_CMD_PHA8BITSW << CMD_SHIFT) |
67 ((phase >> 8) & 0xFF));
68 st->phase_data[1] = cpu_to_be16((AD9832_CMD_PHA16BITSW << CMD_SHIFT) |
69 ((addr - 1) << ADD_SHIFT) |
72 return spi_sync(st->spi, &st->phase_msg);
75 static ssize_t ad9832_write(struct device *dev,
76 struct device_attribute *attr,
80 struct iio_dev *indio_dev = dev_get_drvdata(dev);
81 struct ad9832_state *st = iio_priv(indio_dev);
82 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
86 ret = strict_strtoul(buf, 10, &val);
90 mutex_lock(&indio_dev->mlock);
91 switch ((u32) this_attr->address) {
94 ret = ad9832_write_frequency(st, this_attr->address, val);
100 ret = ad9832_write_phase(st, this_attr->address, val);
102 case AD9832_PINCTRL_EN:
104 st->ctrl_ss &= ~AD9832_SELSRC;
106 st->ctrl_ss |= AD9832_SELSRC;
107 st->data = cpu_to_be16((AD9832_CMD_SYNCSELSRC << CMD_SHIFT) |
109 ret = spi_sync(st->spi, &st->msg);
111 case AD9832_FREQ_SYM:
113 st->ctrl_fp |= AD9832_FREQ;
115 st->ctrl_fp &= ~AD9832_FREQ;
120 st->data = cpu_to_be16((AD9832_CMD_FPSELECT << CMD_SHIFT) |
122 ret = spi_sync(st->spi, &st->msg);
124 case AD9832_PHASE_SYM:
125 if (val < 0 || val > 3) {
130 st->ctrl_fp &= ~AD9832_PHASE(3);
131 st->ctrl_fp |= AD9832_PHASE(val);
133 st->data = cpu_to_be16((AD9832_CMD_FPSELECT << CMD_SHIFT) |
135 ret = spi_sync(st->spi, &st->msg);
137 case AD9832_OUTPUT_EN:
139 st->ctrl_src &= ~(AD9832_RESET | AD9832_SLEEP |
142 st->ctrl_src |= AD9832_RESET;
144 st->data = cpu_to_be16((AD9832_CMD_SLEEPRESCLR << CMD_SHIFT) |
146 ret = spi_sync(st->spi, &st->msg);
151 mutex_unlock(&indio_dev->mlock);
154 return ret ? ret : len;
158 * see dds.h for further information
161 static IIO_DEV_ATTR_FREQ(0, 0, S_IWUSR, NULL, ad9832_write, AD9832_FREQ0HM);
162 static IIO_DEV_ATTR_FREQ(0, 1, S_IWUSR, NULL, ad9832_write, AD9832_FREQ1HM);
163 static IIO_DEV_ATTR_FREQSYMBOL(0, S_IWUSR, NULL, ad9832_write, AD9832_FREQ_SYM);
164 static IIO_CONST_ATTR_FREQ_SCALE(0, "1"); /* 1Hz */
166 static IIO_DEV_ATTR_PHASE(0, 0, S_IWUSR, NULL, ad9832_write, AD9832_PHASE0H);
167 static IIO_DEV_ATTR_PHASE(0, 1, S_IWUSR, NULL, ad9832_write, AD9832_PHASE1H);
168 static IIO_DEV_ATTR_PHASE(0, 2, S_IWUSR, NULL, ad9832_write, AD9832_PHASE2H);
169 static IIO_DEV_ATTR_PHASE(0, 3, S_IWUSR, NULL, ad9832_write, AD9832_PHASE3H);
170 static IIO_DEV_ATTR_PHASESYMBOL(0, S_IWUSR, NULL,
171 ad9832_write, AD9832_PHASE_SYM);
172 static IIO_CONST_ATTR_PHASE_SCALE(0, "0.0015339808"); /* 2PI/2^12 rad*/
174 static IIO_DEV_ATTR_PINCONTROL_EN(0, S_IWUSR, NULL,
175 ad9832_write, AD9832_PINCTRL_EN);
176 static IIO_DEV_ATTR_OUT_ENABLE(0, S_IWUSR, NULL,
177 ad9832_write, AD9832_OUTPUT_EN);
179 static struct attribute *ad9832_attributes[] = {
180 &iio_dev_attr_dds0_freq0.dev_attr.attr,
181 &iio_dev_attr_dds0_freq1.dev_attr.attr,
182 &iio_const_attr_dds0_freq_scale.dev_attr.attr,
183 &iio_dev_attr_dds0_phase0.dev_attr.attr,
184 &iio_dev_attr_dds0_phase1.dev_attr.attr,
185 &iio_dev_attr_dds0_phase2.dev_attr.attr,
186 &iio_dev_attr_dds0_phase3.dev_attr.attr,
187 &iio_const_attr_dds0_phase_scale.dev_attr.attr,
188 &iio_dev_attr_dds0_pincontrol_en.dev_attr.attr,
189 &iio_dev_attr_dds0_freqsymbol.dev_attr.attr,
190 &iio_dev_attr_dds0_phasesymbol.dev_attr.attr,
191 &iio_dev_attr_dds0_out_enable.dev_attr.attr,
195 static const struct attribute_group ad9832_attribute_group = {
196 .attrs = ad9832_attributes,
199 static const struct iio_info ad9832_info = {
200 .attrs = &ad9832_attribute_group,
201 .driver_module = THIS_MODULE,
204 static int __devinit ad9832_probe(struct spi_device *spi)
206 struct ad9832_platform_data *pdata = spi->dev.platform_data;
207 struct iio_dev *indio_dev;
208 struct ad9832_state *st;
209 struct regulator *reg;
213 dev_dbg(&spi->dev, "no platform data?\n");
217 reg = regulator_get(&spi->dev, "vcc");
219 ret = regulator_enable(reg);
224 indio_dev = iio_allocate_device(sizeof(*st));
225 if (indio_dev == NULL) {
227 goto error_disable_reg;
229 spi_set_drvdata(spi, indio_dev);
230 st = iio_priv(indio_dev);
232 st->mclk = pdata->mclk;
235 indio_dev->dev.parent = &spi->dev;
236 indio_dev->name = spi_get_device_id(spi)->name;
237 indio_dev->info = &ad9832_info;
238 indio_dev->modes = INDIO_DIRECT_MODE;
240 /* Setup default messages */
242 st->xfer.tx_buf = &st->data;
245 spi_message_init(&st->msg);
246 spi_message_add_tail(&st->xfer, &st->msg);
248 st->freq_xfer[0].tx_buf = &st->freq_data[0];
249 st->freq_xfer[0].len = 2;
250 st->freq_xfer[0].cs_change = 1;
251 st->freq_xfer[1].tx_buf = &st->freq_data[1];
252 st->freq_xfer[1].len = 2;
253 st->freq_xfer[1].cs_change = 1;
254 st->freq_xfer[2].tx_buf = &st->freq_data[2];
255 st->freq_xfer[2].len = 2;
256 st->freq_xfer[2].cs_change = 1;
257 st->freq_xfer[3].tx_buf = &st->freq_data[3];
258 st->freq_xfer[3].len = 2;
260 spi_message_init(&st->freq_msg);
261 spi_message_add_tail(&st->freq_xfer[0], &st->freq_msg);
262 spi_message_add_tail(&st->freq_xfer[1], &st->freq_msg);
263 spi_message_add_tail(&st->freq_xfer[2], &st->freq_msg);
264 spi_message_add_tail(&st->freq_xfer[3], &st->freq_msg);
266 st->phase_xfer[0].tx_buf = &st->phase_data[0];
267 st->phase_xfer[0].len = 2;
268 st->phase_xfer[0].cs_change = 1;
269 st->phase_xfer[1].tx_buf = &st->phase_data[1];
270 st->phase_xfer[1].len = 2;
272 spi_message_init(&st->phase_msg);
273 spi_message_add_tail(&st->phase_xfer[0], &st->phase_msg);
274 spi_message_add_tail(&st->phase_xfer[1], &st->phase_msg);
276 st->ctrl_src = AD9832_SLEEP | AD9832_RESET | AD9832_CLR;
277 st->data = cpu_to_be16((AD9832_CMD_SLEEPRESCLR << CMD_SHIFT) |
279 ret = spi_sync(st->spi, &st->msg);
281 dev_err(&spi->dev, "device init failed\n");
282 goto error_free_device;
285 ret = ad9832_write_frequency(st, AD9832_FREQ0HM, pdata->freq0);
287 goto error_free_device;
289 ret = ad9832_write_frequency(st, AD9832_FREQ1HM, pdata->freq1);
291 goto error_free_device;
293 ret = ad9832_write_phase(st, AD9832_PHASE0H, pdata->phase0);
295 goto error_free_device;
297 ret = ad9832_write_phase(st, AD9832_PHASE1H, pdata->phase1);
299 goto error_free_device;
301 ret = ad9832_write_phase(st, AD9832_PHASE2H, pdata->phase2);
303 goto error_free_device;
305 ret = ad9832_write_phase(st, AD9832_PHASE3H, pdata->phase3);
307 goto error_free_device;
309 ret = iio_device_register(indio_dev);
311 goto error_free_device;
316 iio_free_device(indio_dev);
319 regulator_disable(reg);
327 static int __devexit ad9832_remove(struct spi_device *spi)
329 struct iio_dev *indio_dev = spi_get_drvdata(spi);
330 struct ad9832_state *st = iio_priv(indio_dev);
332 iio_device_unregister(indio_dev);
333 if (!IS_ERR(st->reg)) {
334 regulator_disable(st->reg);
335 regulator_put(st->reg);
337 iio_free_device(indio_dev);
342 static const struct spi_device_id ad9832_id[] = {
348 static struct spi_driver ad9832_driver = {
351 .bus = &spi_bus_type,
352 .owner = THIS_MODULE,
354 .probe = ad9832_probe,
355 .remove = __devexit_p(ad9832_remove),
356 .id_table = ad9832_id,
359 static int __init ad9832_init(void)
361 return spi_register_driver(&ad9832_driver);
363 module_init(ad9832_init);
365 static void __exit ad9832_exit(void)
367 spi_unregister_driver(&ad9832_driver);
369 module_exit(ad9832_exit);
371 MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
372 MODULE_DESCRIPTION("Analog Devices AD9832/AD9835 DDS");
373 MODULE_LICENSE("GPL v2");
374 MODULE_ALIAS("spi:ad9832");