drivers/staging/imgtec/apollo/adf_pdp.c

   1 /* -*- mode: c; indent-tabs-mode: t; c-basic-offset: 8; tab-width: 8 -*- */
   2 /* vi: set ts=8 sw=8 sts=8: */
   3 /*************************************************************************/ /*!
   4 @File           adf_pdp.c
   5 @Codingstyle    LinuxKernel
   6 @Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
   7 @License        Dual MIT/GPLv2
   8
   9 The contents of this file are subject to the MIT license as set out below.
  10
  11 Permission is hereby granted, free of charge, to any person obtaining a copy
  12 of this software and associated documentation files (the "Software"), to deal
  13 in the Software without restriction, including without limitation the rights
  14 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  15 copies of the Software, and to permit persons to whom the Software is
  16 furnished to do so, subject to the following conditions:
  17
  18 The above copyright notice and this permission notice shall be included in
  19 all copies or substantial portions of the Software.
  20
  21 Alternatively, the contents of this file may be used under the terms of
  22 the GNU General Public License Version 2 ("GPL") in which case the provisions
  23 of GPL are applicable instead of those above.
  24
  25 If you wish to allow use of your version of this file only under the terms of
  26 GPL, and not to allow others to use your version of this file under the terms
  27 of the MIT license, indicate your decision by deleting the provisions above
  28 and replace them with the notice and other provisions required by GPL as set
  29 out in the file called "GPL-COPYING" included in this distribution. If you do
  30 not delete the provisions above, a recipient may use your version of this file
  31 under the terms of either the MIT license or GPL.
  32
  33 This License is also included in this distribution in the file called
  34 "MIT-COPYING".
  35
  36 EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
  37 PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
  38 BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
  39 PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
  40 COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  41 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  42 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  43 */ /**************************************************************************/
  44
  45 /*
  46  * This is an example ADF display driver for the testchip's PDP output
  47  */
  48
  49 /* #define SUPPORT_ADF_PDP_FBDEV */
  50
  51 #include <linux/module.h>
  52 #include <linux/device.h>
  53 #include <linux/pci.h>
  54 #include <linux/interrupt.h>
  55 #include <linux/delay.h>
  56 #include <linux/platform_device.h>
  57 #include <linux/wait.h>
  58
  59 #include <drm/drm_fourcc.h>
  60
  61 #include <video/adf.h>
  62 #include <video/adf_client.h>
  63
  64 #ifdef SUPPORT_ADF_PDP_FBDEV
  65 #include <video/adf_fbdev.h>
  66 #endif
  67
  68 #include PVR_ANDROID_ION_HEADER
  69
  70 /* for sync_fence_put */
  71 #include PVR_ANDROID_SYNC_HEADER
  72
  73 #include "apollo_drv.h"
  74 #include "adf_common.h"
  75 #include "debugfs_dma_buf.h"
  76
  77 #include "pdp_regs.h"
  78 #include "tcf_rgbpdp_regs.h"
  79 #include "tcf_pll.h"
  80
  81 #include "pvrmodule.h"
  82
  83 #define DRV_NAME APOLLO_DEVICE_NAME_PDP
  84
  85 #ifndef ADF_PDP_WIDTH
  86 #define ADF_PDP_WIDTH 1280
  87 #endif
  88
  89 #ifndef ADF_PDP_HEIGHT
  90 #define ADF_PDP_HEIGHT 720
  91 #endif
  92
  93 MODULE_DESCRIPTION("APOLLO PDP display driver");
  94
  95 static int pdp_display_width = ADF_PDP_WIDTH;
  96 static int pdp_display_height = ADF_PDP_HEIGHT;
  97 module_param(pdp_display_width, int, S_IRUSR | S_IRGRP | S_IROTH);
  98 MODULE_PARM_DESC(pdp_display_width, "PDP display width");
  99 module_param(pdp_display_height, int, S_IRUSR | S_IRGRP | S_IROTH);
 100 MODULE_PARM_DESC(pdp_display_height, "PDP display height");
 101
 102 static DEFINE_SPINLOCK(gFlipLock);
 103
 104 struct pdp_timing_data {
 105         u32 h_display;
 106         u32 h_back_porch;
 107         u32 h_total;
 108         u32 h_active_start;
 109         u32 h_left_border;
 110         u32 h_right_border;
 111         u32 h_front_porch;
 112
 113         u32 v_display;
 114         u32 v_back_porch;
 115         u32 v_total;
 116         u32 v_active_start;
 117         u32 v_top_border;
 118         u32 v_bottom_border;
 119         u32 v_front_porch;
 120         u32 v_refresh;
 121         u32 clock_freq;
 122 };
 123
 124 static const struct pdp_timing_data pdp_supported_modes[] = {
 125         {
 126                 .h_display              =       640,
 127                 .h_back_porch           =       64,
 128                 .h_total                =       800,
 129                 .h_active_start         =       144,
 130                 .h_left_border          =       144,
 131                 .h_right_border         =       784,
 132                 .h_front_porch          =       784,
 133
 134                 .v_display              =       480,
 135                 .v_back_porch           =       7,
 136                 .v_total                =       497,
 137                 .v_active_start         =       16,
 138                 .v_top_border           =       16,
 139                 .v_bottom_border        =       496,
 140                 .v_front_porch          =       496,
 141
 142                 .v_refresh              =       60,
 143                 .clock_freq             =       23856000,
 144         },
 145         {
 146                 .h_display              =       800,
 147                 .h_back_porch           =       80,
 148                 .h_total                =       1024,
 149                 .h_active_start         =       192,
 150                 .h_left_border          =       192,
 151                 .h_right_border         =       992,
 152                 .h_front_porch          =       992,
 153
 154                 .v_display              =       600,
 155                 .v_back_porch           =       7,
 156                 .v_total                =       621,
 157                 .v_active_start         =       20,
 158                 .v_top_border           =       20,
 159                 .v_bottom_border        =       620,
 160                 .v_front_porch          =       620,
 161
 162                 .v_refresh              =       60,
 163                 .clock_freq             =       38154000,
 164         },
 165         {
 166                 .h_display              =       1024,
 167                 .h_back_porch           =       104,
 168                 .h_total                =       1344,
 169                 .h_active_start         =       264,
 170                 .h_left_border          =       264,
 171                 .h_right_border         =       1288,
 172                 .h_front_porch          =       1288,
 173
 174                 .v_display              =       768,
 175                 .v_back_porch           =       7,
 176                 .v_total                =       795,
 177                 .v_active_start         =       26,
 178                 .v_top_border           =       26,
 179                 .v_bottom_border        =       794,
 180                 .v_front_porch          =       794,
 181
 182                 .v_refresh              =       59,
 183                 .clock_freq             =       64108000,
 184         },
 185         {
 186                 .h_display              =       1280,
 187                 .h_back_porch           =       136,
 188                 .h_total                =       1664,
 189                 .h_active_start         =       328,
 190                 .h_left_border          =       328,
 191                 .h_right_border         =       1608,
 192                 .h_front_porch          =       1608,
 193
 194                 .v_display              =       720,
 195                 .v_back_porch           =       7,
 196                 .v_total                =       745,
 197                 .v_active_start         =       24,
 198                 .v_top_border           =       24,
 199                 .v_bottom_border        =       744,
 200                 .v_front_porch          =       744,
 201
 202                 .v_refresh              =       59,
 203                 .clock_freq             =       74380000,
 204         },
 205         {
 206                 .h_display              =       1280,
 207                 .h_back_porch           =       136,
 208                 .h_total                =       1680,
 209                 .h_active_start         =       336,
 210                 .h_left_border          =       336,
 211                 .h_right_border         =       1616,
 212                 .h_front_porch          =       1616,
 213
 214                 .v_display              =       768,
 215                 .v_back_porch           =       7,
 216                 .v_total                =       795,
 217                 .v_active_start         =       26,
 218                 .v_top_border           =       26,
 219                 .v_bottom_border        =       794,
 220                 .v_front_porch          =       794,
 221
 222                 .v_refresh              =       59,
 223                 .clock_freq             =       80136000,
 224         },
 225         {
 226                 .h_display              =       1280,
 227                 .h_back_porch           =       136,
 228                 .h_total                =       1680,
 229                 .h_active_start         =       336,
 230                 .h_left_border          =       336,
 231                 .h_right_border         =       1616,
 232                 .h_front_porch          =       1616,
 233
 234                 .v_display              =       800,
 235                 .v_back_porch           =       7,
 236                 .v_total                =       828,
 237                 .v_active_start         =       27,
 238                 .v_top_border           =       27,
 239                 .v_bottom_border        =       827,
 240                 .v_front_porch          =       827,
 241
 242                 .v_refresh              =       59,
 243                 .clock_freq             =       83462000,
 244         },
 245         {
 246                 .h_display              =       1280,
 247                 .h_back_porch           =       136,
 248                 .h_total                =       1712,
 249                 .h_active_start         =       352,
 250                 .h_left_border          =       352,
 251                 .h_right_border         =       1632,
 252                 .h_front_porch          =       1632,
 253
 254                 .v_display              =       1024,
 255                 .v_back_porch           =       7,
 256                 .v_total                =       1059,
 257                 .v_active_start         =       34,
 258                 .v_top_border           =       34,
 259                 .v_bottom_border        =       1058,
 260                 .v_front_porch          =       1058,
 261
 262                 .v_refresh              =       60,
 263                 .clock_freq             =       108780000,
 264         },
 265         {}
 266 };
 267
 268
 269 struct adf_pdp_device {
 270         struct ion_client *ion_client;
 271
 272         struct adf_device adf_device;
 273         struct adf_interface adf_interface;
 274         struct adf_overlay_engine adf_overlay;
 275 #ifdef SUPPORT_ADF_PDP_FBDEV
 276         struct adf_fbdev adf_fbdev;
 277 #endif
 278
 279         struct platform_device *pdev;
 280
 281         struct apollo_pdp_platform_data *pdata;
 282
 283         void __iomem *regs;
 284         resource_size_t regs_size;
 285
 286         void __iomem *pll_regs;
 287         resource_size_t pll_regs_size;
 288
 289         struct drm_mode_modeinfo *supported_modes;
 290         int num_supported_modes;
 291
 292         const struct pdp_timing_data *current_timings;
 293
 294         atomic_t refcount;
 295
 296         atomic_t num_validates;
 297         int num_posts;
 298
 299         atomic_t vsync_triggered;
 300         wait_queue_head_t vsync_wait_queue;
 301         atomic_t requested_vsync_state;
 302         atomic_t vsync_state;
 303
 304         /* This is set when the last client has released this device, causing
 305          * all outstanding posts to be ignored
 306          */
 307         atomic_t released;
 308
 309         struct {
 310                 u32 str1surf;
 311                 u32 str1posn;
 312                 u32 str1addrctrl;
 313         } flip_registers;
 314 };
 315
 316 static const u32 pdp_supported_formats[] = {
 317         DRM_FORMAT_BGRA8888,
 318 };
 319 #define NUM_SUPPORTED_FORMATS 1
 320
 321 static const struct {
 322         u32 drm_format;
 323         u32 bytes_per_pixel;
 324         u32 pixfmt_word;
 325 } pdp_format_table[] = {
 326         { DRM_FORMAT_BGRA8888, 4, DCPDP_STR1SURF_FORMAT_ARGB8888 },
 327         {},
 328 };
 329
 330 static int pdp_mode_count(struct adf_pdp_device *pdp)
 331 {
 332         int i = 0;
 333
 334         while (pdp_supported_modes[i].h_display)
 335                 i++;
 336         return i;
 337 }
 338
 339 static int pdp_mode_id(struct adf_pdp_device *pdp, u32 height, u32 width)
 340 {
 341         int i;
 342
 343         for (i = 0; pdp_supported_modes[i].h_display; i++) {
 344                 const struct pdp_timing_data *tdata = &pdp_supported_modes[i];
 345
 346                 if (tdata->h_display == width && tdata->v_display == height)
 347                         return i;
 348         }
 349         dev_err(&pdp->pdev->dev, "Failed to find matching mode for %dx%d\n",
 350                 width, height);
 351         return -1;
 352 }
 353
 354 static const struct pdp_timing_data *pdp_timing_data(
 355         struct adf_pdp_device *pdp, int mode_id)
 356 {
 357         if (mode_id >= pdp_mode_count(pdp) || mode_id < 0)
 358                 return NULL;
 359         return &pdp_supported_modes[mode_id];
 360 }
 361
 362 static void pdp_mode_to_drm_mode(struct adf_pdp_device *pdp, int mode_id,
 363         struct drm_mode_modeinfo *drm_mode)
 364 {
 365         const struct pdp_timing_data *pdp_mode = pdp_timing_data(pdp, mode_id);
 366
 367         BUG_ON(pdp_mode == NULL);
 368         memset(drm_mode, 0, sizeof(*drm_mode));
 369
 370         drm_mode->hdisplay = pdp_mode->h_display;
 371         drm_mode->vdisplay = pdp_mode->v_display;
 372         drm_mode->vrefresh = pdp_mode->v_refresh;
 373
 374         adf_modeinfo_set_name(drm_mode);
 375 }
 376
 377 static u32 pdp_read_reg(struct adf_pdp_device *pdp, resource_size_t reg_offset)
 378 {
 379         BUG_ON(reg_offset > pdp->regs_size-4);
 380         return ioread32(pdp->regs + reg_offset);
 381 }
 382
 383 static void pdp_write_reg(struct adf_pdp_device *pdp,
 384         resource_size_t reg_offset, u32 reg_value)
 385 {
 386         BUG_ON(reg_offset > pdp->regs_size-4);
 387         iowrite32(reg_value, pdp->regs + reg_offset);
 388 }
 389
 390 static void pll_write_reg(struct adf_pdp_device *pdp,
 391         resource_size_t reg_offset, u32 reg_value)
 392 {
 393         BUG_ON(reg_offset < TCF_PLL_PLL_PDP_CLK0);
 394         BUG_ON(reg_offset > pdp->pll_regs_size + TCF_PLL_PLL_PDP_CLK0 - 4);
 395         iowrite32(reg_value, pdp->pll_regs +
 396                 reg_offset - TCF_PLL_PLL_PDP_CLK0);
 397 }
 398
 399 static void pdp_devres_release(struct device *dev, void *res)
 400 {
 401         /* No extra cleanup needed */
 402 }
 403
 404 static u32 pdp_format_bpp(u32 drm_format)
 405 {
 406         int i;
 407
 408         for (i = 0; pdp_format_table[i].drm_format != 0; i++) {
 409                 if (pdp_format_table[i].drm_format == drm_format)
 410                         return pdp_format_table[i].bytes_per_pixel;
 411         }
 412         WARN(1, "Unsupported drm format");
 413         return 0;
 414 }
 415
 416 static u32 pdp_format(u32 drm_format)
 417 {
 418         int i;
 419
 420         for (i = 0; pdp_format_table[i].drm_format != 0; i++) {
 421                 if (pdp_format_table[i].drm_format == drm_format)
 422                         return pdp_format_table[i].pixfmt_word;
 423         }
 424         WARN(1, "Unsupported drm format");
 425         return 0;
 426 }
 427
 428 static void pdp_enable_scanout(struct adf_pdp_device *pdp)
 429 {
 430         u32 reg_value;
 431         /* Turn on scanout */
 432         reg_value = pdp_read_reg(pdp, TCF_RGBPDP_PVR_TCF_RGBPDP_STR1ADDRCTRL);
 433         reg_value &= ~(STR1STREN_MASK);
 434         reg_value |= 0x1 << STR1STREN_SHIFT;
 435         pdp_write_reg(pdp, TCF_RGBPDP_PVR_TCF_RGBPDP_STR1ADDRCTRL, reg_value);
 436 }
 437
 438 static void pdp_disable_scanout(struct adf_pdp_device *pdp)
 439 {
 440         pdp_write_reg(pdp, TCF_RGBPDP_PVR_TCF_RGBPDP_STR1ADDRCTRL, 0);
 441 }
 442
 443 static bool pdp_vsync_triggered(struct adf_pdp_device *pdp)
 444 {
 445         return atomic_read(&pdp->vsync_triggered) == 1;
 446 }
 447
 448 static void pdp_enable_vsync(struct adf_pdp_device *pdp)
 449 {
 450         u32 reg_value = pdp_read_reg(pdp, TCF_RGBPDP_PVR_TCF_RGBPDP_INTENAB);
 451
 452         reg_value |= (0x1 << INTEN_VBLNK1_SHIFT);
 453         pdp_write_reg(pdp, TCF_RGBPDP_PVR_TCF_RGBPDP_INTENAB, reg_value);
 454 }
 455
 456 static void pdp_disable_vsync(struct adf_pdp_device *pdp)
 457 {
 458         u32 reg_value = pdp_read_reg(pdp, TCF_RGBPDP_PVR_TCF_RGBPDP_INTENAB);
 459
 460         reg_value &= ~(0x1 << INTEN_VBLNK1_SHIFT);
 461         pdp_write_reg(pdp, TCF_RGBPDP_PVR_TCF_RGBPDP_INTENAB, reg_value);
 462 }
 463
 464 static void pdp_enable_interrupt(struct adf_pdp_device *pdp)
 465 {
 466         int err = 0;
 467         err = apollo_enable_interrupt(pdp->pdev->dev.parent,
 468                 APOLLO_INTERRUPT_PDP);
 469         if (err) {
 470                 dev_err(&pdp->pdev->dev,
 471                         "apollo_enable_interrupt failed (%d)\n", err);
 472         }
 473 }
 474
 475 static void pdp_disable_interrupt(struct adf_pdp_device *pdp)
 476 {
 477         int err = 0;
 478         err = apollo_disable_interrupt(pdp->pdev->dev.parent,
 479                 APOLLO_INTERRUPT_PDP);
 480         if (err) {
 481                 dev_err(&pdp->pdev->dev,
 482                         "apollo_disable_interrupt failed (%d)\n", err);
 483         }
 484 }
 485
 486 static void pdp_post(struct adf_device *adf_dev, struct adf_post *cfg,
 487         void *driver_state)
 488 {
 489         int num_validates_snapshot = *(int *)driver_state;
 490         dma_addr_t buf_addr;
 491         u32 reg_value = 0;
 492         unsigned long flags;
 493
 494         /* Set vsync wait timeout to 4x expected vsync */
 495         struct adf_pdp_device *pdp = devres_find(adf_dev->dev,
 496                 pdp_devres_release, NULL, NULL);
 497         long timeout =
 498                 msecs_to_jiffies((1000 / pdp->current_timings->v_refresh) * 4);
 499
 500         /* Null-flip handling, used to push buffers off screen during an error
 501          * state to stop them blocking subsequent rendering
 502          */
 503         if (cfg->n_bufs == 0 || atomic_read(&pdp->released) == 1)
 504                 goto out_update_num_posts;
 505
 506         WARN_ON(cfg->n_bufs != 1);
 507         WARN_ON(cfg->mappings->sg_tables[0]->nents != 1);
 508
 509         spin_lock_irqsave(&gFlipLock, flags);
 510
 511         buf_addr = sg_phys(cfg->mappings->sg_tables[0]->sgl);
 512         /* Convert the cpu address to a device address */
 513         buf_addr -= pdp->pdata->memory_base;
 514
 515         debugfs_dma_buf_set(cfg->bufs[0].dma_bufs[0]);
 516
 517         /* Set surface register w/height, width & format */
 518         reg_value  = (cfg->bufs[0].w-1) << STR1WIDTH_SHIFT;
 519         reg_value |= (cfg->bufs[0].h-1) << STR1HEIGHT_SHIFT;
 520         reg_value |= pdp_format(cfg->bufs[0].format) << STR1PIXFMT_SHIFT;
 521         pdp->flip_registers.str1surf = reg_value;
 522
 523         /* Set stride register */
 524         reg_value = (cfg->bufs[0].pitch[0] >> DCPDP_STR1POSN_STRIDE_SHIFT)-1;
 525         pdp->flip_registers.str1posn = reg_value;
 526
 527         /* Set surface address without resetting any other bits in the
 528          * register
 529          */
 530         reg_value  = pdp_read_reg(pdp, TCF_RGBPDP_PVR_TCF_RGBPDP_STR1ADDRCTRL);
 531         reg_value &= ~(STR1BASE_MASK);
 532         reg_value |= (buf_addr >> DCPDP_STR1ADDRCTRL_BASE_ADDR_SHIFT)
 533                 & STR1BASE_MASK;
 534
 535         pdp->flip_registers.str1addrctrl = reg_value;
 536         atomic_set(&pdp->vsync_triggered, 0);
 537
 538         spin_unlock_irqrestore(&gFlipLock, flags);
 539
 540         /* Wait until the buffer is on-screen, so we know the previous buffer
 541          * has been retired and off-screen.
 542          *
 543          * If vsync was already off when this post was serviced, we need to
 544          * enable the vsync again briefly so the register updates we shadowed
 545          * above get applied and we don't signal the fence prematurely. One
 546          * vsync afterwards, we'll disable the vsync again.
 547          */
 548         if (!atomic_xchg(&pdp->vsync_state, 1))
 549                 pdp_enable_vsync(pdp);
 550
 551         if (wait_event_timeout(pdp->vsync_wait_queue,
 552                 pdp_vsync_triggered(pdp), timeout) == 0) {
 553                 dev_err(&pdp->pdev->dev, "Post VSync wait timeout");
 554                 /* Undefined behaviour if this times out */
 555         }
 556 out_update_num_posts:
 557         pdp->num_posts = num_validates_snapshot;
 558 }
 559
 560 static bool pdp_supports_event(struct adf_obj *obj, enum adf_event_type type)
 561 {
 562         switch (obj->type) {
 563         case ADF_OBJ_INTERFACE:
 564         {
 565                 switch (type) {
 566                 case ADF_EVENT_VSYNC:
 567                         return true;
 568                 default:
 569                         return false;
 570                 }
 571         }
 572         default:
 573                 return false;
 574         }
 575 }
 576
 577 static void pdp_irq_handler(void *data)
 578 {
 579         struct adf_pdp_device *pdp = data;
 580         unsigned long flags;
 581         u32 int_status = pdp_read_reg(pdp, TCF_RGBPDP_PVR_TCF_RGBPDP_INTSTAT);
 582
 583         if (int_status & INTS_VBLNK1_MASK)
 584                 pdp_write_reg(pdp, TCF_RGBPDP_PVR_TCF_RGBPDP_INTCLEAR,
 585                         (0x1 << INTCLR_VBLNK1_SHIFT));
 586
 587         spin_lock_irqsave(&gFlipLock, flags);
 588
 589         /* If we're idle, and a vsync disable was requested, do it now.
 590          * This code assumes that the HWC will always re-enable vsync
 591          * explicitly before posting new configurations.
 592          */
 593         if (atomic_read(&pdp->num_validates) == pdp->num_posts) {
 594                 if (!atomic_read(&pdp->requested_vsync_state)) {
 595                         pdp_disable_vsync(pdp);
 596                         atomic_set(&pdp->vsync_state, 0);
 597                 }
 598         }
 599
 600         if (int_status & INTS_VBLNK1_MASK) {
 601                 /* Write the registers for the next buffer to display */
 602                 pdp_write_reg(pdp, TCF_RGBPDP_PVR_TCF_RGBPDP_STR1SURF,
 603                                           pdp->flip_registers.str1surf);
 604                 pdp_write_reg(pdp, TCF_RGBPDP_PVR_PDP_STR1POSN,
 605                                           pdp->flip_registers.str1posn);
 606                 pdp_write_reg(pdp, TCF_RGBPDP_PVR_TCF_RGBPDP_STR1ADDRCTRL,
 607                                           pdp->flip_registers.str1addrctrl);
 608                 pdp_enable_scanout(pdp);
 609
 610                 adf_vsync_notify(&pdp->adf_interface, ktime_get());
 611                 atomic_set(&pdp->vsync_triggered, 1);
 612                 wake_up(&pdp->vsync_wait_queue);
 613         }
 614
 615         spin_unlock_irqrestore(&gFlipLock, flags);
 616 }
 617
 618 static void pdp_set_event(struct adf_obj *obj, enum adf_event_type type,
 619         bool enabled)
 620 {
 621         struct adf_pdp_device *pdp;
 622         bool old;
 623
 624         switch (type) {
 625         case ADF_EVENT_VSYNC:
 626         {
 627                 pdp = devres_find(obj->parent->dev, pdp_devres_release,
 628                                   NULL, NULL);
 629                 atomic_set(&pdp->requested_vsync_state, enabled);
 630                 if (enabled) {
 631                         old = atomic_xchg(&pdp->vsync_state, enabled);
 632                         if (!old)
 633                                 pdp_enable_vsync(pdp);
 634                 }
 635                 break;
 636         }
 637         default:
 638                 BUG();
 639         }
 640 }
 641
 642 static void pdp_set_clocks(struct adf_pdp_device *pdp, u32 clock_freq_hz)
 643 {
 644         u32 clock_freq_mhz = (clock_freq_hz + 500000) / 1000000;
 645
 646         pll_write_reg(pdp, TCF_PLL_PLL_PDP_CLK0, clock_freq_mhz);
 647         if (clock_freq_mhz >= 50)
 648                 pll_write_reg(pdp, TCF_PLL_PLL_PDP_CLK1TO5, 0);
 649         else
 650                 pll_write_reg(pdp, TCF_PLL_PLL_PDP_CLK1TO5, 0x3);
 651
 652         pll_write_reg(pdp, TCF_PLL_PLL_PDP_DRP_GO, 1);
 653         udelay(1000);
 654         pll_write_reg(pdp, TCF_PLL_PLL_PDP_DRP_GO, 0);
 655 }
 656
 657 static int pdp_modeset(struct adf_interface *intf,
 658         struct drm_mode_modeinfo *mode)
 659 {
 660         u32 reg_value = 0;
 661         int err = 0;
 662         struct adf_pdp_device *pdp = devres_find(intf->base.parent->dev,
 663                 pdp_devres_release, NULL, NULL);
 664         int mode_id = pdp_mode_id(pdp, mode->vdisplay, mode->hdisplay);
 665         const struct pdp_timing_data *tdata = pdp_timing_data(pdp, mode_id);
 666
 667
 668         if (!tdata) {
 669                 dev_err(&pdp->pdev->dev, "Failed to find mode for %ux%u\n",
 670                         mode->hdisplay, mode->vdisplay);
 671                 err = -ENXIO;
 672                 goto err_out;
 673         }
 674         /* Disable scanout */
 675         pdp_disable_scanout(pdp);
 676         /* Disable sync gen */
 677         reg_value = pdp_read_reg(pdp, TCF_RGBPDP_PVR_TCF_RGBPDP_SYNCCTRL);
 678         reg_value &= ~(SYNCACTIVE_MASK);
 679         pdp_write_reg(pdp, TCF_RGBPDP_PVR_TCF_RGBPDP_SYNCCTRL, reg_value);
 680
 681         pdp_set_clocks(pdp, tdata->clock_freq);
 682
 683         if (pdp_read_reg(pdp, TCF_RGBPDP_PVR_TCF_RGBPDP_STRCTRL)
 684                 != 0x0000C010) {
 685                 /* Buffer request threshold */
 686                 pdp_write_reg(pdp, TCF_RGBPDP_PVR_TCF_RGBPDP_STRCTRL,
 687                         0x00001C10);
 688         }
 689
 690         /* Border colour */
 691         pdp_write_reg(pdp, TCF_RGBPDP_PVR_TCF_RGBPDP_BORDCOL, 0x00005544);
 692
 693         /* Update control */
 694         pdp_write_reg(pdp, TCF_RGBPDP_PVR_TCF_RGBPDP_UPDCTRL, 0);
 695
 696         /* Set hsync */
 697         reg_value  = tdata->h_back_porch << HBPS_SHIFT;
 698         reg_value |= tdata->h_total << HT_SHIFT;
 699         pdp_write_reg(pdp, TCF_RGBPDP_PVR_TCF_RGBPDP_HSYNC1, reg_value);
 700
 701         reg_value  = tdata->h_active_start << HAS_SHIFT;
 702         reg_value |= tdata->h_left_border << HLBS_SHIFT;
 703         pdp_write_reg(pdp, TCF_RGBPDP_PVR_TCF_RGBPDP_HSYNC2, reg_value);
 704
 705         reg_value  = tdata->h_front_porch << HFPS_SHIFT;
 706         reg_value |= tdata->h_right_border << HRBS_SHIFT;
 707         pdp_write_reg(pdp, TCF_RGBPDP_PVR_TCF_RGBPDP_HSYNC3, reg_value);
 708
 709         /* Set vsync */
 710         reg_value  = tdata->v_back_porch << VBPS_SHIFT;
 711         reg_value |= tdata->v_total << VT_SHIFT;
 712         pdp_write_reg(pdp, TCF_RGBPDP_PVR_TCF_RGBPDP_VSYNC1, reg_value);
 713
 714         reg_value  = tdata->v_active_start << VAS_SHIFT;
 715         reg_value |= tdata->v_top_border << VTBS_SHIFT;
 716         pdp_write_reg(pdp, TCF_RGBPDP_PVR_TCF_RGBPDP_VSYNC2, reg_value);
 717
 718         reg_value  = tdata->v_front_porch << VFPS_SHIFT;
 719         reg_value |= tdata->v_bottom_border << VBBS_SHIFT;
 720         pdp_write_reg(pdp, TCF_RGBPDP_PVR_TCF_RGBPDP_VSYNC3, reg_value);
 721
 722         /* Horizontal data enable */
 723         reg_value  = tdata->h_active_start << HDES_SHIFT;
 724         reg_value |= tdata->h_front_porch << HDEF_SHIFT;
 725         pdp_write_reg(pdp, TCF_RGBPDP_PVR_TCF_RGBPDP_HDECTRL, reg_value);
 726
 727         /* Vertical data enable */
 728         reg_value  = tdata->v_active_start << VDES_SHIFT;
 729         reg_value |= tdata->v_front_porch << VDEF_SHIFT;
 730         pdp_write_reg(pdp, TCF_RGBPDP_PVR_TCF_RGBPDP_VDECTRL, reg_value);
 731
 732         /* Vertical event start and vertical fetch start */
 733         reg_value  = tdata->v_back_porch << VFETCH_SHIFT;
 734         reg_value |= tdata->v_front_porch << VEVENT_SHIFT;
 735         pdp_write_reg(pdp, TCF_RGBPDP_PVR_TCF_RGBPDP_VEVENT, reg_value);
 736
 737         /* Enable sync gen last and set up polarities of sync/blank */
 738         reg_value  = 0x1 << SYNCACTIVE_SHIFT;
 739         reg_value |= 0x1 << FIELDPOL_SHIFT;
 740         reg_value |= 0x1 << BLNKPOL_SHIFT;
 741         reg_value |= 0x1 << VSPOL_SHIFT;
 742         reg_value |= 0x1 << HSPOL_SHIFT;
 743         pdp_write_reg(pdp, TCF_RGBPDP_PVR_TCF_RGBPDP_SYNCCTRL, reg_value);
 744
 745         intf->current_mode = *mode;
 746         pdp->current_timings = tdata;
 747
 748 err_out:
 749         return err;
 750 }
 751
 752 static int pdp_blank(struct adf_interface *intf,
 753         u8 state)
 754 {
 755         u32 reg_value;
 756         struct adf_pdp_device *pdp = devres_find(intf->base.parent->dev,
 757                 pdp_devres_release, NULL, NULL);
 758
 759         if (state != DRM_MODE_DPMS_OFF &&
 760                 state != DRM_MODE_DPMS_ON)
 761                 return -EINVAL;
 762
 763         reg_value = pdp_read_reg(pdp, TCF_RGBPDP_PVR_TCF_RGBPDP_SYNCCTRL);
 764         switch (state) {
 765         case DRM_MODE_DPMS_OFF:
 766                 reg_value |= 0x1 << POWERDN_SHIFT;
 767                 break;
 768         case DRM_MODE_DPMS_ON:
 769                 reg_value &= ~(POWERDN_MASK);
 770                 break;
 771         }
 772         pdp_write_reg(pdp, TCF_RGBPDP_PVR_TCF_RGBPDP_SYNCCTRL, reg_value);
 773
 774         return 0;
 775 }
 776
 777 static int pdp_alloc_simple_buffer(struct adf_interface *intf, u16 w, u16 h,
 778         u32 format, struct dma_buf **dma_buf, u32 *offset, u32 *pitch)
 779 {
 780         struct adf_pdp_device *pdp = devres_find(intf->base.parent->dev,
 781                 pdp_devres_release, NULL, NULL);
 782         int err = 0;
 783         u32 size = w * h * pdp_format_bpp(format);
 784         struct ion_handle *hdl = ion_alloc(pdp->ion_client, size, 0,
 785                 (1 << pdp->pdata->ion_heap_id), 0);
 786         if (IS_ERR(hdl)) {
 787                 err = PTR_ERR(hdl);
 788                 dev_err(&pdp->pdev->dev, "ion_alloc failed (%d)\n", err);
 789                 goto err_out;
 790         }
 791         *dma_buf = ion_share_dma_buf(pdp->ion_client, hdl);
 792         if (IS_ERR(*dma_buf)) {
 793                 err = PTR_ERR(hdl);
 794                 dev_err(&pdp->pdev->dev,
 795                         "ion_share_dma_buf failed (%d)\n", err);
 796                 goto err_free_buffer;
 797         }
 798         *pitch = w * pdp_format_bpp(format);
 799         *offset = 0;
 800 err_free_buffer:
 801         ion_free(pdp->ion_client, hdl);
 802 err_out:
 803         return err;
 804 }
 805
 806 static int pdp_describe_simple_post(struct adf_interface *intf,
 807         struct adf_buffer *fb, void *data, size_t *size)
 808 {
 809         struct adf_post_ext *post_ext = data;
 810         static int post_id;
 811
 812         struct drm_clip_rect full_screen = {
 813                 .x2 = ADF_PDP_WIDTH,
 814                 .y2 = ADF_PDP_HEIGHT,
 815         };
 816
 817         /* NOTE: an upstream ADF bug means we can't test *size instead */
 818         BUG_ON(sizeof(struct adf_post_ext) +
 819                 1 * sizeof(struct adf_buffer_config_ext)
 820                         > ADF_MAX_CUSTOM_DATA_SIZE);
 821
 822         *size = sizeof(struct adf_post_ext) +
 823                 1 * sizeof(struct adf_buffer_config_ext);
 824
 825         post_ext->post_id = ++post_id;
 826
 827         post_ext->bufs_ext[0].crop        = full_screen;
 828         post_ext->bufs_ext[0].display     = full_screen;
 829         post_ext->bufs_ext[0].transform   = ADF_BUFFER_TRANSFORM_NONE_EXT;
 830         post_ext->bufs_ext[0].blend_type  = ADF_BUFFER_BLENDING_PREMULT_EXT;
 831         post_ext->bufs_ext[0].plane_alpha = 0xff;
 832
 833         return 0;
 834 }
 835
 836 static int
 837 adf_pdp_open(struct adf_obj *obj, struct inode *inode, struct file *file)
 838 {
 839         struct adf_device *dev =
 840                 (struct adf_device *)obj->parent;
 841         struct adf_pdp_device *pdp = devres_find(dev->dev,
 842                 pdp_devres_release, NULL, NULL);
 843         atomic_inc(&pdp->refcount);
 844         atomic_set(&pdp->released, 0);
 845         return 0;
 846 }
 847
 848 static void
 849 adf_pdp_release(struct adf_obj *obj, struct inode *inode, struct file *file)
 850 {
 851         struct adf_device *dev =
 852                 (struct adf_device *)obj->parent;
 853         struct adf_pdp_device *pdp = devres_find(dev->dev,
 854                 pdp_devres_release, NULL, NULL);
 855         struct sync_fence *release_fence;
 856
 857         if (atomic_dec_return(&pdp->refcount))
 858                 return;
 859
 860         /* Make sure we have no outstanding posts waiting */
 861         atomic_set(&pdp->released, 1);
 862         atomic_set(&pdp->requested_vsync_state, 0);
 863         atomic_set(&pdp->vsync_triggered, 1);
 864         wake_up_all(&pdp->vsync_wait_queue);
 865         /* This special "null" flip works around a problem with ADF
 866          * which leaves buffers pinned by the display engine even
 867          * after all ADF clients have closed.
 868          *
 869          * The "null" flip is pipelined like any other. The user won't
 870          * be able to unload this module until it has been posted.
 871          */
 872         release_fence = adf_device_post(dev, NULL, 0, NULL, 0, NULL, 0);
 873         if (IS_ERR_OR_NULL(release_fence)) {
 874                 dev_err(dev->dev,
 875                         "Failed to queue null flip command (err=%d).\n",
 876                         (int)PTR_ERR(release_fence));
 877                 return;
 878         }
 879
 880         sync_fence_put(release_fence);
 881 }
 882
 883 static int pdp_validate(struct adf_device *dev, struct adf_post *cfg,
 884         void **driver_state)
 885 {
 886         struct adf_pdp_device *pdp = devres_find(dev->dev,
 887                 pdp_devres_release, NULL, NULL);
 888         int err = adf_img_validate_simple(dev, cfg, driver_state);
 889
 890         if (err == 0 && cfg->mappings) {
 891                 /* We store a snapshot of num_validates in driver_state at the
 892                  * time validate was called, which will be passed to the post
 893                  * function. This snapshot is copied into (i.e. overwrites)
 894                  * num_posts, rather then simply incrementing num_posts, to
 895                  * handle cases e.g. during fence timeouts where validates
 896                  * are called without corresponding posts.
 897                  */
 898                 int *validates = kmalloc(sizeof(*validates), GFP_KERNEL);
 899                 *validates = atomic_inc_return(&pdp->num_validates);
 900                 *driver_state = validates;
 901         } else {
 902                 *driver_state = NULL;
 903         }
 904         return err;
 905 }
 906
 907 static void pdp_state_free(struct adf_device *dev, void *driver_state)
 908 {
 909         kfree(driver_state);
 910 }
 911
 912 static struct adf_device_ops adf_pdp_device_ops = {
 913         .owner = THIS_MODULE,
 914         .base = {
 915                 .open = adf_pdp_open,
 916                 .release = adf_pdp_release,
 917                 .ioctl = adf_img_ioctl,
 918         },
 919         .state_free = pdp_state_free,
 920         .validate = pdp_validate,
 921         .post = pdp_post,
 922 };
 923
 924 static struct adf_interface_ops adf_pdp_interface_ops = {
 925         .base = {
 926                 .supports_event = pdp_supports_event,
 927                 .set_event = pdp_set_event,
 928         },
 929         .modeset = pdp_modeset,
 930         .blank = pdp_blank,
 931         .alloc_simple_buffer = pdp_alloc_simple_buffer,
 932         .describe_simple_post = pdp_describe_simple_post,
 933 };
 934
 935 static struct adf_overlay_engine_ops adf_pdp_overlay_ops = {
 936         .supported_formats = &pdp_supported_formats[0],
 937         .n_supported_formats = NUM_SUPPORTED_FORMATS,
 938 };
 939
 940 #ifdef SUPPORT_ADF_PDP_FBDEV
 941 static struct fb_ops adf_pdp_fb_ops = {
 942         .owner = THIS_MODULE,
 943         .fb_open = adf_fbdev_open,
 944         .fb_release = adf_fbdev_release,
 945         .fb_check_var = adf_fbdev_check_var,
 946         .fb_set_par = adf_fbdev_set_par,
 947         .fb_blank = adf_fbdev_blank,
 948         .fb_pan_display = adf_fbdev_pan_display,
 949         .fb_fillrect = cfb_fillrect,
 950         .fb_copyarea = cfb_copyarea,
 951         .fb_imageblit = cfb_imageblit,
 952         .fb_mmap = adf_fbdev_mmap,
 953 };
 954 #endif
 955
 956 static int adf_pdp_probe_device(struct platform_device *pdev)
 957 {
 958         struct adf_pdp_device *pdp;
 959         int err = 0;
 960         int i, default_mode_id;
 961         struct resource *registers;
 962         struct pci_dev *pci_dev = to_pci_dev(pdev->dev.parent);
 963         struct apollo_pdp_platform_data *pdata = pdev->dev.platform_data;
 964
 965         pdp = devres_alloc(pdp_devres_release, sizeof(*pdp),
 966                 GFP_KERNEL);
 967         if (!pdp) {
 968                 err = -ENOMEM;
 969                 goto err_out;
 970         }
 971         devres_add(&pdev->dev, pdp);
 972
 973         pdp->pdata = pdata;
 974         pdp->pdev = pdev;
 975
 976         err = pci_enable_device(pci_dev);
 977         if (err) {
 978                 dev_err(&pdev->dev,
 979                         "Failed to enable PDP pci device (%d)\n", err);
 980                 goto err_out;
 981         }
 982
 983         atomic_set(&pdp->refcount, 0);
 984         atomic_set(&pdp->num_validates, 0);
 985         pdp->num_posts = 0;
 986
 987         pdp->ion_client = ion_client_create(pdata->ion_device, "adf_pdp");
 988         if (IS_ERR(pdp->ion_client)) {
 989                 err = PTR_ERR(pdp->ion_client);
 990                 dev_err(&pdev->dev,
 991                         "Failed to create PDP ION client (%d)\n", err);
 992                 goto err_disable_pci;
 993         }
 994
 995         registers = platform_get_resource_byname(pdev,
 996                                                  IORESOURCE_MEM,
 997                                                  "pdp-regs");
 998         pdp->regs = devm_ioremap_resource(&pdev->dev, registers);
 999         if (IS_ERR(pdp->regs)) {
1000                 err = PTR_ERR(pdp->regs);
1001                 dev_err(&pdev->dev, "Failed to map PDP registers (%d)\n", err);
1002                 goto err_destroy_ion_client;
1003         }
1004         pdp->regs_size = resource_size(registers);
1005
1006         registers = platform_get_resource_byname(pdev,
1007                                                  IORESOURCE_MEM,
1008                                                  "pll-regs");
1009         pdp->pll_regs = devm_ioremap_resource(&pdev->dev, registers);
1010         if (IS_ERR(pdp->pll_regs)) {
1011                 err = PTR_ERR(pdp->pll_regs);
1012                 dev_err(&pdev->dev, "Failed to map PDP registers (%d)\n", err);
1013                 goto err_destroy_ion_client;
1014         }
1015         pdp->pll_regs_size = resource_size(registers);
1016
1017         err = adf_device_init(&pdp->adf_device, &pdp->pdev->dev,
1018                 &adf_pdp_device_ops, "pdp_device");
1019         if (err) {
1020                 dev_err(&pdev->dev, "Failed to init ADF device (%d)\n", err);
1021                 goto err_destroy_ion_client;
1022         }
1023
1024         err = adf_interface_init(&pdp->adf_interface, &pdp->adf_device,
1025                 ADF_INTF_DVI, 0, ADF_INTF_FLAG_PRIMARY, &adf_pdp_interface_ops,
1026                 "pdp_interface");
1027         if (err) {
1028                 dev_err(&pdev->dev, "Failed to init ADF interface (%d)\n", err);
1029                 goto err_destroy_adf_device;
1030         }
1031
1032         err = adf_overlay_engine_init(&pdp->adf_overlay, &pdp->adf_device,
1033                 &adf_pdp_overlay_ops, "pdp_overlay");
1034         if (err) {
1035                 dev_err(&pdev->dev, "Failed to init ADF overlay (%d)\n", err);
1036                 goto err_destroy_adf_interface;
1037         }
1038
1039         err = adf_attachment_allow(&pdp->adf_device, &pdp->adf_overlay,
1040                 &pdp->adf_interface);
1041         if (err) {
1042                 dev_err(&pdev->dev, "Failed to attach overlay (%d)\n", err);
1043                 goto err_destroy_adf_overlay;
1044         }
1045
1046         pdp->num_supported_modes = pdp_mode_count(pdp);
1047         pdp->supported_modes = kzalloc(sizeof(*pdp->supported_modes)
1048                 * pdp->num_supported_modes, GFP_KERNEL);
1049
1050         if (!pdp->supported_modes) {
1051                 dev_err(&pdev->dev, "Failed to allocate supported modeinfo structs\n");
1052                 err = -ENOMEM;
1053                 goto err_destroy_adf_overlay;
1054         }
1055
1056         for (i = 0; i < pdp->num_supported_modes; i++)
1057                 pdp_mode_to_drm_mode(pdp, i, &pdp->supported_modes[i]);
1058
1059         default_mode_id = pdp_mode_id(pdp, pdp_display_height,
1060                 pdp_display_width);
1061         if (default_mode_id == -1) {
1062                 default_mode_id = 0;
1063                 dev_err(&pdev->dev, "No modeline found for requested display size (%dx%d)\n",
1064                         pdp_display_width, pdp_display_height);
1065         }
1066
1067         /* Initial modeset... */
1068         err = pdp_modeset(&pdp->adf_interface,
1069                 &pdp->supported_modes[default_mode_id]);
1070         if (err) {
1071                 dev_err(&pdev->dev, "Initial modeset failed (%d)\n", err);
1072                 goto err_destroy_modelist;
1073         }
1074
1075         err = adf_hotplug_notify_connected(&pdp->adf_interface,
1076                 pdp->supported_modes, pdp->num_supported_modes);
1077         if (err) {
1078                 dev_err(&pdev->dev, "Initial hotplug notify failed (%d)\n",
1079                         err);
1080                 goto err_destroy_modelist;
1081         }
1082         err = apollo_set_interrupt_handler(pdp->pdev->dev.parent,
1083                                            APOLLO_INTERRUPT_PDP,
1084                                            pdp_irq_handler, pdp);
1085         if (err) {
1086                 dev_err(&pdev->dev, "Failed to set interrupt handler (%d)\n",
1087                         err);
1088                 goto err_destroy_modelist;
1089         }
1090 #ifdef SUPPORT_ADF_PDP_FBDEV
1091         err = adf_fbdev_init(&pdp->adf_fbdev, &pdp->adf_interface,
1092                 &pdp->adf_overlay, pdp_display_width,
1093                 pdp_display_height, DRM_FORMAT_BGRA8888,
1094                 &adf_pdp_fb_ops, "adf_pdp_fb");
1095         if (err) {
1096                 dev_err(&pdev->dev, "Failed to init ADF fbdev (%d)\n", err);
1097                 goto err_destroy_modelist;
1098         }
1099 #endif
1100
1101         init_waitqueue_head(&pdp->vsync_wait_queue);
1102         atomic_set(&pdp->requested_vsync_state, 0);
1103         atomic_set(&pdp->vsync_state, 0);
1104
1105         if (debugfs_dma_buf_init("pdp_raw"))
1106                 dev_err(&pdev->dev, "Failed to create debug fs file for raw access\n");
1107
1108         pdp_enable_interrupt(pdp);
1109
1110         return err;
1111 err_destroy_modelist:
1112         kfree(pdp->supported_modes);
1113 err_destroy_adf_overlay:
1114         adf_overlay_engine_destroy(&pdp->adf_overlay);
1115 err_destroy_adf_interface:
1116         adf_interface_destroy(&pdp->adf_interface);
1117 err_destroy_adf_device:
1118         adf_device_destroy(&pdp->adf_device);
1119 err_destroy_ion_client:
1120         ion_client_destroy(pdp->ion_client);
1121 err_disable_pci:
1122         pci_disable_device(pci_dev);
1123 err_out:
1124         dev_err(&pdev->dev, "Failed to initialise PDP device\n");
1125         return err;
1126 }
1127
1128 static int adf_pdp_remove_device(struct platform_device *pdev)
1129 {
1130         int err = 0;
1131         struct pci_dev *pci_dev = to_pci_dev(pdev->dev.parent);
1132         struct adf_pdp_device *pdp = devres_find(&pdev->dev, pdp_devres_release,
1133                 NULL, NULL);
1134
1135         debugfs_dma_buf_deinit();
1136
1137         pdp_disable_scanout(pdp);
1138
1139         pdp_disable_vsync(pdp);
1140         pdp_disable_interrupt(pdp);
1141         apollo_set_interrupt_handler(pdp->pdev->dev.parent,
1142                                      APOLLO_INTERRUPT_PDP,
1143                                      NULL, NULL);
1144         /* Disable scanout */
1145         pdp_write_reg(pdp, TCF_RGBPDP_PVR_TCF_RGBPDP_STR1ADDRCTRL, 0);
1146         kfree(pdp->supported_modes);
1147 #ifdef SUPPORT_ADF_PDP_FBDEV
1148         adf_fbdev_destroy(&pdp->adf_fbdev);
1149 #endif
1150         adf_overlay_engine_destroy(&pdp->adf_overlay);
1151         adf_interface_destroy(&pdp->adf_interface);
1152         adf_device_destroy(&pdp->adf_device);
1153         ion_client_destroy(pdp->ion_client);
1154         pci_disable_device(pci_dev);
1155         return err;
1156 }
1157
1158 static void adf_pdp_shutdown_device(struct platform_device *pdev)
1159 {
1160         /* No cleanup needed, all done in remove_device */
1161 }
1162
1163 static struct platform_device_id pdp_platform_device_id_table[] = {
1164         { .name = APOLLO_DEVICE_NAME_PDP, .driver_data = 0 },
1165         { },
1166 };
1167
1168 static struct platform_driver pdp_platform_driver = {
1169         .probe = adf_pdp_probe_device,
1170         .remove = adf_pdp_remove_device,
1171         .shutdown = adf_pdp_shutdown_device,
1172         .driver = {
1173                 .name = DRV_NAME,
1174         },
1175         .id_table = pdp_platform_device_id_table,
1176 };
1177
1178 static int __init adf_pdp_init(void)
1179 {
1180         return platform_driver_register(&pdp_platform_driver);
1181 }
1182
1183 static void __exit adf_pdp_exit(void)
1184 {
1185         platform_driver_unregister(&pdp_platform_driver);
1186 }
1187
1188 module_init(adf_pdp_init);
1189 module_exit(adf_pdp_exit);