drivers/staging/imgtec/apollo/adf_tc5_pdp.c

   1 /* -*- mode: c; indent-tabs-mode: t; c-basic-offset: 8; tab-width: 8 -*- */
   2 /* vi: set ts=8 sw=8 sts=8: */
   3 /*************************************************************************/ /*!
   4 @File           adf_pdp.c
   5 @Codingstyle    LinuxKernel
   6 @Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
   7 @License        Dual MIT/GPLv2
   8
   9 The contents of this file are subject to the MIT license as set out below.
  10
  11 Permission is hereby granted, free of charge, to any person obtaining a copy
  12 of this software and associated documentation files (the "Software"), to deal
  13 in the Software without restriction, including without limitation the rights
  14 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  15 copies of the Software, and to permit persons to whom the Software is
  16 furnished to do so, subject to the following conditions:
  17
  18 The above copyright notice and this permission notice shall be included in
  19 all copies or substantial portions of the Software.
  20
  21 Alternatively, the contents of this file may be used under the terms of
  22 the GNU General Public License Version 2 ("GPL") in which case the provisions
  23 of GPL are applicable instead of those above.
  24
  25 If you wish to allow use of your version of this file only under the terms of
  26 GPL, and not to allow others to use your version of this file under the terms
  27 of the MIT license, indicate your decision by deleting the provisions above
  28 and replace them with the notice and other provisions required by GPL as set
  29 out in the file called "GPL-COPYING" included in this distribution. If you do
  30 not delete the provisions above, a recipient may use your version of this file
  31 under the terms of either the MIT license or GPL.
  32
  33 This License is also included in this distribution in the file called
  34 "MIT-COPYING".
  35
  36 EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
  37 PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
  38 BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
  39 PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
  40 COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  41 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  42 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  43 */ /**************************************************************************/
  44
  45 /*
  46  * This is an example ADF display driver for the testchip's 5 PDP with fbdc
  47  * support
  48  */
  49
  50 #include <linux/module.h>
  51 #include <linux/device.h>
  52 #include <linux/pci.h>
  53 #include <linux/interrupt.h>
  54 #include <linux/delay.h>
  55 #include <linux/platform_device.h>
  56 #include <linux/wait.h>
  57
  58 #include <drm/drm_fourcc.h>
  59
  60 #include <video/adf.h>
  61 #include <video/adf_client.h>
  62
  63 #include PVR_ANDROID_ION_HEADER
  64
  65 /* for sync_fence_put */
  66 #include PVR_ANDROID_SYNC_HEADER
  67
  68 #include "apollo_drv.h"
  69 #include "adf_common.h"
  70 #include "debugfs_dma_buf.h"
  71
  72 #include "pvrmodule.h"
  73
  74 #include "pdp_tc5_regs.h"
  75 #include "pdp_tc5_fbdc_regs.h"
  76
  77 #define DRV_NAME APOLLO_DEVICE_NAME_PDP
  78
  79 #ifndef ADF_PDP_WIDTH
  80 #define ADF_PDP_WIDTH 1280
  81 #endif
  82
  83 #ifndef ADF_PDP_HEIGHT
  84 #define ADF_PDP_HEIGHT 720
  85 #endif
  86
  87 #define DRM_FORMAT_BGRA8888_DIRECT_16x4 fourcc_code('I', 'M', 'G', '0')
  88
  89 MODULE_DESCRIPTION("APOLLO TC5 PDP display driver");
  90
  91 static int pdp_display_width = ADF_PDP_WIDTH;
  92 static int pdp_display_height = ADF_PDP_HEIGHT;
  93 module_param(pdp_display_width, int, S_IRUSR | S_IRGRP | S_IROTH);
  94 MODULE_PARM_DESC(pdp_display_width, "PDP display width");
  95 module_param(pdp_display_height, int, S_IRUSR | S_IRGRP | S_IROTH);
  96 MODULE_PARM_DESC(pdp_display_height, "PDP display height");
  97
  98 static DEFINE_SPINLOCK(gFlipLock);
  99
 100 struct pdp_timing_data {
 101         u32 h_display;
 102         u32 h_back_porch;
 103         u32 h_total;
 104         u32 h_active_start;
 105         u32 h_left_border;
 106         u32 h_right_border;
 107         u32 h_front_porch;
 108
 109         u32 v_display;
 110         u32 v_back_porch;
 111         u32 v_total;
 112         u32 v_active_start;
 113         u32 v_top_border;
 114         u32 v_bottom_border;
 115         u32 v_front_porch;
 116         u32 v_refresh;
 117 };
 118
 119 static const struct pdp_timing_data pdp_supported_modes[] = {
 120         {
 121                 .h_display              =       1280,
 122                 .h_back_porch           =       40,
 123                 .h_total                =       1650,
 124                 .h_active_start         =       260,
 125                 .h_left_border          =       260,
 126                 .h_right_border         =       1540,
 127                 .h_front_porch          =       1540,
 128
 129                 .v_display              =       720,
 130                 .v_back_porch           =       5,
 131                 .v_total                =       750,
 132                 .v_active_start         =       25,
 133                 .v_top_border           =       25,
 134                 .v_bottom_border        =       745,
 135                 .v_front_porch          =       745,
 136
 137                 .v_refresh              =       60,
 138         },
 139         {}
 140 };
 141
 142 struct adf_pdp_device {
 143         struct ion_client *ion_client;
 144
 145         struct adf_device adf_device;
 146         struct adf_interface adf_interface;
 147         struct adf_overlay_engine adf_overlay;
 148
 149         struct platform_device *pdev;
 150
 151         struct apollo_pdp_platform_data *pdata;
 152
 153         void __iomem *regs;
 154         resource_size_t regs_size;
 155
 156         void __iomem *fbdc_regs;
 157         resource_size_t fbdc_regs_size;
 158
 159         void __iomem *i2c_regs;
 160         resource_size_t i2c_regs_size;
 161
 162         struct drm_mode_modeinfo *supported_modes;
 163         int num_supported_modes;
 164
 165         atomic_t refcount;
 166
 167         atomic_t num_validates;
 168         int num_posts;
 169
 170         atomic_t vsync_triggered;
 171         wait_queue_head_t vsync_wait_queue;
 172         atomic_t requested_vsync_state;
 173         atomic_t vsync_state;
 174
 175         const struct pdp_timing_data *current_timings;
 176         u32 current_drm_format;
 177
 178         u32 baseaddr;
 179 };
 180
 181 static const u32 pdp_supported_formats[] = {
 182         DRM_FORMAT_BGRA8888_DIRECT_16x4,
 183 };
 184 #define NUM_SUPPORTED_FORMATS 1
 185
 186 static const struct {
 187         u32 drm_format;
 188         u32 bytes_per_pixel;
 189         u32 pixfmt_word;
 190 } pdp_format_table[] = {
 191         /* 01000b / 8h 8-bit alpha + 24-bit rgb888 [RGBA] */
 192         { DRM_FORMAT_BGRA8888_DIRECT_16x4, 4, 0x8 },
 193         {},
 194 };
 195
 196 static int pdp_mode_count(struct adf_pdp_device *pdp)
 197 {
 198         int i = 0;
 199
 200         while (pdp_supported_modes[i].h_display)
 201                 i++;
 202         return i;
 203 }
 204
 205 static int pdp_mode_id(struct adf_pdp_device *pdp, u32 height, u32 width)
 206 {
 207         int i;
 208
 209         for (i = 0; pdp_supported_modes[i].h_display; i++) {
 210                 const struct pdp_timing_data *tdata = &pdp_supported_modes[i];
 211
 212                 if (tdata->h_display == width && tdata->v_display == height)
 213                         return i;
 214         }
 215         dev_err(&pdp->pdev->dev, "Failed to find matching mode for %dx%d\n",
 216                 width, height);
 217         return -1;
 218 }
 219
 220 static const struct pdp_timing_data *pdp_timing_data(
 221         struct adf_pdp_device *pdp, int mode_id)
 222 {
 223         if (mode_id >= pdp_mode_count(pdp) || mode_id < 0)
 224                 return NULL;
 225         return &pdp_supported_modes[mode_id];
 226 }
 227
 228 static void pdp_mode_to_drm_mode(struct adf_pdp_device *pdp, int mode_id,
 229         struct drm_mode_modeinfo *drm_mode)
 230 {
 231         const struct pdp_timing_data *pdp_mode;
 232
 233         pdp_mode = pdp_timing_data(pdp, mode_id);
 234         BUG_ON(pdp_mode == NULL);
 235
 236         memset(drm_mode, 0, sizeof(*drm_mode));
 237
 238         drm_mode->hdisplay = pdp_mode->h_display;
 239         drm_mode->vdisplay = pdp_mode->v_display;
 240         drm_mode->vrefresh = pdp_mode->v_refresh;
 241
 242         adf_modeinfo_set_name(drm_mode);
 243 }
 244
 245 static u32 pdp_read_reg(struct adf_pdp_device *pdp, resource_size_t reg_offset)
 246 {
 247         BUG_ON(reg_offset > pdp->regs_size-4);
 248         return ioread32(pdp->regs + reg_offset);
 249 }
 250
 251 static void pdp_write_reg(struct adf_pdp_device *pdp,
 252         resource_size_t reg_offset, u32 reg_value)
 253 {
 254         BUG_ON(reg_offset > pdp->regs_size-4);
 255         iowrite32(reg_value, pdp->regs + reg_offset);
 256 }
 257
 258 static void pdp_write_fbdc_reg(struct adf_pdp_device *pdp,
 259         resource_size_t reg_offset, u32 reg_value)
 260 {
 261         BUG_ON(reg_offset > pdp->fbdc_regs_size-4);
 262         iowrite32(reg_value, pdp->fbdc_regs + reg_offset);
 263 }
 264
 265 #define I2C_TIMEOUT 10000
 266
 267 static void pdp_write_i2c(struct adf_pdp_device *pdp, u32 reg_addr, u32 data)
 268 {
 269         int i;
 270
 271         iowrite32(0x7a, pdp->i2c_regs + 0x04);
 272         iowrite32(reg_addr, pdp->i2c_regs + 0x08);
 273         iowrite32(data, pdp->i2c_regs + 0x0c);
 274         iowrite32(0x1, pdp->i2c_regs + 0x14);
 275
 276         for (i = 0; i < I2C_TIMEOUT; i++) {
 277                 if (ioread32(pdp->i2c_regs + 0x18) == 0)
 278                         break;
 279         }
 280
 281         if (i == I2C_TIMEOUT)
 282                 dev_err(&pdp->pdev->dev, "i2c write timeout\n");
 283 }
 284
 285 static u32 pdp_read_i2c(struct adf_pdp_device *pdp, u32 reg_addr)
 286 {
 287         int i;
 288
 289         iowrite32(0x7b, pdp->i2c_regs + 0x04);
 290         iowrite32(reg_addr, pdp->i2c_regs + 0x08);
 291         iowrite32(0x1, pdp->i2c_regs + 0x14);
 292
 293         for (i = 0; i < I2C_TIMEOUT; i++) {
 294                 if (ioread32(pdp->i2c_regs + 0x18) == 0)
 295                         break;
 296         }
 297
 298         if (i == I2C_TIMEOUT) {
 299                 dev_err(&pdp->pdev->dev, "i2c read timeout\n");
 300                 return 0;
 301         }
 302         return ioread32(pdp->i2c_regs + 0x10);
 303 }
 304
 305 static void pdp_devres_release(struct device *dev, void *res)
 306 {
 307         /* No extra cleanup needed */
 308 }
 309
 310 static u32 pdp_format_bpp(u32 drm_format)
 311 {
 312         int i;
 313
 314         for (i = 0; pdp_format_table[i].drm_format != 0; i++) {
 315                 if (pdp_format_table[i].drm_format == drm_format)
 316                         return pdp_format_table[i].bytes_per_pixel;
 317         }
 318         WARN(1, "Unsupported drm format");
 319         return 0;
 320 }
 321
 322 static u32 pdp_format(u32 drm_format)
 323 {
 324         int i;
 325
 326         for (i = 0; pdp_format_table[i].drm_format != 0; i++) {
 327                 if (pdp_format_table[i].drm_format == drm_format)
 328                         return pdp_format_table[i].pixfmt_word;
 329         }
 330         WARN(1, "Unsupported drm format");
 331         return 0;
 332 }
 333
 334 static void pdp_enable_scanout(struct adf_pdp_device *pdp, u32 base_addr)
 335 {
 336         u32 reg_value;
 337
 338         /* Set the base address to the fbdc module */
 339         pdp_write_fbdc_reg(pdp, PVR5__PDP_FBDC_INTRFC_BASE_ADDRESS,
 340                                            base_addr);
 341         /* Turn on scanout */
 342         reg_value = pdp_read_reg(pdp, PVR5__PDP_PVR_PDP_GRPH1CTRL);
 343         reg_value &= ~(PVR5__GRPH1STREN_MASK);
 344         reg_value |= 0x1 << PVR5__GRPH1STREN_SHIFT;
 345         pdp_write_reg(pdp, PVR5__PDP_PVR_PDP_GRPH1CTRL, reg_value);
 346 }
 347
 348 static void pdp_disable_scanout(struct adf_pdp_device *pdp)
 349 {
 350         u32 reg_value;
 351
 352         /* Turn off scanout */
 353         reg_value = pdp_read_reg(pdp, PVR5__PDP_PVR_PDP_GRPH1CTRL);
 354         reg_value &= ~(PVR5__GRPH1STREN_MASK);
 355         pdp_write_reg(pdp, PVR5__PDP_PVR_PDP_GRPH1CTRL, reg_value);
 356         /* Reset the base address in the fbdc module */
 357         pdp_write_fbdc_reg(pdp, PVR5__PDP_FBDC_INTRFC_BASE_ADDRESS,
 358                                            0);
 359 }
 360
 361 static bool pdp_vsync_triggered(struct adf_pdp_device *pdp)
 362 {
 363         return atomic_read(&pdp->vsync_triggered) == 1;
 364 }
 365
 366 static void pdp_enable_ints(struct adf_pdp_device *pdp)
 367 {
 368         int err = 0;
 369         u32 reg_value;
 370
 371         reg_value = pdp_read_reg(pdp, PVR5__PDP_PVR_PDP_INTENAB);
 372         reg_value &= ~(PVR5__INTEN_VBLNK0_MASK);
 373         reg_value |= 0x1 << PVR5__INTEN_VBLNK0_SHIFT;
 374         pdp_write_reg(pdp, PVR5__PDP_PVR_PDP_INTENAB, reg_value);
 375
 376         err = apollo_enable_interrupt(pdp->pdev->dev.parent,
 377                 APOLLO_INTERRUPT_TC5_PDP);
 378         if (err) {
 379                 dev_err(&pdp->pdev->dev,
 380                         "apollo_enable_interrupt failed (%d)\n", err);
 381         }
 382 }
 383
 384 static void pdp_disable_ints(struct adf_pdp_device *pdp)
 385 {
 386         int err = 0;
 387         u32 reg_value;
 388
 389         reg_value = pdp_read_reg(pdp, PVR5__PDP_PVR_PDP_INTENAB);
 390         reg_value &= ~(PVR5__INTEN_VBLNK0_MASK);
 391         pdp_write_reg(pdp, PVR5__PDP_PVR_PDP_INTENAB, reg_value);
 392
 393         err = apollo_disable_interrupt(pdp->pdev->dev.parent,
 394                 APOLLO_INTERRUPT_TC5_PDP);
 395         if (err) {
 396                 dev_err(&pdp->pdev->dev,
 397                         "apollo_disable_interrupt failed (%d)\n", err);
 398         }
 399 }
 400
 401 static void pdp_post(struct adf_device *adf_dev, struct adf_post *cfg,
 402         void *driver_state)
 403 {
 404         int num_validates_snapshot = *(int *)driver_state;
 405         unsigned long flags;
 406
 407         /* Set vsync wait timeout to 4x expected vsync */
 408         struct adf_pdp_device *pdp = devres_find(adf_dev->dev,
 409                 pdp_devres_release, NULL, NULL);
 410         long timeout =
 411                 msecs_to_jiffies((1000 / pdp->current_timings->v_refresh) * 4);
 412
 413         /* Null-flip handling, used to push buffers off screen during an error
 414          * state to stop them blocking subsequent rendering */
 415         if (cfg->n_bufs == 0) {
 416                 pdp_disable_scanout(pdp);
 417                 return;
 418         }
 419
 420         /* We don't support changing the configuration on the fly */
 421         if (pdp->current_timings->h_display != cfg->bufs[0].w ||
 422                 pdp->current_timings->v_display != cfg->bufs[0].h ||
 423                 pdp->current_drm_format != cfg->bufs[0].format) {
 424                 dev_err(&pdp->pdev->dev, "Unsupported configuration on post\n");
 425                 return;
 426         }
 427
 428         WARN_ON(cfg->n_bufs != 1);
 429         WARN_ON(cfg->mappings->sg_tables[0]->nents != 1);
 430
 431         spin_lock_irqsave(&gFlipLock, flags);
 432
 433         debugfs_dma_buf_set(cfg->bufs[0].dma_bufs[0]);
 434
 435         /* Set surface address and enable the scanouts */
 436         pdp_enable_scanout(pdp, sg_phys(cfg->mappings->sg_tables[0]->sgl) -
 437                                 pdp->pdata->memory_base);
 438
 439         atomic_set(&pdp->vsync_triggered, 0);
 440
 441         spin_unlock_irqrestore(&gFlipLock, flags);
 442
 443         /* Wait until the buffer is on-screen, so we know the previous buffer
 444          * has been retired and off-screen.
 445          *
 446          * If vsync was already off when this post was serviced, we need to
 447          * enable the vsync again briefly so the register updates we shadowed
 448          * above get applied and we don't signal the fence prematurely. One
 449          * vsync afterwards, we'll disable the vsync again.
 450          */
 451         if (!atomic_xchg(&pdp->vsync_state, 1))
 452                 pdp_enable_ints(pdp);
 453
 454         if (wait_event_timeout(pdp->vsync_wait_queue,
 455                 pdp_vsync_triggered(pdp), timeout) == 0) {
 456                 dev_err(&pdp->pdev->dev, "Post VSync wait timeout");
 457                 /* Undefined behaviour if this times out */
 458         }
 459
 460         pdp->num_posts = num_validates_snapshot;
 461 }
 462
 463 static bool pdp_supports_event(struct adf_obj *obj, enum adf_event_type type)
 464 {
 465         switch (obj->type) {
 466         case ADF_OBJ_INTERFACE:
 467         {
 468                 switch (type) {
 469                 case ADF_EVENT_VSYNC:
 470                         return true;
 471                 default:
 472                         return false;
 473                 }
 474         }
 475         default:
 476                 return false;
 477         }
 478 }
 479
 480 static void pdp_irq_handler(void *data)
 481 {
 482         struct adf_pdp_device *pdp = data;
 483         unsigned long flags;
 484         u32 int_status;
 485
 486         int_status = pdp_read_reg(pdp, PVR5__PDP_PVR_PDP_INTSTAT);
 487
 488         spin_lock_irqsave(&gFlipLock, flags);
 489
 490         /* If we're idle, and a vsync disable was requested, do it now.
 491          * This code assumes that the HWC will always re-enable vsync
 492          * explicitly before posting new configurations.
 493          */
 494         if (atomic_read(&pdp->num_validates) == pdp->num_posts) {
 495                 if (!atomic_read(&pdp->requested_vsync_state)) {
 496                         pdp_disable_ints(pdp);
 497                         atomic_set(&pdp->vsync_state, 0);
 498                 }
 499         }
 500
 501         if ((int_status & PVR5__INTS_VBLNK0_MASK)) {
 502                 /* Notify the framework of the just occurred vblank */
 503                 adf_vsync_notify(&pdp->adf_interface, ktime_get());
 504                 atomic_set(&pdp->vsync_triggered, 1);
 505                 wake_up(&pdp->vsync_wait_queue);
 506         }
 507
 508         spin_unlock_irqrestore(&gFlipLock, flags);
 509 }
 510
 511 static void pdp_set_event(struct adf_obj *obj, enum adf_event_type type,
 512         bool enabled)
 513 {
 514         struct adf_pdp_device *pdp;
 515         bool old;
 516
 517         switch (type) {
 518         case ADF_EVENT_VSYNC:
 519         {
 520                 pdp = devres_find(obj->parent->dev, pdp_devres_release,
 521                                   NULL, NULL);
 522                 atomic_set(&pdp->requested_vsync_state, enabled);
 523                 if (enabled) {
 524                         old = atomic_xchg(&pdp->vsync_state, enabled);
 525                         if (!old)
 526                                 pdp_enable_ints(pdp);
 527                 }
 528                 break;
 529         }
 530         default:
 531                 BUG();
 532         }
 533 }
 534
 535 static int pdp_unblank_hdmi(struct adf_pdp_device *pdp)
 536 {
 537         int err = 0, i;
 538         u32 reg_value;
 539
 540         /* Powering up the ADV7511 sometimes doesn't come up immediately, so
 541          * give multiple power ons.
 542          */
 543         for (i = 0; i < 6; i++) {
 544                 pdp_write_i2c(pdp, 0x41, 0x10);
 545                 msleep(500);
 546         }
 547         msleep(1000);
 548         reg_value = pdp_read_i2c(pdp, 0x41);
 549         if (reg_value == 0x10) {
 550                 dev_err(&pdp->pdev->dev, "i2c: ADV7511 powered up\n");
 551         } else {
 552                 dev_err(&pdp->pdev->dev, "i2c: Failed to power up ADV7511\n");
 553                 err = -EFAULT;
 554         }
 555
 556         return err;
 557 }
 558
 559 static void pdp_blank_hdmi(struct adf_pdp_device *pdp)
 560 {
 561         pdp_write_i2c(pdp, 0x41, 0x50);
 562 }
 563
 564 static void pdp_enable_hdmi(struct adf_pdp_device *pdp)
 565 {
 566         u32 reg_value = 0;
 567         int i;
 568
 569         /* Set scl clock.
 570            Assuming i2c_master clock is at 50 MHz */
 571         iowrite32(0x18, pdp->i2c_regs);
 572
 573         reg_value = pdp_read_i2c(pdp, 0xf5);
 574         if (reg_value != 0x75) {
 575                 dev_err(&pdp->pdev->dev, "i2c: 1st register read failed: %x\n",
 576                         reg_value);
 577                 goto err_out;
 578         }
 579
 580         reg_value = pdp_read_i2c(pdp, 0xf6);
 581         if (reg_value != 0x11) {
 582                 dev_err(&pdp->pdev->dev, "i2c: 2nd register read failed: %x\n",
 583                         reg_value);
 584                 goto err_out;
 585         }
 586
 587         /* Check the HPD and Monitor Sense */
 588         for (i = 0; i < 50; i++) {
 589                 reg_value = pdp_read_i2c(pdp, 0x42);
 590                 if (reg_value == 0x70) {
 591                         dev_err(&pdp->pdev->dev, "i2c: Hot Plug and Monitor Sense detected ...\n");
 592                         break;
 593                 } else if (reg_value == 0x50) {
 594                         dev_err(&pdp->pdev->dev, "i2c: Only Hot Plug detected ...\n");
 595                 } else if (reg_value == 0x03) {
 596                         dev_err(&pdp->pdev->dev, "i2c: Only Monitor Sense detected ...\n");
 597                 }
 598         }
 599
 600         if (pdp_unblank_hdmi(pdp))
 601                 goto err_out;
 602
 603         /* Writing the fixed registers */
 604         pdp_write_i2c(pdp, 0x98, 0x03);
 605         pdp_write_i2c(pdp, 0x9a, 0xe0);
 606         pdp_write_i2c(pdp, 0x9c, 0x30);
 607         pdp_write_i2c(pdp, 0x9d, 0x61);
 608         pdp_write_i2c(pdp, 0xa2, 0xa4);
 609         pdp_write_i2c(pdp, 0xa3, 0xa4);
 610         pdp_write_i2c(pdp, 0xe0, 0xd0);
 611         pdp_write_i2c(pdp, 0xf9, 0x00);
 612
 613         /* Starting video input */
 614         /* Disable I2S */
 615         pdp_write_i2c(pdp, 0x0c, 0x80);
 616
 617         /* Select input video format */
 618         pdp_write_i2c(pdp, 0x15, 0x10);
 619
 620         /* Select Colour Depth and output format */
 621         pdp_write_i2c(pdp, 0x16, 0x30);
 622
 623         /* Select Aspect Ratio */
 624         pdp_write_i2c(pdp, 0x17, 0x02);
 625
 626         /* Other settings */
 627         pdp_write_i2c(pdp, 0x48, 0x00);
 628         pdp_write_i2c(pdp, 0x55, 0x12);
 629
 630         /* Select Picture Aspect Ratio */
 631         pdp_write_i2c(pdp, 0x56, 0x28);
 632
 633         /* GC enable */
 634         pdp_write_i2c(pdp, 0x40, 0x80);
 635
 636         /* 24 bits/pixel */
 637         pdp_write_i2c(pdp, 0x4c, 0x04);
 638
 639         /* Select HDMI Mode */
 640         pdp_write_i2c(pdp, 0xaf, 0x16);
 641
 642         /* Set VIC to Receiver */
 643         pdp_write_i2c(pdp, 0x3d, 0x04);
 644
 645         for (i = 0; i < 50; i++) {
 646                 reg_value = pdp_read_i2c(pdp, 0x3e);
 647                 if (reg_value == 0x10) {
 648                         dev_err(&pdp->pdev->dev, "i2c: VIC detected as 720P, 60 Hz, 16:9...\n");
 649                         break;
 650                 }
 651         }
 652
 653         if (i == 50)
 654                 dev_err(&pdp->pdev->dev, "i2c: Desired VIC not detected\n");
 655
 656         /* Write to PD register again */
 657         pdp_write_i2c(pdp, 0x41, 0x10);
 658
 659 err_out:
 660         return;
 661 }
 662
 663 static int pdp_modeset(struct adf_interface *intf,
 664         struct drm_mode_modeinfo *mode)
 665 {
 666         const struct pdp_timing_data *tdata;
 667         struct adf_pdp_device *pdp;
 668         int mode_id, err = 0;
 669         u32 reg_value = 0;
 670
 671         pdp = devres_find(intf->base.parent->dev, pdp_devres_release,
 672                           NULL, NULL);
 673         mode_id = pdp_mode_id(pdp, mode->vdisplay, mode->hdisplay);
 674         tdata = pdp_timing_data(pdp, mode_id);
 675
 676         if (!tdata) {
 677                 dev_err(&pdp->pdev->dev, "Failed to find mode for %ux%u\n",
 678                         mode->hdisplay, mode->vdisplay);
 679                 err = -ENXIO;
 680                 goto err_out;
 681         }
 682
 683         /* Make sure all the following register writes are applied instantly */
 684         reg_value  = 0x1 << PVR5__BYPASS_DOUBLE_BUFFERING_SHIFT;
 685         reg_value |= 0x1 << PVR5__REGISTERS_VALID_SHIFT;
 686         pdp_write_reg(pdp, PVR5__PDP_PVR_PDP_REGISTER_UPDATE_CTRL, reg_value);
 687
 688         /* Power down mode */
 689         reg_value = 0x1 << PVR5__POWERDN_SHIFT;
 690         pdp_write_reg(pdp, PVR5__PDP_PVR_PDP_SYNCCTRL, reg_value);
 691
 692         /* Background color (green) */
 693         reg_value = 0x0099FF66;
 694         pdp_write_reg(pdp, PVR5__PDP_PVR_PDP_BGNDCOL, reg_value);
 695
 696         /* Set alpha blend mode to global alpha blending (10b / 2h) and
 697          * disable everything else.
 698          */
 699         reg_value = 0x2 << PVR5__GRPH1BLEND_SHIFT;
 700         pdp_write_reg(pdp, PVR5__PDP_PVR_PDP_GRPH1CTRL, reg_value);
 701
 702         /* Global alpha */
 703         reg_value = 0xff << PVR5__GRPH1GALPHA_SHIFT;
 704         pdp_write_reg(pdp, PVR5__PDP_PVR_PDP_GRPH1BLND, reg_value);
 705
 706         /* Reset base addr of the non-FBCDC part. This is not used. */
 707         pdp_write_reg(pdp, PVR5__PDP_PVR_PDP_GRPH1_BASEADDR, 0);
 708
 709         /* Graphics video pixel format:
 710          * 01000b / 8h 8-bit alpha + 24-bit rgb888 [RGBA].
 711          */
 712         pdp->current_drm_format = DRM_FORMAT_BGRA8888_DIRECT_16x4;
 713         reg_value = pdp_format(pdp->current_drm_format)
 714                         << PVR5__GRPH1PIXFMT_SHIFT;
 715         pdp_write_reg(pdp, PVR5__PDP_PVR_PDP_GRPH1SURF, reg_value);
 716
 717         /* Reset position of the plane */
 718         reg_value  = 0 << PVR5__GRPH1XSTART_SHIFT;
 719         reg_value |= 0 << PVR5__GRPH1YSTART_SHIFT;
 720         pdp_write_reg(pdp, PVR5__PDP_PVR_PDP_GRPH1POSN, reg_value);
 721
 722         /* Stride of surface in 16byte words - 1 */
 723         reg_value = (tdata->h_display * 4 / 16 - 1) << PVR5__GRPH1STRIDE_SHIFT;
 724         pdp_write_reg(pdp, PVR5__PDP_PVR_PDP_GRPH1STRIDE, reg_value);
 725
 726         /* Size:
 727          * Width of surface in pixels - 1
 728          * Height of surface in lines - 1 */
 729         reg_value  = (tdata->h_display - 1) << PVR5__GRPH1WIDTH_SHIFT;
 730         reg_value |= (tdata->v_display - 1) << PVR5__GRPH1HEIGHT_SHIFT;
 731         pdp_write_reg(pdp, PVR5__PDP_PVR_PDP_GRPH1SIZE, reg_value);
 732
 733         /* H-time */
 734         reg_value  = tdata->h_back_porch << PVR5__HBPS_SHIFT;
 735         reg_value |= tdata->h_total << PVR5__HT_SHIFT;
 736         pdp_write_reg(pdp, PVR5__PDP_PVR_PDP_HSYNC1, reg_value);
 737         reg_value  = tdata->h_active_start << PVR5__HAS_SHIFT;
 738         reg_value |= tdata->h_left_border << PVR5__HLBS_SHIFT;
 739         pdp_write_reg(pdp, PVR5__PDP_PVR_PDP_HSYNC2, reg_value);
 740         reg_value  = tdata->h_front_porch << PVR5__HFPS_SHIFT;
 741         reg_value |= tdata->h_right_border << PVR5__HRBS_SHIFT;
 742         pdp_write_reg(pdp, PVR5__PDP_PVR_PDP_HSYNC3, reg_value);
 743
 744         /* V-time */
 745         reg_value  = tdata->v_back_porch << PVR5__VBPS_SHIFT;
 746         reg_value |= tdata->v_total << PVR5__VT_SHIFT;
 747         pdp_write_reg(pdp, PVR5__PDP_PVR_PDP_VSYNC1, reg_value);
 748         reg_value  = tdata->v_active_start << PVR5__VAS_SHIFT;
 749         reg_value |= tdata->v_top_border << PVR5__VTBS_SHIFT;
 750         pdp_write_reg(pdp, PVR5__PDP_PVR_PDP_VSYNC2, reg_value);
 751         reg_value  = tdata->v_front_porch << PVR5__VFPS_SHIFT;
 752         reg_value |= tdata->v_bottom_border << PVR5__VBBS_SHIFT;
 753         pdp_write_reg(pdp, PVR5__PDP_PVR_PDP_VSYNC3, reg_value);
 754
 755         /* Horizontal data enable */
 756         reg_value  = tdata->h_left_border << PVR5__HDES_SHIFT;
 757         reg_value |= tdata->h_front_porch << PVR5__HDEF_SHIFT;
 758         pdp_write_reg(pdp, PVR5__PDP_PVR_PDP_HDECTRL, reg_value);
 759
 760         /* Vertical data enable */
 761         reg_value  = tdata->v_top_border << PVR5__VDES_SHIFT;
 762         reg_value |= tdata->v_front_porch << PVR5__VDEF_SHIFT;
 763         pdp_write_reg(pdp, PVR5__PDP_PVR_PDP_VDECTRL, reg_value);
 764
 765         /* Vertical event start and vertical fetch start */
 766         reg_value  = tdata->v_back_porch << PVR5__VFETCH_SHIFT;
 767         reg_value |= tdata->v_bottom_border << PVR5__VEVENT_SHIFT;
 768         pdp_write_reg(pdp, PVR5__PDP_PVR_PDP_VEVENT, reg_value);
 769
 770         /* Now enable the fbdc module (direct_16x4) */
 771         /* Set the number of tiles per plane */
 772         pdp_write_fbdc_reg(pdp, PVR5__PDP_FBDC_INTRFC_NUM_TILES,
 773                 (tdata->h_display * tdata->v_display) / (16 * 4));
 774         /* Set the number of the tile per line */
 775         pdp_write_fbdc_reg(pdp, PVR5__PDP_FBDC_INTRFC_PER_LINE,
 776                                            tdata->h_display / 16);
 777         /* Set the color format */
 778         pdp_write_fbdc_reg(pdp, PVR5__PDP_FBDC_INTRFC_PIXEL_FORMAT, 0xc);
 779         /* Reset base address */
 780         pdp_write_fbdc_reg(pdp, PVR5__PDP_FBDC_INTRFC_BASE_ADDRESS, 0x0);
 781         /* Set invalidate request */
 782         reg_value = pdp_read_reg(pdp, PVR5__PDP_PVR_PDP_SYNCCTRL);
 783         if ((reg_value & PVR5__VSPOL_MASK) >> PVR5__VSPOL_SHIFT == 0x1) {
 784                 pdp_write_fbdc_reg(pdp,
 785                         PVR5__PDP_FBDC_INTRFC_INVALIDATE_REQUEST, 0x1);
 786         } else {
 787                 pdp_write_fbdc_reg(pdp,
 788                         PVR5__PDP_FBDC_INTRFC_INVALIDATE_REQUEST, 0x0);
 789         }
 790
 791         /* Enable vsync again */
 792         reg_value = pdp_read_reg(pdp, PVR5__PDP_PVR_PDP_SYNCCTRL);
 793         reg_value &= ~(PVR5__SYNCACTIVE_MASK);
 794         reg_value |= 0x1 << PVR5__SYNCACTIVE_SHIFT;
 795         reg_value &= ~(PVR5__BLNKPOL_MASK);
 796         reg_value |= 0x1 << PVR5__BLNKPOL_SHIFT;
 797         pdp_write_reg(pdp, PVR5__PDP_PVR_PDP_SYNCCTRL, reg_value);
 798
 799         /* Update control */
 800         reg_value  = 0x1 << PVR5__USE_VBLANK_SHIFT;
 801         reg_value |= 0x1 << PVR5__REGISTERS_VALID_SHIFT;
 802         pdp_write_reg(pdp, PVR5__PDP_PVR_PDP_REGISTER_UPDATE_CTRL, reg_value);
 803
 804         intf->current_mode = *mode;
 805         pdp->current_timings = tdata;
 806
 807         pdp_enable_hdmi(pdp);
 808
 809 err_out:
 810         return err;
 811 }
 812
 813 static int pdp_blank(struct adf_interface *intf,
 814         u8 state)
 815 {
 816         struct adf_pdp_device *pdp;
 817         u32 reg_value;
 818
 819         pdp = devres_find(intf->base.parent->dev, pdp_devres_release,
 820                           NULL, NULL);
 821
 822         if (state != DRM_MODE_DPMS_OFF && state != DRM_MODE_DPMS_ON)
 823                 return -EINVAL;
 824
 825         reg_value = pdp_read_reg(pdp, PVR5__PDP_PVR_PDP_SYNCCTRL);
 826         switch (state) {
 827         case DRM_MODE_DPMS_OFF:
 828                 reg_value &= ~(PVR5__POWERDN_MASK);
 829                 reg_value |= 0x1 << PVR5__POWERDN_SHIFT;
 830 /*              pdp_blank_hdmi(pdp);*/
 831                 break;
 832         case DRM_MODE_DPMS_ON:
 833                 reg_value &= ~(PVR5__POWERDN_MASK);
 834 /*              pdp_unblank_hdmi(pdp);*/
 835                 break;
 836         }
 837         pdp_write_reg(pdp, PVR5__PDP_PVR_PDP_SYNCCTRL, reg_value);
 838
 839         return 0;
 840 }
 841
 842 static int pdp_alloc_simple_buffer(struct adf_interface *intf, u16 w, u16 h,
 843         u32 format, struct dma_buf **dma_buf, u32 *offset, u32 *pitch)
 844 {
 845         u32 size = w * h * pdp_format_bpp(format);
 846         struct adf_pdp_device *pdp;
 847         struct ion_handle *hdl;
 848         int err = 0;
 849
 850         pdp = devres_find(intf->base.parent->dev, pdp_devres_release,
 851                           NULL, NULL);
 852         hdl = ion_alloc(pdp->ion_client, size, 0,
 853                 (1 << pdp->pdata->ion_heap_id), 0);
 854         if (IS_ERR(hdl)) {
 855                 err = PTR_ERR(hdl);
 856                 dev_err(&pdp->pdev->dev, "ion_alloc failed (%d)\n", err);
 857                 goto err_out;
 858         }
 859         *dma_buf = ion_share_dma_buf(pdp->ion_client, hdl);
 860         if (IS_ERR(*dma_buf)) {
 861                 err = PTR_ERR(hdl);
 862                 dev_err(&pdp->pdev->dev,
 863                         "ion_share_dma_buf failed (%d)\n", err);
 864                 goto err_free_buffer;
 865         }
 866         *pitch = w * pdp_format_bpp(format);
 867         *offset = 0;
 868 err_free_buffer:
 869         ion_free(pdp->ion_client, hdl);
 870 err_out:
 871         return err;
 872 }
 873
 874 static int pdp_describe_simple_post(struct adf_interface *intf,
 875         struct adf_buffer *fb, void *data, size_t *size)
 876 {
 877         struct adf_post_ext *post_ext = data;
 878         static int post_id;
 879
 880         struct drm_clip_rect full_screen = {
 881                 .x2 = ADF_PDP_WIDTH,
 882                 .y2 = ADF_PDP_HEIGHT,
 883         };
 884
 885         /* NOTE: an upstream ADF bug means we can't test *size instead */
 886         BUG_ON(ADF_MAX_CUSTOM_DATA_SIZE < sizeof(struct adf_post_ext) +
 887                                 1 * sizeof(struct adf_buffer_config_ext));
 888
 889         *size = sizeof(struct adf_post_ext) +
 890                 1 * sizeof(struct adf_buffer_config_ext);
 891
 892         post_ext->post_id = ++post_id;
 893
 894         post_ext->bufs_ext[0].crop        = full_screen;
 895         post_ext->bufs_ext[0].display     = full_screen;
 896         post_ext->bufs_ext[0].transform   = ADF_BUFFER_TRANSFORM_NONE_EXT;
 897         post_ext->bufs_ext[0].blend_type  = ADF_BUFFER_BLENDING_PREMULT_EXT;
 898         post_ext->bufs_ext[0].plane_alpha = 0xff;
 899
 900         return 0;
 901 }
 902
 903 static int
 904 adf_pdp_open(struct adf_obj *obj, struct inode *inode, struct file *file)
 905 {
 906         struct adf_device *dev = (struct adf_device *)obj->parent;
 907         struct adf_pdp_device *pdp;
 908
 909         pdp = devres_find(dev->dev, pdp_devres_release, NULL, NULL);
 910
 911         atomic_inc(&pdp->refcount);
 912         return 0;
 913 }
 914
 915 static void
 916 adf_pdp_release(struct adf_obj *obj, struct inode *inode, struct file *file)
 917 {
 918         struct adf_device *dev = (struct adf_device *)obj->parent;
 919         struct sync_fence *release_fence;
 920         struct adf_pdp_device *pdp;
 921
 922         pdp = devres_find(dev->dev, pdp_devres_release, NULL, NULL);
 923
 924         if (atomic_dec_return(&pdp->refcount))
 925                 return;
 926
 927         /* Make sure we have no outstanding posts waiting */
 928         atomic_set(&pdp->vsync_triggered, 1);
 929         wake_up_all(&pdp->vsync_wait_queue);
 930         /* This special "null" flip works around a problem with ADF
 931          * which leaves buffers pinned by the display engine even
 932          * after all ADF clients have closed.
 933          *
 934          * The "null" flip is pipelined like any other. The user won't
 935          * be able to unload this module until it has been posted.
 936          */
 937         release_fence = adf_device_post(dev, NULL, 0, NULL, 0, NULL, 0);
 938         if (IS_ERR_OR_NULL(release_fence)) {
 939                 dev_err(dev->dev,
 940                         "Failed to queue null flip command (err=%d).\n",
 941                         (int)PTR_ERR(release_fence));
 942                 return;
 943         }
 944
 945         sync_fence_put(release_fence);
 946 }
 947
 948 static int adf_img_validate_custom_format(struct adf_device *dev,
 949         struct adf_buffer *buf)
 950 {
 951         int i;
 952
 953         for (i = 0; pdp_format_table[i].drm_format != 0; i++) {
 954                 if (pdp_format_table[i].drm_format == buf->format)
 955                         return 1;
 956         }
 957         return 0;
 958 }
 959
 960 static int pdp_validate(struct adf_device *dev, struct adf_post *cfg,
 961         void **driver_state)
 962 {
 963         struct adf_pdp_device *pdp;
 964         int err;
 965
 966         pdp = devres_find(dev->dev, pdp_devres_release, NULL, NULL);
 967
 968         err = adf_img_validate_simple(dev, cfg, driver_state);
 969         if (err == 0 && cfg->mappings) {
 970                 /* We store a snapshot of num_validates in driver_state at the
 971                  * time validate was called, which will be passed to the post
 972                  * function. This snapshot is copied into (i.e. overwrites)
 973                  * num_posts, rather then simply incrementing num_posts, to
 974                  * handle cases e.g. during fence timeouts where validates
 975                  * are called without corresponding posts.
 976                  */
 977                 int *validates = kmalloc(sizeof(*validates), GFP_KERNEL);
 978                 *validates = atomic_inc_return(&pdp->num_validates);
 979                 *driver_state = validates;
 980         } else {
 981                 *driver_state = NULL;
 982         }
 983         return err;
 984 }
 985
 986 static void pdp_state_free(struct adf_device *dev, void *driver_state)
 987 {
 988         kfree(driver_state);
 989 }
 990
 991 static struct adf_device_ops adf_pdp_device_ops = {
 992         .owner = THIS_MODULE,
 993         .base = {
 994                 .open = adf_pdp_open,
 995                 .release = adf_pdp_release,
 996                 .ioctl = adf_img_ioctl,
 997         },
 998         .validate_custom_format = adf_img_validate_custom_format,
 999         .validate = pdp_validate,
1000         .post = pdp_post,
1001         .state_free = pdp_state_free,
1002 };
1003
1004 static struct adf_interface_ops adf_pdp_interface_ops = {
1005         .base = {
1006                 .supports_event = pdp_supports_event,
1007                 .set_event = pdp_set_event,
1008         },
1009         .modeset = pdp_modeset,
1010         .blank = pdp_blank,
1011         .alloc_simple_buffer = pdp_alloc_simple_buffer,
1012         .describe_simple_post = pdp_describe_simple_post,
1013 };
1014
1015 static struct adf_overlay_engine_ops adf_pdp_overlay_ops = {
1016         .supported_formats = &pdp_supported_formats[0],
1017         .n_supported_formats = NUM_SUPPORTED_FORMATS,
1018 };
1019
1020 static int adf_pdp_probe_device(struct platform_device *pdev)
1021 {
1022         struct apollo_pdp_platform_data *pdata = pdev->dev.platform_data;
1023         struct pci_dev *pci_dev = to_pci_dev(pdev->dev.parent);
1024         int err = 0, i, default_mode_id;
1025         struct adf_pdp_device *pdp;
1026         struct resource *registers;
1027         u32 core_id, core_rev;
1028
1029         pdp = devres_alloc(pdp_devres_release, sizeof(*pdp), GFP_KERNEL);
1030         if (!pdp) {
1031                 err = -ENOMEM;
1032                 goto err_out;
1033         }
1034         devres_add(&pdev->dev, pdp);
1035
1036         pdp->pdata = pdata;
1037         pdp->pdev = pdev;
1038
1039         err = pci_enable_device(pci_dev);
1040         if (err) {
1041                 dev_err(&pdev->dev,
1042                         "Failed to enable PDP pci device (%d)\n", err);
1043                 goto err_out;
1044         }
1045
1046         atomic_set(&pdp->refcount, 0);
1047         atomic_set(&pdp->num_validates, 0);
1048         pdp->num_posts = 0;
1049
1050         pdp->ion_client = ion_client_create(pdata->ion_device, "adf_pdp");
1051         if (IS_ERR(pdp->ion_client)) {
1052                 err = PTR_ERR(pdp->ion_client);
1053                 dev_err(&pdev->dev,
1054                         "Failed to create PDP ION client (%d)\n", err);
1055                 goto err_disable_pci;
1056         }
1057
1058         registers = platform_get_resource_byname(pdev,
1059                                                  IORESOURCE_MEM,
1060                                                  "tc5-pdp2-regs");
1061         pdp->regs = devm_ioremap_resource(&pdev->dev, registers);
1062         if (IS_ERR(pdp->regs)) {
1063                 err = PTR_ERR(pdp->regs);
1064                 dev_err(&pdev->dev, "Failed to map PDP registers (%d)\n", err);
1065                 goto err_destroy_ion_client;
1066         }
1067         pdp->regs_size = resource_size(registers);
1068
1069         registers = platform_get_resource_byname(pdev,
1070                                                  IORESOURCE_MEM,
1071                                                  "tc5-pdp2-fbdc-regs");
1072         pdp->fbdc_regs = devm_ioremap_resource(&pdev->dev, registers);
1073         if (IS_ERR(pdp->fbdc_regs)) {
1074                 err = PTR_ERR(pdp->fbdc_regs);
1075                 dev_err(&pdev->dev, "Failed to map PDP fbdc registers (%d)\n",
1076                         err);
1077                 goto err_destroy_ion_client;
1078         }
1079         pdp->fbdc_regs_size = resource_size(registers);
1080
1081         registers = platform_get_resource_byname(pdev,
1082                                                  IORESOURCE_MEM,
1083                                                  "tc5-adv5711-regs");
1084         pdp->i2c_regs = devm_ioremap_resource(&pdev->dev, registers);
1085         if (IS_ERR(pdp->i2c_regs)) {
1086                 err = PTR_ERR(pdp->i2c_regs);
1087                 dev_err(&pdev->dev, "Failed to map ADV5711 i2c registers (%d)\n",
1088                         err);
1089                 goto err_destroy_ion_client;
1090         }
1091         pdp->i2c_regs_size = resource_size(registers);
1092
1093         core_id = pdp_read_reg(pdp, PVR5__PDP_PVR_PDP_CORE_ID);
1094         core_rev = pdp_read_reg(pdp, PVR5__PDP_PVR_PDP_CORE_REV);
1095
1096         dev_err(&pdev->dev, "pdp2 core id/rev: %d.%d.%d/%d.%d.%d\n",
1097                 (core_id & PVR5__GROUP_ID_MASK) >> PVR5__GROUP_ID_SHIFT,
1098                 (core_id & PVR5__CORE_ID_MASK) >> PVR5__CORE_ID_SHIFT,
1099                 (core_id & PVR5__CONFIG_ID_MASK) >> PVR5__CONFIG_ID_SHIFT,
1100                 (core_rev & PVR5__MAJOR_REV_MASK) >> PVR5__MAJOR_REV_SHIFT,
1101                 (core_rev & PVR5__MINOR_REV_MASK) >> PVR5__MINOR_REV_SHIFT,
1102                 (core_rev & PVR5__MAINT_REV_MASK) >> PVR5__MAINT_REV_SHIFT);
1103
1104
1105         err = adf_device_init(&pdp->adf_device, &pdp->pdev->dev,
1106                 &adf_pdp_device_ops, "pdp_device");
1107         if (err) {
1108                 dev_err(&pdev->dev, "Failed to init ADF device (%d)\n", err);
1109                 goto err_destroy_ion_client;
1110         }
1111
1112         err = adf_interface_init(&pdp->adf_interface, &pdp->adf_device,
1113                 ADF_INTF_DVI, 0, ADF_INTF_FLAG_PRIMARY, &adf_pdp_interface_ops,
1114                 "pdp_interface");
1115         if (err) {
1116                 dev_err(&pdev->dev, "Failed to init ADF interface (%d)\n", err);
1117                 goto err_destroy_adf_device;
1118         }
1119
1120         err = adf_overlay_engine_init(&pdp->adf_overlay, &pdp->adf_device,
1121                 &adf_pdp_overlay_ops, "pdp_overlay");
1122         if (err) {
1123                 dev_err(&pdev->dev, "Failed to init ADF overlay (%d)\n", err);
1124                 goto err_destroy_adf_interface;
1125         }
1126
1127         err = adf_attachment_allow(&pdp->adf_device, &pdp->adf_overlay,
1128                 &pdp->adf_interface);
1129         if (err) {
1130                 dev_err(&pdev->dev, "Failed to attach overlay (%d)\n", err);
1131                 goto err_destroy_adf_overlay;
1132         }
1133
1134         pdp->num_supported_modes = pdp_mode_count(pdp);
1135         pdp->supported_modes = kzalloc(sizeof(*pdp->supported_modes)
1136                 * pdp->num_supported_modes, GFP_KERNEL);
1137
1138         if (!pdp->supported_modes) {
1139                 dev_err(&pdev->dev, "Failed to allocate supported modeinfo structs\n");
1140                 err = -ENOMEM;
1141                 goto err_destroy_adf_overlay;
1142         }
1143
1144         for (i = 0; i < pdp->num_supported_modes; i++)
1145                 pdp_mode_to_drm_mode(pdp, i, &pdp->supported_modes[i]);
1146
1147         default_mode_id = pdp_mode_id(pdp, pdp_display_height,
1148                 pdp_display_width);
1149         if (default_mode_id == -1) {
1150                 default_mode_id = 0;
1151                 dev_err(&pdev->dev, "No modeline found for requested display size (%dx%d)\n",
1152                         pdp_display_width, pdp_display_height);
1153         }
1154
1155         /* Initial modeset... */
1156         err = pdp_modeset(&pdp->adf_interface,
1157                 &pdp->supported_modes[default_mode_id]);
1158         if (err) {
1159                 dev_err(&pdev->dev, "Initial modeset failed (%d)\n", err);
1160                 goto err_destroy_modelist;
1161         }
1162
1163         err = adf_hotplug_notify_connected(&pdp->adf_interface,
1164                 pdp->supported_modes, pdp->num_supported_modes);
1165         if (err) {
1166                 dev_err(&pdev->dev, "Initial hotplug notify failed (%d)\n",
1167                         err);
1168                 goto err_destroy_modelist;
1169         }
1170         err = apollo_set_interrupt_handler(pdp->pdev->dev.parent,
1171                                            APOLLO_INTERRUPT_TC5_PDP,
1172                                            pdp_irq_handler, pdp);
1173         if (err) {
1174                 dev_err(&pdev->dev, "Failed to set interrupt handler (%d)\n",
1175                         err);
1176                 goto err_destroy_modelist;
1177         }
1178
1179         init_waitqueue_head(&pdp->vsync_wait_queue);
1180         atomic_set(&pdp->requested_vsync_state, 0);
1181         atomic_set(&pdp->vsync_state, 0);
1182
1183         if (debugfs_dma_buf_init("pdp_raw"))
1184                 dev_err(&pdev->dev, "Failed to create debug fs file for raw access\n");
1185
1186         return err;
1187 err_destroy_modelist:
1188         kfree(pdp->supported_modes);
1189 err_destroy_adf_overlay:
1190         adf_overlay_engine_destroy(&pdp->adf_overlay);
1191 err_destroy_adf_interface:
1192         adf_interface_destroy(&pdp->adf_interface);
1193 err_destroy_adf_device:
1194         adf_device_destroy(&pdp->adf_device);
1195 err_destroy_ion_client:
1196         ion_client_destroy(pdp->ion_client);
1197 err_disable_pci:
1198         pci_disable_device(pci_dev);
1199 err_out:
1200         dev_err(&pdev->dev, "Failed to initialise PDP device\n");
1201         return err;
1202 }
1203
1204 static int adf_pdp_remove_device(struct platform_device *pdev)
1205 {
1206         struct pci_dev *pci_dev = to_pci_dev(pdev->dev.parent);
1207         struct adf_pdp_device *pdp;
1208         int err = 0;
1209
1210         pdp = devres_find(&pdev->dev, pdp_devres_release, NULL, NULL);
1211
1212         debugfs_dma_buf_deinit();
1213
1214         /* Disable scanout */
1215         pdp_disable_scanout(pdp);
1216         pdp_disable_ints(pdp);
1217         apollo_set_interrupt_handler(pdp->pdev->dev.parent,
1218                                      APOLLO_INTERRUPT_TC5_PDP,
1219                                      NULL, NULL);
1220         /* Disable hdmi */
1221         pdp_blank_hdmi(pdp);
1222         kfree(pdp->supported_modes);
1223         adf_overlay_engine_destroy(&pdp->adf_overlay);
1224         adf_interface_destroy(&pdp->adf_interface);
1225         adf_device_destroy(&pdp->adf_device);
1226         ion_client_destroy(pdp->ion_client);
1227         pci_disable_device(pci_dev);
1228         return err;
1229 }
1230
1231 static void adf_pdp_shutdown_device(struct platform_device *pdev)
1232 {
1233         /* No cleanup needed, all done in remove_device */
1234 }
1235
1236 static struct platform_device_id pdp_platform_device_id_table[] = {
1237         { .name = APOLLO_DEVICE_NAME_PDP, .driver_data = 0 },
1238         { },
1239 };
1240
1241 static struct platform_driver pdp_platform_driver = {
1242         .probe = adf_pdp_probe_device,
1243         .remove = adf_pdp_remove_device,
1244         .shutdown = adf_pdp_shutdown_device,
1245         .driver = {
1246                 .name = DRV_NAME,
1247         },
1248         .id_table = pdp_platform_device_id_table,
1249 };
1250
1251 static int __init adf_pdp_init(void)
1252 {
1253         return platform_driver_register(&pdp_platform_driver);
1254 }
1255
1256 static void __exit adf_pdp_exit(void)
1257 {
1258         platform_driver_unregister(&pdp_platform_driver);
1259 }
1260
1261 module_init(adf_pdp_init);
1262 module_exit(adf_pdp_exit);