1 /**************************************************************************/ /*!
3 @Title Common Device header
4 @Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
5 @Description Device related function templates and defines
6 @License Dual MIT/GPLv2
8 The contents of this file are subject to the MIT license as set out below.
10 Permission is hereby granted, free of charge, to any person obtaining a copy
11 of this software and associated documentation files (the "Software"), to deal
12 in the Software without restriction, including without limitation the rights
13 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
14 copies of the Software, and to permit persons to whom the Software is
15 furnished to do so, subject to the following conditions:
17 The above copyright notice and this permission notice shall be included in
18 all copies or substantial portions of the Software.
20 Alternatively, the contents of this file may be used under the terms of
21 the GNU General Public License Version 2 ("GPL") in which case the provisions
22 of GPL are applicable instead of those above.
24 If you wish to allow use of your version of this file only under the terms of
25 GPL, and not to allow others to use your version of this file under the terms
26 of the MIT license, indicate your decision by deleting the provisions above
27 and replace them with the notice and other provisions required by GPL as set
28 out in the file called "GPL-COPYING" included in this distribution. If you do
29 not delete the provisions above, a recipient may use your version of this file
30 under the terms of either the MIT license or GPL.
32 This License is also included in this distribution in the file called
35 EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
36 PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
37 BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
38 PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
39 COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
40 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
41 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
42 */ /***************************************************************************/
48 #include "devicemem_heapcfg.h"
49 #include "mmu_common.h"
50 #include "ra.h" /* RA_ARENA */
51 #include "pvrsrv_device.h"
54 #include <powervr/sync_external.h>
61 #if defined(SUPPORT_GPUVIRT_VALIDATION)
62 #include "virt_validation_defs.h"
65 #if defined(SUPPORT_BUFFER_SYNC)
66 struct pvr_buffer_sync_context;
69 typedef struct _PVRSRV_POWER_DEV_TAG_ PVRSRV_POWER_DEV;
71 #if defined(PVRSRV_ENABLE_FULL_SYNC_TRACKING)
75 /*********************************************************************/ /*!
76 @Function AllocUFOCallback
77 @Description Device specific callback for allocation of an UFO block
79 @Input psDeviceNode Pointer to device node to allocate
81 @Output ppsMemDesc Pointer to pointer for the memdesc of
83 @Output pui32SyncAddr FW Base address of the UFO block
84 @Output puiSyncPrimBlockSize Size of the UFO block
86 @Return PVRSRV_OK if allocation was successful
88 /*********************************************************************/
89 typedef PVRSRV_ERROR (*AllocUFOBlockCallback)(struct _PVRSRV_DEVICE_NODE_ *psDeviceNode,
90 DEVMEM_MEMDESC **ppsMemDesc,
91 IMG_UINT32 *pui32SyncAddr,
92 IMG_UINT32 *puiSyncPrimBlockSize);
94 /*********************************************************************/ /*!
95 @Function FreeUFOCallback
96 @Description Device specific callback for freeing of an UFO
98 @Input psDeviceNode Pointer to device node that the UFO block was
100 @Input psMemDesc Pointer to pointer for the memdesc of
101 the UFO block to free.
103 /*********************************************************************/
104 typedef void (*FreeUFOBlockCallback)(struct _PVRSRV_DEVICE_NODE_ *psDeviceNode,
105 DEVMEM_MEMDESC *psMemDesc);
107 typedef struct _PVRSRV_DEVICE_IDENTIFIER_
109 /* Pdump memory and register bank names */
110 IMG_CHAR *pszPDumpDevName;
111 IMG_CHAR *pszPDumpRegName;
112 } PVRSRV_DEVICE_IDENTIFIER;
114 typedef struct _DEVICE_MEMORY_INFO_
116 /* heap count. Doesn't include additional heaps from PVRSRVCreateDeviceMemHeap */
117 IMG_UINT32 ui32HeapCount;
119 /* Blueprints for creating new device memory contexts */
120 IMG_UINT32 uiNumHeapConfigs;
121 DEVMEM_HEAP_CONFIG *psDeviceMemoryHeapConfigArray;
122 DEVMEM_HEAP_BLUEPRINT *psDeviceMemoryHeap;
123 } DEVICE_MEMORY_INFO;
126 typedef struct _PG_HANDLE_
131 IMG_UINT64 ui64Handle;
133 /*Order of the corresponding allocation */
134 IMG_UINT32 ui32Order;
137 #define MMU_BAD_PHYS_ADDR (0xbadbad00badULL)
138 typedef struct __DUMMY_PAGE__
140 /*Page handle for the dummy page allocated (UMA/LMA)*/
141 PG_HANDLE sDummyPageHandle;
142 POS_LOCK psDummyPgLock;
143 ATOMIC_T atRefCounter;
144 /*Dummy page size in terms of log2 */
145 IMG_UINT32 ui32Log2DummyPgSize;
146 IMG_UINT64 ui64DummyPgPhysAddr;
148 #define DUMMY_PAGE ("DUMMY_PAGE")
149 IMG_HANDLE hPdumpDummyPg;
151 } PVRSRV_DUMMY_PAGE ;
153 typedef enum _PVRSRV_DEVICE_STATE_
155 PVRSRV_DEVICE_STATE_UNDEFINED = 0,
156 PVRSRV_DEVICE_STATE_INIT,
157 PVRSRV_DEVICE_STATE_ACTIVE,
158 PVRSRV_DEVICE_STATE_DEINIT,
159 PVRSRV_DEVICE_STATE_BAD,
160 } PVRSRV_DEVICE_STATE;
162 typedef enum _PVRSRV_DEVICE_HEALTH_STATUS_
164 PVRSRV_DEVICE_HEALTH_STATUS_OK = 0,
165 PVRSRV_DEVICE_HEALTH_STATUS_NOT_RESPONDING,
166 PVRSRV_DEVICE_HEALTH_STATUS_DEAD
167 } PVRSRV_DEVICE_HEALTH_STATUS;
169 typedef enum _PVRSRV_DEVICE_HEALTH_REASON_
171 PVRSRV_DEVICE_HEALTH_REASON_NONE = 0,
172 PVRSRV_DEVICE_HEALTH_REASON_ASSERTED,
173 PVRSRV_DEVICE_HEALTH_REASON_POLL_FAILING,
174 PVRSRV_DEVICE_HEALTH_REASON_TIMEOUTS,
175 PVRSRV_DEVICE_HEALTH_REASON_QUEUE_CORRUPT,
176 PVRSRV_DEVICE_HEALTH_REASON_QUEUE_STALLED
177 } PVRSRV_DEVICE_HEALTH_REASON;
179 typedef PVRSRV_ERROR (*FN_CREATERAMBACKEDPMR)(struct _PVRSRV_DEVICE_NODE_ *psDevNode,
180 IMG_DEVMEM_SIZE_T uiSize,
181 IMG_DEVMEM_SIZE_T uiChunkSize,
182 IMG_UINT32 ui32NumPhysChunks,
183 IMG_UINT32 ui32NumVirtChunks,
184 IMG_UINT32 *pui32MappingTable,
185 IMG_UINT32 uiLog2PageSize,
186 PVRSRV_MEMALLOCFLAGS_T uiFlags,
187 const IMG_CHAR *pszAnnotation,
190 typedef struct _PVRSRV_DEVICE_NODE_
192 PVRSRV_DEVICE_IDENTIFIER sDevId;
194 PVRSRV_DEVICE_STATE eDevState;
195 ATOMIC_T eHealthStatus; /* Holds values from PVRSRV_DEVICE_HEALTH_STATUS */
196 ATOMIC_T eHealthReason; /* Holds values from PVRSRV_DEVICE_HEALTH_REASON */
198 IMG_HANDLE *hDebugTable;
200 /* device specific MMU attributes */
201 MMU_DEVICEATTRIBS *psMMUDevAttrs;
202 /* device specific MMU firmware atrributes, used only in some devices*/
203 MMU_DEVICEATTRIBS *psFirmwareMMUDevAttrs;
205 /* lock for power state transitions */
207 /* current system device power state */
208 PVRSRV_SYS_POWER_STATE eCurrentSysPowerState;
209 PVRSRV_POWER_DEV *psPowerDev;
212 callbacks the device must support:
215 FN_CREATERAMBACKEDPMR pfnCreateRamBackedPMR[PVRSRV_DEVICE_PHYS_HEAP_LAST];
217 PVRSRV_ERROR (*pfnDevPxAlloc)(struct _PVRSRV_DEVICE_NODE_ *psDevNode, size_t uiSize,
218 PG_HANDLE *psMemHandle, IMG_DEV_PHYADDR *psDevPAddr);
220 void (*pfnDevPxFree)(struct _PVRSRV_DEVICE_NODE_ *psDevNode, PG_HANDLE *psMemHandle);
222 PVRSRV_ERROR (*pfnDevPxMap)(struct _PVRSRV_DEVICE_NODE_ *psDevNode, PG_HANDLE *pshMemHandle,
223 size_t uiSize, IMG_DEV_PHYADDR *psDevPAddr,
226 void (*pfnDevPxUnMap)(struct _PVRSRV_DEVICE_NODE_ *psDevNode,
227 PG_HANDLE *psMemHandle, void *pvPtr);
229 PVRSRV_ERROR (*pfnDevPxClean)(struct _PVRSRV_DEVICE_NODE_ *psDevNode,
230 PG_HANDLE *pshMemHandle,
232 IMG_UINT32 uiLength);
234 IMG_UINT32 uiMMUPxLog2AllocGran;
236 void (*pfnMMUCacheInvalidate)(struct _PVRSRV_DEVICE_NODE_ *psDevNode,
237 IMG_HANDLE hDeviceData,
241 PVRSRV_ERROR (*pfnMMUCacheInvalidateKick)(struct _PVRSRV_DEVICE_NODE_ *psDevNode,
242 IMG_UINT32 *pui32NextMMUInvalidateUpdate,
243 IMG_BOOL bInterrupt);
245 IMG_UINT32 (*pfnMMUCacheGetInvalidateCounter)(struct _PVRSRV_DEVICE_NODE_ *psDevNode);
248 void (*pfnDumpDebugInfo)(struct _PVRSRV_DEVICE_NODE_ *psDevNode);
250 PVRSRV_ERROR (*pfnUpdateHealthStatus)(struct _PVRSRV_DEVICE_NODE_ *psDevNode,
251 IMG_BOOL bIsTimerPoll);
253 PVRSRV_ERROR (*pfnResetHWRLogs)(struct _PVRSRV_DEVICE_NODE_ *psDevNode);
255 /* Method to drain device HWPerf packets from firmware buffer to host buffer */
256 PVRSRV_ERROR (*pfnServiceHWPerf)(struct _PVRSRV_DEVICE_NODE_ *psDevNode);
258 PVRSRV_ERROR (*pfnDeviceVersionString)(struct _PVRSRV_DEVICE_NODE_ *psDevNode, IMG_CHAR **ppszVersionString);
260 PVRSRV_ERROR (*pfnDeviceClockSpeed)(struct _PVRSRV_DEVICE_NODE_ *psDevNode, IMG_PUINT32 pui32RGXClockSpeed);
262 PVRSRV_ERROR (*pfnSoftReset)(struct _PVRSRV_DEVICE_NODE_ *psDevNode, IMG_UINT64 ui64ResetValue1, IMG_UINT64 ui64ResetValue2);
264 #if defined(SUPPORT_KERNEL_SRVINIT) && defined(RGXFW_ALIGNCHECKS)
265 PVRSRV_ERROR (*pfnAlignmentCheck)(struct _PVRSRV_DEVICE_NODE_ *psDevNode, IMG_UINT32 ui32FWAlignChecksSize, IMG_UINT32 aui32FWAlignChecks[]);
267 IMG_BOOL (*pfnCheckDeviceFeature)(struct _PVRSRV_DEVICE_NODE_ *psDevNode, IMG_UINT64 ui64FeatureMask);
269 IMG_INT32 (*pfnGetDeviceFeatureValue)(struct _PVRSRV_DEVICE_NODE_ *psDevNode, IMG_UINT64 ui64FeatureMask);
271 PVRSRV_DEVICE_CONFIG *psDevConfig;
273 /* device post-finalise compatibility check */
274 PVRSRV_ERROR (*pfnInitDeviceCompatCheck) (struct _PVRSRV_DEVICE_NODE_*);
276 /* information about the device's address space and heaps */
277 DEVICE_MEMORY_INFO sDevMemoryInfo;
279 /* device's shared-virtual-memory heap size */
280 IMG_UINT64 ui64GeneralSVMHeapSize;
282 /* private device information */
287 #if defined(SUPPORT_GPUVIRT_VALIDATION)
288 RA_ARENA *psOSidSubArena[GPUVIRT_VALIDATION_NUM_OS];
292 #define PVRSRV_MAX_RA_NAME_LENGTH (50)
293 RA_ARENA **apsLocalDevMemArenas;
294 IMG_CHAR **apszRANames;
295 IMG_UINT32 ui32NumOfLocalMemArenas;
297 #if defined(SUPPORT_PVRSRV_GPUVIRT)
298 IMG_CHAR szKernelFwRAName[RGXFW_NUM_OS][PVRSRV_MAX_RA_NAME_LENGTH];
299 RA_ARENA *psKernelFwMemArena[RGXFW_NUM_OS];
300 IMG_UINT32 uiKernelFwRAIdx;
301 RA_BASE_T ui64RABase[RGXFW_NUM_OS];
304 IMG_UINT32 ui32RegisteredPhysHeaps;
305 PHYS_HEAP **papsRegisteredPhysHeaps;
308 * Pointers to the device's physical memory heap(s)
309 * The first entry (apsPhysHeap[PVRSRV_DEVICE_PHYS_HEAP_GPU_LOCAL]) will be used for allocations
310 * where the PVRSRV_MEMALLOCFLAG_CPU_LOCAL flag is not set. Normally this will be an LMA heap
311 * (but the device configuration could specify a UMA heap here, if desired)
312 * The second entry (apsPhysHeap[PVRSRV_DEVICE_PHYS_HEAP_CPU_LOCAL]) will be used for allocations
313 * where the PVRSRV_MEMALLOCFLAG_CPU_LOCAL flag is set. Normally this will be a UMA heap
314 * (but the configuration could specify an LMA heap here, if desired)
315 * The third entry (apsPhysHeap[PVRSRV_DEVICE_PHYS_HEAP_FW_LOCAL]) will be used for allocations
316 * where the PVRSRV_MEMALLOCFLAG_FW_LOCAL flag is set; this is used when SUPPORT_PVRSRV_GPUVIRT is enabled
317 * The device configuration will always specify two physical heap IDs - in the event of the device
318 * only using one physical heap, both of these IDs will be the same, and hence both pointers below
319 * will also be the same; when SUPPORT_PVRSRV_GPUVIRT is enabled the device configuration specifies
320 * three physical heap IDs, the last being for PVRSRV_DEVICE_PHYS_HEAP_FW_LOCAL allocations
322 PHYS_HEAP *apsPhysHeap[PVRSRV_DEVICE_PHYS_HEAP_LAST];
324 struct _PVRSRV_DEVICE_NODE_ *psNext;
325 struct _PVRSRV_DEVICE_NODE_ **ppsThis;
327 /* Functions for notification about memory contexts */
328 PVRSRV_ERROR (*pfnRegisterMemoryContext)(struct _PVRSRV_DEVICE_NODE_ *psDeviceNode,
329 MMU_CONTEXT *psMMUContext,
330 IMG_HANDLE *hPrivData);
331 void (*pfnUnregisterMemoryContext)(IMG_HANDLE hPrivData);
333 /* Functions for allocation/freeing of UFOs */
334 AllocUFOBlockCallback pfnAllocUFOBlock; /*!< Callback for allocation of a block of UFO memory */
335 FreeUFOBlockCallback pfnFreeUFOBlock; /*!< Callback for freeing of a block of UFO memory */
337 #if defined(SUPPORT_BUFFER_SYNC)
338 struct pvr_buffer_sync_context *psBufferSyncContext;
341 IMG_HANDLE hSyncServerNotify;
342 POS_LOCK hSyncServerListLock;
343 DLLIST_NODE sSyncServerSyncsList;
345 #if defined(PVRSRV_ENABLE_FULL_SYNC_TRACKING)
346 IMG_HANDLE hSyncServerRecordNotify;
347 POS_LOCK hSyncServerRecordLock;
348 DLLIST_NODE sSyncServerRecordList;
349 struct SYNC_RECORD *apsSyncServerRecordsFreed[PVRSRV_FULL_SYNC_TRACKING_HISTORY_LEN];
350 IMG_UINT32 uiSyncServerRecordFreeIdx;
353 PSYNC_PRIM_CONTEXT hSyncPrimContext;
355 PVRSRV_CLIENT_SYNC_PRIM *psSyncPrim;
356 /* With this sync-prim we make sure the MMU cache is flushed
357 * before we free the page table memory */
358 PVRSRV_CLIENT_SYNC_PRIM *psMMUCacheSyncPrim;
359 IMG_UINT32 ui32NextMMUInvalidateUpdate;
361 IMG_HANDLE hCmdCompNotify;
362 IMG_HANDLE hDbgReqNotify;
363 IMG_HANDLE hHtbDbgReqNotify;
364 IMG_HANDLE hAppHintDbgReqNotify;
366 PVRSRV_DUMMY_PAGE sDummyPage;
368 DLLIST_NODE sMemoryContextPageFaultNotifyListHead;
371 /* device-level callback which is called when pdump.exe starts.
372 * Should be implemented in device-specific init code, e.g. rgxinit.c
374 PVRSRV_ERROR (*pfnPDumpInitDevice)(struct _PVRSRV_DEVICE_NODE_ *psDeviceNode);
375 /* device-level callback to return pdump ID associated to a memory context */
376 IMG_UINT32 (*pfnMMUGetContextID)(IMG_HANDLE hDevMemContext);
378 } PVRSRV_DEVICE_NODE;
380 PVRSRV_ERROR IMG_CALLCONV PVRSRVDeviceFinalise(PVRSRV_DEVICE_NODE *psDeviceNode,
381 IMG_BOOL bInitSuccessful);
383 PVRSRV_ERROR IMG_CALLCONV PVRSRVDevInitCompatCheck(PVRSRV_DEVICE_NODE *psDeviceNode);
385 PVRSRV_ERROR IMG_CALLCONV RGXClientConnectCompatCheck_ClientAgainstFW(PVRSRV_DEVICE_NODE * psDeviceNode, IMG_UINT32 ui32ClientBuildOptions);
388 #endif /* __DEVICE_H__ */
390 /******************************************************************************
391 End of file (device.h)
392 ******************************************************************************/