1 /*************************************************************************/ /*!
3 @Title arm specific OS functions
4 @Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
5 @Description OS functions who's implementation are processor specific
6 @License Dual MIT/GPLv2
8 The contents of this file are subject to the MIT license as set out below.
10 Permission is hereby granted, free of charge, to any person obtaining a copy
11 of this software and associated documentation files (the "Software"), to deal
12 in the Software without restriction, including without limitation the rights
13 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
14 copies of the Software, and to permit persons to whom the Software is
15 furnished to do so, subject to the following conditions:
17 The above copyright notice and this permission notice shall be included in
18 all copies or substantial portions of the Software.
20 Alternatively, the contents of this file may be used under the terms of
21 the GNU General Public License Version 2 ("GPL") in which case the provisions
22 of GPL are applicable instead of those above.
24 If you wish to allow use of your version of this file only under the terms of
25 GPL, and not to allow others to use your version of this file under the terms
26 of the MIT license, indicate your decision by deleting the provisions above
27 and replace them with the notice and other provisions required by GPL as set
28 out in the file called "GPL-COPYING" included in this distribution. If you do
29 not delete the provisions above, a recipient may use your version of this file
30 under the terms of either the MIT license or GPL.
32 This License is also included in this distribution in the file called
35 EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
36 PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
37 BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
38 PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
39 COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
40 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
41 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
42 */ /**************************************************************************/
43 #include <linux/version.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/spinlock.h>
46 #if (LINUX_VERSION_CODE < KERNEL_VERSION(3,15,0))
47 #include <asm/system.h>
49 #include <asm/cacheflush.h>
51 #include "pvrsrv_error.h"
52 #include "img_types.h"
54 #include "pvr_debug.h"
58 #if defined(CONFIG_OUTER_CACHE)
60 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,16,0))
62 /* Since 3.16 the outer_xxx() functions require irqs to be disabled and no
63 * other cache masters must operate on the outer cache. */
64 static DEFINE_SPINLOCK(gsCacheFlushLock);
66 #define OUTER_CLEAN_RANGE() { \
67 unsigned long uiLockFlags; \
69 spin_lock_irqsave(&gsCacheFlushLock, uiLockFlags); \
70 outer_clean_range(0, ULONG_MAX); \
71 spin_unlock_irqrestore(&gsCacheFlushLock, uiLockFlags); \
74 #define OUTER_FLUSH_ALL() { \
75 unsigned long uiLockFlags; \
77 spin_lock_irqsave(&gsCacheFlushLock, uiLockFlags); \
79 spin_unlock_irqrestore(&gsCacheFlushLock, uiLockFlags); \
82 #else /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3,16,0)) */
84 /* No need to disable IRQs for older kernels */
85 #define OUTER_CLEAN_RANGE() outer_clean_range(0, ULONG_MAX)
86 #define OUTER_FLUSH_ALL() outer_flush_all()
87 #endif /*(LINUX_VERSION_CODE >= KERNEL_VERSION(3,16,0)) */
89 #else /* CONFIG_OUTER_CACHE */
91 /* Don't do anything if we have no outer cache */
92 #define OUTER_CLEAN_RANGE()
93 #define OUTER_FLUSH_ALL()
94 #endif /* CONFIG_OUTER_CACHE */
96 static void per_cpu_cache_flush(void *arg)
98 PVR_UNREFERENCED_PARAMETER(arg);
102 PVRSRV_ERROR OSCPUOperation(PVRSRV_CACHE_OP uiCacheOp)
104 PVRSRV_ERROR eError = PVRSRV_OK;
109 case PVRSRV_CACHE_OP_CLEAN:
110 on_each_cpu(per_cpu_cache_flush, NULL, 1);
114 case PVRSRV_CACHE_OP_INVALIDATE:
115 case PVRSRV_CACHE_OP_FLUSH:
116 on_each_cpu(per_cpu_cache_flush, NULL, 1);
120 case PVRSRV_CACHE_OP_NONE:
124 PVR_DPF((PVR_DBG_ERROR,
125 "%s: Global cache operation type %d is invalid",
126 __FUNCTION__, uiCacheOp));
127 eError = PVRSRV_ERROR_INVALID_PARAMS;
135 static inline size_t pvr_dmac_range_len(const void *pvStart, const void *pvEnd)
137 return (size_t)((char *)pvEnd - (char *)pvStart);
140 void OSFlushCPUCacheRangeKM(PVRSRV_DEVICE_NODE *psDevNode,
143 IMG_CPU_PHYADDR sCPUPhysStart,
144 IMG_CPU_PHYADDR sCPUPhysEnd)
146 PVR_UNREFERENCED_PARAMETER(psDevNode);
148 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,7,0))
149 arm_dma_ops.sync_single_for_device(NULL, sCPUPhysStart.uiAddr, sCPUPhysEnd.uiAddr - sCPUPhysStart.uiAddr, DMA_TO_DEVICE);
150 arm_dma_ops.sync_single_for_cpu(NULL, sCPUPhysStart.uiAddr, sCPUPhysEnd.uiAddr - sCPUPhysStart.uiAddr, DMA_FROM_DEVICE);
151 #else /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3,7,0)) */
153 dmac_flush_range(pvVirtStart, pvVirtEnd);
156 outer_flush_range(sCPUPhysStart.uiAddr, sCPUPhysEnd.uiAddr);
157 #endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3,7,0)) */
160 void OSCleanCPUCacheRangeKM(PVRSRV_DEVICE_NODE *psDevNode,
163 IMG_CPU_PHYADDR sCPUPhysStart,
164 IMG_CPU_PHYADDR sCPUPhysEnd)
166 PVR_UNREFERENCED_PARAMETER(psDevNode);
168 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,7,0))
169 arm_dma_ops.sync_single_for_device(NULL, sCPUPhysStart.uiAddr, sCPUPhysEnd.uiAddr - sCPUPhysStart.uiAddr, DMA_TO_DEVICE);
170 #else /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3,7,0)) */
172 dmac_map_area(pvVirtStart, pvr_dmac_range_len(pvVirtStart, pvVirtEnd), DMA_TO_DEVICE);
175 outer_clean_range(sCPUPhysStart.uiAddr, sCPUPhysEnd.uiAddr);
176 #endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3,7,0)) */
179 void OSInvalidateCPUCacheRangeKM(PVRSRV_DEVICE_NODE *psDevNode,
182 IMG_CPU_PHYADDR sCPUPhysStart,
183 IMG_CPU_PHYADDR sCPUPhysEnd)
185 PVR_UNREFERENCED_PARAMETER(psDevNode);
187 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,7,0))
188 arm_dma_ops.sync_single_for_cpu(NULL, sCPUPhysStart.uiAddr, sCPUPhysEnd.uiAddr - sCPUPhysStart.uiAddr, DMA_FROM_DEVICE);
189 #else /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3,7,0)) */
190 #if defined(PVR_LINUX_DONT_USE_RANGE_BASED_INVALIDATE)
191 OSCleanCPUCacheRangeKM(psDevNode, pvVirtStart, pvVirtEnd, sCPUPhysStart, sCPUPhysEnd);
194 dmac_map_area(pvVirtStart, pvr_dmac_range_len(pvVirtStart, pvVirtEnd), DMA_FROM_DEVICE);
197 outer_inv_range(sCPUPhysStart.uiAddr, sCPUPhysEnd.uiAddr);
199 #endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3,7,0)) */
202 PVRSRV_CACHE_OP_ADDR_TYPE OSCPUCacheOpAddressType(PVRSRV_CACHE_OP uiCacheOp)
204 PVR_UNREFERENCED_PARAMETER(uiCacheOp);
205 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,7,0))
206 return PVRSRV_CACHE_OP_ADDR_TYPE_PHYSICAL;
208 return PVRSRV_CACHE_OP_ADDR_TYPE_BOTH;
212 /* User Enable Register */
213 #define PMUSERENR_EN 0x00000001 /* enable user access to the counters */
215 static void per_cpu_perf_counter_user_access_en(void *data)
217 PVR_UNREFERENCED_PARAMETER(data);
218 #if !defined(CONFIG_L4)
219 /* Enable user-mode access to counters. */
220 asm volatile("mcr p15, 0, %0, c9, c14, 0" :: "r"(PMUSERENR_EN));
224 void OSUserModeAccessToPerfCountersEn(void)
226 on_each_cpu(per_cpu_perf_counter_user_access_en, NULL, 1);