drivers/staging/imgtec/rogue/rgx_fwif_hwperf.h

   1 /*************************************************************************/ /*!
   2 @File           rgx_fwif_hwperf.h
   3 @Title          RGX HWPerf support
   4 @Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
   5 @Description    Shared header between RGX firmware and Init process
   6 @License        Dual MIT/GPLv2
   7
   8 The contents of this file are subject to the MIT license as set out below.
   9
  10 Permission is hereby granted, free of charge, to any person obtaining a copy
  11 of this software and associated documentation files (the "Software"), to deal
  12 in the Software without restriction, including without limitation the rights
  13 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  14 copies of the Software, and to permit persons to whom the Software is
  15 furnished to do so, subject to the following conditions:
  16
  17 The above copyright notice and this permission notice shall be included in
  18 all copies or substantial portions of the Software.
  19
  20 Alternatively, the contents of this file may be used under the terms of
  21 the GNU General Public License Version 2 ("GPL") in which case the provisions
  22 of GPL are applicable instead of those above.
  23
  24 If you wish to allow use of your version of this file only under the terms of
  25 GPL, and not to allow others to use your version of this file under the terms
  26 of the MIT license, indicate your decision by deleting the provisions above
  27 and replace them with the notice and other provisions required by GPL as set
  28 out in the file called "GPL-COPYING" included in this distribution. If you do
  29 not delete the provisions above, a recipient may use your version of this file
  30 under the terms of either the MIT license or GPL.
  31
  32 This License is also included in this distribution in the file called
  33 "MIT-COPYING".
  34
  35 EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
  36 PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
  37 BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
  38 PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
  39 COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  40 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  41 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  42 */ /**************************************************************************/
  43 #ifndef RGX_FWIF_HWPERF_H
  44 #define RGX_FWIF_HWPERF_H
  45
  46 #include "rgx_fwif_shared.h"
  47 #include "rgx_hwperf_km.h"
  48 #include "rgxdefs_km.h"
  49
  50
  51 /*****************************************************************************/
  52
  53 /* Structure to hold a block's parameters for passing between the BG context
  54  * and the IRQ context when applying a configuration request. */
  55 typedef struct _RGXFWIF_HWPERF_CTL_BLK_
  56 {
  57         IMG_BOOL                bValid;
  58         IMG_BOOL                bEnabled;
  59         IMG_UINT32              eBlockID;
  60         IMG_UINT32              uiCounterMask;
  61         IMG_UINT64  RGXFW_ALIGN aui64CounterCfg[RGX_CNTBLK_COUNTERS_MAX];
  62 }  RGXFWIF_HWPERF_CTL_BLK;
  63
  64 /* Structure used to hold the configuration of the non-mux counters blocks */
  65 typedef struct _RGXFW_HWPERF_SELECT_
  66 {
  67         IMG_UINT32            ui32NumSelectedCounters;
  68         IMG_UINT32            aui32SelectedCountersIDs[RGX_HWPERF_MAX_CUSTOM_CNTRS];
  69 } RGXFW_HWPERF_SELECT;
  70
  71 /* Structure to hold the whole configuration request details for all blocks
  72  * The block masks and counts are used to optimise reading of this data. */
  73 typedef struct _RGXFWIF_HWPERF_CTL_
  74 {
  75         IMG_BOOL                           bResetOrdinal;
  76
  77         IMG_UINT32                         ui32SelectedCountersBlockMask;
  78         RGXFW_HWPERF_SELECT RGXFW_ALIGN    SelCntr[RGX_HWPERF_MAX_CUSTOM_BLKS];
  79
  80         IMG_UINT32                         ui32EnabledBlksCount;
  81         RGXFWIF_HWPERF_CTL_BLK RGXFW_ALIGN sBlkCfg[RGX_HWPERF_MAX_DEFINED_BLKS];
  82 } UNCACHED_ALIGN RGXFWIF_HWPERF_CTL;
  83
  84 /* NOTE: The switch statement in this function must be kept in alignment with
  85  * the enumeration RGX_HWPERF_CNTBLK_ID defined in rgx_hwperf_km.h. ASSERTs may
  86  * result if not.
  87  * The function provides a hash lookup to get a handle on the global store for
  88  * a block's configuration store from it's block ID.
  89  */
  90 #ifdef INLINE_IS_PRAGMA
  91 #pragma inline(rgxfw_hwperf_get_block_ctl)
  92 #endif
  93 static INLINE RGXFWIF_HWPERF_CTL_BLK* rgxfw_hwperf_get_block_ctl(
  94                 RGX_HWPERF_CNTBLK_ID eBlockID, RGXFWIF_HWPERF_CTL *psHWPerfInitData)
  95 {
  96         IMG_INT32 i32Idx = -1;
  97
  98         /* Hash the block ID into a control configuration array index */
  99         switch(eBlockID)
 100         {
 101                 case RGX_CNTBLK_ID_TA:
 102                 case RGX_CNTBLK_ID_RASTER:
 103                 case RGX_CNTBLK_ID_HUB:
 104                 case RGX_CNTBLK_ID_TORNADO:
 105                 case RGX_CNTBLK_ID_JONES:
 106                 case RGX_CNTBLK_ID_BF:
 107                 case RGX_CNTBLK_ID_BT:
 108                 case RGX_CNTBLK_ID_RT:
 109                 case RGX_CNTBLK_ID_SH:
 110                 {
 111                         i32Idx = eBlockID;
 112                         break;
 113                 }
 114                 case RGX_CNTBLK_ID_TPU_MCU0:
 115                 case RGX_CNTBLK_ID_TPU_MCU1:
 116                 case RGX_CNTBLK_ID_TPU_MCU2:
 117                 case RGX_CNTBLK_ID_TPU_MCU3:
 118                 case RGX_CNTBLK_ID_TPU_MCU4:
 119                 case RGX_CNTBLK_ID_TPU_MCU5:
 120                 case RGX_CNTBLK_ID_TPU_MCU6:
 121                 case RGX_CNTBLK_ID_TPU_MCU7:
 122                 {
 123                         i32Idx = RGX_CNTBLK_ID_DIRECT_LAST +
 124                                                 (eBlockID & RGX_CNTBLK_ID_UNIT_MASK);
 125                         break;
 126                 }
 127                 case RGX_CNTBLK_ID_USC0:
 128                 case RGX_CNTBLK_ID_USC1:
 129                 case RGX_CNTBLK_ID_USC2:
 130                 case RGX_CNTBLK_ID_USC3:
 131                 case RGX_CNTBLK_ID_USC4:
 132                 case RGX_CNTBLK_ID_USC5:
 133                 case RGX_CNTBLK_ID_USC6:
 134                 case RGX_CNTBLK_ID_USC7:
 135                 case RGX_CNTBLK_ID_USC8:
 136                 case RGX_CNTBLK_ID_USC9:
 137                 case RGX_CNTBLK_ID_USC10:
 138                 case RGX_CNTBLK_ID_USC11:
 139                 case RGX_CNTBLK_ID_USC12:
 140                 case RGX_CNTBLK_ID_USC13:
 141                 case RGX_CNTBLK_ID_USC14:
 142                 case RGX_CNTBLK_ID_USC15:
 143                 {
 144                         i32Idx = RGX_CNTBLK_ID_DIRECT_LAST +
 145                                                 RGX_CNTBLK_INDIRECT_COUNT(TPU_MCU, 7) +
 146                                                 (eBlockID & RGX_CNTBLK_ID_UNIT_MASK);
 147                         break;
 148                 }
 149                 case RGX_CNTBLK_ID_TEXAS0:
 150                 case RGX_CNTBLK_ID_TEXAS1:
 151                 case RGX_CNTBLK_ID_TEXAS2:
 152                 case RGX_CNTBLK_ID_TEXAS3:
 153                 case RGX_CNTBLK_ID_TEXAS4:
 154                 case RGX_CNTBLK_ID_TEXAS5:
 155                 case RGX_CNTBLK_ID_TEXAS6:
 156                 case RGX_CNTBLK_ID_TEXAS7:
 157                 {
 158                         i32Idx = RGX_CNTBLK_ID_DIRECT_LAST +
 159                                                 RGX_CNTBLK_INDIRECT_COUNT(TPU_MCU, 7) +
 160                                                 RGX_CNTBLK_INDIRECT_COUNT(USC, 15) +
 161                                                 (eBlockID & RGX_CNTBLK_ID_UNIT_MASK);
 162                         break;
 163                 }
 164                 case RGX_CNTBLK_ID_RASTER0:
 165                 case RGX_CNTBLK_ID_RASTER1:
 166                 case RGX_CNTBLK_ID_RASTER2:
 167                 case RGX_CNTBLK_ID_RASTER3:
 168                 {
 169                         i32Idx = RGX_CNTBLK_ID_DIRECT_LAST +
 170                                                 RGX_CNTBLK_INDIRECT_COUNT(TPU_MCU, 7) +
 171                                                 RGX_CNTBLK_INDIRECT_COUNT(USC, 15) +
 172                                                 RGX_CNTBLK_INDIRECT_COUNT(TEXAS, 7) +
 173                                                 (eBlockID & RGX_CNTBLK_ID_UNIT_MASK);
 174                         break;
 175                 }
 176                 case RGX_CNTBLK_ID_BLACKPEARL0:
 177                 case RGX_CNTBLK_ID_BLACKPEARL1:
 178                 case RGX_CNTBLK_ID_BLACKPEARL2:
 179                 case RGX_CNTBLK_ID_BLACKPEARL3:
 180                 {
 181                         i32Idx = RGX_CNTBLK_ID_DIRECT_LAST +
 182                                                 RGX_CNTBLK_INDIRECT_COUNT(TPU_MCU, 7) +
 183                                                 RGX_CNTBLK_INDIRECT_COUNT(USC, 15) +
 184                                                 RGX_CNTBLK_INDIRECT_COUNT(TEXAS, 7) +
 185                                                 RGX_CNTBLK_INDIRECT_COUNT(RASTER, 3) +
 186                                                 (eBlockID & RGX_CNTBLK_ID_UNIT_MASK);
 187                         break;
 188                 }
 189                 case RGX_CNTBLK_ID_PBE0:
 190                 case RGX_CNTBLK_ID_PBE1:
 191                 case RGX_CNTBLK_ID_PBE2:
 192                 case RGX_CNTBLK_ID_PBE3:
 193                 case RGX_CNTBLK_ID_PBE4:
 194                 case RGX_CNTBLK_ID_PBE5:
 195                 case RGX_CNTBLK_ID_PBE6:
 196                 case RGX_CNTBLK_ID_PBE7:
 197                 case RGX_CNTBLK_ID_PBE8:
 198                 case RGX_CNTBLK_ID_PBE9:
 199                 case RGX_CNTBLK_ID_PBE10:
 200                 case RGX_CNTBLK_ID_PBE11:
 201                 case RGX_CNTBLK_ID_PBE12:
 202                 case RGX_CNTBLK_ID_PBE13:
 203                 case RGX_CNTBLK_ID_PBE14:
 204                 case RGX_CNTBLK_ID_PBE15:
 205                 {
 206                         i32Idx = RGX_CNTBLK_ID_DIRECT_LAST +
 207                                                 RGX_CNTBLK_INDIRECT_COUNT(TPU_MCU, 7) +
 208                                                 RGX_CNTBLK_INDIRECT_COUNT(USC, 15) +
 209                                                 RGX_CNTBLK_INDIRECT_COUNT(TEXAS, 7) +
 210                                                 RGX_CNTBLK_INDIRECT_COUNT(RASTER, 3) +
 211                                                 RGX_CNTBLK_INDIRECT_COUNT(BLACKPEARL, 3) +
 212                                                 (eBlockID & RGX_CNTBLK_ID_UNIT_MASK);
 213                         break;
 214                 }
 215                 case RGX_CNTBLK_ID_BX_TU0:
 216                 case RGX_CNTBLK_ID_BX_TU1:
 217                 case RGX_CNTBLK_ID_BX_TU2:
 218                 case RGX_CNTBLK_ID_BX_TU3:
 219                 {
 220                         i32Idx = RGX_CNTBLK_ID_DIRECT_LAST +
 221                                                 RGX_CNTBLK_INDIRECT_COUNT(TPU_MCU, 7) +
 222                                                 RGX_CNTBLK_INDIRECT_COUNT(USC, 15) +
 223                                                 RGX_CNTBLK_INDIRECT_COUNT(TEXAS, 7) +
 224                                                 RGX_CNTBLK_INDIRECT_COUNT(RASTER, 3) +
 225                                                 RGX_CNTBLK_INDIRECT_COUNT(BLACKPEARL, 3) +
 226                                                 RGX_CNTBLK_INDIRECT_COUNT(PBE, 15) +
 227                                                 (eBlockID & RGX_CNTBLK_ID_UNIT_MASK);
 228                         break;
 229                 }
 230                 default:
 231                 {
 232                         return NULL;
 233                 }
 234         }
 235         if ((i32Idx < 0) || (i32Idx >= RGX_HWPERF_MAX_DEFINED_BLKS))
 236         {
 237                 return NULL;
 238         }
 239         return &psHWPerfInitData->sBlkCfg[i32Idx];
 240 }
 241
 242 #endif