drivers/staging/imgtec/rogue/rgxdevice.h

   1 /*************************************************************************/ /*!
   2 @File
   3 @Title          RGX device node header file
   4 @Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
   5 @Description    Header for the RGX device node
   6 @License        Dual MIT/GPLv2
   7
   8 The contents of this file are subject to the MIT license as set out below.
   9
  10 Permission is hereby granted, free of charge, to any person obtaining a copy
  11 of this software and associated documentation files (the "Software"), to deal
  12 in the Software without restriction, including without limitation the rights
  13 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  14 copies of the Software, and to permit persons to whom the Software is
  15 furnished to do so, subject to the following conditions:
  16
  17 The above copyright notice and this permission notice shall be included in
  18 all copies or substantial portions of the Software.
  19
  20 Alternatively, the contents of this file may be used under the terms of
  21 the GNU General Public License Version 2 ("GPL") in which case the provisions
  22 of GPL are applicable instead of those above.
  23
  24 If you wish to allow use of your version of this file only under the terms of
  25 GPL, and not to allow others to use your version of this file under the terms
  26 of the MIT license, indicate your decision by deleting the provisions above
  27 and replace them with the notice and other provisions required by GPL as set
  28 out in the file called "GPL-COPYING" included in this distribution. If you do
  29 not delete the provisions above, a recipient may use your version of this file
  30 under the terms of either the MIT license or GPL.
  31
  32 This License is also included in this distribution in the file called
  33 "MIT-COPYING".
  34
  35 EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
  36 PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
  37 BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
  38 PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
  39 COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  40 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  41 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  42 */ /**************************************************************************/
  43
  44 #if !defined(__RGXDEVICE_H__)
  45 #define __RGXDEVICE_H__
  46
  47 #include "img_types.h"
  48 #include "pvrsrv_device_types.h"
  49 #include "mmu_common.h"
  50 #include "rgx_fwif_km.h"
  51 #include "rgx_fwif.h"
  52 #include "rgxscript.h"
  53 #include "cache_ops.h"
  54 #include "device.h"
  55 #include "osfunc.h"
  56 #include "rgxlayer_km_impl.h"
  57 #if defined(SUPPORT_WORKLOAD_ESTIMATION)
  58 #include "hash.h"
  59 #endif
  60 typedef struct _RGX_SERVER_COMMON_CONTEXT_ RGX_SERVER_COMMON_CONTEXT;
  61
  62 typedef struct {
  63         DEVMEM_MEMDESC          *psFWFrameworkMemDesc;
  64         IMG_DEV_VIRTADDR        *psMCUFenceAddr;
  65         IMG_DEV_VIRTADDR        *psResumeSignalAddr;
  66 } RGX_COMMON_CONTEXT_INFO;
  67
  68
  69 /*!
  70  ******************************************************************************
  71  * Device state flags
  72  *****************************************************************************/
  73 #define RGXKM_DEVICE_STATE_ZERO_FREELIST                        (0x1 << 0)              /*!< Zeroing the physical pages of reconstructed free lists */
  74 #define RGXKM_DEVICE_STATE_FTRACE_EN                            (0x1 << 1)              /*!< Used to enable device FTrace thread to consume HWPerf data */
  75 #define RGXKM_DEVICE_STATE_DISABLE_DW_LOGGING_EN        (0x1 << 2)              /*!< Used to disable the Devices Watchdog logging */
  76 #define RGXKM_DEVICE_STATE_DUST_REQUEST_INJECT_EN       (0x1 << 3)              /*!< Used for validation to inject dust requests every TA/3D kick */
  77
  78 /*!
  79  ******************************************************************************
  80  * GPU DVFS Table
  81  *****************************************************************************/
  82
  83 #define RGX_GPU_DVFS_TABLE_SIZE            100                      /* DVFS Table size */
  84 #define RGX_GPU_DVFS_GET_INDEX(clockfreq)  ((clockfreq) / 10000000) /* Assuming different GPU clocks are separated by at least 10MHz
  85                                                                      * WARNING: this macro must be used only with nominal values of
  86                                                                      * the GPU clock speed (the ones provided by the customer code) */
  87 #define RGX_GPU_DVFS_FIRST_CALIBRATION_TIME_US       25000          /* Time required to calibrate a clock frequency the first time */
  88 #define RGX_GPU_DVFS_TRANSITION_CALIBRATION_TIME_US  150000         /* Time required for a recalibration after a DVFS transition */
  89 #define RGX_GPU_DVFS_PERIODIC_CALIBRATION_TIME_US    10000000       /* Time before the next periodic calibration and correlation */
  90
  91 typedef struct _RGX_GPU_DVFS_TABLE_
  92 {
  93         IMG_UINT64 ui64CalibrationCRTimestamp;              /*!< CR timestamp used to calibrate GPU frequencies (beginning of a calibration period) */
  94         IMG_UINT64 ui64CalibrationOSTimestamp;              /*!< OS timestamp used to calibrate GPU frequencies (beginning of a calibration period) */
  95         IMG_UINT64 ui64CalibrationCRTimediff;               /*!< CR timediff used to calibrate GPU frequencies (calibration period) */
  96         IMG_UINT64 ui64CalibrationOSTimediff;               /*!< OS timediff used to calibrate GPU frequencies (calibration period) */
  97         IMG_UINT32 ui32CalibrationPeriod;                   /*!< Threshold used to determine whether the current GPU frequency should be calibrated */
  98         IMG_UINT32 ui32CurrentDVFSId;                       /*!< Current table entry index */
  99         IMG_BOOL   bAccumulatePeriod;                       /*!< Accumulate many consecutive periods to get a better calibration at the end */
 100         IMG_UINT32 aui32DVFSClock[RGX_GPU_DVFS_TABLE_SIZE]; /*!< DVFS clocks table (clocks in Hz) */
 101 } RGX_GPU_DVFS_TABLE;
 102
 103
 104 /*!
 105  ******************************************************************************
 106  * GPU utilisation statistics
 107  *****************************************************************************/
 108
 109 typedef struct _RGXFWIF_GPU_UTIL_STATS_
 110 {
 111         IMG_BOOL   bValid;                /* If TRUE, statistics are valid.
 112                                              FALSE if the driver couldn't get reliable stats. */
 113         IMG_UINT64 ui64GpuStatActiveHigh; /* GPU active high statistic */
 114         IMG_UINT64 ui64GpuStatActiveLow;  /* GPU active low (i.e. TLA active only) statistic */
 115         IMG_UINT64 ui64GpuStatBlocked;    /* GPU blocked statistic */
 116         IMG_UINT64 ui64GpuStatIdle;       /* GPU idle statistic */
 117         IMG_UINT64 ui64GpuStatCumulative; /* Sum of active/blocked/idle stats */
 118 } RGXFWIF_GPU_UTIL_STATS;
 119
 120
 121 typedef struct _RGX_REG_CONFIG_
 122 {
 123         IMG_BOOL               bEnabled;
 124         RGXFWIF_REG_CFG_TYPE   eRegCfgTypeToPush;
 125         IMG_UINT32             ui32NumRegRecords;
 126 } RGX_REG_CONFIG;
 127
 128 typedef struct _PVRSRV_STUB_PBDESC_ PVRSRV_STUB_PBDESC;
 129
 130 typedef struct
 131 {
 132         IMG_UINT32                      ui32DustCount1;
 133         IMG_UINT32                      ui32DustCount2;
 134         IMG_BOOL                        bToggle;
 135 } RGX_DUST_STATE;
 136
 137 typedef struct _PVRSRV_DEVICE_FEATURE_CONFIG_
 138 {
 139         IMG_UINT64 ui64ErnsBrns;
 140         IMG_UINT64 ui64Features;
 141         IMG_UINT32 ui32B;
 142         IMG_UINT32 ui32V;
 143         IMG_UINT32 ui32N;
 144         IMG_UINT32 ui32C;
 145         IMG_UINT32 ui32NumClusters;
 146         IMG_UINT32 ui32CtrlStreamFormat;
 147         IMG_UINT32 ui32FBCDCArch;
 148         IMG_UINT32 ui32META;
 149         IMG_UINT32 ui32MCMB;
 150         IMG_UINT32 ui32MCMS;
 151         IMG_UINT32 ui32MDMACount;
 152         IMG_UINT32 ui32NIIP;
 153         IMG_UINT32 ui32PBW;
 154         IMG_UINT32 ui32STEArch;
 155         IMG_UINT32 ui32SVCE;
 156         IMG_UINT32 ui32SLCBanks;
 157         IMG_UINT32 ui32CacheLineSize;
 158         IMG_UINT32 ui32SLCSize;
 159         IMG_UINT32 ui32VASB;
 160         IMG_UINT32 ui32MAXDMCount;
 161         IMG_UINT32 ui32MAXDMMTSCount;
 162         IMG_UINT32 ui32MAXDustCount;
 163 #define         MAX_BVNC_STRING_LEN             (50)
 164         IMG_PCHAR  pszBVNCString;
 165 }PVRSRV_DEVICE_FEATURE_CONFIG;
 166
 167 /* there is a corresponding define in rgxapi.h */
 168 #define RGX_MAX_TIMER_QUERIES 16
 169
 170 #if defined(SUPPORT_WORKLOAD_ESTIMATION)
 171 /* For the workload estimation return data array */
 172 /* The max amount of commands the MTS can have is 255, therefore 512 (LOG2 = 9)
 173  * is large enough to account for all corner cases.
 174  */
 175 #define RETURN_DATA_ARRAY_SIZE_LOG2 (9)
 176 #define RETURN_DATA_ARRAY_SIZE      ((1UL) << RETURN_DATA_ARRAY_SIZE_LOG2)
 177 #define RETURN_DATA_ARRAY_WRAP_MASK (RETURN_DATA_ARRAY_SIZE - 1)
 178
 179 #define WORKLOAD_HASH_SIZE 64
 180
 181 typedef struct _WORKEST_HOST_DATA_ WORKEST_HOST_DATA;
 182
 183 typedef struct _RGX_WORKLOAD_TA3D_
 184 {
 185         IMG_UINT32                              ui32RenderTargetSize;
 186         IMG_UINT32                              ui32NumberOfDrawCalls;
 187         IMG_UINT32                              ui32NumberOfIndices;
 188         IMG_UINT32                              ui32NumberOfMRTs;
 189 } RGX_WORKLOAD_TA3D;
 190
 191 typedef struct _WORKLOAD_MATCHING_DATA_
 192 {
 193         HASH_TABLE                  *psWorkloadDataHash;
 194         RGX_WORKLOAD_TA3D           asWorkloadHashKeys[WORKLOAD_HASH_SIZE];
 195         IMG_UINT64                  aui64HashCycleData[WORKLOAD_HASH_SIZE];
 196         IMG_UINT32                  ui32HashArrayWO;
 197         POS_LOCK                    psWorkEstHashLock;
 198 } WORKLOAD_MATCHING_DATA;
 199
 200 struct _WORKEST_HOST_DATA_{
 201         WORKLOAD_MATCHING_DATA      sWorkloadMatchingDataTA;
 202         WORKLOAD_MATCHING_DATA      sWorkloadMatchingData3D;
 203         IMG_UINT32                  ui32WorkEstCCBReceived;
 204 };
 205 typedef struct _WORKEST_RETURN_DATA_ {
 206         WORKEST_HOST_DATA           *psWorkEstHostData;
 207         WORKLOAD_MATCHING_DATA      *psWorkloadMatchingData;
 208         RGX_WORKLOAD_TA3D           sWorkloadCharacteristics;
 209 } WORKEST_RETURN_DATA;
 210 #endif
 211
 212
 213 typedef struct
 214 {
 215 #if defined(PDUMP)
 216         IMG_HANDLE      hPdumpPages;
 217 #endif
 218         PG_HANDLE       sPages;
 219         IMG_DEV_PHYADDR sPhysAddr;
 220 } RGX_MIPS_ADDRESS_TRAMPOLINE;
 221
 222
 223 /*!
 224  ******************************************************************************
 225  * RGX Device info
 226  *****************************************************************************/
 227
 228 typedef struct _PVRSRV_RGXDEV_INFO_
 229 {
 230         PVRSRV_DEVICE_NODE              *psDeviceNode;
 231
 232         PVRSRV_DEVICE_FEATURE_CONFIG    sDevFeatureCfg;
 233
 234         /* FIXME: This is a workaround due to having 2 inits but only 1 deinit */
 235         IMG_BOOL                                bDevInit2Done;
 236
 237         IMG_BOOL                bFirmwareInitialised;
 238         IMG_BOOL                                bPDPEnabled;
 239
 240         IMG_HANDLE                              hDbgReqNotify;
 241
 242         /* Kernel mode linear address of device registers */
 243         void                                    *pvRegsBaseKM;
 244
 245         /* FIXME: The alloc for this should go through OSAllocMem in future */
 246         IMG_HANDLE                              hRegMapping;
 247
 248         /* System physical address of device registers*/
 249         IMG_CPU_PHYADDR                 sRegsPhysBase;
 250         /*  Register region size in bytes */
 251         IMG_UINT32                              ui32RegSize;
 252
 253         PVRSRV_STUB_PBDESC              *psStubPBDescListKM;
 254
 255         /* Firmware memory context info */
 256         DEVMEM_CONTEXT                  *psKernelDevmemCtx;
 257         DEVMEM_HEAP                             *psFirmwareHeap;
 258         MMU_CONTEXT                             *psKernelMMUCtx;
 259
 260         void                                    *pvDeviceMemoryHeap;
 261
 262         /* Kernel CCB */
 263         DEVMEM_MEMDESC                  *psKernelCCBCtlMemDesc;    /*!< memdesc for Kernel CCB control */
 264         RGXFWIF_CCB_CTL                 *psKernelCCBCtl;           /*!< kernel mapping for Kernel CCB control */
 265         DEVMEM_MEMDESC                  *psKernelCCBMemDesc;       /*!< memdesc for Kernel CCB */
 266         IMG_UINT8                               *psKernelCCB;              /*!< kernel mapping for Kernel CCB */
 267
 268         /* Firmware CCB */
 269         DEVMEM_MEMDESC                  *psFirmwareCCBCtlMemDesc;   /*!< memdesc for Firmware CCB control */
 270         RGXFWIF_CCB_CTL                 *psFirmwareCCBCtl;          /*!< kernel mapping for Firmware CCB control */
 271         DEVMEM_MEMDESC                  *psFirmwareCCBMemDesc;      /*!< memdesc for Firmware CCB */
 272         IMG_UINT8                               *psFirmwareCCB;             /*!< kernel mapping for Firmware CCB */
 273
 274         /* Workload Estimation Firmware CCB */
 275         DEVMEM_MEMDESC                  *psWorkEstFirmwareCCBCtlMemDesc;   /*!< memdesc for Workload Estimation Firmware CCB control */
 276         RGXFWIF_CCB_CTL                 *psWorkEstFirmwareCCBCtl;          /*!< kernel mapping for Workload Estimation Firmware CCB control */
 277         DEVMEM_MEMDESC                  *psWorkEstFirmwareCCBMemDesc;      /*!< memdesc for Workload Estimation Firmware CCB */
 278         IMG_UINT8                               *psWorkEstFirmwareCCB;             /*!< kernel mapping for Workload Estimation Firmware CCB */
 279
 280         IMG_BOOL                                bEnableFWPoisonOnFree;             /*!< Enable poisoning of FW allocations when freed */
 281         IMG_BYTE                                ubFWPoisonOnFreeValue;             /*!< Byte value used when poisoning FW allocations */
 282
 283         /*
 284                 if we don't preallocate the pagetables we must
 285                 insert newly allocated page tables dynamically
 286         */
 287         void                                    *pvMMUContextList;
 288
 289         IMG_UINT32                              ui32ClkGateStatusReg;
 290         IMG_UINT32                              ui32ClkGateStatusMask;
 291         RGX_SCRIPTS                             *psScripts;
 292
 293         DEVMEM_MEMDESC                  *psRGXFWCodeMemDesc;
 294         IMG_DEV_VIRTADDR                sFWCodeDevVAddrBase;
 295         DEVMEM_MEMDESC                  *psRGXFWDataMemDesc;
 296         IMG_DEV_VIRTADDR                sFWDataDevVAddrBase;
 297         RGX_MIPS_ADDRESS_TRAMPOLINE     sTrampoline;
 298
 299         DEVMEM_MEMDESC                  *psRGXFWCorememMemDesc;
 300         IMG_DEV_VIRTADDR                sFWCorememCodeDevVAddrBase;
 301         RGXFWIF_DEV_VIRTADDR    sFWCorememCodeFWAddr;
 302
 303 #if defined(RGXFW_ALIGNCHECKS)
 304         DEVMEM_MEMDESC                  *psRGXFWAlignChecksMemDesc;
 305 #endif
 306
 307         DEVMEM_MEMDESC                  *psRGXFWSigTAChecksMemDesc;
 308         IMG_UINT32                              ui32SigTAChecksSize;
 309
 310         DEVMEM_MEMDESC                  *psRGXFWSig3DChecksMemDesc;
 311         IMG_UINT32                              ui32Sig3DChecksSize;
 312
 313         DEVMEM_MEMDESC                  *psRGXFWSigRTChecksMemDesc;
 314         IMG_UINT32                              ui32SigRTChecksSize;
 315
 316         DEVMEM_MEMDESC                  *psRGXFWSigSHChecksMemDesc;
 317         IMG_UINT32                              ui32SigSHChecksSize;
 318
 319 #if defined (PDUMP)
 320         IMG_BOOL                                bDumpedKCCBCtlAlready;
 321 #endif
 322
 323 #if defined(PVRSRV_GPUVIRT_GUESTDRV)
 324         /*
 325                 Guest drivers do not support these functionalities:
 326                         - H/W perf & device power management
 327                         - F/W initialization & management
 328                         - GPU dvfs, trace & utilization
 329          */
 330         DEVMEM_MEMDESC                  *psRGXFWIfInitMemDesc;
 331         RGXFWIF_DEV_VIRTADDR    sFWInitFWAddr;
 332 #else
 333         DEVMEM_MEMDESC                  *psRGXFWIfTraceBufCtlMemDesc;   /*!< memdesc of trace buffer control structure */
 334         DEVMEM_MEMDESC                  *psRGXFWIfTraceBufferMemDesc[RGXFW_THREAD_NUM]; /*!< memdesc of actual FW trace (log) buffer(s) */
 335         RGXFWIF_TRACEBUF                *psRGXFWIfTraceBuf;             /* structure containing trace control data and actual trace buffer */
 336
 337         DEVMEM_MEMDESC                  *psRGXFWIfHWRInfoBufCtlMemDesc;
 338         RGXFWIF_HWRINFOBUF              *psRGXFWIfHWRInfoBuf;
 339
 340         DEVMEM_MEMDESC                  *psRGXFWIfGpuUtilFWCbCtlMemDesc;
 341         RGXFWIF_GPU_UTIL_FWCB   *psRGXFWIfGpuUtilFWCb;
 342
 343         DEVMEM_MEMDESC                  *psRGXFWIfHWPerfBufMemDesc;
 344         IMG_BYTE                                *psRGXFWIfHWPerfBuf;
 345         IMG_UINT32                              ui32RGXFWIfHWPerfBufSize; /* in bytes */
 346
 347         DEVMEM_MEMDESC                  *psRGXFWIfCorememDataStoreMemDesc;
 348
 349         DEVMEM_MEMDESC                  *psRGXFWIfRegCfgMemDesc;
 350
 351         DEVMEM_MEMDESC                  *psRGXFWIfHWPerfCountersMemDesc;
 352         DEVMEM_MEMDESC                  *psRGXFWIfInitMemDesc;
 353         RGXFWIF_DEV_VIRTADDR    sFWInitFWAddr;
 354
 355         DEVMEM_MEMDESC                  *psRGXFWIfRuntimeCfgMemDesc;
 356         RGXFWIF_RUNTIME_CFG             *psRGXFWIfRuntimeCfg;
 357
 358 #if defined(SUPPORT_PVRSRV_GPUVIRT)
 359         /* Additional guest firmware memory context info */
 360         DEVMEM_HEAP                             *psGuestFirmwareHeap[RGXFW_NUM_OS-1];
 361         DEVMEM_MEMDESC                  *psGuestFirmwareMemDesc[RGXFW_NUM_OS-1];
 362 #endif
 363         DEVMEM_MEMDESC                  *psMETAT1StackMemDesc;
 364
 365 #if defined(SUPPORT_WORKLOAD_ESTIMATION)
 366         /* Array to store data needed for workload estimation when a workload
 367          * has finished and its cycle time is returned to the host.
 368          */
 369         WORKEST_RETURN_DATA             asReturnData[RETURN_DATA_ARRAY_SIZE];
 370         IMG_UINT32                              ui32ReturnDataWO;
 371 #endif
 372
 373 #if defined (SUPPORT_PDVFS)
 374         /**
 375          * Host memdesc and pointer to memory containing core clock rate in Hz.
 376          * Firmware (PDVFS) updates the memory on changing the core clock rate over
 377          * GPIO.
 378          * Note: Shared memory needs atomic access from Host driver and firmware,
 379          * hence size should not be greater than memory transaction granularity.
 380          * Currently it's is chosen to be 32 bits.
 381          */
 382         DEVMEM_MEMDESC                  *psRGXFWIFCoreClkRateMemDesc;
 383         volatile IMG_UINT32             *pui32RGXFWIFCoreClkRate;
 384         /**
 385          * Last sampled core clk rate.
 386          */
 387         volatile IMG_UINT32             ui32CoreClkRateSnapshot;
 388 #endif
 389         /*
 390            HWPerf data for the RGX device
 391          */
 392
 393         POS_LOCK    hHWPerfLock;  /*! Critical section lock that protects HWPerf code
 394                                    *  from multiple thread duplicate init/deinit
 395                                    *  and loss/freeing of FW & Host resources while in
 396                                    *  use in another thread e.g. MSIR. */
 397
 398         IMG_UINT64  ui64HWPerfFilter; /*! Event filter for FW events (settable by AppHint) */
 399         IMG_HANDLE  hHWPerfStream;    /*! TL Stream buffer (L2) for firmware event stream */
 400
 401         IMG_UINT32  ui32HWPerfHostFilter;      /*! Event filter for HWPerfHost stream (settable by AppHint) */
 402         POS_LOCK    hLockHWPerfHostStream;     /*! Lock guarding access to HWPerfHost stream from multiple threads */
 403         IMG_HANDLE  hHWPerfHostStream;         /*! TL Stream buffer for host only event stream */
 404         IMG_UINT32  ui32HWPerfHostBufSize;     /*! Host side buffer size in bytes */
 405         IMG_UINT32  ui32HWPerfHostNextOrdinal; /*! Ordinal number for HWPerfHost events */
 406
 407 #if defined(SUPPORT_GPUTRACE_EVENTS)
 408         void        *pvGpuFtraceData;
 409 #endif
 410
 411         /* Poll data for detecting firmware fatal errors */
 412         IMG_UINT32                              aui32CrLastPollAddr[RGXFW_THREAD_NUM];
 413         IMG_UINT32                              ui32KCCBCmdsExecutedLastTime;
 414         IMG_BOOL                                bKCCBCmdsWaitingLastTime;
 415         IMG_UINT32                              ui32GEOTimeoutsLastTime;
 416
 417         /* Client stall detection */
 418         IMG_UINT32                              ui32StalledClientMask;
 419 #endif
 420
 421         IMG_BOOL                                bWorkEstEnabled;
 422         IMG_BOOL                                bPDVFSEnabled;
 423
 424         void                                    *pvLISRData;
 425         void                                    *pvMISRData;
 426         void                                    *pvAPMISRData;
 427         RGX_ACTIVEPM_CONF               eActivePMConf;
 428
 429         volatile IMG_UINT32             aui32SampleIRQCount[RGXFW_THREAD_NUM];
 430
 431         DEVMEM_MEMDESC                  *psRGXFaultAddressMemDesc;
 432
 433         DEVMEM_MEMDESC                  *psRGXFWHWBRN37200MemDesc;
 434
 435         DEVMEM_MEMDESC                  *psSLC3FenceMemDesc;
 436
 437         /* If we do 10 deferred memory allocations per second, then the ID would wrap around after 13 years */
 438         IMG_UINT32                              ui32ZSBufferCurrID;     /*!< ID assigned to the next deferred devmem allocation */
 439         IMG_UINT32                              ui32FreelistCurrID;     /*!< ID assigned to the next freelist */
 440         IMG_UINT32                              ui32RPMFreelistCurrID;  /*!< ID assigned to the next RPM freelist */
 441
 442         POS_LOCK                                hLockZSBuffer;          /*!< Lock to protect simultaneous access to ZSBuffers */
 443         DLLIST_NODE                             sZSBufferHead;          /*!< List of on-demand ZSBuffers */
 444         POS_LOCK                                hLockFreeList;          /*!< Lock to protect simultaneous access to Freelists */
 445         DLLIST_NODE                             sFreeListHead;          /*!< List of growable Freelists */
 446         POS_LOCK                                hLockRPMFreeList;       /*!< Lock to protect simultaneous access to RPM Freelists */
 447         DLLIST_NODE                             sRPMFreeListHead;       /*!< List of growable RPM Freelists */
 448         POS_LOCK                                hLockRPMContext;        /*!< Lock to protect simultaneous access to RPM contexts */
 449         PSYNC_PRIM_CONTEXT              hSyncPrimContext;
 450         PVRSRV_CLIENT_SYNC_PRIM *psPowSyncPrim;
 451
 452         IMG_UINT32                              ui32ActivePMReqOk;
 453         IMG_UINT32                              ui32ActivePMReqDenied;
 454         IMG_UINT32                              ui32ActivePMReqTotal;
 455
 456         IMG_HANDLE                              hProcessQueuesMISR;
 457
 458         IMG_UINT32                              ui32DeviceFlags;                /*!< Flags to track general device state */
 459
 460         /* Timer Queries */
 461         IMG_UINT32                              ui32ActiveQueryId;              /*!< id of the active line */
 462         IMG_BOOL                                bSaveStart;                             /*!< save the start time of the next kick on the device*/
 463         IMG_BOOL                                bSaveEnd;                               /*!< save the end time of the next kick on the device*/
 464
 465         DEVMEM_MEMDESC                  *psStartTimeMemDesc;    /*!< memdesc for Start Times */
 466         IMG_UINT64                              *pui64StartTimeById;    /*!< CPU mapping of the above */
 467
 468         DEVMEM_MEMDESC                  *psEndTimeMemDesc;      /*!< memdesc for End Timer */
 469         IMG_UINT64                              *pui64EndTimeById;      /*!< CPU mapping of the above */
 470
 471         IMG_UINT32                              aui32ScheduledOnId[RGX_MAX_TIMER_QUERIES];      /*!< kicks Scheduled on QueryId */
 472         DEVMEM_MEMDESC                  *psCompletedMemDesc;    /*!< kicks Completed on QueryId */
 473         IMG_UINT32                              *pui32CompletedById;    /*!< CPU mapping of the above */
 474
 475 #if !defined(PVRSRV_GPUVIRT_GUESTDRV)
 476         /* GPU DVFS Table */
 477         RGX_GPU_DVFS_TABLE  *psGpuDVFSTable;
 478
 479         /* Pointer to function returning the GPU utilisation statistics since the last
 480          * time the function was called. Supports different users at the same time.
 481          *
 482          * psReturnStats [out]: GPU utilisation statistics (active high/active low/idle/blocked)
 483          *                      in microseconds since the last time the function was called
 484          *                      by a specific user (identified by hGpuUtilUser)
 485          *
 486          * Returns PVRSRV_OK in case the call completed without errors,
 487          * some other value otherwise.
 488          */
 489         PVRSRV_ERROR (*pfnGetGpuUtilStats) (PVRSRV_DEVICE_NODE *psDeviceNode,
 490                                             IMG_HANDLE hGpuUtilUser,
 491                                             RGXFWIF_GPU_UTIL_STATS *psReturnStats);
 492 #endif
 493
 494         POS_LOCK                                hGPUUtilLock;
 495
 496         /* Register configuration */
 497         RGX_REG_CONFIG                  sRegCongfig;
 498
 499         IMG_BOOL                                bRGXPowered;
 500         DLLIST_NODE                             sMemoryContextList;
 501
 502         POSWR_LOCK                              hRenderCtxListLock;
 503         POSWR_LOCK                              hComputeCtxListLock;
 504         POSWR_LOCK                              hTransferCtxListLock;
 505         POSWR_LOCK                              hTDMCtxListLock;
 506         POSWR_LOCK                              hRaytraceCtxListLock;
 507         POSWR_LOCK                              hMemoryCtxListLock;
 508         POSWR_LOCK                              hKickSyncCtxListLock;
 509
 510         /* Linked list of deferred KCCB commands due to a full KCCB */
 511         DLLIST_NODE                             sKCCBDeferredCommandsListHead;
 512
 513         /* Linked lists of contexts on this device */
 514         DLLIST_NODE                             sRenderCtxtListHead;
 515         DLLIST_NODE                             sComputeCtxtListHead;
 516         DLLIST_NODE                             sTransferCtxtListHead;
 517         DLLIST_NODE                             sTDMCtxtListHead;
 518         DLLIST_NODE                             sRaytraceCtxtListHead;
 519         DLLIST_NODE                             sKickSyncCtxtListHead;
 520
 521         DLLIST_NODE                     sCommonCtxtListHead;
 522         IMG_UINT32                              ui32CommonCtxtCurrentID;        /*!< ID assigned to the next common context */
 523
 524 #if defined(SUPPORT_PAGE_FAULT_DEBUG)
 525         POS_LOCK                                hDebugFaultInfoLock;    /*!< Lock to protect the debug fault info list */
 526         POS_LOCK                                hMMUCtxUnregLock;               /*!< Lock to protect list of unregistered MMU contexts */
 527 #endif
 528
 529         POS_LOCK                                hNMILock; /*!< Lock to protect NMI operations */
 530
 531         RGX_DUST_STATE                  sDustReqState;
 532
 533         RGX_POWER_LAYER_PARAMS  sPowerParams;
 534
 535         RGXFWIF_DM                              eBPDM;                                  /*!< Current breakpoint data master */
 536         IMG_BOOL                                bBPSet;                                 /*!< A Breakpoint has been set */
 537
 538         IMG_UINT32                              ui32CoherencyTestsDone;
 539 } PVRSRV_RGXDEV_INFO;
 540
 541
 542
 543 typedef struct _RGX_TIMING_INFORMATION_
 544 {
 545         /*! GPU default voltage */
 546         IMG_UINT32                      ui32CoreVoltage;
 547
 548         /*! GPU default core clock speed in Hz */
 549         IMG_UINT32                      ui32CoreClockSpeed;
 550
 551         /*! Active Power Management: GPU actively requests the host driver to be powered off */
 552         IMG_BOOL                        bEnableActivePM;
 553
 554         /*! Enable the GPU to power off internal Power Islands independently from the host driver */
 555         IMG_BOOL                        bEnableRDPowIsland;
 556
 557         /*! Active Power Management: Delay between the GPU idle and the request to the host */
 558         IMG_UINT32                      ui32ActivePMLatencyms;
 559
 560 } RGX_TIMING_INFORMATION;
 561
 562 typedef struct _RGX_DATA_
 563 {
 564         /*! Timing information */
 565         RGX_TIMING_INFORMATION  *psRGXTimingInfo;
 566         IMG_BOOL bHasTDFWCodePhysHeap;
 567         IMG_UINT32 uiTDFWCodePhysHeapID;
 568         IMG_BOOL bHasTDSecureBufPhysHeap;
 569         IMG_UINT32 uiTDSecureBufPhysHeapID;
 570 } RGX_DATA;
 571
 572
 573 /*
 574         RGX PDUMP register bank name (prefix)
 575 */
 576 #define RGX_PDUMPREG_NAME               "RGXREG"
 577
 578 #endif /* __RGXDEVICE_H__ */