drivers/staging/imgtec/rogue/rgxsrvinit.c

   1 /*************************************************************************/ /*!
   2 @File
   3 @Title          Services initialisation routines
   4 @Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
   5 @Description    Device specific functions
   6 @License        Dual MIT/GPLv2
   7
   8 The contents of this file are subject to the MIT license as set out below.
   9
  10 Permission is hereby granted, free of charge, to any person obtaining a copy
  11 of this software and associated documentation files (the "Software"), to deal
  12 in the Software without restriction, including without limitation the rights
  13 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  14 copies of the Software, and to permit persons to whom the Software is
  15 furnished to do so, subject to the following conditions:
  16
  17 The above copyright notice and this permission notice shall be included in
  18 all copies or substantial portions of the Software.
  19
  20 Alternatively, the contents of this file may be used under the terms of
  21 the GNU General Public License Version 2 ("GPL") in which case the provisions
  22 of GPL are applicable instead of those above.
  23
  24 If you wish to allow use of your version of this file only under the terms of
  25 GPL, and not to allow others to use your version of this file under the terms
  26 of the MIT license, indicate your decision by deleting the provisions above
  27 and replace them with the notice and other provisions required by GPL as set
  28 out in the file called "GPL-COPYING" included in this distribution. If you do
  29 not delete the provisions above, a recipient may use your version of this file
  30 under the terms of either the MIT license or GPL.
  31
  32 This License is also included in this distribution in the file called
  33 "MIT-COPYING".
  34
  35 EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
  36 PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
  37 BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
  38 PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
  39 COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  40 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  41 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  42 */ /**************************************************************************/
  43
  44 #include "img_defs.h"
  45 #include "srvinit.h"
  46 #include "pvr_debug.h"
  47 #include "osfunc.h"
  48 #include "km_apphint_defs.h"
  49 #include "htbuffer_types.h"
  50 #include "htbuffer_init.h"
  51
  52 #include "devicemem.h"
  53 #include "devicemem_pdump.h"
  54
  55 #include "client_rgxinit_bridge.h"
  56
  57 #include "rgx_fwif_sig.h"
  58
  59 #include "rgx_compat_bvnc.h"
  60
  61 #include "srvinit_osfunc.h"
  62
  63 #if !defined(SUPPORT_KERNEL_SRVINIT)
  64 #include "rgxdefs.h"
  65 #else
  66 #include "rgxdefs_km.h"
  67 #endif
  68
  69 #if defined(SUPPORT_GPUVIRT_VALIDATION)
  70 #include "virt_validation_defs.h"
  71 #endif
  72
  73 #include "srvinit_pdump.h"
  74
  75 #include "rgx_fwif_hwperf.h"
  76 #include "rgx_hwperf_table.h"
  77
  78 #include "rgxsrvinit_script.h"
  79
  80 #include "rgxfwload.h"
  81 #include "rgxlayer_impl.h"
  82 #include "rgxfwimageutils.h"
  83
  84 #include "rgx_hwperf_km.h"
  85 #include "rgx_bvnc_defs_km.h"
  86
  87 #if !defined(SUPPORT_KERNEL_SRVINIT)
  88 #include "rgx_hwperf.h"
  89 #include "rgx_fwif_km.h"
  90 #include "rgx_fwif_client.h"
  91 #include "rgx_fwif_alignchecks.h"
  92 #else
  93 #include "rgxdevice.h"
  94 #endif
  95 static RGX_INIT_COMMAND asDbgCommands[RGX_MAX_DEBUG_COMMANDS];
  96
  97 #if defined(SUPPORT_TRUSTED_DEVICE)
  98 #if !defined(SUPPORT_KERNEL_SRVINIT)
  99 #error "SUPPORT_KERNEL_SRVINIT is required by SUPPORT_TRUSTED_DEVICE!"
 100 #endif
 101 #include "rgxdevice.h"
 102 #include "pvrsrv_device.h"
 103 #endif
 104
 105
 106 #define HW_PERF_FILTER_DEFAULT         0x00000000 /* Default to no HWPerf */
 107 #define HW_PERF_FILTER_DEFAULT_ALL_ON  0xFFFFFFFF /* All events */
 108
 109
 110 #if defined(SUPPORT_KERNEL_SRVINIT) && defined(SUPPORT_VALIDATION)
 111 #include "pvrsrv_apphint.h"
 112 #endif
 113
 114 #if defined(SUPPORT_KERNEL_SRVINIT) && defined(LINUX)
 115 #include "km_apphint.h"
 116 #include "os_srvinit_param.h"
 117 #else
 118 #include "srvinit_param.h"
 119 /*!
 120 *******************************************************************************
 121  * AppHint mnemonic data type helper tables
 122 ******************************************************************************/
 123 /* apphint map of name vs. enable flag */
 124 static SRV_INIT_PARAM_UINT32_LOOKUP htb_loggroup_tbl[] = {
 125 #define X(a, b) { #b, HTB_LOG_GROUP_FLAG(a) },
 126         HTB_LOG_SFGROUPLIST
 127 #undef X
 128 };
 129 /* apphint map of arg vs. OpMode */
 130 static SRV_INIT_PARAM_UINT32_LOOKUP htb_opmode_tbl[] = {
 131         { "droplatest", HTB_OPMODE_DROPLATEST},
 132         { "dropoldest", HTB_OPMODE_DROPOLDEST},
 133         /* HTB should never be started in HTB_OPMODE_BLOCK
 134          * as this can lead to deadlocks
 135          */
 136 };
 137
 138 static SRV_INIT_PARAM_UINT32_LOOKUP fwt_logtype_tbl[] = {
 139         { "trace", 2},
 140         { "tbi", 1},
 141         { "none", 0}
 142 };
 143
 144 static SRV_INIT_PARAM_UINT32_LOOKUP timecorr_clk_tbl[] = {
 145         { "mono", 0 },
 146         { "mono_raw", 1 },
 147         { "sched", 2 }
 148 };
 149
 150 static SRV_INIT_PARAM_UINT32_LOOKUP fwt_loggroup_tbl[] = { RGXFWIF_LOG_GROUP_NAME_VALUE_MAP };
 151
 152 /*
 153  * Services AppHints initialisation
 154  */
 155 #define X(a, b, c, d, e) SrvInitParamInit ## b( a, d, e )
 156 APPHINT_LIST_ALL
 157 #undef X
 158 #endif /* SUPPORT_KERNEL_SRVINIT && LINUX */
 159
 160 /*
 161  * Container for all the apphints used by this module
 162  */
 163 typedef struct _RGX_SRVINIT_APPHINTS_
 164 {
 165         IMG_BOOL   bDustRequestInject;
 166         IMG_BOOL   bEnableSignatureChecks;
 167         IMG_UINT32 ui32SignatureChecksBufSize;
 168
 169 #if defined(DEBUG)
 170         IMG_BOOL   bAssertOnOutOfMem;
 171         IMG_BOOL   bAssertOnHWRTrigger;
 172 #endif
 173         IMG_BOOL   bCheckMlist;
 174         IMG_BOOL   bDisableClockGating;
 175         IMG_BOOL   bDisableDMOverlap;
 176         IMG_BOOL   bDisableFEDLogging;
 177         IMG_BOOL   bDisablePDP;
 178         IMG_BOOL   bEnableCDMKillRand;
 179         IMG_BOOL   bEnableFTrace;
 180         IMG_BOOL   bEnableHWPerf;
 181         IMG_BOOL   bEnableHWPerfHost;
 182         IMG_BOOL   bEnableHWR;
 183         IMG_BOOL   bEnableRTUBypass;
 184         IMG_BOOL   bFilteringMode;
 185         IMG_BOOL   bHWPerfDisableCustomCounterFilter;
 186         IMG_BOOL   bZeroFreelist;
 187         IMG_UINT32 ui32EnableFWContextSwitch;
 188         IMG_UINT32 ui32FWContextSwitchProfile;
 189         IMG_UINT32 ui32HWPerfFWBufSize;
 190         IMG_UINT32 ui32HWPerfHostBufSize;
 191         IMG_UINT32 ui32HWPerfFilter0;
 192         IMG_UINT32 ui32HWPerfFilter1;
 193         IMG_UINT32 ui32HWPerfHostFilter;
 194         IMG_UINT32 ui32TimeCorrClock;
 195         IMG_UINT32 ui32HWRDebugDumpLimit;
 196         IMG_UINT32 ui32JonesDisableMask;
 197         IMG_UINT32 ui32LogType;
 198         IMG_UINT32 ui32TruncateMode;
 199         FW_PERF_CONF eFirmwarePerf;
 200         RGX_ACTIVEPM_CONF eRGXActivePMConf;
 201         RGX_META_T1_CONF eUseMETAT1;
 202         RGX_RD_POWER_ISLAND_CONF eRGXRDPowerIslandConf;
 203
 204 #if defined(SUPPORT_GPUVIRT_VALIDATION)
 205         IMG_UINT32 aui32OSidMin[GPUVIRT_VALIDATION_NUM_OS][GPUVIRT_VALIDATION_NUM_REGIONS];
 206         IMG_UINT32 aui32OSidMax[GPUVIRT_VALIDATION_NUM_OS][GPUVIRT_VALIDATION_NUM_REGIONS];
 207 #endif
 208         IMG_BOOL   bEnableTrustedDeviceAceConfig;
 209 } RGX_SRVINIT_APPHINTS;
 210
 211
 212 /*!
 213 *******************************************************************************
 214
 215  @Function      GetApphints
 216
 217  @Description   Read init time apphints and initialise internal variables
 218
 219  @Input         psHints : Pointer to apphints container
 220
 221  @Return        void
 222
 223 ******************************************************************************/
 224 static INLINE void GetApphints(RGX_SRVINIT_APPHINTS *psHints, IMG_UINT64 ui64ErnsBrns, IMG_UINT64 ui64Features)
 225 {
 226         void *pvParamState = SrvInitParamOpen();
 227         IMG_UINT32 ui32ParamTemp;
 228         IMG_BOOL bS7TopInfra = IMG_FALSE, bE42290 = IMG_FALSE, bTPUFiltermodeCtrl = IMG_FALSE, \
 229                         bE41805 = IMG_FALSE, bE42606 = IMG_FALSE, bAXIACELite = IMG_FALSE;
 230
 231 #if defined(PVRSRV_GPUVIRT_GUESTDRV)
 232         PVR_UNREFERENCED_PARAMETER(bE41805);
 233         PVR_UNREFERENCED_PARAMETER(bE42606);
 234         PVR_UNREFERENCED_PARAMETER(bE42290);
 235         PVR_UNREFERENCED_PARAMETER(bS7TopInfra);
 236         PVR_UNREFERENCED_PARAMETER(bTPUFiltermodeCtrl);
 237 #endif
 238
 239 #if !defined(SUPPORT_KERNEL_SRVINIT)
 240         PVR_UNREFERENCED_PARAMETER(ui64ErnsBrns);
 241         PVR_UNREFERENCED_PARAMETER(ui64Features);
 242         PVR_UNREFERENCED_PARAMETER(bAXIACELite);
 243 #if defined(RGX_FEATURE_S7_TOP_INFRASTRUCTURE)
 244         bS7TopInfra = IMG_TRUE;
 245 #endif
 246 #if defined(HW_ERN_42290)
 247         bE42290 = IMG_TRUE;
 248 #endif
 249 #if defined(HW_ERN_41805)
 250         bE41805 = IMG_TRUE;
 251 #endif
 252 #if defined(HW_ERN_42606)
 253         bE42606 = IMG_TRUE;
 254 #endif
 255 #if defined(RGX_FEATURE_AXI_ACELITE)
 256         bAXIACELite = IMG_TRUE;
 257 #endif
 258 #else
 259         if(ui64Features & RGX_FEATURE_S7_TOP_INFRASTRUCTURE_BIT_MASK)
 260         {
 261                 bS7TopInfra = IMG_TRUE;
 262         }
 263
 264         if(ui64Features & RGX_FEATURE_TPU_FILTERING_MODE_CONTROL_BIT_MASK)
 265         {
 266                 bTPUFiltermodeCtrl = IMG_TRUE;
 267         }
 268
 269         if(ui64ErnsBrns & HW_ERN_42290_BIT_MASK)
 270         {
 271                 bE42290 = IMG_TRUE;
 272         }
 273
 274         if(ui64ErnsBrns & HW_ERN_41805_BIT_MASK)
 275         {
 276                 bE41805 = IMG_TRUE;
 277         }
 278
 279         if(ui64ErnsBrns & HW_ERN_42606_BIT_MASK)
 280         {
 281                 bE42606 = IMG_TRUE;
 282         }
 283
 284         if(ui64Features & RGX_FEATURE_AXI_ACELITE_BIT_MASK)
 285         {
 286                 bAXIACELite = IMG_TRUE;
 287         }
 288 #endif
 289         /*
 290          * KM AppHints not passed through the srvinit interface
 291          */
 292 #if !defined(SUPPORT_KERNEL_SRVINIT)
 293         SrvInitParamUnreferenced(FWPoisonOnFreeValue);
 294         SrvInitParamUnreferenced(EnableFWPoisonOnFree);
 295         SrvInitParamUnreferenced(GeneralNon4KHeapPageSize);
 296         SrvInitParamUnreferenced(WatchdogThreadWeight);
 297         SrvInitParamUnreferenced(WatchdogThreadPriority);
 298         SrvInitParamUnreferenced(CleanupThreadWeight);
 299         SrvInitParamUnreferenced(CleanupThreadPriority);
 300         SrvInitParamUnreferenced(RGXBVNC);
 301 #endif
 302
 303         /*
 304          * NB AppHints initialised to a default value via SrvInitParamInit* macros above
 305          */
 306
 307         SrvInitParamGetBOOL(pvParamState,     DustRequestInject, psHints->bDustRequestInject);
 308         SrvInitParamGetBOOL(pvParamState,     EnableSignatureChecks, psHints->bEnableSignatureChecks);
 309         SrvInitParamGetUINT32(pvParamState,   SignatureChecksBufSize, psHints->ui32SignatureChecksBufSize);
 310
 311 #if defined(DEBUG)
 312         SrvInitParamGetBOOL(pvParamState,    AssertOutOfMemory, psHints->bAssertOnOutOfMem);
 313         SrvInitParamGetBOOL(pvParamState,    AssertOnHWRTrigger, psHints->bAssertOnHWRTrigger);
 314 #endif
 315         SrvInitParamGetBOOL(pvParamState,    CheckMList, psHints->bCheckMlist);
 316         SrvInitParamGetBOOL(pvParamState,    DisableClockGating, psHints->bDisableClockGating);
 317         SrvInitParamGetBOOL(pvParamState,    DisableDMOverlap, psHints->bDisableDMOverlap);
 318         SrvInitParamGetBOOL(pvParamState,    DisableFEDLogging, psHints->bDisableFEDLogging);
 319         SrvInitParamGetUINT32(pvParamState,  EnableAPM, ui32ParamTemp);
 320         psHints->eRGXActivePMConf = ui32ParamTemp;
 321         SrvInitParamGetBOOL(pvParamState,    EnableCDMKillingRandMode, psHints->bEnableCDMKillRand);
 322         SrvInitParamGetBOOL(pvParamState,    EnableFTraceGPU, psHints->bEnableFTrace);
 323         SrvInitParamGetUINT32(pvParamState,  EnableFWContextSwitch, psHints->ui32EnableFWContextSwitch);
 324         SrvInitParamGetBOOL(pvParamState,    EnableHWPerf, psHints->bEnableHWPerf);
 325         SrvInitParamGetBOOL(pvParamState,    EnableHWPerfHost, psHints->bEnableHWPerfHost);
 326         SrvInitParamGetBOOL(pvParamState,    EnableHWR, psHints->bEnableHWR);
 327         SrvInitParamGetUINT32(pvParamState,  EnableRDPowerIsland, ui32ParamTemp);
 328         psHints->eRGXRDPowerIslandConf = ui32ParamTemp;
 329         SrvInitParamGetBOOL(pvParamState,    EnableRTUBypass, psHints->bEnableRTUBypass);
 330         SrvInitParamGetUINT32(pvParamState,  FirmwarePerf, ui32ParamTemp);
 331         psHints->eFirmwarePerf = ui32ParamTemp;
 332         SrvInitParamGetUINT32(pvParamState,  FWContextSwitchProfile, psHints->ui32FWContextSwitchProfile);
 333         SrvInitParamGetBOOL(pvParamState,    HWPerfDisableCustomCounterFilter, psHints->bHWPerfDisableCustomCounterFilter);
 334         SrvInitParamGetUINT32(pvParamState,  HWPerfHostBufSizeInKB, psHints->ui32HWPerfHostBufSize);
 335         SrvInitParamGetUINT32(pvParamState,  HWPerfFWBufSizeInKB, psHints->ui32HWPerfFWBufSize);
 336 #if defined(SUPPORT_KERNEL_SRVINIT) && defined(LINUX)
 337         /* name changes */
 338         {
 339                 IMG_UINT64 ui64Tmp;
 340                 SrvInitParamGetBOOL(pvParamState,    DisablePDumpPanic, psHints->bDisablePDP);
 341                 SrvInitParamGetUINT64(pvParamState,  HWPerfFWFilter, ui64Tmp);
 342                 psHints->ui32HWPerfFilter0 = (IMG_UINT32)(ui64Tmp & 0xffffffffllu);
 343                 psHints->ui32HWPerfFilter1 = (IMG_UINT32)((ui64Tmp >> 32) & 0xffffffffllu);
 344         }
 345 #else
 346         SrvInitParamGetBOOL(pvParamState,    DisablePDP, psHints->bDisablePDP);
 347         SrvInitParamGetUINT32(pvParamState,  HWPerfFilter0, psHints->ui32HWPerfFilter0);
 348         SrvInitParamGetUINT32(pvParamState,  HWPerfFilter1, psHints->ui32HWPerfFilter1);
 349         SrvInitParamUnreferenced(DisablePDumpPanic);
 350         SrvInitParamUnreferenced(HWPerfFWFilter);
 351         SrvInitParamUnreferenced(RGXBVNC);
 352 #endif
 353         SrvInitParamGetUINT32(pvParamState,  HWPerfHostFilter, psHints->ui32HWPerfHostFilter);
 354         SrvInitParamGetUINT32List(pvParamState,  TimeCorrClock, psHints->ui32TimeCorrClock);
 355         SrvInitParamGetUINT32(pvParamState,  HWRDebugDumpLimit, ui32ParamTemp);
 356         psHints->ui32HWRDebugDumpLimit = MIN(ui32ParamTemp, RGXFWIF_HWR_DEBUG_DUMP_ALL);
 357
 358         if(bS7TopInfra)
 359         {
 360         #define RGX_CR_JONES_FIX_MT_ORDER_ISP_TE_CLRMSK (0XFFFFFFCFU)
 361         #define RGX_CR_JONES_FIX_MT_ORDER_ISP_EN        (0X00000020U)
 362         #define RGX_CR_JONES_FIX_MT_ORDER_TE_EN         (0X00000010U)
 363
 364                 SrvInitParamGetUINT32(pvParamState,  JonesDisableMask, ui32ParamTemp);
 365                 if (((ui32ParamTemp & ~RGX_CR_JONES_FIX_MT_ORDER_ISP_TE_CLRMSK) == RGX_CR_JONES_FIX_MT_ORDER_ISP_EN) ||
 366                         ((ui32ParamTemp & ~RGX_CR_JONES_FIX_MT_ORDER_ISP_TE_CLRMSK) == RGX_CR_JONES_FIX_MT_ORDER_TE_EN))
 367                 {
 368                         ui32ParamTemp |= (RGX_CR_JONES_FIX_MT_ORDER_TE_EN |
 369                                                           RGX_CR_JONES_FIX_MT_ORDER_ISP_EN);
 370                         PVR_DPF((PVR_DBG_WARNING, "Tile reordering mode requires both TE and ISP enabled. Forcing JonesDisableMask = %d",
 371                                         ui32ParamTemp));
 372                 }
 373                 psHints->ui32JonesDisableMask = ui32ParamTemp;
 374         }
 375
 376         if ( (bE42290) && (bTPUFiltermodeCtrl))
 377         {
 378                 SrvInitParamGetBOOL(pvParamState,    NewFilteringMode, psHints->bFilteringMode);
 379         }
 380
 381         if(bE41805 || bE42606)
 382         {
 383                 SrvInitParamGetUINT32(pvParamState,  TruncateMode, psHints->ui32TruncateMode);
 384         }
 385 #if defined(EMULATOR)
 386         if(bAXIACELite)
 387         {
 388                 SrvInitParamGetBOOL(pvParamState, EnableTrustedDeviceAceConfig, psHints->bEnableTrustedDeviceAceConfig);
 389         }
 390 #else
 391 #if !defined(SUPPORT_KERNEL_SRVINIT)
 392         SrvInitParamUnreferenced(EnableTrustedDeviceAceConfig);
 393 #endif
 394 #endif
 395
 396         SrvInitParamGetUINT32(pvParamState,  UseMETAT1, ui32ParamTemp);
 397         psHints->eUseMETAT1 = ui32ParamTemp & RGXFWIF_INICFG_METAT1_MASK;
 398
 399         SrvInitParamGetBOOL(pvParamState,    ZeroFreelist, psHints->bZeroFreelist);
 400
 401
 402         /*
 403          * HWPerf filter apphints setup
 404          */
 405         if (psHints->bEnableHWPerf)
 406         {
 407                 if (psHints->ui32HWPerfFilter0 == 0 && psHints->ui32HWPerfFilter1 == 0)
 408                 {
 409                         psHints->ui32HWPerfFilter0 = HW_PERF_FILTER_DEFAULT_ALL_ON;
 410                         psHints->ui32HWPerfFilter1 = HW_PERF_FILTER_DEFAULT_ALL_ON;
 411                 }
 412         }
 413         else
 414         {
 415                 if (psHints->ui32HWPerfFilter0 != 0 || psHints->ui32HWPerfFilter1 != 0)
 416                 {
 417                         psHints->bEnableHWPerf = IMG_TRUE;
 418                 }
 419         }
 420
 421 #if defined(SUPPORT_GPUTRACE_EVENTS)
 422         if (psHints->bEnableFTrace)
 423         {
 424                 /* In case we have not set EnableHWPerf AppHint just request creation
 425                  * of certain events we need for the FTrace i.e. only the Kick/Finish
 426                  * HW events */
 427                 if (!psHints->bEnableHWPerf)
 428                 {
 429                         psHints->ui32HWPerfFilter0 = (IMG_UINT32) (RGX_HWPERF_EVENT_MASK_HW_KICKFINISH & 0xFFFFFFFF);
 430                         psHints->ui32HWPerfFilter1 = (IMG_UINT32) ((RGX_HWPERF_EVENT_MASK_HW_KICKFINISH & 0xFFFFFFFF00000000) >> 32);
 431                 }
 432                 else
 433                 {
 434                         psHints->ui32HWPerfFilter0 = HW_PERF_FILTER_DEFAULT_ALL_ON;
 435                         psHints->ui32HWPerfFilter1 = HW_PERF_FILTER_DEFAULT_ALL_ON;
 436                 }
 437
 438         }
 439 #endif
 440
 441         if (psHints->bEnableHWPerfHost)
 442         {
 443                 if (psHints->ui32HWPerfHostFilter == 0)
 444                 {
 445                         psHints->ui32HWPerfHostFilter = HW_PERF_FILTER_DEFAULT_ALL_ON;
 446                 }
 447         }
 448         else
 449         {
 450                 if (psHints->ui32HWPerfHostFilter != 0)
 451                 {
 452                         psHints->bEnableHWPerfHost = IMG_TRUE;
 453                 }
 454         }
 455
 456         /*
 457          * FW logs apphints
 458          */
 459         {
 460                 IMG_UINT32 ui32LogType;
 461                 IMG_BOOL bFirmwareLogTypeConfigured, bAnyLogGroupConfigured;
 462
 463                 SrvInitParamGetUINT32BitField(pvParamState, EnableLogGroup, ui32LogType);
 464                 bAnyLogGroupConfigured = ui32LogType ? IMG_TRUE : IMG_FALSE;
 465                 bFirmwareLogTypeConfigured = SrvInitParamGetUINT32List(pvParamState, FirmwareLogType, ui32ParamTemp);
 466
 467                 if (bFirmwareLogTypeConfigured)
 468                 {
 469                         if (ui32ParamTemp == 2 /* TRACE */)
 470                         {
 471                                 if (!bAnyLogGroupConfigured)
 472                                 {
 473                                         /* No groups configured - defaulting to MAIN group */
 474                                         ui32LogType |= RGXFWIF_LOG_TYPE_GROUP_MAIN;
 475                                 }
 476                                 ui32LogType |= RGXFWIF_LOG_TYPE_TRACE;
 477                         }
 478                         else if (ui32ParamTemp == 1 /* TBI */)
 479                         {
 480                                 if (!bAnyLogGroupConfigured)
 481                                 {
 482                                         /* No groups configured - defaulting to MAIN group */
 483                                         ui32LogType |= RGXFWIF_LOG_TYPE_GROUP_MAIN;
 484                                 }
 485                                 ui32LogType &= ~RGXFWIF_LOG_TYPE_TRACE;
 486                         }
 487                         else if (ui32ParamTemp == 0 /* NONE */)
 488                         {
 489                                 ui32LogType = RGXFWIF_LOG_TYPE_NONE;
 490                         }
 491                 }
 492                 else
 493                 {
 494                         /* No log type configured - defaulting to TRACE */
 495                         ui32LogType |= RGXFWIF_LOG_TYPE_TRACE;
 496                 }
 497
 498                 psHints->ui32LogType = ui32LogType;
 499         }
 500
 501 #if defined(SUPPORT_GPUVIRT_VALIDATION)
 502         /*
 503          * GPU virtualisation validation apphints
 504          */
 505         {
 506                 IMG_UINT uiCounter, uiRegion;
 507
 508                 PVR_DPF((PVR_DBG_MESSAGE,"\n[GPU Virtualization Validation]: Reading OSid limits\n"));
 509
 510                 for (uiRegion = 0; uiRegion < GPUVIRT_VALIDATION_NUM_REGIONS; uiRegion++)
 511                 {
 512                         for (uiCounter = 0; uiCounter < GPUVIRT_VALIDATION_NUM_OS; uiCounter++)
 513                         {
 514                                 IMG_CHAR   pszHintString[GPUVIRT_VALIDATION_MAX_STRING_LENGTH];
 515                                 IMG_UINT32 ui32Default = 0;
 516
 517                                 snprintf(pszHintString, GPUVIRT_VALIDATION_MAX_STRING_LENGTH, "OSidRegion%dMin%d", uiRegion, uiCounter);
 518                                 PVRSRVGetAppHint(pvParamState,
 519                                                  pszHintString,
 520                                                  IMG_UINT_TYPE,
 521                                                  &ui32Default,
 522                                                  &(psHints->aui32OSidMin[uiCounter][uiRegion]));
 523
 524                                 snprintf(pszHintString, GPUVIRT_VALIDATION_MAX_STRING_LENGTH, "OSidRegion%dMax%d", uiRegion, uiCounter);
 525                                 PVRSRVGetAppHint(pvParamState,
 526                                                  pszHintString,
 527                                                  IMG_UINT_TYPE,
 528                                                  &ui32Default,
 529                                                  &(psHints->aui32OSidMax[uiCounter][uiRegion]));
 530                         }
 531                 }
 532
 533                 for (uiCounter = 0; uiCounter < GPUVIRT_VALIDATION_NUM_OS; uiCounter++)
 534                 {
 535                         for (uiRegion = 0; uiRegion < GPUVIRT_VALIDATION_NUM_REGIONS; uiRegion++)
 536                         {
 537                                 PVR_DPF((PVR_DBG_MESSAGE,
 538                                          "\n[GPU Virtualization Validation]: Region:%d, OSid:%d, Min:%u, Max:%u\n",
 539                                          uiRegion, uiCounter,
 540                                          psHints->aui32OSidMin[uiCounter][uiRegion],
 541                                          psHints->aui32OSidMax[uiCounter][uiRegion]));
 542                         }
 543                 }
 544         }
 545 #endif /* defined(SUPPORT_GPUVIRT_VALIDATION) */
 546
 547
 548         SrvInitParamClose(pvParamState);
 549 }
 550
 551
 552 /*!
 553 *******************************************************************************
 554
 555  @Function      GetFWConfigFlags
 556
 557  @Description   Initialise and return FW config flags
 558
 559  @Input         psHints            : Apphints container
 560  @Input         pui32FWConfigFlags : Pointer to config flags
 561
 562  @Return        void
 563
 564 ******************************************************************************/
 565 static INLINE void GetFWConfigFlags(RGX_SRVINIT_APPHINTS *psHints,
 566                                     IMG_UINT32 *pui32FWConfigFlags)
 567 {
 568         IMG_UINT32 ui32FWConfigFlags = 0;
 569
 570 #if defined(DEBUG)
 571         ui32FWConfigFlags |= psHints->bAssertOnOutOfMem ? RGXFWIF_INICFG_ASSERT_ON_OUTOFMEMORY : 0;
 572         ui32FWConfigFlags |= psHints->bAssertOnHWRTrigger ? RGXFWIF_INICFG_ASSERT_ON_HWR_TRIGGER : 0;
 573 #endif
 574         ui32FWConfigFlags |= psHints->bCheckMlist ? RGXFWIF_INICFG_CHECK_MLIST_EN : 0;
 575         ui32FWConfigFlags |= psHints->bDisableClockGating ? RGXFWIF_INICFG_DISABLE_CLKGATING_EN : 0;
 576         ui32FWConfigFlags |= psHints->bDisableDMOverlap ? RGXFWIF_INICFG_DISABLE_DM_OVERLAP : 0;
 577         ui32FWConfigFlags |= psHints->bDisablePDP ? RGXFWIF_SRVCFG_DISABLE_PDP_EN : 0;
 578         ui32FWConfigFlags |= psHints->bEnableCDMKillRand ? RGXFWIF_INICFG_CDM_KILL_MODE_RAND_EN : 0;
 579 #if defined(SUPPORT_GPUTRACE_EVENTS)
 580         /* Since FTrace GPU events depends on HWPerf, ensure it is enabled here */
 581         ui32FWConfigFlags |= psHints->bEnableFTrace ? RGXFWIF_INICFG_HWPERF_EN : 0;
 582 #endif
 583         ui32FWConfigFlags |= psHints->bEnableHWPerf ? RGXFWIF_INICFG_HWPERF_EN : 0;
 584 #if !defined(NO_HARDWARE)
 585         ui32FWConfigFlags |= psHints->bEnableHWR ? RGXFWIF_INICFG_HWR_EN : 0;
 586 #endif
 587         ui32FWConfigFlags |= psHints->bEnableRTUBypass ? RGXFWIF_INICFG_RTU_BYPASS_EN : 0;
 588         ui32FWConfigFlags |= psHints->bHWPerfDisableCustomCounterFilter ? RGXFWIF_INICFG_HWP_DISABLE_FILTER : 0;
 589         ui32FWConfigFlags |= (psHints->eFirmwarePerf == FW_PERF_CONF_CUSTOM_TIMER) ? RGXFWIF_INICFG_CUSTOM_PERF_TIMER_EN : 0;
 590         ui32FWConfigFlags |= (psHints->eFirmwarePerf == FW_PERF_CONF_POLLS) ? RGXFWIF_INICFG_POLL_COUNTERS_EN : 0;
 591         ui32FWConfigFlags |= psHints->eUseMETAT1 << RGXFWIF_INICFG_METAT1_SHIFT;
 592         ui32FWConfigFlags |= psHints->ui32EnableFWContextSwitch & ~RGXFWIF_INICFG_CTXSWITCH_CLRMSK;
 593         ui32FWConfigFlags |= (psHints->ui32FWContextSwitchProfile << RGXFWIF_INICFG_CTXSWITCH_PROFILE_SHIFT) & RGXFWIF_INICFG_CTXSWITCH_PROFILE_MASK;
 594
 595         *pui32FWConfigFlags = ui32FWConfigFlags;
 596 }
 597
 598
 599 /*!
 600 *******************************************************************************
 601
 602  @Function      GetFilterFlags
 603
 604  @Description   Initialise and return filter flags
 605
 606  @Input         psHints : Apphints container
 607
 608  @Return        Filter flags
 609
 610 ******************************************************************************/
 611 static INLINE IMG_UINT32 GetFilterFlags(RGX_SRVINIT_APPHINTS *psHints)
 612 {
 613         IMG_UINT32 ui32FilterFlags = 0;
 614
 615         ui32FilterFlags |= psHints->bFilteringMode ? RGXFWIF_FILTCFG_NEW_FILTER_MODE : 0;
 616         if (psHints->ui32TruncateMode == 2)
 617         {
 618                 ui32FilterFlags |= RGXFWIF_FILTCFG_TRUNCATE_INT;
 619         }
 620         else if (psHints->ui32TruncateMode == 3)
 621         {
 622                 ui32FilterFlags |= RGXFWIF_FILTCFG_TRUNCATE_HALF;
 623         }
 624
 625         return ui32FilterFlags;
 626 }
 627
 628
 629 /*!
 630 *******************************************************************************
 631
 632  @Function      GetDeviceFlags
 633
 634  @Description   Initialise and return device flags
 635
 636  @Input         psHints          : Apphints container
 637  @Input         pui32DeviceFlags : Pointer to device flags
 638
 639  @Return        void
 640
 641 ******************************************************************************/
 642 static INLINE void GetDeviceFlags(RGX_SRVINIT_APPHINTS *psHints,
 643                                   IMG_UINT32 *pui32DeviceFlags)
 644 {
 645         IMG_UINT32 ui32DeviceFlags = 0;
 646
 647         ui32DeviceFlags |= psHints->bDustRequestInject? RGXKMIF_DEVICE_STATE_DUST_REQUEST_INJECT_EN : 0;
 648
 649         ui32DeviceFlags |= psHints->bZeroFreelist ? RGXKMIF_DEVICE_STATE_ZERO_FREELIST : 0;
 650         ui32DeviceFlags |= psHints->bDisableFEDLogging ? RGXKMIF_DEVICE_STATE_DISABLE_DW_LOGGING_EN : 0;
 651         ui32DeviceFlags |= psHints->bEnableHWPerfHost ? RGXKMIF_DEVICE_STATE_HWPERF_HOST_EN : 0;
 652 #if defined(SUPPORT_GPUTRACE_EVENTS)
 653         ui32DeviceFlags |= psHints->bEnableFTrace ? RGXKMIF_DEVICE_STATE_FTRACE_EN : 0;
 654 #endif
 655
 656         *pui32DeviceFlags = ui32DeviceFlags;
 657 }
 658
 659
 660 /*!
 661 *******************************************************************************
 662
 663  @Function              PrepareDebugScript
 664
 665  @Description   Generates a script to dump debug info
 666
 667  @Input                 psScript
 668
 669  @Return                IMG_BOOL True if it runs out of cmds when building the script
 670
 671 ******************************************************************************/
 672 static IMG_BOOL PrepareDebugScript(RGX_SCRIPT_BUILD* psDbgInitScript,
 673                                         IMG_BOOL bFirmwarePerf,
 674                                         void *pvDeviceInfo)
 675 {
 676 #define DBG_READ(T, R, S)               if (!ScriptDBGReadRGXReg(psDbgInitScript, T, R, S)) return IMG_FALSE;
 677 #if defined(RGX_FEATURE_META) || defined(SUPPORT_KERNEL_SRVINIT)
 678 #define DBG_MSP_READ(R, S)              if (!ScriptDBGReadMetaRegThroughSP(psDbgInitScript, R, S)) return IMG_FALSE;
 679 #define DBG_MCR_READ(R, S)              if (!ScriptDBGReadMetaCoreReg(psDbgInitScript, R, S)) return IMG_FALSE;
 680 #else
 681 #define DBG_MSP_READ(R, S)
 682 #define DBG_MCR_READ(R, S)
 683 #endif
 684 #define DBG_CALC(R, S, T, U, V) if (!ScriptDBGCalc(psDbgInitScript, R, S, T, U, V)) return IMG_FALSE;
 685 #define DBG_STRING(S)                   if (!ScriptDBGString(psDbgInitScript, S)) return IMG_FALSE;
 686 #define DBG_READ32(R, S)                                DBG_READ(RGX_INIT_OP_DBG_READ32_HW_REG, R, S)
 687 #define DBG_READ64(R, S)                                DBG_READ(RGX_INIT_OP_DBG_READ64_HW_REG, R, S)
 688 #define DBG_CALC_TA_AND_3D(R, S, T, U)  DBG_CALC(RGX_INIT_OP_DBG_CALC, R, S, T, U)
 689         IMG_BOOL        bS7Infra, bXTInfra, e44871, bRayTracing, e47025, bVIVTSlc, bMIPS, bPBVNC;
 690         IMG_UINT32      ui32SLCBanks = 0, ui32Meta = 0;
 691 #if !defined(SUPPORT_KERNEL_SRVINIT)
 692         PVR_UNREFERENCED_PARAMETER(pvDeviceInfo);
 693 #else
 694         PVRSRV_RGXDEV_INFO *psDevInfo = (PVRSRV_RGXDEV_INFO *)pvDeviceInfo;
 695 #endif
 696         PVR_UNREFERENCED_PARAMETER(bFirmwarePerf);
 697         bS7Infra = bXTInfra = e44871 = bRayTracing = e47025 = bVIVTSlc = bMIPS = bPBVNC = IMG_FALSE;
 698
 699
 700 #if !defined(SUPPORT_KERNEL_SRVINIT)
 701         #if defined(RGX_FEATURE_META)
 702                 ui32Meta = RGX_FEATURE_META;
 703         #endif
 704         #if defined(RGX_FEATURE_S7_TOP_INFRASTRUCTURE)
 705                 bS7Infra = IMG_TRUE;
 706         #endif
 707
 708         #if defined(RGX_FEATURE_XT_TOP_INFRASTRUCTURE)
 709                 bXTInfra = IMG_TRUE;
 710         #endif
 711
 712         #if     defined(FIX_HW_BRN_44871)
 713                 e44871 = IMG_TRUE;
 714         #endif
 715
 716         #if     defined(HW_ERN_47025)
 717                 e47025 = IMG_TRUE;
 718         #endif
 719
 720         #if defined(RGX_FEATURE_RAY_TRACING)
 721                 bRayTracing = IMG_TRUE;
 722         #endif
 723
 724         #if defined(RGX_FEATURE_SLC_BANKS)
 725                 ui32SLCBanks = RGX_FEATURE_SLC_BANKS;
 726         #endif
 727
 728         #if defined(RGX_FEATURE_SLC_VIVT)
 729                 bVIVTSlc = IMG_TRUE;
 730         #endif
 731
 732         #if defined(RGX_FEATURE_MIPS)
 733                 bMIPS = IMG_TRUE;
 734         #endif
 735         #if defined(RGX_FEATURE_PBVNC_COREID_REG)
 736                 bPBVNC = IMG_TRUE;
 737         #endif
 738 #else
 739         do{
 740                 if(NULL == psDevInfo)
 741                         break;
 742
 743                 if(psDevInfo->sDevFeatureCfg.ui64Features & RGX_FEATURE_PBVNC_COREID_REG_BIT_MASK)
 744                 {
 745                         bPBVNC = IMG_TRUE;
 746                 }
 747
 748                 if(psDevInfo->sDevFeatureCfg.ui32META)
 749                 {
 750                         ui32Meta = psDevInfo->sDevFeatureCfg.ui32META;
 751                 }
 752
 753                 if(psDevInfo->sDevFeatureCfg.ui64Features & RGX_FEATURE_S7_TOP_INFRASTRUCTURE_BIT_MASK)
 754                 {
 755                         bS7Infra = IMG_TRUE;
 756                 }
 757
 758                 if(psDevInfo->sDevFeatureCfg.ui64Features & RGX_FEATURE_XT_TOP_INFRASTRUCTURE_BIT_MASK)
 759                 {
 760                         bXTInfra = IMG_TRUE;
 761                 }
 762
 763                 if(psDevInfo->sDevFeatureCfg.ui64Features & RGX_FEATURE_RAY_TRACING_BIT_MASK)
 764                 {
 765                         bRayTracing = IMG_TRUE;
 766                 }
 767
 768                 if(psDevInfo->sDevFeatureCfg.ui64Features & RGX_FEATURE_SLC_VIVT_BIT_MASK)
 769                 {
 770                         bVIVTSlc = IMG_TRUE;
 771                 }
 772
 773                 if(psDevInfo->sDevFeatureCfg.ui64Features & RGX_FEATURE_MIPS_BIT_MASK)
 774                 {
 775                         bMIPS = IMG_TRUE;
 776                 }
 777
 778
 779                 if(psDevInfo->sDevFeatureCfg.ui32SLCBanks)
 780                 {
 781                         ui32SLCBanks = psDevInfo->sDevFeatureCfg.ui32SLCBanks;
 782                 }
 783
 784                 if(psDevInfo->sDevFeatureCfg.ui64ErnsBrns & FIX_HW_BRN_44871_BIT_MASK)
 785                 {
 786                         e44871 = IMG_TRUE;
 787                 }
 788
 789                 if(psDevInfo->sDevFeatureCfg.ui64ErnsBrns & HW_ERN_47025_POS)
 790                 {
 791                         e47025 = IMG_TRUE;
 792                 }
 793
 794         }while(0);
 795 #endif
 796
 797         if(bPBVNC)
 798         {
 799                 DBG_READ64(RGX_CR_CORE_ID,                                                      "CORE_ID                         ");
 800         }else
 801         {
 802                 DBG_READ32(RGX_CR_CORE_ID,                                                      "CORE_ID                         ");
 803         }
 804
 805         DBG_READ32(RGX_CR_CORE_REVISION,                                        "CORE_REVISION                   ");
 806         DBG_READ32(RGX_CR_DESIGNER_REV_FIELD1,                          "DESIGNER_REV_FIELD1             ");
 807         DBG_READ32(RGX_CR_DESIGNER_REV_FIELD2,                          "DESIGNER_REV_FIELD2             ");
 808         DBG_READ64(RGX_CR_CHANGESET_NUMBER,                                     "CHANGESET_NUMBER                ");
 809         if(ui32Meta)
 810         {
 811                 DBG_READ32(RGX_CR_META_SP_MSLVIRQSTATUS,                        "META_SP_MSLVIRQSTATUS           ");
 812         }
 813         DBG_READ64(RGX_CR_CLK_CTRL,                                                     "CLK_CTRL                        ");
 814         DBG_READ64(RGX_CR_CLK_STATUS,                                           "CLK_STATUS                      ");
 815         DBG_READ64(RGX_CR_CLK_CTRL2,                                            "CLK_CTRL2                       ");
 816         DBG_READ64(RGX_CR_CLK_STATUS2,                                          "CLK_STATUS2                     ");
 817         if (bS7Infra)
 818         {
 819                 DBG_READ64(RGX_CR_CLK_XTPLUS_CTRL,                                      "CLK_XTPLUS_CTRL                 ");
 820                 DBG_READ64(RGX_CR_CLK_XTPLUS_STATUS,                            "CLK_XTPLUS_STATUS               ");
 821         }
 822         DBG_READ32(RGX_CR_EVENT_STATUS,                                         "EVENT_STATUS                    ");
 823         DBG_READ64(RGX_CR_TIMER,                                                        "TIMER                           ");
 824         if (bS7Infra)
 825         {
 826                 DBG_READ64(RGX_CR_MMU_FAULT_STATUS,                                     "MMU_FAULT_STATUS                ");
 827                 DBG_READ64(RGX_CR_MMU_FAULT_STATUS_META,                        "MMU_FAULT_STATUS_META           ");
 828         }
 829         else
 830         {
 831                 DBG_READ32(RGX_CR_BIF_FAULT_BANK0_MMU_STATUS,           "BIF_FAULT_BANK0_MMU_STATUS      ");
 832                 DBG_READ64(RGX_CR_BIF_FAULT_BANK0_REQ_STATUS,           "BIF_FAULT_BANK0_REQ_STATUS      ");
 833                 DBG_READ32(RGX_CR_BIF_FAULT_BANK1_MMU_STATUS,           "BIF_FAULT_BANK1_MMU_STATUS      ");
 834                 DBG_READ64(RGX_CR_BIF_FAULT_BANK1_REQ_STATUS,           "BIF_FAULT_BANK1_REQ_STATUS      ");
 835         }
 836
 837         DBG_READ32(RGX_CR_BIF_MMU_STATUS,                                       "BIF_MMU_STATUS                  ");
 838         DBG_READ32(RGX_CR_BIF_MMU_ENTRY,                                        "BIF_MMU_ENTRY                   ");
 839         DBG_READ64(RGX_CR_BIF_MMU_ENTRY_STATUS,                         "BIF_MMU_ENTRY_STATUS            ");
 840         if (bS7Infra)
 841         {
 842                 DBG_READ32(RGX_CR_BIF_JONES_OUTSTANDING_READ,           "BIF_JONES_OUTSTANDING_READ      ");
 843                 DBG_READ32(RGX_CR_BIF_BLACKPEARL_OUTSTANDING_READ,      "BIF_BLACKPEARL_OUTSTANDING_READ ");
 844                 DBG_READ32(RGX_CR_BIF_DUST_OUTSTANDING_READ,            "BIF_DUST_OUTSTANDING_READ       ");
 845         }else
 846         {
 847
 848                 if (!bXTInfra)
 849                 {
 850                         DBG_READ32(RGX_CR_BIF_STATUS_MMU,                                       "BIF_STATUS_MMU                  ");
 851                         DBG_READ32(RGX_CR_BIF_READS_EXT_STATUS,                         "BIF_READS_EXT_STATUS            ");
 852                         DBG_READ32(RGX_CR_BIF_READS_INT_STATUS,                         "BIF_READS_INT_STATUS            ");
 853                 }
 854                 DBG_READ32(RGX_CR_BIFPM_STATUS_MMU,                                     "BIFPM_STATUS_MMU                ");
 855                 DBG_READ32(RGX_CR_BIFPM_READS_EXT_STATUS,                       "BIFPM_READS_EXT_STATUS          ");
 856                 DBG_READ32(RGX_CR_BIFPM_READS_INT_STATUS,                       "BIFPM_READS_INT_STATUS          ");
 857         }
 858
 859         if(e44871)
 860         {
 861                 DBG_STRING("Warning: BRN44871 is present");
 862         }
 863
 864         if(e47025)
 865         {
 866                 DBG_READ64(RGX_CR_CDM_CONTEXT_LOAD_PDS0,                        "CDM_CONTEXT_LOAD_PDS0           ");
 867                 DBG_READ64(RGX_CR_CDM_CONTEXT_LOAD_PDS1,                        "CDM_CONTEXT_LOAD_PDS1           ");
 868         }
 869
 870         DBG_READ32(RGX_CR_SLC_STATUS0,                                          "SLC_STATUS0                     ");
 871         DBG_READ64(RGX_CR_SLC_STATUS1,                                          "SLC_STATUS1                     ");
 872
 873         if (ui32SLCBanks)
 874         {
 875                 DBG_READ64(RGX_CR_SLC_STATUS2,                                          "SLC_STATUS2                     ");
 876         }
 877
 878         if (bVIVTSlc)
 879         {
 880                 DBG_READ64(RGX_CR_CONTEXT_MAPPING0,                                     "CONTEXT_MAPPING0                ");
 881                 DBG_READ64(RGX_CR_CONTEXT_MAPPING1,                                     "CONTEXT_MAPPING1                ");
 882                 DBG_READ64(RGX_CR_CONTEXT_MAPPING2,                                     "CONTEXT_MAPPING2                ");
 883                 DBG_READ64(RGX_CR_CONTEXT_MAPPING3,                                     "CONTEXT_MAPPING3                ");
 884                 DBG_READ64(RGX_CR_CONTEXT_MAPPING4,                                     "CONTEXT_MAPPING4                ");
 885         }else{
 886                 DBG_READ64(RGX_CR_BIF_CAT_BASE_INDEX,                           "BIF_CAT_BASE_INDEX              ");
 887                 DBG_READ64(RGX_CR_BIF_CAT_BASE0,                                        "BIF_CAT_BASE0                   ");
 888                 DBG_READ64(RGX_CR_BIF_CAT_BASE1,                                        "BIF_CAT_BASE1                   ");
 889                 DBG_READ64(RGX_CR_BIF_CAT_BASE2,                                        "BIF_CAT_BASE2                   ");
 890                 DBG_READ64(RGX_CR_BIF_CAT_BASE3,                                        "BIF_CAT_BASE3                   ");
 891                 DBG_READ64(RGX_CR_BIF_CAT_BASE4,                                        "BIF_CAT_BASE4                   ");
 892                 DBG_READ64(RGX_CR_BIF_CAT_BASE5,                                        "BIF_CAT_BASE5                   ");
 893                 DBG_READ64(RGX_CR_BIF_CAT_BASE6,                                        "BIF_CAT_BASE6                   ");
 894                 DBG_READ64(RGX_CR_BIF_CAT_BASE7,                                        "BIF_CAT_BASE7                   ");
 895         }
 896
 897         DBG_READ32(RGX_CR_BIF_CTRL_INVAL,                                       "BIF_CTRL_INVAL                  ");
 898         DBG_READ32(RGX_CR_BIF_CTRL,                                                     "BIF_CTRL                        ");
 899
 900         DBG_READ64(RGX_CR_BIF_PM_CAT_BASE_VCE0,                         "BIF_PM_CAT_BASE_VCE0            ");
 901         DBG_READ64(RGX_CR_BIF_PM_CAT_BASE_TE0,                          "BIF_PM_CAT_BASE_TE0             ");
 902         DBG_READ64(RGX_CR_BIF_PM_CAT_BASE_ALIST0,                       "BIF_PM_CAT_BASE_ALIST0          ");
 903         DBG_READ64(RGX_CR_BIF_PM_CAT_BASE_VCE1,                         "BIF_PM_CAT_BASE_VCE1            ");
 904         DBG_READ64(RGX_CR_BIF_PM_CAT_BASE_TE1,                          "BIF_PM_CAT_BASE_TE1             ");
 905         DBG_READ64(RGX_CR_BIF_PM_CAT_BASE_ALIST1,                       "BIF_PM_CAT_BASE_ALIST1          ");
 906
 907         DBG_READ32(RGX_CR_PERF_TA_PHASE,                                        "PERF_TA_PHASE                   ");
 908         DBG_READ32(RGX_CR_PERF_TA_CYCLE,                                        "PERF_TA_CYCLE                   ");
 909         DBG_READ32(RGX_CR_PERF_3D_PHASE,                                        "PERF_3D_PHASE                   ");
 910         DBG_READ32(RGX_CR_PERF_3D_CYCLE,                                        "PERF_3D_CYCLE                   ");
 911
 912         DBG_READ32(RGX_CR_PERF_TA_OR_3D_CYCLE,                          "PERF_TA_OR_3D_CYCLE             ");
 913         DBG_CALC_TA_AND_3D(RGX_CR_PERF_TA_CYCLE, RGX_CR_PERF_3D_CYCLE, RGX_CR_PERF_TA_OR_3D_CYCLE,
 914                                                                                                                 "PERF_TA_AND_3D_CYCLE            ");
 915
 916         DBG_READ32(RGX_CR_PERF_COMPUTE_PHASE,                           "PERF_COMPUTE_PHASE              ");
 917         DBG_READ32(RGX_CR_PERF_COMPUTE_CYCLE,                           "PERF_COMPUTE_CYCLE              ");
 918
 919         DBG_READ32(RGX_CR_PM_PARTIAL_RENDER_ENABLE,                     "PARTIAL_RENDER_ENABLE           ");
 920
 921         DBG_READ32(RGX_CR_ISP_RENDER,                                           "ISP_RENDER                      ");
 922         DBG_READ64(RGX_CR_TLA_STATUS,                                           "TLA_STATUS                      ");
 923         DBG_READ64(RGX_CR_MCU_FENCE,                                            "MCU_FENCE                       ");
 924
 925         DBG_READ32(RGX_CR_VDM_CONTEXT_STORE_STATUS,                     "VDM_CONTEXT_STORE_STATUS        ");
 926         DBG_READ64(RGX_CR_VDM_CONTEXT_STORE_TASK0,                      "VDM_CONTEXT_STORE_TASK0         ");
 927         DBG_READ64(RGX_CR_VDM_CONTEXT_STORE_TASK1,                      "VDM_CONTEXT_STORE_TASK1         ");
 928         DBG_READ64(RGX_CR_VDM_CONTEXT_STORE_TASK2,                      "VDM_CONTEXT_STORE_TASK2         ");
 929         DBG_READ64(RGX_CR_VDM_CONTEXT_RESUME_TASK0,                     "VDM_CONTEXT_RESUME_TASK0        ");
 930         DBG_READ64(RGX_CR_VDM_CONTEXT_RESUME_TASK1,                     "VDM_CONTEXT_RESUME_TASK1        ");
 931         DBG_READ64(RGX_CR_VDM_CONTEXT_RESUME_TASK2,                     "VDM_CONTEXT_RESUME_TASK2        ");
 932
 933         DBG_READ32(RGX_CR_ISP_CTL,                                                      "ISP_CTL                         ");
 934         DBG_READ32(RGX_CR_ISP_STATUS,                                           "ISP_STATUS                      ");
 935         DBG_READ32(RGX_CR_MTS_INTCTX,                                           "MTS_INTCTX                      ");
 936         DBG_READ32(RGX_CR_MTS_BGCTX,                                            "MTS_BGCTX                       ");
 937         DBG_READ32(RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE,           "MTS_BGCTX_COUNTED_SCHEDULE      ");
 938         DBG_READ32(RGX_CR_MTS_SCHEDULE,                                         "MTS_SCHEDULE                    ");
 939         DBG_READ32(RGX_CR_MTS_GPU_INT_STATUS,                           "MTS_GPU_INT_STATUS              ");
 940
 941         DBG_READ32(RGX_CR_CDM_CONTEXT_STORE_STATUS,                     "CDM_CONTEXT_STORE_STATUS        ");
 942         DBG_READ64(RGX_CR_CDM_CONTEXT_PDS0,                                     "CDM_CONTEXT_PDS0                ");
 943         DBG_READ64(RGX_CR_CDM_CONTEXT_PDS1,                                     "CDM_CONTEXT_PDS1                ");
 944         DBG_READ64(RGX_CR_CDM_TERMINATE_PDS,                            "CDM_TERMINATE_PDS               ");
 945         DBG_READ64(RGX_CR_CDM_TERMINATE_PDS1,                           "CDM_TERMINATE_PDS1              ");
 946
 947         if(e47025)
 948         {
 949                 DBG_READ64(RGX_CR_CDM_CONTEXT_LOAD_PDS0,                        "CDM_CONTEXT_LOAD_PDS0           ");
 950                 DBG_READ64(RGX_CR_CDM_CONTEXT_LOAD_PDS1,                        "CDM_CONTEXT_LOAD_PDS1           ");
 951         }
 952
 953         if(bRayTracing)
 954         {
 955 #if defined(RGX_FEATURE_RAY_TRACING) || defined(SUPPORT_KERNEL_SRVINIT)
 956                 DBG_READ32(DPX_CR_BIF_MMU_STATUS,                                       "DPX_CR_BIF_MMU_STATUS           ");
 957                 DBG_READ64(DPX_CR_BIF_FAULT_BANK_MMU_STATUS,            "DPX_CR_BIF_FAULT_BANK_MMU_STATUS");
 958                 DBG_READ64(DPX_CR_BIF_FAULT_BANK_REQ_STATUS,            "DPX_CR_BIF_FAULT_BANK_REQ_STATUS");
 959
 960                 DBG_READ64(RGX_CR_RPM_SHF_FPL,                                          "RGX_CR_RPM_SHF_FPL                  ");
 961                 DBG_READ32(RGX_CR_RPM_SHF_FPL_READ,                                     "RGX_CR_RPM_SHF_FPL_READ         ");
 962                 DBG_READ32(RGX_CR_RPM_SHF_FPL_WRITE,                            "RGX_CR_RPM_SHF_FPL_WRITE        ");
 963                 DBG_READ64(RGX_CR_RPM_SHG_FPL,                                          "RGX_CR_RPM_SHG_FPL                  ");
 964                 DBG_READ32(RGX_CR_RPM_SHG_FPL_READ,                                     "RGX_CR_RPM_SHG_FPL_READ         ");
 965                 DBG_READ32(RGX_CR_RPM_SHG_FPL_WRITE,                            "RGX_CR_RPM_SHG_FPL_WRITE        ");
 966 #endif
 967         }
 968
 969         if (bS7Infra)
 970         {
 971                 DBG_READ32(RGX_CR_JONES_IDLE,                                           "JONES_IDLE                      ");
 972         }
 973
 974         DBG_READ32(RGX_CR_SIDEKICK_IDLE,                                        "SIDEKICK_IDLE                   ");
 975         if (!bS7Infra)
 976         {
 977                 DBG_READ32(RGX_CR_SLC_IDLE,                                                     "SLC_IDLE                        ");
 978         }else
 979         {
 980                 DBG_READ32(RGX_CR_SLC3_IDLE,                                            "SLC3_IDLE                       ");
 981                 DBG_READ64(RGX_CR_SLC3_STATUS,                                          "SLC3_STATUS                     ");
 982                 DBG_READ32(RGX_CR_SLC3_FAULT_STOP_STATUS,                       "SLC3_FAULT_STOP_STATUS          ");
 983         }
 984
 985         if (ui32Meta)
 986         {
 987                 DBG_MSP_READ(META_CR_T0ENABLE_OFFSET,                           "T0 TXENABLE                     ");
 988                 DBG_MSP_READ(META_CR_T0STATUS_OFFSET,                           "T0 TXSTATUS                     ");
 989                 DBG_MSP_READ(META_CR_T0DEFR_OFFSET,                                     "T0 TXDEFR                       ");
 990                 DBG_MCR_READ(META_CR_THR0_PC,                                           "T0 PC                           ");
 991                 DBG_MCR_READ(META_CR_THR0_PCX,                                          "T0 PCX                          ");
 992                 DBG_MCR_READ(META_CR_THR0_SP,                                           "T0 SP                           ");
 993         }
 994
 995         if ((ui32Meta == MTP218) || (ui32Meta == MTP219))
 996         {
 997                 DBG_MSP_READ(META_CR_T1ENABLE_OFFSET,                           "T1 TXENABLE                     ");
 998                 DBG_MSP_READ(META_CR_T1STATUS_OFFSET,                           "T1 TXSTATUS                     ");
 999                 DBG_MSP_READ(META_CR_T1DEFR_OFFSET,                                     "T1 TXDEFR                       ");
1000                 DBG_MCR_READ(META_CR_THR1_PC,                                           "T1 PC                           ");
1001                 DBG_MCR_READ(META_CR_THR1_PCX,                                          "T1 PCX                          ");
1002                 DBG_MCR_READ(META_CR_THR1_SP,                                           "T1 SP                           ");
1003         }
1004
1005         if (bFirmwarePerf)
1006         {
1007                 DBG_MSP_READ(META_CR_PERF_COUNT0,                               "PERF_COUNT0                     ");
1008                 DBG_MSP_READ(META_CR_PERF_COUNT1,                               "PERF_COUNT1                     ");
1009         }
1010
1011         if (bMIPS)
1012         {
1013                 DBG_READ32(RGX_CR_MIPS_EXCEPTION_STATUS,            "MIPS_EXCEPTION_STATUS           ");
1014         }
1015
1016         return IMG_TRUE;
1017 }
1018
1019
1020 #if defined(SUPPORT_TRUSTED_DEVICE) && !defined(NO_HARDWARE)
1021 /*************************************************************************/ /*!
1022  @Function       RGXTDProcessFWImage
1023
1024  @Description    Fetch and send data used by the trusted device to complete
1025                  the FW image setup
1026
1027  @Input          psDeviceNode - Device node
1028  @Input          psRGXFW      - Firmware blob
1029
1030  @Return         PVRSRV_ERROR
1031 */ /**************************************************************************/
1032 static PVRSRV_ERROR RGXTDProcessFWImage(PVRSRV_DEVICE_NODE *psDeviceNode,
1033                                         struct RGXFW *psRGXFW)
1034 {
1035         PVRSRV_DEVICE_CONFIG *psDevConfig = psDeviceNode->psDevConfig;
1036         PVRSRV_RGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice;
1037         PVRSRV_TD_FW_PARAMS sTDFWParams;
1038         PVRSRV_ERROR eError;
1039
1040         if (psDevConfig->pfnTDSendFWImage == NULL)
1041         {
1042                 PVR_DPF((PVR_DBG_ERROR, "RGXTDProcessFWImage: TDProcessFWImage not implemented!"));
1043                 return PVRSRV_ERROR_NOT_IMPLEMENTED;
1044         }
1045
1046         sTDFWParams.pvFirmware = RGXFirmwareData(psRGXFW);
1047         sTDFWParams.ui32FirmwareSize = RGXFirmwareSize(psRGXFW);
1048         sTDFWParams.sFWCodeDevVAddrBase = psDevInfo->sFWCodeDevVAddrBase;
1049         sTDFWParams.sFWDataDevVAddrBase = psDevInfo->sFWDataDevVAddrBase;
1050         sTDFWParams.sFWCorememCodeFWAddr = psDevInfo->sFWCorememCodeFWAddr;
1051         sTDFWParams.sFWInitFWAddr = psDevInfo->sFWInitFWAddr;
1052
1053         eError = psDevConfig->pfnTDSendFWImage(psDevConfig->hSysData, &sTDFWParams);
1054
1055         return eError;
1056 }
1057 #endif
1058
1059 /*!
1060 *******************************************************************************
1061
1062  @Function     AcquireHostData
1063
1064  @Description  Acquire Device MemDesc and CPU pointer for a given PMR
1065
1066  @Input        hServices      : Services connection
1067  @Input        hPMR           : PMR
1068  @Output       ppsHostMemDesc : Returned MemDesc
1069  @Output       ppvHostAddr    : Returned CPU pointer
1070
1071  @Return       PVRSRV_ERROR
1072
1073 ******************************************************************************/
1074 static INLINE
1075 PVRSRV_ERROR AcquireHostData(SHARED_DEV_CONNECTION hServices,
1076                              IMG_HANDLE hPMR,
1077                              DEVMEM_MEMDESC **ppsHostMemDesc,
1078                              void **ppvHostAddr)
1079 {
1080         IMG_HANDLE hImportHandle;
1081         IMG_DEVMEM_SIZE_T uiImportSize;
1082         PVRSRV_ERROR eError;
1083
1084         eError = DevmemMakeLocalImportHandle(hServices,
1085                                              hPMR,
1086                                              &hImportHandle);
1087         if (eError != PVRSRV_OK)
1088         {
1089                 PVR_DPF((PVR_DBG_ERROR, "AcquireHostData: DevmemMakeLocalImportHandle failed (%d)", eError));
1090                 goto acquire_failmakehandle;
1091         }
1092
1093         eError = DevmemLocalImport(hServices,
1094                                    hImportHandle,
1095                                    PVRSRV_MEMALLOCFLAG_CPU_READABLE |
1096                                    PVRSRV_MEMALLOCFLAG_CPU_WRITEABLE |
1097                                    PVRSRV_MEMALLOCFLAG_GPU_CACHE_INCOHERENT |
1098                                    PVRSRV_MEMALLOCFLAG_CPU_WRITE_COMBINE,
1099                                    ppsHostMemDesc,
1100                                    &uiImportSize,
1101                                    "AcquireHostData");
1102         if (eError != PVRSRV_OK)
1103         {
1104                 PVR_DPF((PVR_DBG_ERROR, "AcquireHostData: DevmemLocalImport failed (%d)", eError));
1105                 goto acquire_failimport;
1106         }
1107
1108         eError = DevmemAcquireCpuVirtAddr(*ppsHostMemDesc,
1109                                           ppvHostAddr);
1110         if (eError != PVRSRV_OK)
1111         {
1112                 PVR_DPF((PVR_DBG_ERROR, "AcquireHostData: DevmemAcquireCpuVirtAddr failed (%d)", eError));
1113                 goto acquire_failcpuaddr;
1114         }
1115
1116         /* We don't need the import handle anymore */
1117         DevmemUnmakeLocalImportHandle(hServices, hImportHandle);
1118
1119         return PVRSRV_OK;
1120
1121
1122 acquire_failcpuaddr:
1123         DevmemFree(*ppsHostMemDesc);
1124
1125 acquire_failimport:
1126         DevmemUnmakeLocalImportHandle(hServices, hImportHandle);
1127
1128 acquire_failmakehandle:
1129         return eError;
1130 }
1131
1132 /*!
1133 *******************************************************************************
1134
1135  @Function     ReleaseHostData
1136
1137  @Description  Releases resources associated with a Device MemDesc
1138
1139  @Input        psHostMemDesc : MemDesc to free
1140
1141  @Return       PVRSRV_ERROR
1142
1143 ******************************************************************************/
1144 static INLINE void ReleaseHostData(DEVMEM_MEMDESC *psHostMemDesc)
1145 {
1146         DevmemReleaseCpuVirtAddr(psHostMemDesc);
1147         DevmemFree(psHostMemDesc);
1148 }
1149
1150 /*!
1151 *******************************************************************************
1152
1153  @Function     GetFirmwareBVNC
1154
1155  @Description  Retrieves FW BVNC information from binary data
1156
1157  @Input        psRGXFW : Firmware binary handle to get BVNC from
1158
1159  @Output       psRGXFWBVNC : structure store BVNC info
1160
1161  @Return       IMG_TRUE upon success, IMG_FALSE otherwise
1162
1163 ******************************************************************************/
1164 static INLINE IMG_BOOL GetFirmwareBVNC(struct RGXFW *psRGXFW,
1165                                        RGXFWIF_COMPCHECKS_BVNC *psFWBVNC)
1166 {
1167 #if defined(LINUX)
1168         const size_t FWSize = RGXFirmwareSize(psRGXFW);
1169         const RGXFWIF_COMPCHECKS_BVNC * psBinBVNC;
1170 #endif
1171
1172 #if !defined(LINUX)
1173         /* Check not available in non linux OSes. Just fill the struct and return true */
1174         psFWBVNC->ui32LayoutVersion = RGXFWIF_COMPCHECKS_LAYOUT_VERSION;
1175         psFWBVNC->ui32VLenMax = RGXFWIF_COMPCHECKS_BVNC_V_LEN_MAX;
1176 #if !defined(SUPPORT_KERNEL_SRVINIT)
1177         rgx_bvnc_packed(&psFWBVNC->ui64BNC, psFWBVNC->aszV, psFWBVNC->ui32VLenMax,
1178                         RGX_BNC_B, RGX_BVNC_V_ST, RGX_BNC_N, RGX_BNC_C);
1179 #else
1180         rgx_bvnc_packed(&psFWBVNC->ui64BNC, psFWBVNC->aszV, psFWBVNC->ui32VLenMax,
1181                         RGX_BNC_KM_B, RGX_BVNC_KM_V_ST, RGX_BNC_KM_N, RGX_BNC_KM_C);
1182 #endif /* SUPPORT_KERNEL_SRVINIT */
1183
1184 #else
1185
1186         if (FWSize < FW_BVNC_BACKWARDS_OFFSET)
1187         {
1188                 PVR_DPF((PVR_DBG_ERROR, "%s: Firmware is too small (%zu bytes)",
1189                          __func__, FWSize));
1190                 return IMG_FALSE;
1191         }
1192
1193         psBinBVNC = (RGXFWIF_COMPCHECKS_BVNC *) ((IMG_UINT8 *) (RGXFirmwareData(psRGXFW)) +
1194                                                  (FWSize - FW_BVNC_BACKWARDS_OFFSET));
1195
1196         psFWBVNC->ui32LayoutVersion = RGX_INT32_FROM_BE(psBinBVNC->ui32LayoutVersion);
1197
1198         psFWBVNC->ui32VLenMax = RGX_INT32_FROM_BE(psBinBVNC->ui32VLenMax);
1199
1200         psFWBVNC->ui64BNC = RGX_INT64_FROM_BE(psBinBVNC->ui64BNC);
1201
1202         strncpy(psFWBVNC->aszV, psBinBVNC->aszV, sizeof(psFWBVNC->aszV));
1203 #endif /* defined(LINUX) */
1204
1205         return IMG_TRUE;
1206 }
1207
1208
1209 /*!
1210 *******************************************************************************
1211
1212  @Function     RGXInitFirmwareBridgeWrapper
1213
1214  @Description  Calls the proper RGXInitFirmware bridge version
1215
1216  @Return       PVRSRV_ERROR
1217
1218 ******************************************************************************/
1219 static INLINE PVRSRV_ERROR RGXInitFirmwareBridgeWrapper(SHARED_DEV_CONNECTION    hServices,
1220                                                         RGXFWIF_DEV_VIRTADDR     *psRGXFwInit,
1221                                                         IMG_BOOL                 bEnableSignatureChecks,
1222                                                         IMG_UINT32               ui32SignatureChecksBufSize,
1223                                                         IMG_UINT32               ui32HWPerfFWBufSizeKB,
1224                                                         IMG_UINT64               ui64HWPerfFilter,
1225                                                         IMG_UINT32               ui32RGXFWAlignChecksArrLength,
1226                                                         IMG_UINT32               *pui32RGXFWAlignChecks,
1227                                                         IMG_UINT32               ui32FWConfigFlags,
1228                                                         IMG_UINT32               ui32LogType,
1229                                                         IMG_UINT32               ui32FilterFlags,
1230                                                         IMG_UINT32               ui32JonesDisableMask,
1231                                                         IMG_UINT32               ui32HWRDebugDumpLimit,
1232                                                         RGXFWIF_COMPCHECKS_BVNC  *psClientBVNC,
1233                                                         RGXFWIF_COMPCHECKS_BVNC  *psFirmwareBVNC,
1234                                                         IMG_UINT32               ui32HWPerfCountersDataSize,
1235                                                         IMG_HANDLE               *phHWPerfDataPMR,
1236                                                         RGX_RD_POWER_ISLAND_CONF eRGXRDPowerIslandConf,
1237                                                         FW_PERF_CONF             eFirmwarePerf)
1238 {
1239         PVRSRV_ERROR eError;
1240
1241         RGX_FW_INIT_IN_PARAMS sInParams = {
1242                 RGXFWINITPARAMS_VERSION,
1243                 bEnableSignatureChecks,
1244                 ui32SignatureChecksBufSize,
1245                 ui32HWPerfFWBufSizeKB,
1246                 ui64HWPerfFilter,
1247                 ui32FWConfigFlags,
1248                 ui32LogType,
1249                 ui32FilterFlags,
1250                 ui32JonesDisableMask,
1251                 ui32HWRDebugDumpLimit,
1252                 { 0 },
1253                 { 0 },
1254                 ui32HWPerfCountersDataSize,
1255                 eRGXRDPowerIslandConf,
1256                 eFirmwarePerf,
1257                 { 0 }
1258         };
1259
1260         memcpy(&(sInParams.sClientBVNC), psClientBVNC, sizeof (sInParams.sClientBVNC));
1261         memcpy(&(sInParams.sFirmwareBVNC), psFirmwareBVNC, sizeof (sInParams.sFirmwareBVNC));
1262
1263
1264         eError = BridgeRGXInitFirmwareExtended(hServices, ui32RGXFWAlignChecksArrLength,
1265                                                pui32RGXFWAlignChecks, psRGXFwInit, phHWPerfDataPMR, &sInParams);
1266
1267         /* Error calling the bridge could be due to old KM not implementing the extended version */
1268         if ((eError == PVRSRV_ERROR_BRIDGE_CALL_FAILED)
1269             || (eError == PVRSRV_ERROR_BRIDGE_EINVAL))
1270         {
1271                 eError = BridgeRGXInitFirmware(hServices,
1272                                                psRGXFwInit,
1273                                                bEnableSignatureChecks,
1274                                                ui32SignatureChecksBufSize,
1275                                                ui32HWPerfFWBufSizeKB,
1276                                                ui64HWPerfFilter,
1277                                                ui32RGXFWAlignChecksArrLength,
1278                                                pui32RGXFWAlignChecks,
1279                                                ui32FWConfigFlags,
1280                                                ui32LogType,
1281                                                ui32FilterFlags,
1282                                                ui32JonesDisableMask,
1283                                                ui32HWRDebugDumpLimit,
1284                                                psClientBVNC,
1285                                                ui32HWPerfCountersDataSize,
1286                                                phHWPerfDataPMR,
1287                                                eRGXRDPowerIslandConf,
1288                                                eFirmwarePerf);
1289         }
1290
1291         return eError;
1292 }
1293
1294 /*!
1295 *******************************************************************************
1296
1297  @Function     InitFirmware
1298
1299  @Description  Allocate, initialise and pdump Firmware code and data memory
1300
1301  @Input        hServices       : Services connection
1302  @Input        psHints         : Apphints
1303  @Input        psBVNC          : Compatibility checks
1304  @Output       phFWCodePMR     : FW code PMR handle
1305  @Output       phFWDataPMR     : FW data PMR handle
1306  @Output       phFWCorememPMR  : FW coremem code PMR handle
1307  @Output       phHWPerfDataPMR : HWPerf control PMR handle
1308
1309  @Return       PVRSRV_ERROR
1310
1311 ******************************************************************************/
1312 static PVRSRV_ERROR InitFirmware(SHARED_DEV_CONNECTION hServices,
1313                                  RGX_SRVINIT_APPHINTS *psHints,
1314                                  RGXFWIF_COMPCHECKS_BVNC *psBVNC,
1315                                  IMG_HANDLE *phFWCodePMR,
1316                                  IMG_HANDLE *phFWDataPMR,
1317                                  IMG_HANDLE *phFWCorememPMR,
1318                                  IMG_HANDLE *phHWPerfDataPMR)
1319 {
1320         struct RGXFW      *psRGXFW = NULL;
1321         const IMG_BYTE    *pbRGXFirmware = NULL;
1322         RGXFWIF_COMPCHECKS_BVNC sFWBVNC;
1323
1324         /* FW code memory */
1325         IMG_DEVMEM_SIZE_T uiFWCodeAllocSize;
1326         IMG_DEV_VIRTADDR  sFWCodeDevVAddrBase;
1327         DEVMEM_MEMDESC    *psFWCodeHostMemDesc;
1328         void              *pvFWCodeHostAddr;
1329
1330         /* FW data memory */
1331         IMG_DEVMEM_SIZE_T uiFWDataAllocSize;
1332         IMG_DEV_VIRTADDR  sFWDataDevVAddrBase;
1333         DEVMEM_MEMDESC    *psFWDataHostMemDesc;
1334         void              *pvFWDataHostAddr;
1335
1336         /* FW coremem code memory */
1337         IMG_DEVMEM_SIZE_T uiFWCorememCodeAllocSize;
1338         IMG_DEV_VIRTADDR  sFWCorememDevVAddrBase;
1339
1340         /*
1341          * Only declare psFWCorememHostMemDesc where used (PVR_UNREFERENCED_PARAMETER doesn't
1342          * help for local vars when using certain compilers)
1343          */
1344         DEVMEM_MEMDESC    *psFWCorememHostMemDesc;
1345         void              *pvFWCorememHostAddr = NULL;
1346
1347         RGXFWIF_DEV_VIRTADDR sFWCorememFWAddr; /* FW coremem data */
1348         RGXFWIF_DEV_VIRTADDR sRGXFwInit;       /* FW init struct */
1349         RGX_INIT_LAYER_PARAMS sInitParams;
1350 #if !defined(SUPPORT_KERNEL_SRVINIT)
1351         IMG_UINT32 aui32RGXFWAlignChecks[] = {RGXFW_ALIGN_CHECKS_INIT};
1352 #endif
1353         IMG_UINT32 ui32FWConfigFlags;
1354         PVRSRV_ERROR eError;
1355         IMG_CHAR *pszFWFilename = NULL;
1356         IMG_CHAR *pszFWpFilename = NULL;
1357 #if defined(SUPPORT_KERNEL_SRVINIT)
1358         IMG_CHAR aszFWFilenameStr[OSStringLength(RGX_FW_FILENAME)+MAX_BVNC_STRING_LEN+2];
1359         IMG_CHAR aszFWpFilenameStr[OSStringLength(RGX_FW_FILENAME)+MAX_BVNC_STRING_LEN+3];
1360         PVRSRV_DEVICE_NODE *psDeviceNode = (PVRSRV_DEVICE_NODE *)hServices;
1361         PVRSRV_RGXDEV_INFO *psDevInfo = (PVRSRV_RGXDEV_INFO *)psDeviceNode->pvDevice;
1362
1363         pszFWFilename = &aszFWFilenameStr[0];
1364         OSSNPrintf(pszFWFilename, OSStringLength(RGX_FW_FILENAME)+MAX_BVNC_STRING_LEN+2, "%s.%d.%d.%d.%d", RGX_FW_FILENAME,
1365                    psDevInfo->sDevFeatureCfg.ui32B, psDevInfo->sDevFeatureCfg.ui32V,
1366                    psDevInfo->sDevFeatureCfg.ui32N, psDevInfo->sDevFeatureCfg.ui32C);
1367         pszFWpFilename = &aszFWpFilenameStr[0];
1368         OSSNPrintf(pszFWpFilename, OSStringLength(RGX_FW_FILENAME)+MAX_BVNC_STRING_LEN+3, "%s.%d.%dp.%d.%d", RGX_FW_FILENAME,
1369                    psDevInfo->sDevFeatureCfg.ui32B, psDevInfo->sDevFeatureCfg.ui32V,
1370                    psDevInfo->sDevFeatureCfg.ui32N, psDevInfo->sDevFeatureCfg.ui32C);
1371 #endif /* defined(SUPPORT_KERNEL_SRVINIT) */
1372 #if !defined(PVRSRV_GPUVIRT_GUESTDRV)
1373         /*
1374          * Get pointer to Firmware image
1375          */
1376
1377         psRGXFW = RGXLoadFirmware(hServices, pszFWFilename, pszFWpFilename);
1378         if (psRGXFW == NULL)
1379         {
1380                 PVR_DPF((PVR_DBG_ERROR, "InitFirmware: RGXLoadFirmware failed"));
1381                 eError = PVRSRV_ERROR_INIT_FAILURE;
1382                 goto cleanup_initfw;
1383         }
1384         pbRGXFirmware = RGXFirmwareData(psRGXFW);
1385
1386         if (!GetFirmwareBVNC(psRGXFW, &sFWBVNC))
1387         {
1388                 PVR_DPF((PVR_DBG_ERROR, "InitFirmware: RGXLoadFirmware failed to get Firmware BVNC"));
1389                 eError = PVRSRV_ERROR_INIT_FAILURE;
1390                 goto cleanup_initfw;
1391         }
1392
1393         sInitParams.hServices = hServices;
1394
1395         /*
1396          * Allocate Firmware memory
1397          */
1398
1399         eError = RGXGetFWImageAllocSize(&sInitParams,
1400                                         &uiFWCodeAllocSize,
1401                                         &uiFWDataAllocSize,
1402                                         &uiFWCorememCodeAllocSize);
1403
1404         if (eError != PVRSRV_OK)
1405         {
1406                 PVR_DPF((PVR_DBG_ERROR, "InitFirmware: RGXGetFWImageAllocSize failed"));
1407                 goto cleanup_initfw;
1408         }
1409
1410 #if defined(SUPPORT_TRUSTED_DEVICE)
1411         /* Disable META core memory allocation unless the META DMA is available */
1412 #if defined(SUPPORT_KERNEL_SRVINIT)
1413         if (!RGXDeviceHasFeatureInit(&sInitParams, RGX_FEATURE_META_DMA_BIT_MASK))
1414         {
1415                 uiFWCorememCodeAllocSize = 0;
1416         }
1417 #elif !defined(RGX_FEATURE_META_DMA)
1418         uiFWCorememCodeAllocSize = 0;
1419 #endif
1420 #endif
1421 #else
1422         PVR_UNREFERENCED_PARAMETER(pszFWFilename);
1423         PVR_UNREFERENCED_PARAMETER(pszFWpFilename);
1424         PVR_UNREFERENCED_PARAMETER(sInitParams);
1425         PVR_UNREFERENCED_PARAMETER(pbRGXFirmware);
1426         uiFWCodeAllocSize = 0;
1427         uiFWDataAllocSize = 0;
1428         uiFWCorememCodeAllocSize = 0;
1429 #endif
1430
1431         eError = BridgeRGXInitAllocFWImgMem(hServices,
1432                                             uiFWCodeAllocSize,
1433                                             uiFWDataAllocSize,
1434                                             uiFWCorememCodeAllocSize,
1435                                             phFWCodePMR,
1436                                             &sFWCodeDevVAddrBase,
1437                                             phFWDataPMR,
1438                                             &sFWDataDevVAddrBase,
1439                                             phFWCorememPMR,
1440                                             &sFWCorememDevVAddrBase,
1441                                             &sFWCorememFWAddr);
1442         if (eError != PVRSRV_OK)
1443         {
1444                 PVR_DPF((PVR_DBG_ERROR, "InitFirmware: PVRSRVRGXInitAllocFWImgMem failed (%d)", eError));
1445                 goto cleanup_initfw;
1446         }
1447
1448
1449         /*
1450          * Setup Firmware initialisation data
1451          */
1452
1453         GetFWConfigFlags(psHints, &ui32FWConfigFlags);
1454
1455         eError = RGXInitFirmwareBridgeWrapper(hServices,
1456                                               &sRGXFwInit,
1457                                               psHints->bEnableSignatureChecks,
1458                                               psHints->ui32SignatureChecksBufSize,
1459                                               psHints->ui32HWPerfFWBufSize,
1460                                               (IMG_UINT64)psHints->ui32HWPerfFilter0 |
1461                                               ((IMG_UINT64)psHints->ui32HWPerfFilter1 << 32),
1462 #if defined(SUPPORT_KERNEL_SRVINIT)
1463                                               0,
1464                                               NULL,
1465 #else
1466                                               IMG_ARR_NUM_ELEMS(aui32RGXFWAlignChecks),
1467                                               aui32RGXFWAlignChecks,
1468 #endif
1469                                               ui32FWConfigFlags,
1470                                               psHints->ui32LogType,
1471                                               GetFilterFlags(psHints),
1472                                               psHints->ui32JonesDisableMask,
1473                                               psHints->ui32HWRDebugDumpLimit,
1474                                               psBVNC,
1475                                               &sFWBVNC,
1476                                               sizeof(RGXFWIF_HWPERF_CTL),
1477                                               phHWPerfDataPMR,
1478                                               psHints->eRGXRDPowerIslandConf,
1479                                               psHints->eFirmwarePerf);
1480
1481         if (eError != PVRSRV_OK)
1482         {
1483                 PVR_DPF((PVR_DBG_ERROR, "InitFirmware: PVRSRVRGXInitFirmware failed (%d)", eError));
1484                 goto cleanup_initfw;
1485         }
1486 #if defined(PVRSRV_GPUVIRT_GUESTDRV)
1487         PVR_UNREFERENCED_PARAMETER(pvFWCorememHostAddr);
1488         PVR_UNREFERENCED_PARAMETER(psFWCorememHostMemDesc);
1489         PVR_UNREFERENCED_PARAMETER(pvFWDataHostAddr);
1490         PVR_UNREFERENCED_PARAMETER(psFWDataHostMemDesc);
1491         PVR_UNREFERENCED_PARAMETER(pvFWCodeHostAddr);
1492         PVR_UNREFERENCED_PARAMETER(psFWCodeHostMemDesc);
1493 #else
1494         /*
1495          * Acquire pointers to Firmware allocations
1496          */
1497
1498 #if !defined(SUPPORT_TRUSTED_DEVICE) || defined(NO_HARDWARE)
1499         eError = AcquireHostData(hServices,
1500                                  *phFWCodePMR,
1501                                  &psFWCodeHostMemDesc,
1502                                  &pvFWCodeHostAddr);
1503         if (eError != PVRSRV_OK)
1504         {
1505                 PVR_DPF((PVR_DBG_ERROR, "InitFirmware: AcquireHostData for FW code failed (%d)", eError));
1506                 goto release_code;
1507         }
1508 #else
1509         PVR_UNREFERENCED_PARAMETER(psFWCodeHostMemDesc);
1510
1511         /* We can't get a pointer to a secure FW allocation from within the DDK */
1512         pvFWCodeHostAddr = NULL;
1513 #endif
1514
1515         eError = AcquireHostData(hServices,
1516                                  *phFWDataPMR,
1517                                  &psFWDataHostMemDesc,
1518                                  &pvFWDataHostAddr);
1519         if (eError != PVRSRV_OK)
1520         {
1521                 PVR_DPF((PVR_DBG_ERROR, "InitFirmware: AcquireHostData for FW data failed (%d)", eError));
1522                 goto release_data;
1523         }
1524
1525 #if !defined(SUPPORT_TRUSTED_DEVICE) || defined(NO_HARDWARE)
1526         if (uiFWCorememCodeAllocSize)
1527         {
1528                 eError = AcquireHostData(hServices,
1529                                                                  *phFWCorememPMR,
1530                                                                  &psFWCorememHostMemDesc,
1531                                                                  &pvFWCorememHostAddr);
1532                 if (eError != PVRSRV_OK)
1533                 {
1534                         PVR_DPF((PVR_DBG_ERROR, "InitFirmware: AcquireHostData for FW coremem code failed (%d)", eError));
1535                         goto release_corememcode;
1536                 }
1537         }
1538 #else
1539         PVR_UNREFERENCED_PARAMETER(psFWCorememHostMemDesc);
1540
1541         /* We can't get a pointer to a secure FW allocation from within the DDK */
1542         pvFWCorememHostAddr = NULL;
1543 #endif
1544
1545
1546         /*
1547          * Process the Firmware image and setup code and data segments.
1548          *
1549          * When the trusted device is enabled and the FW code lives
1550          * in secure memory we will only setup the data segments here,
1551          * while the code segments will be loaded to secure memory
1552          * by the trusted device.
1553          */
1554
1555         eError = RGXProcessFWImage(&sInitParams,
1556                                    pbRGXFirmware,
1557                                    pvFWCodeHostAddr,
1558                                    pvFWDataHostAddr,
1559                                    pvFWCorememHostAddr,
1560                                    &sFWCodeDevVAddrBase,
1561                                    &sFWDataDevVAddrBase,
1562                                    &sFWCorememDevVAddrBase,
1563                                    &sFWCorememFWAddr,
1564                                    &sRGXFwInit,
1565 #if defined(RGXFW_META_SUPPORT_2ND_THREAD)
1566                                    2,
1567 #else
1568                                    psHints->eUseMETAT1 == RGX_META_T1_OFF ? 1 : 2,
1569 #endif
1570                                    psHints->eUseMETAT1 == RGX_META_T1_MAIN ? 1 : 0);
1571         if (eError != PVRSRV_OK)
1572         {
1573                 PVR_DPF((PVR_DBG_ERROR, "InitFirmware: RGXProcessFWImage failed (%d)", eError));
1574                 goto release_fw_allocations;
1575         }
1576
1577 #if defined(SUPPORT_TRUSTED_DEVICE) && !defined(NO_HARDWARE)
1578         RGXTDProcessFWImage(hServices, psRGXFW);
1579 #endif
1580
1581
1582         /*
1583          * Perform final steps (if any) on the kernel
1584          * before pdumping the Firmware allocations
1585          */
1586         eError = BridgeRGXInitFinaliseFWImage(hServices);
1587
1588         if (eError != PVRSRV_OK)
1589         {
1590                 PVR_DPF((PVR_DBG_ERROR, "InitFirmware: RGXInitFinaliseFWImage failed (%d)", eError));
1591                 goto release_fw_allocations;
1592         }
1593
1594         /*
1595          * PDump Firmware allocations
1596          */
1597
1598 #if !defined(SUPPORT_TRUSTED_DEVICE) || defined(NO_HARDWARE)
1599         SRVINITPDumpComment(hServices, "Dump firmware code image");
1600         DevmemPDumpLoadMem(psFWCodeHostMemDesc,
1601                            0,
1602                            uiFWCodeAllocSize,
1603                            PDUMP_FLAGS_CONTINUOUS);
1604 #endif
1605
1606         SRVINITPDumpComment(hServices, "Dump firmware data image");
1607         DevmemPDumpLoadMem(psFWDataHostMemDesc,
1608                            0,
1609                            uiFWDataAllocSize,
1610                            PDUMP_FLAGS_CONTINUOUS);
1611
1612 #if !defined(SUPPORT_TRUSTED_DEVICE) || defined(NO_HARDWARE)
1613         if (uiFWCorememCodeAllocSize)
1614         {
1615                 SRVINITPDumpComment(hServices, "Dump firmware coremem image");
1616                 DevmemPDumpLoadMem(psFWCorememHostMemDesc,
1617                                                    0,
1618                                                    uiFWCorememCodeAllocSize,
1619                                                    PDUMP_FLAGS_CONTINUOUS);
1620         }
1621 #endif
1622
1623
1624         /*
1625          * Release Firmware allocations and clean up
1626          */
1627
1628 release_fw_allocations:
1629 #if !defined(SUPPORT_TRUSTED_DEVICE) || defined(NO_HARDWARE)
1630 release_corememcode:
1631         if (uiFWCorememCodeAllocSize)
1632         {
1633                 ReleaseHostData(psFWCorememHostMemDesc);
1634         }
1635 #endif
1636
1637 release_data:
1638         ReleaseHostData(psFWDataHostMemDesc);
1639
1640 #if !defined(SUPPORT_TRUSTED_DEVICE) || defined(NO_HARDWARE)
1641 release_code:
1642         ReleaseHostData(psFWCodeHostMemDesc);
1643 #endif
1644 #endif /* PVRSRV_GPUVIRT_GUESTDRV */
1645 cleanup_initfw:
1646         if (psRGXFW != NULL)
1647         {
1648                 RGXUnloadFirmware(psRGXFW);
1649         }
1650
1651         return eError;
1652 }
1653
1654
1655 #if defined(PDUMP)
1656 /*!
1657 *******************************************************************************
1658
1659  @Function      InitialiseHWPerfCounters
1660
1661  @Description
1662
1663  Initialisation of hardware performance counters and dumping them out to pdump, so that they can be modified at a later point.
1664
1665  @Input hServices
1666
1667  @Input psHWPerfDataMemDesc
1668
1669  @Input psHWPerfInitDataInt
1670
1671  @Return  void
1672
1673 ******************************************************************************/
1674
1675 static void InitialiseHWPerfCounters(SHARED_DEV_CONNECTION hServices, DEVMEM_MEMDESC *psHWPerfDataMemDesc, RGXFWIF_HWPERF_CTL *psHWPerfInitDataInt)
1676 {
1677         RGXFWIF_HWPERF_CTL_BLK *psHWPerfInitBlkData;
1678         IMG_UINT32 ui32CntBlkModelLen;
1679         const RGXFW_HWPERF_CNTBLK_TYPE_MODEL *asCntBlkTypeModel;
1680         const RGXFW_HWPERF_CNTBLK_TYPE_MODEL* psBlkTypeDesc;
1681         IMG_UINT32 ui32BlockID, ui32BlkCfgIdx, ui32CounterIdx ;
1682         void *pvDev = NULL;     // Use SHARED_DEV_CONNECTION here?
1683         RGX_HWPERF_CNTBLK_RT_INFO sCntBlkRtInfo;
1684
1685 #if defined(SUPPORT_KERNEL_SRVINIT)
1686         {
1687                 PVRSRV_DEVICE_NODE *psDeviceNode = (PVRSRV_DEVICE_NODE *)hServices;
1688                 pvDev = psDeviceNode->pvDevice;
1689         }
1690 #endif
1691         ui32CntBlkModelLen = RGXGetHWPerfBlockConfig(&asCntBlkTypeModel);
1692         for(ui32BlkCfgIdx = 0; ui32BlkCfgIdx < ui32CntBlkModelLen; ui32BlkCfgIdx++)
1693         {
1694                 /* Exit early if this core does not have any of these counter blocks
1695                  * due to core type/BVNC features.... */
1696                 psBlkTypeDesc = &asCntBlkTypeModel[ui32BlkCfgIdx];
1697                 if (psBlkTypeDesc->pfnIsBlkPresent(psBlkTypeDesc, pvDev, &sCntBlkRtInfo) == IMG_FALSE)
1698                 {
1699                         continue;
1700                 }
1701
1702                 /* Program all counters in one block so those already on may
1703                  * be configured off and vice-a-versa. */
1704                 for (ui32BlockID = psBlkTypeDesc->uiCntBlkIdBase;
1705                                          ui32BlockID < psBlkTypeDesc->uiCntBlkIdBase+sCntBlkRtInfo.uiNumUnits;
1706                                          ui32BlockID++)
1707                 {
1708
1709                         SRVINITPDumpComment(hServices, "Unit %d Block : %s", ui32BlockID-psBlkTypeDesc->uiCntBlkIdBase, psBlkTypeDesc->pszBlockNameComment);
1710                         /* Get the block configure store to update from the global store of
1711                          * block configuration. This is used to remember the configuration
1712                          * between configurations and core power on in APM */
1713                         psHWPerfInitBlkData = rgxfw_hwperf_get_block_ctl(ui32BlockID, psHWPerfInitDataInt);
1714                         /* Assert to check for HWPerf block mis-configuration */
1715                         PVR_ASSERT(psHWPerfInitBlkData);
1716
1717                         psHWPerfInitBlkData->bValid = IMG_TRUE;
1718                         SRVINITPDumpComment(hServices, "bValid: This specifies if the layout block is valid for the given BVNC.");
1719                         DevmemPDumpLoadMemValue32(psHWPerfDataMemDesc,
1720                                                         (size_t)&(psHWPerfInitBlkData->bValid) - (size_t)(psHWPerfInitDataInt),
1721                                                         psHWPerfInitBlkData->bValid,
1722                                                         PDUMP_FLAGS_CONTINUOUS);
1723
1724                         psHWPerfInitBlkData->bEnabled = IMG_FALSE;
1725                         SRVINITPDumpComment(hServices, "bEnabled: Set to 0x1 if the block needs to be enabled during playback. ");
1726                         DevmemPDumpLoadMemValue32(psHWPerfDataMemDesc,
1727                                                         (size_t)&(psHWPerfInitBlkData->bEnabled) - (size_t)(psHWPerfInitDataInt),
1728                                                         psHWPerfInitBlkData->bEnabled,
1729                                                         PDUMP_FLAGS_CONTINUOUS);
1730
1731                         psHWPerfInitBlkData->eBlockID = ui32BlockID;
1732                         SRVINITPDumpComment(hServices, "eBlockID: The Block ID for the layout block. See RGX_HWPERF_CNTBLK_ID for further information.");
1733                         DevmemPDumpLoadMemValue32(psHWPerfDataMemDesc,
1734                                                         (size_t)&(psHWPerfInitBlkData->eBlockID) - (size_t)(psHWPerfInitDataInt),
1735                                                         psHWPerfInitBlkData->eBlockID,
1736                                                         PDUMP_FLAGS_CONTINUOUS);
1737
1738                         psHWPerfInitBlkData->uiCounterMask = 0x00;
1739                         SRVINITPDumpComment(hServices, "uiCounterMask: Bitmask for selecting the counters that need to be configured.(Bit 0 - counter0, bit 1 - counter1 and so on. ");
1740                         DevmemPDumpLoadMemValue32(psHWPerfDataMemDesc,
1741                                                         (size_t)&(psHWPerfInitBlkData->uiCounterMask) - (size_t)(psHWPerfInitDataInt),
1742                                                         psHWPerfInitBlkData->uiCounterMask,
1743                                                         PDUMP_FLAGS_CONTINUOUS);
1744
1745                         for(ui32CounterIdx = RGX_CNTBLK_COUNTER0_ID; ui32CounterIdx < psBlkTypeDesc->uiNumCounters; ui32CounterIdx++)
1746                         {
1747                                 psHWPerfInitBlkData->aui64CounterCfg[ui32CounterIdx] = IMG_UINT64_C(0x0000000000000000);
1748
1749                                 SRVINITPDumpComment(hServices, "%s_COUNTER_%d", psBlkTypeDesc->pszBlockNameComment,ui32CounterIdx);
1750                                 DevmemPDumpLoadMemValue64(psHWPerfDataMemDesc,
1751                                                         (size_t)&(psHWPerfInitBlkData->aui64CounterCfg[ui32CounterIdx]) - (size_t)(psHWPerfInitDataInt),
1752                                                         psHWPerfInitBlkData->aui64CounterCfg[ui32CounterIdx],
1753                                                         PDUMP_FLAGS_CONTINUOUS);
1754
1755                         }
1756                 }
1757         }
1758 }
1759 /*!
1760 *******************************************************************************
1761
1762  @Function      InitialiseCustomCounters
1763
1764  @Description
1765
1766  Initialisation of custom counters and dumping them out to pdump, so that they can be modified at a later point.
1767
1768  @Input hServices
1769
1770  @Input psHWPerfDataMemDesc
1771
1772  @Return  void
1773
1774 ******************************************************************************/
1775
1776 static void InitialiseCustomCounters(SHARED_DEV_CONNECTION hServices, DEVMEM_MEMDESC *psHWPerfDataMemDesc)
1777 {
1778         IMG_UINT32 ui32CustomBlock, ui32CounterID;
1779
1780         SRVINITPDumpComment(hServices, "ui32SelectedCountersBlockMask - The Bitmask of the custom counters that are to be selected");
1781         DevmemPDumpLoadMemValue32(psHWPerfDataMemDesc,
1782                                                 offsetof(RGXFWIF_HWPERF_CTL, ui32SelectedCountersBlockMask),
1783                                                 0,
1784                                                 PDUMP_FLAGS_CONTINUOUS);
1785
1786         for( ui32CustomBlock = 0; ui32CustomBlock < RGX_HWPERF_MAX_CUSTOM_BLKS; ui32CustomBlock++ )
1787         {
1788                 /*
1789                  * Some compilers cannot cope with the use of offsetof() below - the specific problem being the use of
1790                  * a non-const variable in the expression, which it needs to be const. Typical compiler error produced is
1791                  * "expression must have a constant value".
1792                  */
1793                 const IMG_DEVMEM_OFFSET_T uiOffsetOfCustomBlockSelectedCounters
1794                 = (IMG_DEVMEM_OFFSET_T)(uintptr_t)&(((RGXFWIF_HWPERF_CTL *)0)->SelCntr[ui32CustomBlock].ui32NumSelectedCounters);
1795
1796                 SRVINITPDumpComment(hServices, "ui32NumSelectedCounters - The Number of counters selected for this Custom Block: %d",ui32CustomBlock );
1797                 DevmemPDumpLoadMemValue32(psHWPerfDataMemDesc,
1798                                         uiOffsetOfCustomBlockSelectedCounters,
1799                                         0,
1800                                         PDUMP_FLAGS_CONTINUOUS);
1801
1802                 for(ui32CounterID = 0; ui32CounterID < RGX_HWPERF_MAX_CUSTOM_CNTRS; ui32CounterID++ )
1803                 {
1804                         const IMG_DEVMEM_OFFSET_T uiOffsetOfCustomBlockSelectedCounterIDs
1805                         = (IMG_DEVMEM_OFFSET_T)(uintptr_t)&(((RGXFWIF_HWPERF_CTL *)0)->SelCntr[ui32CustomBlock].aui32SelectedCountersIDs[ui32CounterID]);
1806
1807                         SRVINITPDumpComment(hServices, "CUSTOMBLK_%d_COUNTERID_%d",ui32CustomBlock, ui32CounterID);
1808                         DevmemPDumpLoadMemValue32(psHWPerfDataMemDesc,
1809                                         uiOffsetOfCustomBlockSelectedCounterIDs,
1810                                         0,
1811                                         PDUMP_FLAGS_CONTINUOUS);
1812                 }
1813         }
1814 }
1815
1816 /*!
1817 *******************************************************************************
1818
1819  @Function     InitialiseAllCounters
1820
1821  @Description  Initialise HWPerf and custom counters
1822
1823  @Input        hServices      : Services connection
1824  @Input        hHWPerfDataPMR : HWPerf control PMR handle
1825
1826  @Return       PVRSRV_ERROR
1827
1828 ******************************************************************************/
1829 static PVRSRV_ERROR InitialiseAllCounters(SHARED_DEV_CONNECTION hServices,
1830                                           IMG_HANDLE hHWPerfDataPMR)
1831 {
1832         RGXFWIF_HWPERF_CTL *psHWPerfInitData;
1833         DEVMEM_MEMDESC *psHWPerfDataMemDesc;
1834         PVRSRV_ERROR eError;
1835
1836         eError = AcquireHostData(hServices,
1837                                  hHWPerfDataPMR,
1838                                  &psHWPerfDataMemDesc,
1839                                  (void **)&psHWPerfInitData);
1840
1841
1842         if (eError != PVRSRV_OK)
1843         {
1844                 PVR_LOGG_IF_ERROR(eError, "DevmemAcquireCpuVirtAddr", failHWPerfCountersMemDescAqCpuVirt);
1845         }
1846
1847         InitialiseHWPerfCounters(hServices, psHWPerfDataMemDesc, psHWPerfInitData);
1848         InitialiseCustomCounters(hServices, psHWPerfDataMemDesc);
1849
1850 failHWPerfCountersMemDescAqCpuVirt:
1851         ReleaseHostData(psHWPerfDataMemDesc);
1852
1853         return eError;
1854 }
1855 #endif /* PDUMP */
1856
1857 static void
1858 _ParseHTBAppHints(SHARED_DEV_CONNECTION hServices)
1859 {
1860         PVRSRV_ERROR eError;
1861         void * pvParamState = NULL;
1862         IMG_UINT32 ui32LogType;
1863         IMG_BOOL bAnyLogGroupConfigured;
1864
1865         IMG_CHAR * szBufferName = "PVRHTBuffer";
1866         IMG_UINT32 ui32BufferSize;
1867         HTB_OPMODE_CTRL eOpMode;
1868
1869         /* Services initialisation parameters */
1870         pvParamState = SrvInitParamOpen();
1871
1872         SrvInitParamGetUINT32BitField(pvParamState, EnableHTBLogGroup, ui32LogType);
1873         bAnyLogGroupConfigured = ui32LogType ? IMG_TRUE: IMG_FALSE;
1874         SrvInitParamGetUINT32List(pvParamState, HTBOperationMode, eOpMode);
1875         SrvInitParamGetUINT32(pvParamState, HTBufferSize, ui32BufferSize);
1876
1877         eError = HTBConfigure(hServices, szBufferName, ui32BufferSize);
1878         PVR_LOGG_IF_ERROR(eError, "PVRSRVHTBConfigure", cleanup);
1879
1880         if (bAnyLogGroupConfigured)
1881         {
1882                 eError = HTBControl(hServices, 1, &ui32LogType, 0, 0, HTB_LOGMODE_ALLPID, eOpMode);
1883                 PVR_LOGG_IF_ERROR(eError, "PVRSRVHTBControl", cleanup);
1884         }
1885
1886 cleanup:
1887         SrvInitParamClose(pvParamState);
1888 }
1889
1890 #if defined(PDUMP) && defined(SUPPORT_KERNEL_SRVINIT) && defined(__KERNEL__)
1891 static void RGXInitFWSigRegisters(PVRSRV_RGXDEV_INFO *psDevInfo)
1892 {
1893         IMG_UINT32      ui32PhantomCnt = 0;
1894
1895         if (psDevInfo->sDevFeatureCfg.ui64Features & RGX_FEATURE_CLUSTER_GROUPING_BIT_MASK)
1896         {
1897                 ui32PhantomCnt = RGX_GET_NUM_PHANTOMS(psDevInfo->sDevFeatureCfg.ui32NumClusters) - 1;
1898         }
1899
1900         /*Initialise the TA related signature registers */
1901         if(0 == gui32TASigRegCount)
1902         {
1903                 if(psDevInfo->sDevFeatureCfg.ui64Features & RGX_FEATURE_SCALABLE_VDM_GPP_BIT_MASK)
1904                 {
1905                         asTASigRegList[gui32TASigRegCount++] =  (RGXFW_REGISTER_LIST){RGX_CR_USC_UVB_CHECKSUM, RGX_CR_BLACKPEARL_INDIRECT,0, ui32PhantomCnt};
1906                 }else
1907                 {
1908                         asTASigRegList[gui32TASigRegCount++] =  (RGXFW_REGISTER_LIST){RGX_CR_USC_UVS0_CHECKSUM, 0, 0, 0};
1909                         asTASigRegList[gui32TASigRegCount++] =  (RGXFW_REGISTER_LIST){RGX_CR_USC_UVS1_CHECKSUM, 0, 0, 0};
1910                         asTASigRegList[gui32TASigRegCount++] =  (RGXFW_REGISTER_LIST){RGX_CR_USC_UVS2_CHECKSUM, 0, 0, 0};
1911                         asTASigRegList[gui32TASigRegCount++] =  (RGXFW_REGISTER_LIST){RGX_CR_USC_UVS3_CHECKSUM, 0, 0, 0};
1912                         asTASigRegList[gui32TASigRegCount++] =  (RGXFW_REGISTER_LIST){RGX_CR_USC_UVS4_CHECKSUM, 0, 0, 0};
1913                         asTASigRegList[gui32TASigRegCount++] =  (RGXFW_REGISTER_LIST){RGX_CR_USC_UVS5_CHECKSUM, 0, 0, 0};
1914                 }
1915
1916                 if(psDevInfo->sDevFeatureCfg.ui64Features & RGX_FEATURE_SCALABLE_TE_ARCH_BIT_MASK)
1917                 {
1918                         if(psDevInfo->sDevFeatureCfg.ui64Features & RGX_FEATURE_SCALABLE_VDM_GPP_BIT_MASK)
1919                         {
1920                                 asTASigRegList[gui32TASigRegCount++] =  (RGXFW_REGISTER_LIST){RGX_CR_PPP_CLIP_CHECKSUM, RGX_CR_BLACKPEARL_INDIRECT,0, ui32PhantomCnt};
1921                         }else
1922                         {
1923                                 asTASigRegList[gui32TASigRegCount++] =  (RGXFW_REGISTER_LIST){RGX_CR_PPP, 0, 0, 0};
1924                         }
1925                         asTASigRegList[gui32TASigRegCount++] =  (RGXFW_REGISTER_LIST){RGX_CR_TE_CHECKSUM,0, 0, 0};
1926                 }else
1927                 {
1928                         asTASigRegList[gui32TASigRegCount++] =  (RGXFW_REGISTER_LIST){RGX_CR_PPP_SIGNATURE, 0, 0, 0};
1929                         asTASigRegList[gui32TASigRegCount++] =  (RGXFW_REGISTER_LIST){RGX_CR_TE_SIGNATURE, 0, 0, 0};
1930                 }
1931
1932                 asTASigRegList[gui32TASigRegCount++] = (RGXFW_REGISTER_LIST){RGX_CR_VCE_CHECKSUM, 0, 0, 0};
1933
1934                 if(0 == (psDevInfo->sDevFeatureCfg.ui64Features & RGX_FEATURE_PDS_PER_DUST_BIT_MASK))
1935                 {
1936                         asTASigRegList[gui32TASigRegCount++] =  (RGXFW_REGISTER_LIST){RGX_CR_PDS_DOUTM_STM_SIGNATURE,0, 0, 0};
1937                 }
1938         }
1939
1940         if(0 == gui323DSigRegCount)
1941         {
1942                 /* List of 3D signature and checksum register addresses */
1943                 if(0 == (psDevInfo->sDevFeatureCfg.ui64Features & RGX_FEATURE_S7_TOP_INFRASTRUCTURE_BIT_MASK))
1944                 {
1945                         as3DSigRegList[gui323DSigRegCount++] = (RGXFW_REGISTER_LIST){RGX_CR_ISP_PDS_CHECKSUM,                   0,                                                      0, 0};
1946                         as3DSigRegList[gui323DSigRegCount++] = (RGXFW_REGISTER_LIST){RGX_CR_ISP_TPF_CHECKSUM,                   0,                                                      0, 0};
1947                         as3DSigRegList[gui323DSigRegCount++] = (RGXFW_REGISTER_LIST){RGX_CR_TFPU_PLANE0_CHECKSUM,               0,                                                      0, 0};
1948                         as3DSigRegList[gui323DSigRegCount++] = (RGXFW_REGISTER_LIST){RGX_CR_TFPU_PLANE1_CHECKSUM,               0,                                                      0, 0};
1949                         as3DSigRegList[gui323DSigRegCount++] = (RGXFW_REGISTER_LIST){RGX_CR_PBE_CHECKSUM,                               0,                                                      0, 0};
1950                         as3DSigRegList[gui323DSigRegCount++] = (RGXFW_REGISTER_LIST){RGX_CR_IFPU_ISP_CHECKSUM,                  0,                                                      0, 0};
1951                 }else
1952                 {
1953                         as3DSigRegList[gui323DSigRegCount++] = (RGXFW_REGISTER_LIST){RGX_CR_ISP_PDS_CHECKSUM,                   RGX_CR_BLACKPEARL_INDIRECT,     0, ui32PhantomCnt};
1954                         as3DSigRegList[gui323DSigRegCount++] = (RGXFW_REGISTER_LIST){RGX_CR_ISP_TPF_CHECKSUM,                   RGX_CR_BLACKPEARL_INDIRECT,     0, ui32PhantomCnt};
1955                         as3DSigRegList[gui323DSigRegCount++] = (RGXFW_REGISTER_LIST){RGX_CR_TFPU_PLANE0_CHECKSUM,               RGX_CR_BLACKPEARL_INDIRECT,     0, ui32PhantomCnt};
1956                         as3DSigRegList[gui323DSigRegCount++] = (RGXFW_REGISTER_LIST){RGX_CR_TFPU_PLANE1_CHECKSUM,               RGX_CR_BLACKPEARL_INDIRECT,     0, ui32PhantomCnt};
1957                         as3DSigRegList[gui323DSigRegCount++] = (RGXFW_REGISTER_LIST){RGX_CR_PBE_CHECKSUM,                               RGX_CR_PBE_INDIRECT,            0, psDevInfo->sDevFeatureCfg.ui32NumClusters-1};
1958                         as3DSigRegList[gui323DSigRegCount++] = (RGXFW_REGISTER_LIST){RGX_CR_IFPU_ISP_CHECKSUM,                  RGX_CR_BLACKPEARL_INDIRECT,     0, ui32PhantomCnt};
1959                 };
1960
1961         }
1962
1963 }
1964 #endif
1965
1966 /*!
1967 *******************************************************************************
1968
1969  @Function      RGXInit
1970
1971  @Description
1972
1973  RGX Initialisation
1974
1975  @Input hServices
1976
1977  @Return   PVRSRV_ERROR
1978
1979 ******************************************************************************/
1980 IMG_INTERNAL
1981 PVRSRV_ERROR RGXInit(SHARED_DEV_CONNECTION hServices)
1982 {
1983         PVRSRV_ERROR eError;
1984         RGXFWIF_COMPCHECKS_BVNC_DECLARE_AND_INIT(sBVNC);
1985
1986         /* Services initialisation parameters */
1987         RGX_SRVINIT_APPHINTS sApphints = {0};
1988         IMG_UINT32 ui32DeviceFlags;
1989         IMG_UINT64      ui64ErnsBrns = 0, ui64Features = 0;
1990
1991         /* Server scripts */
1992         RGX_SCRIPT_BUILD sDbgInitScript = {RGX_MAX_DEBUG_COMMANDS,  0, IMG_FALSE, asDbgCommands};
1993
1994         /* FW allocations handles */
1995         IMG_HANDLE hFWCodePMR;
1996         IMG_HANDLE hFWDataPMR;
1997         IMG_HANDLE hFWCorememPMR;
1998
1999         /* HWPerf Ctl allocation handle */
2000         IMG_HANDLE hHWPerfDataPMR;
2001
2002 #if defined(SUPPORT_KERNEL_SRVINIT)
2003         PVRSRV_DEVICE_NODE *psDeviceNode = (PVRSRV_DEVICE_NODE *)hServices;
2004         PVRSRV_RGXDEV_INFO *psDevInfo = (PVRSRV_RGXDEV_INFO *)psDeviceNode->pvDevice;
2005
2006         IMG_CHAR sV[RGXFWIF_COMPCHECKS_BVNC_V_LEN_MAX];
2007
2008         OSSNPrintf(sV, sizeof(sV), "%d", psDevInfo->sDevFeatureCfg.ui32V);
2009         /*
2010          * FIXME:
2011          * Is this check redundant for the kernel mode version of srvinit?
2012          * How do we check the user mode BVNC in this case?
2013          */
2014         rgx_bvnc_packed(&sBVNC.ui64BNC, sBVNC.aszV, sBVNC.ui32VLenMax, psDevInfo->sDevFeatureCfg.ui32B, \
2015                                                         sV,     \
2016                                                         psDevInfo->sDevFeatureCfg.ui32N, psDevInfo->sDevFeatureCfg.ui32C);
2017
2018
2019         ui64ErnsBrns = psDevInfo->sDevFeatureCfg.ui64ErnsBrns;
2020         ui64Features = psDevInfo->sDevFeatureCfg.ui64Features;
2021 #else
2022         rgx_bvnc_packed(&sBVNC.ui64BNC, sBVNC.aszV, sBVNC.ui32VLenMax, RGX_BVNC_B, RGX_BVNC_V_ST, RGX_BVNC_N, RGX_BVNC_C);
2023 #endif
2024
2025         /* Services initialisation parameters */
2026         _ParseHTBAppHints(hServices);
2027         GetApphints(&sApphints, ui64ErnsBrns, ui64Features);
2028         GetDeviceFlags(&sApphints, &ui32DeviceFlags);
2029
2030 #if defined(SUPPORT_GPUVIRT_VALIDATION)
2031 {
2032         IMG_UINT    uiOS, uiRegion;
2033         IMG_UINT32  aui32Buffer[GPUVIRT_VALIDATION_NUM_OS * GPUVIRT_VALIDATION_NUM_REGIONS * 2]; /* The final 2 is 1 for Min and 1 for Max */
2034         IMG_UINT32  ui32Counter = 0;
2035
2036         for (uiOS = 0; uiOS < GPUVIRT_VALIDATION_NUM_OS; uiOS++)
2037         {
2038                 for (uiRegion = 0; uiRegion < GPUVIRT_VALIDATION_NUM_REGIONS; uiRegion++)
2039                 {
2040                         aui32Buffer[ui32Counter++] = sApphints.aui32OSidMin[uiOS][uiRegion];
2041                         aui32Buffer[ui32Counter++] = sApphints.aui32OSidMax[uiOS][uiRegion];
2042                 }
2043         }
2044
2045         BridgeGPUVIRTPopulateLMASubArenas(hServices, ui32Counter, aui32Buffer, sApphints.bEnableTrustedDeviceAceConfig);
2046 }
2047 #endif
2048
2049
2050         eError = InitFirmware(hServices,
2051                               &sApphints,
2052                               &sBVNC,
2053                               &hFWCodePMR,
2054                               &hFWDataPMR,
2055                               &hFWCorememPMR,
2056                               &hHWPerfDataPMR);
2057         if (eError != PVRSRV_OK)
2058         {
2059                 PVR_DPF((PVR_DBG_ERROR, "RGXInit: InitFirmware failed (%d)", eError));
2060                 goto cleanup;
2061         }
2062
2063         /*
2064          * Build Debug info script
2065          */
2066         sDbgInitScript.psCommands = asDbgCommands;
2067
2068 #if defined(SUPPORT_KERNEL_SRVINIT)
2069         if(!PrepareDebugScript(&sDbgInitScript, sApphints.eFirmwarePerf != FW_PERF_CONF_NONE, psDevInfo))
2070 #else
2071         if(!PrepareDebugScript(&sDbgInitScript, sApphints.eFirmwarePerf != FW_PERF_CONF_NONE, NULL))
2072 #endif
2073         {
2074                 PVR_DPF((PVR_DBG_ERROR, "RGXInit: Run out of mem for the dbg commands"));
2075         }
2076
2077         /* finish the script */
2078         if(!ScriptHalt(&sDbgInitScript))
2079         {
2080                 PVR_DPF((PVR_DBG_ERROR, "RGXInit: Run out of mem for the terminating dbg script"));
2081         }
2082
2083 #if defined(PDUMP)
2084         eError = InitialiseAllCounters(hServices, hHWPerfDataPMR);
2085         if (eError != PVRSRV_OK)
2086         {
2087                 PVR_DPF((PVR_DBG_ERROR, "RGXInit: InitialiseAllCounters failed (%d)", eError));
2088                 goto cleanup;
2089         }
2090 #endif
2091
2092         /*
2093          * Perform second stage of RGX initialisation
2094          */
2095         eError = BridgeRGXInitDevPart2(hServices,
2096                                        sDbgInitScript.psCommands,
2097                                        ui32DeviceFlags,
2098                                        sApphints.ui32HWPerfHostBufSize,
2099                                        sApphints.ui32HWPerfHostFilter,
2100                                        sApphints.eRGXActivePMConf,
2101                                        hFWCodePMR,
2102                                        hFWDataPMR,
2103                                        hFWCorememPMR,
2104                                        hHWPerfDataPMR);
2105
2106         if (eError != PVRSRV_OK)
2107         {
2108                 PVR_DPF((PVR_DBG_ERROR, "RGXInit: BridgeRGXInitDevPart2 failed (%d)", eError));
2109                 goto cleanup;
2110         }
2111
2112 #if defined(SUPPORT_KERNEL_SRVINIT) && defined(SUPPORT_VALIDATION)
2113         PVRSRVAppHintDumpState();
2114 #endif
2115
2116 #if defined(PDUMP)
2117         /*
2118          * Dump the list of signature registers
2119          */
2120         {
2121                 IMG_UINT32 i;
2122                 IMG_UINT32 ui32TASigRegCount = 0, ui323DSigRegCount= 0;
2123                 IMG_BOOL        bRayTracing = IMG_FALSE;
2124
2125 #if defined(SUPPORT_KERNEL_SRVINIT) && defined(__KERNEL__)
2126                 RGXInitFWSigRegisters(psDevInfo);
2127                 ui32TASigRegCount = gui32TASigRegCount;
2128                 ui323DSigRegCount = gui323DSigRegCount;
2129                 if(psDevInfo->sDevFeatureCfg.ui64Features & RGX_FEATURE_RAY_TRACING_BIT_MASK)
2130                 {
2131                         bRayTracing = IMG_TRUE;
2132                 }
2133 #if defined(DEBUG)
2134                 if (gui32TASigRegCount > SIG_REG_TA_MAX_COUNT)
2135                 {
2136                         PVR_DPF((PVR_DBG_ERROR, "%s: TA signature registers max count exceeded",__func__));
2137                         PVR_ASSERT(0);
2138                 }
2139                 if (gui323DSigRegCount > SIG_REG_3D_MAX_COUNT)
2140                 {
2141                         PVR_DPF((PVR_DBG_ERROR, "%s: 3D signature registers max count exceeded",__func__));
2142                         PVR_ASSERT(0);
2143                 }
2144 #endif
2145 #else
2146                 ui32TASigRegCount = sizeof(asTASigRegList)/sizeof(RGXFW_REGISTER_LIST);
2147                 ui323DSigRegCount = sizeof(as3DSigRegList)/sizeof(RGXFW_REGISTER_LIST);
2148 #if defined(RGX_FEATURE_RAY_TRACING)
2149                 bRayTracing = IMG_TRUE;
2150 #endif
2151 #endif
2152
2153
2154
2155                 SRVINITPDumpComment(hServices, "Signature TA registers: ");
2156                 for (i = 0; i < ui32TASigRegCount; i++)
2157                 {
2158                         if (asTASigRegList[i].ui16IndirectRegNum != 0)
2159                         {
2160                                 SRVINITPDumpComment(hServices, " * 0x%8.8X (indirect via 0x%8.8X %d to %d)",
2161                                               asTASigRegList[i].ui16RegNum, asTASigRegList[i].ui16IndirectRegNum,
2162                                               asTASigRegList[i].ui16IndirectStartVal, asTASigRegList[i].ui16IndirectEndVal);
2163                         }
2164                         else
2165                         {
2166                                 SRVINITPDumpComment(hServices, " * 0x%8.8X", asTASigRegList[i].ui16RegNum);
2167                         }
2168                 }
2169
2170                 SRVINITPDumpComment(hServices, "Signature 3D registers: ");
2171                 for (i = 0; i < ui323DSigRegCount; i++)
2172                 {
2173                         if (as3DSigRegList[i].ui16IndirectRegNum != 0)
2174                         {
2175                                 SRVINITPDumpComment(hServices, " * 0x%8.8X (indirect via 0x%8.8X %d to %d)",
2176                                               as3DSigRegList[i].ui16RegNum, as3DSigRegList[i].ui16IndirectRegNum,
2177                                               as3DSigRegList[i].ui16IndirectStartVal, as3DSigRegList[i].ui16IndirectEndVal);
2178                         }
2179                         else
2180                         {
2181                                 SRVINITPDumpComment(hServices, " * 0x%8.8X", as3DSigRegList[i].ui16RegNum);
2182                         }
2183                 }
2184
2185                 if(bRayTracing)
2186                 {
2187 #if defined (RGX_FEATURE_RAY_TRACING) || defined(SUPPORT_KERNEL_SRVINIT)
2188                         SRVINITPDumpComment(hServices, "Signature RTU registers: ");
2189                         for (i = 0; i < sizeof(asRTUSigRegList)/sizeof(RGXFW_REGISTER_LIST); i++)
2190                         {
2191                                 if (asRTUSigRegList[i].ui16IndirectRegNum != 0)
2192                                 {
2193                                         SRVINITPDumpComment(hServices, " * 0x%8.8X (indirect via 0x%8.8X %d to %d)",
2194                                                                   asRTUSigRegList[i].ui16RegNum, asRTUSigRegList[i].ui16IndirectRegNum,
2195                                                                   asRTUSigRegList[i].ui16IndirectStartVal, asRTUSigRegList[i].ui16IndirectEndVal);
2196                                 }
2197                                 else
2198                                 {
2199                                         SRVINITPDumpComment(hServices, " * 0x%8.8X", asRTUSigRegList[i].ui16RegNum);
2200                                 }
2201                         }
2202
2203                         SRVINITPDumpComment(hServices, "Signature SHG registers: ");
2204                         for (i = 0; i < sizeof(asSHGSigRegList)/sizeof(RGXFW_REGISTER_LIST); i++)
2205                         {
2206                                 if (asSHGSigRegList[i].ui16IndirectRegNum != 0)
2207                                 {
2208                                         SRVINITPDumpComment(hServices, " * 0x%8.8X (indirect via 0x%8.8X %d to %d)",
2209                                                                   asSHGSigRegList[i].ui16RegNum, asSHGSigRegList[i].ui16IndirectRegNum,
2210                                                                   asSHGSigRegList[i].ui16IndirectStartVal, asSHGSigRegList[i].ui16IndirectEndVal);
2211                                 }
2212                                 else
2213                                 {
2214                                         SRVINITPDumpComment(hServices, " * 0x%8.8X", asSHGSigRegList[i].ui16RegNum);
2215                                 }
2216                         }
2217 #endif
2218                 }
2219
2220         }
2221 #endif  /* !defined(SUPPORT_KERNEL_SRVINIT) && defined(PDUMP) */
2222
2223         eError = PVRSRV_OK;
2224
2225 cleanup:
2226         return eError;
2227 }
2228
2229 /******************************************************************************
2230  End of file (rgxsrvinit.c)
2231 ******************************************************************************/