drivers/staging/imx-drm/imx-hdmi.c

   1 /*
   2  * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * SH-Mobile High-Definition Multimedia Interface (HDMI) driver
  10  * for SLISHDMI13T and SLIPHDMIT IP cores
  11  *
  12  * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
  13  */
  14
  15 #include <linux/irq.h>
  16 #include <linux/delay.h>
  17 #include <linux/err.h>
  18 #include <linux/clk.h>
  19 #include <linux/hdmi.h>
  20 #include <linux/regmap.h>
  21 #include <linux/mfd/syscon.h>
  22 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
  23 #include <linux/of_device.h>
  24
  25 #include <drm/drmP.h>
  26 #include <drm/drm_crtc_helper.h>
  27 #include <drm/drm_edid.h>
  28 #include <drm/drm_encoder_slave.h>
  29
  30 #include "ipu-v3/imx-ipu-v3.h"
  31 #include "imx-hdmi.h"
  32 #include "imx-drm.h"
  33
  34 #define HDMI_EDID_LEN           512
  35
  36 #define RGB                     0
  37 #define YCBCR444                1
  38 #define YCBCR422_16BITS         2
  39 #define YCBCR422_8BITS          3
  40 #define XVYCC444                4
  41
  42 enum hdmi_datamap {
  43         RGB444_8B = 0x01,
  44         RGB444_10B = 0x03,
  45         RGB444_12B = 0x05,
  46         RGB444_16B = 0x07,
  47         YCbCr444_8B = 0x09,
  48         YCbCr444_10B = 0x0B,
  49         YCbCr444_12B = 0x0D,
  50         YCbCr444_16B = 0x0F,
  51         YCbCr422_8B = 0x16,
  52         YCbCr422_10B = 0x14,
  53         YCbCr422_12B = 0x12,
  54 };
  55
  56 enum imx_hdmi_devtype {
  57         IMX6Q_HDMI,
  58         IMX6DL_HDMI,
  59 };
  60
  61 static const u16 csc_coeff_default[3][4] = {
  62         { 0x2000, 0x0000, 0x0000, 0x0000 },
  63         { 0x0000, 0x2000, 0x0000, 0x0000 },
  64         { 0x0000, 0x0000, 0x2000, 0x0000 }
  65 };
  66
  67 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
  68         { 0x2000, 0x6926, 0x74fd, 0x010e },
  69         { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
  70         { 0x2000, 0x0000, 0x38b4, 0x7e3b }
  71 };
  72
  73 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
  74         { 0x2000, 0x7106, 0x7a02, 0x00a7 },
  75         { 0x2000, 0x3264, 0x0000, 0x7e6d },
  76         { 0x2000, 0x0000, 0x3b61, 0x7e25 }
  77 };
  78
  79 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
  80         { 0x2591, 0x1322, 0x074b, 0x0000 },
  81         { 0x6535, 0x2000, 0x7acc, 0x0200 },
  82         { 0x6acd, 0x7534, 0x2000, 0x0200 }
  83 };
  84
  85 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
  86         { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
  87         { 0x62f0, 0x2000, 0x7d11, 0x0200 },
  88         { 0x6756, 0x78ab, 0x2000, 0x0200 }
  89 };
  90
  91 struct hdmi_vmode {
  92         bool mdvi;
  93         bool mhsyncpolarity;
  94         bool mvsyncpolarity;
  95         bool minterlaced;
  96         bool mdataenablepolarity;
  97
  98         unsigned int mpixelclock;
  99         unsigned int mpixelrepetitioninput;
 100         unsigned int mpixelrepetitionoutput;
 101 };
 102
 103 struct hdmi_data_info {
 104         unsigned int enc_in_format;
 105         unsigned int enc_out_format;
 106         unsigned int enc_color_depth;
 107         unsigned int colorimetry;
 108         unsigned int pix_repet_factor;
 109         unsigned int hdcp_enable;
 110         struct hdmi_vmode video_mode;
 111 };
 112
 113 struct imx_hdmi {
 114         struct drm_connector connector;
 115         struct imx_drm_connector *imx_drm_connector;
 116         struct drm_encoder encoder;
 117         struct imx_drm_encoder *imx_drm_encoder;
 118
 119         enum imx_hdmi_devtype dev_type;
 120         struct device *dev;
 121         struct clk *isfr_clk;
 122         struct clk *iahb_clk;
 123
 124         struct hdmi_data_info hdmi_data;
 125         int vic;
 126
 127         u8 edid[HDMI_EDID_LEN];
 128         bool cable_plugin;
 129
 130         bool phy_enabled;
 131         struct drm_display_mode previous_mode;
 132
 133         struct regmap *regmap;
 134         struct i2c_adapter *ddc;
 135         void __iomem *regs;
 136
 137         unsigned int sample_rate;
 138         int ratio;
 139 };
 140
 141 static void imx_hdmi_set_ipu_di_mux(struct imx_hdmi *hdmi, int ipu_di)
 142 {
 143         regmap_update_bits(hdmi->regmap, IOMUXC_GPR3,
 144                            IMX6Q_GPR3_HDMI_MUX_CTL_MASK,
 145                            ipu_di << IMX6Q_GPR3_HDMI_MUX_CTL_SHIFT);
 146 }
 147
 148 static inline void hdmi_writeb(struct imx_hdmi *hdmi, u8 val, int offset)
 149 {
 150         writeb(val, hdmi->regs + offset);
 151 }
 152
 153 static inline u8 hdmi_readb(struct imx_hdmi *hdmi, int offset)
 154 {
 155         return readb(hdmi->regs + offset);
 156 }
 157
 158 static void hdmi_modb(struct imx_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
 159 {
 160         u8 val = hdmi_readb(hdmi, reg) & ~mask;
 161         val |= data & mask;
 162         hdmi_writeb(hdmi, val, reg);
 163 }
 164
 165 static void hdmi_mask_writeb(struct imx_hdmi *hdmi, u8 data, unsigned int reg,
 166                       u8 shift, u8 mask)
 167 {
 168         hdmi_modb(hdmi, data << shift, mask, reg);
 169 }
 170
 171 static void hdmi_set_clock_regenerator_n(struct imx_hdmi *hdmi,
 172                                          unsigned int value)
 173 {
 174         hdmi_writeb(hdmi, value & 0xff, HDMI_AUD_N1);
 175         hdmi_writeb(hdmi, (value >> 8) & 0xff, HDMI_AUD_N2);
 176         hdmi_writeb(hdmi, (value >> 16) & 0x0f, HDMI_AUD_N3);
 177
 178         /* nshift factor = 0 */
 179         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
 180 }
 181
 182 static void hdmi_regenerate_cts(struct imx_hdmi *hdmi, unsigned int cts)
 183 {
 184         /* Must be set/cleared first */
 185         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 186
 187         hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
 188         hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
 189         hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
 190                     HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 191 }
 192
 193 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk,
 194                                    unsigned int ratio)
 195 {
 196         unsigned int n = (128 * freq) / 1000;
 197
 198         switch (freq) {
 199         case 32000:
 200                 if (pixel_clk == 25170000)
 201                         n = (ratio == 150) ? 9152 : 4576;
 202                 else if (pixel_clk == 27020000)
 203                         n = (ratio == 150) ? 8192 : 4096;
 204                 else if (pixel_clk == 74170000 || pixel_clk == 148350000)
 205                         n = 11648;
 206                 else
 207                         n = 4096;
 208                 break;
 209
 210         case 44100:
 211                 if (pixel_clk == 25170000)
 212                         n = 7007;
 213                 else if (pixel_clk == 74170000)
 214                         n = 17836;
 215                 else if (pixel_clk == 148350000)
 216                         n = (ratio == 150) ? 17836 : 8918;
 217                 else
 218                         n = 6272;
 219                 break;
 220
 221         case 48000:
 222                 if (pixel_clk == 25170000)
 223                         n = (ratio == 150) ? 9152 : 6864;
 224                 else if (pixel_clk == 27020000)
 225                         n = (ratio == 150) ? 8192 : 6144;
 226                 else if (pixel_clk == 74170000)
 227                         n = 11648;
 228                 else if (pixel_clk == 148350000)
 229                         n = (ratio == 150) ? 11648 : 5824;
 230                 else
 231                         n = 6144;
 232                 break;
 233
 234         case 88200:
 235                 n = hdmi_compute_n(44100, pixel_clk, ratio) * 2;
 236                 break;
 237
 238         case 96000:
 239                 n = hdmi_compute_n(48000, pixel_clk, ratio) * 2;
 240                 break;
 241
 242         case 176400:
 243                 n = hdmi_compute_n(44100, pixel_clk, ratio) * 4;
 244                 break;
 245
 246         case 192000:
 247                 n = hdmi_compute_n(48000, pixel_clk, ratio) * 4;
 248                 break;
 249
 250         default:
 251                 break;
 252         }
 253
 254         return n;
 255 }
 256
 257 static unsigned int hdmi_compute_cts(unsigned int freq, unsigned long pixel_clk,
 258                                      unsigned int ratio)
 259 {
 260         unsigned int cts = 0;
 261
 262         pr_debug("%s: freq: %d pixel_clk: %ld ratio: %d\n", __func__, freq,
 263                  pixel_clk, ratio);
 264
 265         switch (freq) {
 266         case 32000:
 267                 if (pixel_clk == 297000000) {
 268                         cts = 222750;
 269                         break;
 270                 }
 271         case 48000:
 272         case 96000:
 273         case 192000:
 274                 switch (pixel_clk) {
 275                 case 25200000:
 276                 case 27000000:
 277                 case 54000000:
 278                 case 74250000:
 279                 case 148500000:
 280                         cts = pixel_clk / 1000;
 281                         break;
 282                 case 297000000:
 283                         cts = 247500;
 284                         break;
 285                 /*
 286                  * All other TMDS clocks are not supported by
 287                  * DWC_hdmi_tx. The TMDS clocks divided or
 288                  * multiplied by 1,001 coefficients are not
 289                  * supported.
 290                  */
 291                 default:
 292                         break;
 293                 }
 294                 break;
 295         case 44100:
 296         case 88200:
 297         case 176400:
 298                 switch (pixel_clk) {
 299                 case 25200000:
 300                         cts = 28000;
 301                         break;
 302                 case 27000000:
 303                         cts = 30000;
 304                         break;
 305                 case 54000000:
 306                         cts = 60000;
 307                         break;
 308                 case 74250000:
 309                         cts = 82500;
 310                         break;
 311                 case 148500000:
 312                         cts = 165000;
 313                         break;
 314                 case 297000000:
 315                         cts = 247500;
 316                         break;
 317                 default:
 318                         break;
 319                 }
 320                 break;
 321         default:
 322                 break;
 323         }
 324         if (ratio == 100)
 325                 return cts;
 326         else
 327                 return (cts * ratio) / 100;
 328 }
 329
 330 static void hdmi_set_clk_regenerator(struct imx_hdmi *hdmi,
 331         unsigned long pixel_clk)
 332 {
 333         unsigned int clk_n, clk_cts;
 334
 335         clk_n = hdmi_compute_n(hdmi->sample_rate, pixel_clk,
 336                                hdmi->ratio);
 337         clk_cts = hdmi_compute_cts(hdmi->sample_rate, pixel_clk,
 338                                    hdmi->ratio);
 339
 340         if (!clk_cts) {
 341                 dev_dbg(hdmi->dev, "%s: pixel clock not supported: %lu\n",
 342                          __func__, pixel_clk);
 343                 return;
 344         }
 345
 346         dev_dbg(hdmi->dev, "%s: samplerate=%d  ratio=%d  pixelclk=%lu  N=%d cts=%d\n",
 347                 __func__, hdmi->sample_rate, hdmi->ratio,
 348                 pixel_clk, clk_n, clk_cts);
 349
 350         hdmi_set_clock_regenerator_n(hdmi, clk_n);
 351         hdmi_regenerate_cts(hdmi, clk_cts);
 352 }
 353
 354 static void hdmi_init_clk_regenerator(struct imx_hdmi *hdmi)
 355 {
 356         hdmi_set_clk_regenerator(hdmi, 74250000);
 357 }
 358
 359 static void hdmi_clk_regenerator_update_pixel_clock(struct imx_hdmi *hdmi)
 360 {
 361         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock);
 362 }
 363
 364 /*
 365  * this submodule is responsible for the video data synchronization.
 366  * for example, for RGB 4:4:4 input, the data map is defined as
 367  *                      pin{47~40} <==> R[7:0]
 368  *                      pin{31~24} <==> G[7:0]
 369  *                      pin{15~8}  <==> B[7:0]
 370  */
 371 static void hdmi_video_sample(struct imx_hdmi *hdmi)
 372 {
 373         int color_format = 0;
 374         u8 val;
 375
 376         if (hdmi->hdmi_data.enc_in_format == RGB) {
 377                 if (hdmi->hdmi_data.enc_color_depth == 8)
 378                         color_format = 0x01;
 379                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 380                         color_format = 0x03;
 381                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 382                         color_format = 0x05;
 383                 else if (hdmi->hdmi_data.enc_color_depth == 16)
 384                         color_format = 0x07;
 385                 else
 386                         return;
 387         } else if (hdmi->hdmi_data.enc_in_format == YCBCR444) {
 388                 if (hdmi->hdmi_data.enc_color_depth == 8)
 389                         color_format = 0x09;
 390                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 391                         color_format = 0x0B;
 392                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 393                         color_format = 0x0D;
 394                 else if (hdmi->hdmi_data.enc_color_depth == 16)
 395                         color_format = 0x0F;
 396                 else
 397                         return;
 398         } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
 399                 if (hdmi->hdmi_data.enc_color_depth == 8)
 400                         color_format = 0x16;
 401                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 402                         color_format = 0x14;
 403                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 404                         color_format = 0x12;
 405                 else
 406                         return;
 407         }
 408
 409         val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
 410                 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
 411                 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
 412         hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
 413
 414         /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
 415         val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
 416                 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
 417                 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
 418         hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
 419         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
 420         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
 421         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
 422         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
 423         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
 424         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
 425 }
 426
 427 static int is_color_space_conversion(struct imx_hdmi *hdmi)
 428 {
 429         return (hdmi->hdmi_data.enc_in_format !=
 430                 hdmi->hdmi_data.enc_out_format);
 431 }
 432
 433 static int is_color_space_decimation(struct imx_hdmi *hdmi)
 434 {
 435         return ((hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS) &&
 436                 (hdmi->hdmi_data.enc_in_format == RGB ||
 437                 hdmi->hdmi_data.enc_in_format == YCBCR444));
 438 }
 439
 440 static int is_color_space_interpolation(struct imx_hdmi *hdmi)
 441 {
 442         return ((hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) &&
 443                 (hdmi->hdmi_data.enc_out_format == RGB ||
 444                 hdmi->hdmi_data.enc_out_format == YCBCR444));
 445 }
 446
 447 static void imx_hdmi_update_csc_coeffs(struct imx_hdmi *hdmi)
 448 {
 449         const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
 450         unsigned i;
 451         u32 csc_scale = 1;
 452
 453         if (is_color_space_conversion(hdmi)) {
 454                 if (hdmi->hdmi_data.enc_out_format == RGB) {
 455                         if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
 456                                 csc_coeff = &csc_coeff_rgb_out_eitu601;
 457                         else
 458                                 csc_coeff = &csc_coeff_rgb_out_eitu709;
 459                 } else if (hdmi->hdmi_data.enc_in_format == RGB) {
 460                         if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
 461                                 csc_coeff = &csc_coeff_rgb_in_eitu601;
 462                         else
 463                                 csc_coeff = &csc_coeff_rgb_in_eitu709;
 464                         csc_scale = 0;
 465                 }
 466         }
 467
 468         /* The CSC registers are sequential, alternating MSB then LSB */
 469         for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
 470                 u16 coeff_a = (*csc_coeff)[0][i];
 471                 u16 coeff_b = (*csc_coeff)[1][i];
 472                 u16 coeff_c = (*csc_coeff)[2][i];
 473
 474                 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
 475                 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
 476                 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
 477                 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
 478                 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
 479                 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
 480         }
 481
 482         hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
 483                   HDMI_CSC_SCALE);
 484 }
 485
 486 static void hdmi_video_csc(struct imx_hdmi *hdmi)
 487 {
 488         int color_depth = 0;
 489         int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
 490         int decimation = 0;
 491
 492         /* YCC422 interpolation to 444 mode */
 493         if (is_color_space_interpolation(hdmi))
 494                 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
 495         else if (is_color_space_decimation(hdmi))
 496                 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
 497
 498         if (hdmi->hdmi_data.enc_color_depth == 8)
 499                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
 500         else if (hdmi->hdmi_data.enc_color_depth == 10)
 501                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
 502         else if (hdmi->hdmi_data.enc_color_depth == 12)
 503                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
 504         else if (hdmi->hdmi_data.enc_color_depth == 16)
 505                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
 506         else
 507                 return;
 508
 509         /* Configure the CSC registers */
 510         hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
 511         hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
 512                   HDMI_CSC_SCALE);
 513
 514         imx_hdmi_update_csc_coeffs(hdmi);
 515 }
 516
 517 /*
 518  * HDMI video packetizer is used to packetize the data.
 519  * for example, if input is YCC422 mode or repeater is used,
 520  * data should be repacked this module can be bypassed.
 521  */
 522 static void hdmi_video_packetize(struct imx_hdmi *hdmi)
 523 {
 524         unsigned int color_depth = 0;
 525         unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
 526         unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
 527         struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
 528         u8 val, vp_conf;
 529
 530         if (hdmi_data->enc_out_format == RGB
 531                 || hdmi_data->enc_out_format == YCBCR444) {
 532                 if (!hdmi_data->enc_color_depth)
 533                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 534                 else if (hdmi_data->enc_color_depth == 8) {
 535                         color_depth = 4;
 536                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 537                 } else if (hdmi_data->enc_color_depth == 10)
 538                         color_depth = 5;
 539                 else if (hdmi_data->enc_color_depth == 12)
 540                         color_depth = 6;
 541                 else if (hdmi_data->enc_color_depth == 16)
 542                         color_depth = 7;
 543                 else
 544                         return;
 545         } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
 546                 if (!hdmi_data->enc_color_depth ||
 547                     hdmi_data->enc_color_depth == 8)
 548                         remap_size = HDMI_VP_REMAP_YCC422_16bit;
 549                 else if (hdmi_data->enc_color_depth == 10)
 550                         remap_size = HDMI_VP_REMAP_YCC422_20bit;
 551                 else if (hdmi_data->enc_color_depth == 12)
 552                         remap_size = HDMI_VP_REMAP_YCC422_24bit;
 553                 else
 554                         return;
 555                 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
 556         } else
 557                 return;
 558
 559         /* set the packetizer registers */
 560         val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
 561                 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
 562                 ((hdmi_data->pix_repet_factor <<
 563                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
 564                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
 565         hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
 566
 567         hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
 568                   HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
 569
 570         /* Data from pixel repeater block */
 571         if (hdmi_data->pix_repet_factor > 1) {
 572                 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
 573                           HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
 574         } else { /* data from packetizer block */
 575                 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
 576                           HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
 577         }
 578
 579         hdmi_modb(hdmi, vp_conf,
 580                   HDMI_VP_CONF_PR_EN_MASK |
 581                   HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
 582
 583         hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
 584                   HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
 585
 586         hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
 587
 588         if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
 589                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 590                           HDMI_VP_CONF_PP_EN_ENABLE |
 591                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 592         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
 593                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 594                           HDMI_VP_CONF_PP_EN_DISABLE |
 595                           HDMI_VP_CONF_YCC422_EN_ENABLE;
 596         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
 597                 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
 598                           HDMI_VP_CONF_PP_EN_DISABLE |
 599                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 600         } else {
 601                 return;
 602         }
 603
 604         hdmi_modb(hdmi, vp_conf,
 605                   HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
 606                   HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
 607
 608         hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
 609                         HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
 610                   HDMI_VP_STUFF_PP_STUFFING_MASK |
 611                   HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
 612
 613         hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
 614                   HDMI_VP_CONF);
 615 }
 616
 617 static inline void hdmi_phy_test_clear(struct imx_hdmi *hdmi,
 618                                                 unsigned char bit)
 619 {
 620         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
 621                   HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
 622 }
 623
 624 static inline void hdmi_phy_test_enable(struct imx_hdmi *hdmi,
 625                                                 unsigned char bit)
 626 {
 627         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET,
 628                   HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0);
 629 }
 630
 631 static inline void hdmi_phy_test_clock(struct imx_hdmi *hdmi,
 632                                                 unsigned char bit)
 633 {
 634         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET,
 635                   HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0);
 636 }
 637
 638 static inline void hdmi_phy_test_din(struct imx_hdmi *hdmi,
 639                                                 unsigned char bit)
 640 {
 641         hdmi_writeb(hdmi, bit, HDMI_PHY_TST1);
 642 }
 643
 644 static inline void hdmi_phy_test_dout(struct imx_hdmi *hdmi,
 645                                                 unsigned char bit)
 646 {
 647         hdmi_writeb(hdmi, bit, HDMI_PHY_TST2);
 648 }
 649
 650 static bool hdmi_phy_wait_i2c_done(struct imx_hdmi *hdmi, int msec)
 651 {
 652         unsigned char val = 0;
 653         val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3;
 654         while (!val) {
 655                 udelay(1000);
 656                 if (msec-- == 0)
 657                         return false;
 658                 val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3;
 659         }
 660         return true;
 661 }
 662
 663 static void __hdmi_phy_i2c_write(struct imx_hdmi *hdmi, unsigned short data,
 664                               unsigned char addr)
 665 {
 666         hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
 667         hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
 668         hdmi_writeb(hdmi, (unsigned char)(data >> 8),
 669                 HDMI_PHY_I2CM_DATAO_1_ADDR);
 670         hdmi_writeb(hdmi, (unsigned char)(data >> 0),
 671                 HDMI_PHY_I2CM_DATAO_0_ADDR);
 672         hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
 673                 HDMI_PHY_I2CM_OPERATION_ADDR);
 674         hdmi_phy_wait_i2c_done(hdmi, 1000);
 675 }
 676
 677 static int hdmi_phy_i2c_write(struct imx_hdmi *hdmi, unsigned short data,
 678                                      unsigned char addr)
 679 {
 680         __hdmi_phy_i2c_write(hdmi, data, addr);
 681         return 0;
 682 }
 683
 684 static void imx_hdmi_phy_enable_power(struct imx_hdmi *hdmi, u8 enable)
 685 {
 686         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 687                          HDMI_PHY_CONF0_PDZ_OFFSET,
 688                          HDMI_PHY_CONF0_PDZ_MASK);
 689 }
 690
 691 static void imx_hdmi_phy_enable_tmds(struct imx_hdmi *hdmi, u8 enable)
 692 {
 693         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 694                          HDMI_PHY_CONF0_ENTMDS_OFFSET,
 695                          HDMI_PHY_CONF0_ENTMDS_MASK);
 696 }
 697
 698 static void imx_hdmi_phy_gen2_pddq(struct imx_hdmi *hdmi, u8 enable)
 699 {
 700         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 701                          HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
 702                          HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
 703 }
 704
 705 static void imx_hdmi_phy_gen2_txpwron(struct imx_hdmi *hdmi, u8 enable)
 706 {
 707         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 708                          HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
 709                          HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
 710 }
 711
 712 static void imx_hdmi_phy_sel_data_en_pol(struct imx_hdmi *hdmi, u8 enable)
 713 {
 714         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 715                          HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
 716                          HDMI_PHY_CONF0_SELDATAENPOL_MASK);
 717 }
 718
 719 static void imx_hdmi_phy_sel_interface_control(struct imx_hdmi *hdmi, u8 enable)
 720 {
 721         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 722                          HDMI_PHY_CONF0_SELDIPIF_OFFSET,
 723                          HDMI_PHY_CONF0_SELDIPIF_MASK);
 724 }
 725
 726 enum {
 727         RES_8,
 728         RES_10,
 729         RES_12,
 730         RES_MAX,
 731 };
 732
 733 struct mpll_config {
 734         unsigned long mpixelclock;
 735         struct {
 736                 u16 cpce;
 737                 u16 gmp;
 738         } res[RES_MAX];
 739 };
 740
 741 static const struct mpll_config mpll_config[] = {
 742         {
 743                 45250000, {
 744                         { 0x01e0, 0x0000 },
 745                         { 0x21e1, 0x0000 },
 746                         { 0x41e2, 0x0000 }
 747                 },
 748         }, {
 749                 92500000, {
 750                         { 0x0140, 0x0005 },
 751                         { 0x2141, 0x0005 },
 752                         { 0x4142, 0x0005 },
 753                 },
 754         }, {
 755                 148500000, {
 756                         { 0x00a0, 0x000a },
 757                         { 0x20a1, 0x000a },
 758                         { 0x40a2, 0x000a },
 759                 },
 760         }, {
 761                 ~0UL, {
 762                         { 0x00a0, 0x000a },
 763                         { 0x2001, 0x000f },
 764                         { 0x4002, 0x000f },
 765                 },
 766         }
 767 };
 768
 769 struct curr_ctrl {
 770         unsigned long mpixelclock;
 771         u16 curr[RES_MAX];
 772 };
 773
 774 static const struct curr_ctrl curr_ctrl[] = {
 775         /*      pixelclk     bpp8    bpp10   bpp12 */
 776         {
 777                  54000000, { 0x091c, 0x091c, 0x06dc },
 778         }, {
 779                  58400000, { 0x091c, 0x06dc, 0x06dc },
 780         }, {
 781                  72000000, { 0x06dc, 0x06dc, 0x091c },
 782         }, {
 783                  74250000, { 0x06dc, 0x0b5c, 0x091c },
 784         }, {
 785                 118800000, { 0x091c, 0x091c, 0x06dc },
 786         }, {
 787                 216000000, { 0x06dc, 0x0b5c, 0x091c },
 788         }
 789 };
 790
 791 static int hdmi_phy_configure(struct imx_hdmi *hdmi, unsigned char prep,
 792                               unsigned char res, int cscon)
 793 {
 794         unsigned res_idx, i;
 795         u8 val, msec;
 796
 797         if (prep)
 798                 return -EINVAL;
 799
 800         switch (res) {
 801         case 0: /* color resolution 0 is 8 bit colour depth */
 802         case 8:
 803                 res_idx = RES_8;
 804                 break;
 805         case 10:
 806                 res_idx = RES_10;
 807                 break;
 808         case 12:
 809                 res_idx = RES_12;
 810                 break;
 811         default:
 812                 return -EINVAL;
 813         }
 814
 815         /* Enable csc path */
 816         if (cscon)
 817                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH;
 818         else
 819                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS;
 820
 821         hdmi_writeb(hdmi, val, HDMI_MC_FLOWCTRL);
 822
 823         /* gen2 tx power off */
 824         imx_hdmi_phy_gen2_txpwron(hdmi, 0);
 825
 826         /* gen2 pddq */
 827         imx_hdmi_phy_gen2_pddq(hdmi, 1);
 828
 829         /* PHY reset */
 830         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
 831         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
 832
 833         hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
 834
 835         hdmi_phy_test_clear(hdmi, 1);
 836         hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
 837                         HDMI_PHY_I2CM_SLAVE_ADDR);
 838         hdmi_phy_test_clear(hdmi, 0);
 839
 840         /* PLL/MPLL Cfg - always match on final entry */
 841         for (i = 0; i < ARRAY_SIZE(mpll_config) - 1; i++)
 842                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
 843                     mpll_config[i].mpixelclock)
 844                         break;
 845
 846         hdmi_phy_i2c_write(hdmi, mpll_config[i].res[res_idx].cpce, 0x06);
 847         hdmi_phy_i2c_write(hdmi, mpll_config[i].res[res_idx].gmp, 0x15);
 848
 849         for (i = 0; i < ARRAY_SIZE(curr_ctrl); i++)
 850                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
 851                     curr_ctrl[i].mpixelclock)
 852                         break;
 853
 854         if (i >= ARRAY_SIZE(curr_ctrl)) {
 855                 dev_err(hdmi->dev,
 856                                 "Pixel clock %d - unsupported by HDMI\n",
 857                                 hdmi->hdmi_data.video_mode.mpixelclock);
 858                 return -EINVAL;
 859         }
 860
 861         /* CURRCTRL */
 862         hdmi_phy_i2c_write(hdmi, curr_ctrl[i].curr[res_idx], 0x10);
 863
 864         hdmi_phy_i2c_write(hdmi, 0x0000, 0x13);  /* PLLPHBYCTRL */
 865         hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
 866         /* RESISTANCE TERM 133Ohm Cfg */
 867         hdmi_phy_i2c_write(hdmi, 0x0005, 0x19);  /* TXTERM */
 868         /* PREEMP Cgf 0.00 */
 869         hdmi_phy_i2c_write(hdmi, 0x800d, 0x09);  /* CKSYMTXCTRL */
 870         /* TX/CK LVL 10 */
 871         hdmi_phy_i2c_write(hdmi, 0x01ad, 0x0E);  /* VLEVCTRL */
 872         /* REMOVE CLK TERM */
 873         hdmi_phy_i2c_write(hdmi, 0x8000, 0x05);  /* CKCALCTRL */
 874
 875         imx_hdmi_phy_enable_power(hdmi, 1);
 876
 877         /* toggle TMDS enable */
 878         imx_hdmi_phy_enable_tmds(hdmi, 0);
 879         imx_hdmi_phy_enable_tmds(hdmi, 1);
 880
 881         /* gen2 tx power on */
 882         imx_hdmi_phy_gen2_txpwron(hdmi, 1);
 883         imx_hdmi_phy_gen2_pddq(hdmi, 0);
 884
 885         /*Wait for PHY PLL lock */
 886         msec = 5;
 887         do {
 888                 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
 889                 if (!val)
 890                         break;
 891
 892                 if (msec == 0) {
 893                         dev_err(hdmi->dev, "PHY PLL not locked\n");
 894                         return -ETIMEDOUT;
 895                 }
 896
 897                 udelay(1000);
 898                 msec--;
 899         } while (1);
 900
 901         return 0;
 902 }
 903
 904 static int imx_hdmi_phy_init(struct imx_hdmi *hdmi)
 905 {
 906         int i, ret;
 907         bool cscon = false;
 908
 909         /*check csc whether needed activated in HDMI mode */
 910         cscon = (is_color_space_conversion(hdmi) &&
 911                         !hdmi->hdmi_data.video_mode.mdvi);
 912
 913         /* HDMI Phy spec says to do the phy initialization sequence twice */
 914         for (i = 0; i < 2; i++) {
 915                 imx_hdmi_phy_sel_data_en_pol(hdmi, 1);
 916                 imx_hdmi_phy_sel_interface_control(hdmi, 0);
 917                 imx_hdmi_phy_enable_tmds(hdmi, 0);
 918                 imx_hdmi_phy_enable_power(hdmi, 0);
 919
 920                 /* Enable CSC */
 921                 ret = hdmi_phy_configure(hdmi, 0, 8, cscon);
 922                 if (ret)
 923                         return ret;
 924         }
 925
 926         hdmi->phy_enabled = true;
 927         return 0;
 928 }
 929
 930 static void hdmi_tx_hdcp_config(struct imx_hdmi *hdmi)
 931 {
 932         u8 de;
 933
 934         if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
 935                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
 936         else
 937                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
 938
 939         /* disable rx detect */
 940         hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
 941                   HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
 942
 943         hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
 944
 945         hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
 946                   HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
 947 }
 948
 949 static void hdmi_config_AVI(struct imx_hdmi *hdmi)
 950 {
 951         u8 val, pix_fmt, under_scan;
 952         u8 act_ratio, coded_ratio, colorimetry, ext_colorimetry;
 953         bool aspect_16_9;
 954
 955         aspect_16_9 = false; /* FIXME */
 956
 957         /* AVI Data Byte 1 */
 958         if (hdmi->hdmi_data.enc_out_format == YCBCR444)
 959                 pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_YCBCR444;
 960         else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS)
 961                 pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_YCBCR422;
 962         else
 963                 pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_RGB;
 964
 965                 under_scan =  HDMI_FC_AVICONF0_SCAN_INFO_NODATA;
 966
 967         /*
 968          * Active format identification data is present in the AVI InfoFrame.
 969          * Under scan info, no bar data
 970          */
 971         val = pix_fmt | under_scan |
 972                 HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT |
 973                 HDMI_FC_AVICONF0_BAR_DATA_NO_DATA;
 974
 975         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
 976
 977         /* AVI Data Byte 2 -Set the Aspect Ratio */
 978         if (aspect_16_9) {
 979                 act_ratio = HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9;
 980                 coded_ratio = HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9;
 981         } else {
 982                 act_ratio = HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3;
 983                 coded_ratio = HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3;
 984         }
 985
 986         /* Set up colorimetry */
 987         if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
 988                 colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO;
 989                 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
 990                         ext_colorimetry =
 991                                 HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
 992                 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
 993                         ext_colorimetry =
 994                                 HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709;
 995         } else if (hdmi->hdmi_data.enc_out_format != RGB) {
 996                 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
 997                         colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_SMPTE;
 998                 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
 999                         colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_ITUR;
1000                 ext_colorimetry = HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
1001         } else { /* Carries no data */
1002                 colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA;
1003                 ext_colorimetry = HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
1004         }
1005
1006         val = colorimetry | coded_ratio | act_ratio;
1007         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1008
1009         /* AVI Data Byte 3 */
1010         val = HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA | ext_colorimetry |
1011                 HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT |
1012                 HDMI_FC_AVICONF2_SCALING_NONE;
1013         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1014
1015         /* AVI Data Byte 4 */
1016         hdmi_writeb(hdmi, hdmi->vic, HDMI_FC_AVIVID);
1017
1018         /* AVI Data Byte 5- set up input and output pixel repetition */
1019         val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1020                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1021                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1022                 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1023                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1024                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1025         hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1026
1027         /* IT Content and quantization range = don't care */
1028         val = HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS |
1029                 HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED;
1030         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1031
1032         /* AVI Data Bytes 6-13 */
1033         hdmi_writeb(hdmi, 0, HDMI_FC_AVIETB0);
1034         hdmi_writeb(hdmi, 0, HDMI_FC_AVIETB1);
1035         hdmi_writeb(hdmi, 0, HDMI_FC_AVISBB0);
1036         hdmi_writeb(hdmi, 0, HDMI_FC_AVISBB1);
1037         hdmi_writeb(hdmi, 0, HDMI_FC_AVIELB0);
1038         hdmi_writeb(hdmi, 0, HDMI_FC_AVIELB1);
1039         hdmi_writeb(hdmi, 0, HDMI_FC_AVISRB0);
1040         hdmi_writeb(hdmi, 0, HDMI_FC_AVISRB1);
1041 }
1042
1043 static void hdmi_av_composer(struct imx_hdmi *hdmi,
1044                              const struct drm_display_mode *mode)
1045 {
1046         u8 inv_val;
1047         struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1048         int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1049
1050         vmode->mhsyncpolarity = !!(mode->flags & DRM_MODE_FLAG_PHSYNC);
1051         vmode->mvsyncpolarity = !!(mode->flags & DRM_MODE_FLAG_PVSYNC);
1052         vmode->minterlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
1053         vmode->mpixelclock = mode->clock * 1000;
1054
1055         dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1056
1057         /* Set up HDMI_FC_INVIDCONF */
1058         inv_val = (hdmi->hdmi_data.hdcp_enable ?
1059                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1060                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1061
1062         inv_val |= (vmode->mvsyncpolarity ?
1063                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1064                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW);
1065
1066         inv_val |= (vmode->mhsyncpolarity ?
1067                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1068                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW);
1069
1070         inv_val |= (vmode->mdataenablepolarity ?
1071                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1072                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1073
1074         if (hdmi->vic == 39)
1075                 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1076         else
1077                 inv_val |= (vmode->minterlaced ?
1078                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1079                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW);
1080
1081         inv_val |= (vmode->minterlaced ?
1082                 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1083                 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE);
1084
1085         inv_val |= (vmode->mdvi ?
1086                 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE :
1087                 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE);
1088
1089         hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1090
1091         /* Set up horizontal active pixel width */
1092         hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1);
1093         hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0);
1094
1095         /* Set up vertical active lines */
1096         hdmi_writeb(hdmi, mode->vdisplay >> 8, HDMI_FC_INVACTV1);
1097         hdmi_writeb(hdmi, mode->vdisplay, HDMI_FC_INVACTV0);
1098
1099         /* Set up horizontal blanking pixel region width */
1100         hblank = mode->htotal - mode->hdisplay;
1101         hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1102         hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1103
1104         /* Set up vertical blanking pixel region width */
1105         vblank = mode->vtotal - mode->vdisplay;
1106         hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1107
1108         /* Set up HSYNC active edge delay width (in pixel clks) */
1109         h_de_hs = mode->hsync_start - mode->hdisplay;
1110         hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1111         hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1112
1113         /* Set up VSYNC active edge delay (in lines) */
1114         v_de_vs = mode->vsync_start - mode->vdisplay;
1115         hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1116
1117         /* Set up HSYNC active pulse width (in pixel clks) */
1118         hsync_len = mode->hsync_end - mode->hsync_start;
1119         hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1120         hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1121
1122         /* Set up VSYNC active edge delay (in lines) */
1123         vsync_len = mode->vsync_end - mode->vsync_start;
1124         hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1125 }
1126
1127 static void imx_hdmi_phy_disable(struct imx_hdmi *hdmi)
1128 {
1129         if (!hdmi->phy_enabled)
1130                 return;
1131
1132         imx_hdmi_phy_enable_tmds(hdmi, 0);
1133         imx_hdmi_phy_enable_power(hdmi, 0);
1134
1135         hdmi->phy_enabled = false;
1136 }
1137
1138 /* HDMI Initialization Step B.4 */
1139 static void imx_hdmi_enable_video_path(struct imx_hdmi *hdmi)
1140 {
1141         u8 clkdis;
1142
1143         /* control period minimum duration */
1144         hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1145         hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1146         hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1147
1148         /* Set to fill TMDS data channels */
1149         hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1150         hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1151         hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1152
1153         /* Enable pixel clock and tmds data path */
1154         clkdis = 0x7F;
1155         clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1156         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1157
1158         clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1159         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1160
1161         /* Enable csc path */
1162         if (is_color_space_conversion(hdmi)) {
1163                 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1164                 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1165         }
1166 }
1167
1168 static void hdmi_enable_audio_clk(struct imx_hdmi *hdmi)
1169 {
1170         hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS);
1171 }
1172
1173 /* Workaround to clear the overflow condition */
1174 static void imx_hdmi_clear_overflow(struct imx_hdmi *hdmi)
1175 {
1176         int count;
1177         u8 val;
1178
1179         /* TMDS software reset */
1180         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1181
1182         val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1183         if (hdmi->dev_type == IMX6DL_HDMI) {
1184                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1185                 return;
1186         }
1187
1188         for (count = 0; count < 4; count++)
1189                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1190 }
1191
1192 static void hdmi_enable_overflow_interrupts(struct imx_hdmi *hdmi)
1193 {
1194         hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
1195         hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
1196 }
1197
1198 static void hdmi_disable_overflow_interrupts(struct imx_hdmi *hdmi)
1199 {
1200         hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1201                     HDMI_IH_MUTE_FC_STAT2);
1202 }
1203
1204 static int imx_hdmi_setup(struct imx_hdmi *hdmi, struct drm_display_mode *mode)
1205 {
1206         int ret;
1207
1208         hdmi_disable_overflow_interrupts(hdmi);
1209
1210         hdmi->vic = drm_match_cea_mode(mode);
1211
1212         if (!hdmi->vic) {
1213                 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1214                 hdmi->hdmi_data.video_mode.mdvi = true;
1215         } else {
1216                 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1217                 hdmi->hdmi_data.video_mode.mdvi = false;
1218         }
1219
1220         if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
1221                 (hdmi->vic == 21) || (hdmi->vic == 22) ||
1222                 (hdmi->vic == 2) || (hdmi->vic == 3) ||
1223                 (hdmi->vic == 17) || (hdmi->vic == 18))
1224                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
1225         else
1226                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
1227
1228         if ((hdmi->vic == 10) || (hdmi->vic == 11) ||
1229                 (hdmi->vic == 12) || (hdmi->vic == 13) ||
1230                 (hdmi->vic == 14) || (hdmi->vic == 15) ||
1231                 (hdmi->vic == 25) || (hdmi->vic == 26) ||
1232                 (hdmi->vic == 27) || (hdmi->vic == 28) ||
1233                 (hdmi->vic == 29) || (hdmi->vic == 30) ||
1234                 (hdmi->vic == 35) || (hdmi->vic == 36) ||
1235                 (hdmi->vic == 37) || (hdmi->vic == 38))
1236                 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1;
1237         else
1238                 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1239
1240         hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1241
1242         /* TODO: Get input format from IPU (via FB driver interface) */
1243         hdmi->hdmi_data.enc_in_format = RGB;
1244
1245         hdmi->hdmi_data.enc_out_format = RGB;
1246
1247         hdmi->hdmi_data.enc_color_depth = 8;
1248         hdmi->hdmi_data.pix_repet_factor = 0;
1249         hdmi->hdmi_data.hdcp_enable = 0;
1250         hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1251
1252         /* HDMI Initialization Step B.1 */
1253         hdmi_av_composer(hdmi, mode);
1254
1255         /* HDMI Initializateion Step B.2 */
1256         ret = imx_hdmi_phy_init(hdmi);
1257         if (ret)
1258                 return ret;
1259
1260         /* HDMI Initialization Step B.3 */
1261         imx_hdmi_enable_video_path(hdmi);
1262
1263         /* not for DVI mode */
1264         if (hdmi->hdmi_data.video_mode.mdvi)
1265                 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
1266         else {
1267                 dev_dbg(hdmi->dev, "%s CEA mode\n", __func__);
1268
1269                 /* HDMI Initialization Step E - Configure audio */
1270                 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1271                 hdmi_enable_audio_clk(hdmi);
1272
1273                 /* HDMI Initialization Step F - Configure AVI InfoFrame */
1274                 hdmi_config_AVI(hdmi);
1275         }
1276
1277         hdmi_video_packetize(hdmi);
1278         hdmi_video_csc(hdmi);
1279         hdmi_video_sample(hdmi);
1280         hdmi_tx_hdcp_config(hdmi);
1281
1282         imx_hdmi_clear_overflow(hdmi);
1283         if (hdmi->cable_plugin && !hdmi->hdmi_data.video_mode.mdvi)
1284                 hdmi_enable_overflow_interrupts(hdmi);
1285
1286         return 0;
1287 }
1288
1289 /* Wait until we are registered to enable interrupts */
1290 static int imx_hdmi_fb_registered(struct imx_hdmi *hdmi)
1291 {
1292         hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
1293                     HDMI_PHY_I2CM_INT_ADDR);
1294
1295         hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
1296                     HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
1297                     HDMI_PHY_I2CM_CTLINT_ADDR);
1298
1299         /* enable cable hot plug irq */
1300         hdmi_writeb(hdmi, (u8)~HDMI_PHY_HPD, HDMI_PHY_MASK0);
1301
1302         /* Clear Hotplug interrupts */
1303         hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
1304
1305         /* Unmute interrupts */
1306         hdmi_writeb(hdmi, ~HDMI_IH_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0);
1307
1308         return 0;
1309 }
1310
1311 static void initialize_hdmi_ih_mutes(struct imx_hdmi *hdmi)
1312 {
1313         u8 ih_mute;
1314
1315         /*
1316          * Boot up defaults are:
1317          * HDMI_IH_MUTE   = 0x03 (disabled)
1318          * HDMI_IH_MUTE_* = 0x00 (enabled)
1319          *
1320          * Disable top level interrupt bits in HDMI block
1321          */
1322         ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
1323                   HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1324                   HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
1325
1326         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1327
1328         /* by default mask all interrupts */
1329         hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
1330         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
1331         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
1332         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
1333         hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
1334         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
1335         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
1336         hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
1337         hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
1338         hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
1339         hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
1340         hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
1341         hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK);
1342         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
1343         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
1344
1345         /* Disable interrupts in the IH_MUTE_* registers */
1346         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
1347         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
1348         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
1349         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
1350         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
1351         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
1352         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
1353         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
1354         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
1355         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
1356
1357         /* Enable top level interrupt bits in HDMI block */
1358         ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1359                     HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
1360         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1361 }
1362
1363 static void imx_hdmi_poweron(struct imx_hdmi *hdmi)
1364 {
1365         imx_hdmi_setup(hdmi, &hdmi->previous_mode);
1366 }
1367
1368 static void imx_hdmi_poweroff(struct imx_hdmi *hdmi)
1369 {
1370         imx_hdmi_phy_disable(hdmi);
1371 }
1372
1373 static enum drm_connector_status imx_hdmi_connector_detect(struct drm_connector
1374                                                         *connector, bool force)
1375 {
1376         /* FIXME */
1377         return connector_status_connected;
1378 }
1379
1380 static void imx_hdmi_connector_destroy(struct drm_connector *connector)
1381 {
1382 }
1383
1384 static int imx_hdmi_connector_get_modes(struct drm_connector *connector)
1385 {
1386         struct imx_hdmi *hdmi = container_of(connector, struct imx_hdmi,
1387                                              connector);
1388         struct edid *edid;
1389         int ret;
1390
1391         if (!hdmi->ddc)
1392                 return 0;
1393
1394         edid = drm_get_edid(connector, hdmi->ddc);
1395         if (edid) {
1396                 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
1397                         edid->width_cm, edid->height_cm);
1398
1399                 drm_mode_connector_update_edid_property(connector, edid);
1400                 ret = drm_add_edid_modes(connector, edid);
1401                 kfree(edid);
1402         } else {
1403                 dev_dbg(hdmi->dev, "failed to get edid\n");
1404         }
1405
1406         return 0;
1407 }
1408
1409 static struct drm_encoder *imx_hdmi_connector_best_encoder(struct drm_connector
1410                                                            *connector)
1411 {
1412         struct imx_hdmi *hdmi = container_of(connector, struct imx_hdmi,
1413                                              connector);
1414
1415         return &hdmi->encoder;
1416 }
1417
1418 static void imx_hdmi_encoder_mode_set(struct drm_encoder *encoder,
1419                         struct drm_display_mode *mode,
1420                         struct drm_display_mode *adjusted_mode)
1421 {
1422         struct imx_hdmi *hdmi = container_of(encoder, struct imx_hdmi, encoder);
1423
1424         imx_hdmi_setup(hdmi, mode);
1425
1426         /* Store the display mode for plugin/DKMS poweron events */
1427         memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
1428 }
1429
1430 static bool imx_hdmi_encoder_mode_fixup(struct drm_encoder *encoder,
1431                         const struct drm_display_mode *mode,
1432                         struct drm_display_mode *adjusted_mode)
1433 {
1434         return true;
1435 }
1436
1437 static void imx_hdmi_encoder_disable(struct drm_encoder *encoder)
1438 {
1439 }
1440
1441 static void imx_hdmi_encoder_dpms(struct drm_encoder *encoder, int mode)
1442 {
1443         struct imx_hdmi *hdmi = container_of(encoder, struct imx_hdmi, encoder);
1444
1445         if (mode)
1446                 imx_hdmi_poweroff(hdmi);
1447         else
1448                 imx_hdmi_poweron(hdmi);
1449 }
1450
1451 static void imx_hdmi_encoder_prepare(struct drm_encoder *encoder)
1452 {
1453         struct imx_hdmi *hdmi = container_of(encoder, struct imx_hdmi, encoder);
1454
1455         imx_hdmi_poweroff(hdmi);
1456         imx_drm_panel_format(encoder, V4L2_PIX_FMT_RGB24);
1457 }
1458
1459 static void imx_hdmi_encoder_commit(struct drm_encoder *encoder)
1460 {
1461         struct imx_hdmi *hdmi = container_of(encoder, struct imx_hdmi, encoder);
1462         int mux = imx_drm_encoder_get_mux_id(encoder);
1463
1464         imx_hdmi_set_ipu_di_mux(hdmi, mux);
1465
1466         imx_hdmi_poweron(hdmi);
1467 }
1468
1469 static void imx_hdmi_encoder_destroy(struct drm_encoder *encoder)
1470 {
1471         return;
1472 }
1473
1474 static struct drm_encoder_funcs imx_hdmi_encoder_funcs = {
1475         .destroy = imx_hdmi_encoder_destroy,
1476 };
1477
1478 static struct drm_encoder_helper_funcs imx_hdmi_encoder_helper_funcs = {
1479         .dpms = imx_hdmi_encoder_dpms,
1480         .prepare = imx_hdmi_encoder_prepare,
1481         .commit = imx_hdmi_encoder_commit,
1482         .mode_set = imx_hdmi_encoder_mode_set,
1483         .mode_fixup = imx_hdmi_encoder_mode_fixup,
1484         .disable = imx_hdmi_encoder_disable,
1485 };
1486
1487 static struct drm_connector_funcs imx_hdmi_connector_funcs = {
1488         .dpms = drm_helper_connector_dpms,
1489         .fill_modes = drm_helper_probe_single_connector_modes,
1490         .detect = imx_hdmi_connector_detect,
1491         .destroy = imx_hdmi_connector_destroy,
1492 };
1493
1494 static struct drm_connector_helper_funcs imx_hdmi_connector_helper_funcs = {
1495         .get_modes = imx_hdmi_connector_get_modes,
1496         .mode_valid = imx_drm_connector_mode_valid,
1497         .best_encoder = imx_hdmi_connector_best_encoder,
1498 };
1499
1500 static irqreturn_t imx_hdmi_irq(int irq, void *dev_id)
1501 {
1502         struct imx_hdmi *hdmi = dev_id;
1503         u8 intr_stat;
1504         u8 phy_int_pol;
1505
1506         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1507
1508         phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
1509
1510         if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
1511                 if (phy_int_pol & HDMI_PHY_HPD) {
1512                         dev_dbg(hdmi->dev, "EVENT=plugin\n");
1513
1514                         hdmi_modb(hdmi, 0, HDMI_PHY_HPD, HDMI_PHY_POL0);
1515
1516                         imx_hdmi_poweron(hdmi);
1517                 } else {
1518                         dev_dbg(hdmi->dev, "EVENT=plugout\n");
1519
1520                         hdmi_modb(hdmi, HDMI_PHY_HPD, HDMI_PHY_HPD, HDMI_PHY_POL0);
1521
1522                         imx_hdmi_poweroff(hdmi);
1523                 }
1524         }
1525
1526         hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
1527
1528         return IRQ_HANDLED;
1529 }
1530
1531 static int imx_hdmi_register(struct imx_hdmi *hdmi)
1532 {
1533         int ret;
1534
1535         hdmi->connector.funcs = &imx_hdmi_connector_funcs;
1536         hdmi->encoder.funcs = &imx_hdmi_encoder_funcs;
1537
1538         hdmi->encoder.encoder_type = DRM_MODE_ENCODER_TMDS;
1539         hdmi->connector.connector_type = DRM_MODE_CONNECTOR_HDMIA;
1540
1541         drm_encoder_helper_add(&hdmi->encoder, &imx_hdmi_encoder_helper_funcs);
1542         ret = imx_drm_add_encoder(&hdmi->encoder, &hdmi->imx_drm_encoder,
1543                         THIS_MODULE);
1544         if (ret) {
1545                 dev_err(hdmi->dev, "adding encoder failed: %d\n", ret);
1546                 return ret;
1547         }
1548
1549         drm_connector_helper_add(&hdmi->connector,
1550                         &imx_hdmi_connector_helper_funcs);
1551
1552         ret = imx_drm_add_connector(&hdmi->connector,
1553                         &hdmi->imx_drm_connector, THIS_MODULE);
1554         if (ret) {
1555                 imx_drm_remove_encoder(hdmi->imx_drm_encoder);
1556                 dev_err(hdmi->dev, "adding connector failed: %d\n", ret);
1557                 return ret;
1558         }
1559
1560         hdmi->connector.encoder = &hdmi->encoder;
1561
1562         drm_mode_connector_attach_encoder(&hdmi->connector, &hdmi->encoder);
1563
1564         return 0;
1565 }
1566
1567 static struct platform_device_id imx_hdmi_devtype[] = {
1568         {
1569                 .name = "imx6q-hdmi",
1570                 .driver_data = IMX6Q_HDMI,
1571         }, {
1572                 .name = "imx6dl-hdmi",
1573                 .driver_data = IMX6DL_HDMI,
1574         }, { /* sentinel */ }
1575 };
1576 MODULE_DEVICE_TABLE(platform, imx_hdmi_devtype);
1577
1578 static const struct of_device_id imx_hdmi_dt_ids[] = {
1579 { .compatible = "fsl,imx6q-hdmi", .data = &imx_hdmi_devtype[IMX6Q_HDMI], },
1580 { .compatible = "fsl,imx6dl-hdmi", .data = &imx_hdmi_devtype[IMX6DL_HDMI], },
1581 { /* sentinel */ }
1582 };
1583 MODULE_DEVICE_TABLE(of, imx_hdmi_dt_ids);
1584
1585 static int imx_hdmi_platform_probe(struct platform_device *pdev)
1586 {
1587         const struct of_device_id *of_id =
1588                                 of_match_device(imx_hdmi_dt_ids, &pdev->dev);
1589         struct device_node *np = pdev->dev.of_node;
1590         struct device_node *ddc_node;
1591         struct imx_hdmi *hdmi;
1592         struct resource *iores;
1593         int ret, irq;
1594
1595         hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
1596         if (!hdmi)
1597                 return -ENOMEM;
1598
1599         hdmi->dev = &pdev->dev;
1600         hdmi->sample_rate = 48000;
1601         hdmi->ratio = 100;
1602
1603         if (of_id) {
1604                 const struct platform_device_id *device_id = of_id->data;
1605                 hdmi->dev_type = device_id->driver_data;
1606         }
1607
1608         ddc_node = of_parse_phandle(np, "ddc", 0);
1609         if (ddc_node) {
1610                 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
1611                 if (!hdmi->ddc)
1612                         dev_dbg(hdmi->dev, "failed to read ddc node\n");
1613
1614                 of_node_put(ddc_node);
1615         } else {
1616                 dev_dbg(hdmi->dev, "no ddc property found\n");
1617         }
1618
1619         irq = platform_get_irq(pdev, 0);
1620         if (irq < 0)
1621                 return -EINVAL;
1622
1623         ret = devm_request_irq(&pdev->dev, irq, imx_hdmi_irq, 0,
1624                                dev_name(&pdev->dev), hdmi);
1625         if (ret)
1626                 return ret;
1627
1628         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1629         hdmi->regs = devm_ioremap_resource(&pdev->dev, iores);
1630         if (IS_ERR(hdmi->regs))
1631                 return PTR_ERR(hdmi->regs);
1632
1633         hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "gpr");
1634         if (IS_ERR(hdmi->regmap))
1635                 return PTR_ERR(hdmi->regmap);
1636
1637         hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
1638         if (IS_ERR(hdmi->isfr_clk)) {
1639                 ret = PTR_ERR(hdmi->isfr_clk);
1640                 dev_err(hdmi->dev,
1641                         "Unable to get HDMI isfr clk: %d\n", ret);
1642                 return ret;
1643         }
1644
1645         ret = clk_prepare_enable(hdmi->isfr_clk);
1646         if (ret) {
1647                 dev_err(hdmi->dev,
1648                         "Cannot enable HDMI isfr clock: %d\n", ret);
1649                 return ret;
1650         }
1651
1652         hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
1653         if (IS_ERR(hdmi->iahb_clk)) {
1654                 ret = PTR_ERR(hdmi->iahb_clk);
1655                 dev_err(hdmi->dev,
1656                         "Unable to get HDMI iahb clk: %d\n", ret);
1657                 goto err_isfr;
1658         }
1659
1660         ret = clk_prepare_enable(hdmi->iahb_clk);
1661         if (ret) {
1662                 dev_err(hdmi->dev,
1663                         "Cannot enable HDMI iahb clock: %d\n", ret);
1664                 goto err_isfr;
1665         }
1666
1667         /* Product and revision IDs */
1668         dev_info(&pdev->dev,
1669                 "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n",
1670                 hdmi_readb(hdmi, HDMI_DESIGN_ID),
1671                 hdmi_readb(hdmi, HDMI_REVISION_ID),
1672                 hdmi_readb(hdmi, HDMI_PRODUCT_ID0),
1673                 hdmi_readb(hdmi, HDMI_PRODUCT_ID1));
1674
1675         initialize_hdmi_ih_mutes(hdmi);
1676
1677         /*
1678          * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
1679          * N and cts values before enabling phy
1680          */
1681         hdmi_init_clk_regenerator(hdmi);
1682
1683         /*
1684          * Configure registers related to HDMI interrupt
1685          * generation before registering IRQ.
1686          */
1687         hdmi_writeb(hdmi, HDMI_PHY_HPD, HDMI_PHY_POL0);
1688
1689         /* Clear Hotplug interrupts */
1690         hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
1691
1692         ret = imx_hdmi_fb_registered(hdmi);
1693         if (ret)
1694                 goto err_iahb;
1695
1696         ret = imx_hdmi_register(hdmi);
1697         if (ret)
1698                 goto err_iahb;
1699
1700         imx_drm_encoder_add_possible_crtcs(hdmi->imx_drm_encoder, np);
1701
1702         platform_set_drvdata(pdev, hdmi);
1703
1704         return 0;
1705
1706 err_iahb:
1707         clk_disable_unprepare(hdmi->iahb_clk);
1708 err_isfr:
1709         clk_disable_unprepare(hdmi->isfr_clk);
1710
1711         return ret;
1712 }
1713
1714 static int imx_hdmi_platform_remove(struct platform_device *pdev)
1715 {
1716         struct imx_hdmi *hdmi = platform_get_drvdata(pdev);
1717         struct drm_connector *connector = &hdmi->connector;
1718         struct drm_encoder *encoder = &hdmi->encoder;
1719
1720         drm_mode_connector_detach_encoder(connector, encoder);
1721         imx_drm_remove_connector(hdmi->imx_drm_connector);
1722         imx_drm_remove_encoder(hdmi->imx_drm_encoder);
1723
1724         clk_disable_unprepare(hdmi->iahb_clk);
1725         clk_disable_unprepare(hdmi->isfr_clk);
1726         i2c_put_adapter(hdmi->ddc);
1727
1728         return 0;
1729 }
1730
1731 static struct platform_driver imx_hdmi_driver = {
1732         .probe  = imx_hdmi_platform_probe,
1733         .remove = imx_hdmi_platform_remove,
1734         .driver = {
1735                 .name = "imx-hdmi",
1736                 .owner = THIS_MODULE,
1737                 .of_match_table = imx_hdmi_dt_ids,
1738         },
1739 };
1740
1741 module_platform_driver(imx_hdmi_driver);
1742
1743 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
1744 MODULE_DESCRIPTION("i.MX6 HDMI transmitter driver");
1745 MODULE_LICENSE("GPL");
1746 MODULE_ALIAS("platform:imx-hdmi");