2 * Intel MID Resistive Touch Screen Driver
4 * Copyright (C) 2008 Intel Corp
6 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
21 * Questions/Comments/Bug fixes to Sreedhara (sreedhara.ds@intel.com)
22 * Ramesh Agarwal (ramesh.agarwal@intel.com)
23 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
26 * review conversion of r/m/w sequences
29 #include <linux/module.h>
30 #include <linux/init.h>
31 #include <linux/input.h>
32 #include <linux/interrupt.h>
33 #include <linux/err.h>
34 #include <linux/param.h>
35 #include <linux/slab.h>
36 #include <linux/platform_device.h>
37 #include <linux/irq.h>
38 #include <linux/delay.h>
39 #include <asm/intel_scu_ipc.h>
41 /* PMIC Interrupt registers */
42 #define PMIC_REG_ID1 0x00 /* PMIC ID1 register */
44 /* PMIC Interrupt registers */
45 #define PMIC_REG_INT 0x04 /* PMIC interrupt register */
46 #define PMIC_REG_MINT 0x05 /* PMIC interrupt mask register */
48 /* ADC Interrupt registers */
49 #define PMIC_REG_ADCINT 0x5F /* ADC interrupt register */
50 #define PMIC_REG_MADCINT 0x60 /* ADC interrupt mask register */
52 /* ADC Control registers */
53 #define PMIC_REG_ADCCNTL1 0x61 /* ADC control register */
55 /* ADC Channel Selection registers */
56 #define PMICADDR0 0xA4
57 #define END_OF_CHANNEL 0x1F
59 /* ADC Result register */
60 #define PMIC_REG_ADCSNS0H 0x64
62 /* ADC channels for touch screen */
63 #define MRST_TS_CHAN10 0xA /* Touch screen X+ connection */
64 #define MRST_TS_CHAN11 0xB /* Touch screen X- connection */
65 #define MRST_TS_CHAN12 0xC /* Touch screen Y+ connection */
66 #define MRST_TS_CHAN13 0xD /* Touch screen Y- connection */
68 /* Touch screen channel BIAS constants */
69 #define MRST_XBIAS 0x20
70 #define MRST_YBIAS 0x40
71 #define MRST_ZBIAS 0x80
73 /* Touch screen coordinates */
75 #define MRST_X_MAX 1024
78 #define MRST_Y_MAX 1024
80 #define MRST_PRESSURE_MIN 0
81 #define MRST_PRESSURE_NOMINAL 50
82 #define MRST_PRESSURE_MAX 100
84 #define WAIT_ADC_COMPLETION 10 /* msec */
86 /* PMIC ADC round robin delays */
87 #define ADC_LOOP_DELAY0 0x0 /* Continuous loop */
88 #define ADC_LOOP_DELAY1 0x1 /* 4.5 ms approximate */
90 /* PMIC Vendor Identifiers */
91 #define PMIC_VENDOR_FS 0 /* PMIC vendor FreeScale */
92 #define PMIC_VENDOR_MAXIM 1 /* PMIC vendor MAXIM */
93 #define PMIC_VENDOR_NEC 2 /* PMIC vendor NEC */
94 #define MRSTOUCH_MAX_CHANNELS 32 /* Maximum ADC channels */
96 /* Touch screen device structure */
98 struct device *dev; /* device associated with touch screen */
99 struct input_dev *input;
101 u16 asr; /* Address selection register */
103 unsigned int vendor; /* PMIC vendor */
104 unsigned int rev; /* PMIC revision */
106 int (*read_prepare)(struct mrstouch_dev *tsdev);
107 int (*read)(struct mrstouch_dev *tsdev, u16 *x, u16 *y, u16 *z);
108 int (*read_finish)(struct mrstouch_dev *tsdev);
112 /*************************** NEC and Maxim Interface ************************/
114 static int mrstouch_nec_adc_read_prepare(struct mrstouch_dev *tsdev)
119 err = intel_scu_ipc_ioread16(PMIC_REG_MADCINT, ®);
123 reg &= 0xDFFF; /* Disable pendet */
125 /* Set MADCINT and update ADCCNTL1 (next reg byte) */
126 return intel_scu_ipc_iowrite16(PMIC_REG_MADCINT, reg);
130 * Enables PENDET interrupt.
132 static int mrstouch_nec_adc_read_finish(struct mrstouch_dev *tsdev)
140 err = intel_scu_ipc_ioread16(PMIC_REG_MADCINT, ®);
145 reg |= 0x2000; /* Enable pendet */
147 /* Set MADCINT and update ADCCNTL1 (next reg byte) */
148 err = intel_scu_ipc_iowrite16(PMIC_REG_MADCINT, reg);
153 * Sometimes even after the register write succeeds
154 * the PMIC register value is not updated. Retry few iterations
158 err = intel_scu_ipc_ioread8(PMIC_REG_ADCCNTL1, &r);
162 pendet_enabled = (r >> 5) & 0x01;
164 if (!pendet_enabled) {
167 "Touch screen disabled.\n");
173 err = intel_scu_ipc_iowrite8(PMIC_REG_ADCCNTL1,
178 } while (!pendet_enabled);
184 * Reads PMIC ADC touch screen result
185 * Reads ADC storage registers for higher 7 and lower 3 bits and
186 * converts the two readings into a single value and turns off gain bit
188 static int mrstouch_ts_chan_read(u16 offset, u16 chan, u16 *vp, u16 *vm)
194 result = PMIC_REG_ADCSNS0H + offset;
196 if (chan == MRST_TS_CHAN12)
199 err = intel_scu_ipc_ioread32(result, &res);
203 /* Mash the bits up */
205 *vp = (res & 0xFF) << 3; /* Highest 7 bits */
206 *vp |= (res >> 8) & 0x07; /* Lower 3 bits */
211 *vm = (res & 0xFF) << 3; /* Highest 7 bits */
212 *vm |= (res >> 8) & 0x07; /* Lower 3 bits */
219 * Enables X, Y and Z bias values
220 * Enables YPYM for X channels and XPXM for Y channels
222 static int mrstouch_ts_bias_set(uint offset, uint bias)
229 chan = PMICADDR0 + offset;
230 start = MRST_TS_CHAN10;
232 for (count = 0; count <= 3; count++) {
234 data[count] = bias | (start + count);
237 return intel_scu_ipc_writev(reg, data, 4);
240 /* To read touch screen channel values */
241 static int mrstouch_nec_adc_read(struct mrstouch_dev *tsdev,
242 u16 *x, u16 *y, u16 *z)
247 /* configure Y bias for X channels */
248 err = mrstouch_ts_bias_set(tsdev->asr, MRST_YBIAS);
252 msleep(WAIT_ADC_COMPLETION);
254 /* read x+ and x- channels */
255 err = mrstouch_ts_chan_read(tsdev->asr, MRST_TS_CHAN10, x, &xm);
259 /* configure x bias for y channels */
260 err = mrstouch_ts_bias_set(tsdev->asr, MRST_XBIAS);
264 msleep(WAIT_ADC_COMPLETION);
266 /* read y+ and y- channels */
267 err = mrstouch_ts_chan_read(tsdev->asr, MRST_TS_CHAN12, y, &ym);
271 /* configure z bias for x and y channels */
272 err = mrstouch_ts_bias_set(tsdev->asr, MRST_ZBIAS);
276 msleep(WAIT_ADC_COMPLETION);
278 /* read z+ and z- channels */
279 err = mrstouch_ts_chan_read(tsdev->asr, MRST_TS_CHAN10, z, &zm);
286 dev_err(tsdev->dev, "ipc error during adc read\n");
291 /*************************** Freescale Interface ************************/
293 static int mrstouch_fs_adc_read_prepare(struct mrstouch_dev *tsdev)
301 err = intel_scu_ipc_update_register(PMIC_REG_MADCINT, 0x00, 0x02);
305 chan = PMICADDR0 + tsdev->asr;
308 for (count = 0; count <= 3; count++) {
312 reg[count] = chan++; /* Dummy */
315 err = intel_scu_ipc_writev(reg, data, 5);
319 msleep(WAIT_ADC_COMPLETION);
322 for (count = 0; count <= 3; count++) {
326 reg[count] = chan++; /* Dummy */
329 err = intel_scu_ipc_writev(reg, data, 5);
333 msleep(WAIT_ADC_COMPLETION);
336 err = intel_scu_ipc_iowrite32(chan + 2, 0x8A8A8A8A);
340 msleep(WAIT_ADC_COMPLETION);
345 dev_err(tsdev->dev, "ipc error during %s\n", __func__);
349 static int mrstouch_fs_adc_read(struct mrstouch_dev *tsdev,
350 u16 *x, u16 *y, u16 *z)
357 result = PMIC_REG_ADCSNS0H + tsdev->asr;
361 reg[2] = result + 16;
362 reg[3] = result + 17;
364 err = intel_scu_ipc_readv(reg, data, 4);
368 *x = data[0] << 3; /* Higher 7 bits */
369 *x |= data[1] & 0x7; /* Lower 3 bits */
372 *y = data[2] << 3; /* Higher 7 bits */
373 *y |= data[3] & 0x7; /* Lower 3 bits */
377 reg[0] = result + 28;
378 reg[1] = result + 29;
380 err = intel_scu_ipc_readv(reg, data, 4);
384 *z = data[0] << 3; /* Higher 7 bits */
385 *z |= data[1] & 0x7; /* Lower 3 bits */
391 dev_err(tsdev->dev, "ipc error during %s\n", __func__);
395 static int mrstouch_fs_adc_read_finish(struct mrstouch_dev *tsdev)
402 /* Clear all TS channels */
403 chan = PMICADDR0 + tsdev->asr;
404 for (count = 0; count <= 4; count++) {
408 err = intel_scu_ipc_writev(reg, data, 5);
412 for (count = 0; count <= 4; count++) {
416 err = intel_scu_ipc_writev(reg, data, 5);
420 err = intel_scu_ipc_iowrite32(chan + 2, 0x00000000);
425 err = intel_scu_ipc_update_register(PMIC_REG_MADCINT, 0x02, 0x02);
432 dev_err(tsdev->dev, "ipc error during %s\n", __func__);
436 static void mrstouch_report_event(struct input_dev *input,
437 unsigned int x, unsigned int y, unsigned int z)
439 if (z > MRST_PRESSURE_NOMINAL) {
440 /* Pen touched, report button touch and coordinates */
441 input_report_key(input, BTN_TOUCH, 1);
442 input_report_abs(input, ABS_X, x);
443 input_report_abs(input, ABS_Y, y);
445 input_report_key(input, BTN_TOUCH, 0);
448 input_report_abs(input, ABS_PRESSURE, z);
452 /* PENDET interrupt handler */
453 static irqreturn_t mrstouch_pendet_irq(int irq, void *dev_id)
455 struct mrstouch_dev *tsdev = dev_id;
459 * Should we lower thread priority? Probably not, since we are
460 * not spinning but sleeping...
463 if (tsdev->read_prepare(tsdev))
467 if (tsdev->read(tsdev, &x, &y, &z))
470 mrstouch_report_event(tsdev->input, x, y, z);
471 } while (z > MRST_PRESSURE_NOMINAL);
473 tsdev->read_finish(tsdev);
479 /* Utility to read PMIC ID */
480 static int __devinit mrstouch_read_pmic_id(uint *vendor, uint *rev)
485 err = intel_scu_ipc_ioread8(PMIC_REG_ID1, &r);
490 *rev = (r >> 3) & 0x7;
496 * Parse ADC channels to find end of the channel configured by other ADC user
497 * NEC and MAXIM requires 4 channels and FreeScale needs 18 channels
499 static int __devinit mrstouch_chan_parse(struct mrstouch_dev *tsdev)
506 for (i = 0; i < MRSTOUCH_MAX_CHANNELS; i++) {
510 err = intel_scu_ipc_ioread8(PMICADDR0 + i, &r8);
514 if (r8 == END_OF_CHANNEL) {
522 if (tsdev->vendor == PMIC_VENDOR_FS) {
523 if (found && found > (MRSTOUCH_MAX_CHANNELS - 18))
526 if (found && found > (MRSTOUCH_MAX_CHANNELS - 4))
534 * Writes touch screen channels to ADC address selection registers
536 static int __devinit mrstouch_ts_chan_set(uint offset)
542 chan = PMICADDR0 + offset;
543 for (count = 0; count <= 3; count++) {
544 ret = intel_scu_ipc_iowrite8(chan++, MRST_TS_CHAN10 + count);
548 return intel_scu_ipc_iowrite8(chan++, END_OF_CHANNEL);
552 static int __devinit mrstouch_adc_init(struct mrstouch_dev *tsdev)
557 err = mrstouch_read_pmic_id(&tsdev->vendor, &tsdev->rev);
559 dev_err(tsdev->dev, "Unable to read PMIC id\n");
563 switch (tsdev->vendor) {
564 case PMIC_VENDOR_NEC:
565 case PMIC_VENDOR_MAXIM:
566 tsdev->read_prepare = mrstouch_nec_adc_read_prepare;
567 tsdev->read = mrstouch_nec_adc_read;
568 tsdev->read_finish = mrstouch_nec_adc_read_finish;
572 tsdev->read_prepare = mrstouch_fs_adc_read_prepare;
573 tsdev->read = mrstouch_fs_adc_read;
574 tsdev->read_finish = mrstouch_fs_adc_read_finish;
579 "Unsupported touchscreen: %d\n", tsdev->vendor);
583 start = mrstouch_chan_parse(tsdev);
585 dev_err(tsdev->dev, "Unable to parse channels\n");
592 * ADC power on, start, enable PENDET and set loop delay
593 * ADC loop delay is set to 4.5 ms approximately
594 * Loop delay more than this results in jitter in adc readings
595 * Setting loop delay to 0 (continous loop) in MAXIM stops PENDET
596 * interrupt generation sometimes.
599 if (tsdev->vendor == PMIC_VENDOR_FS) {
600 ra = 0xE0 | ADC_LOOP_DELAY0;
603 /* NEC and MAXIm not consistent with loop delay 0 */
604 ra = 0xE0 | ADC_LOOP_DELAY1;
607 /* configure touch screen channels */
608 err = mrstouch_ts_chan_set(tsdev->asr);
613 err = intel_scu_ipc_update_register(PMIC_REG_ADCCNTL1, ra, 0xE7);
617 err = intel_scu_ipc_update_register(PMIC_REG_MADCINT, rm, 0x03);
625 /* Probe function for touch screen driver */
626 static int __devinit mrstouch_probe(struct platform_device *pdev)
628 struct mrstouch_dev *tsdev;
629 struct input_dev *input;
633 irq = platform_get_irq(pdev, 0);
635 dev_err(&pdev->dev, "no interrupt assigned\n");
639 tsdev = kzalloc(sizeof(struct mrstouch_dev), GFP_KERNEL);
640 input = input_allocate_device();
641 if (!tsdev || !input) {
642 dev_err(&pdev->dev, "unable to allocate memory\n");
647 tsdev->dev = &pdev->dev;
648 tsdev->input = input;
651 snprintf(tsdev->phys, sizeof(tsdev->phys),
652 "%s/input0", dev_name(tsdev->dev));
654 err = mrstouch_adc_init(tsdev);
656 dev_err(&pdev->dev, "ADC initialization failed\n");
660 input->name = "mrst_touchscreen";
661 input->phys = tsdev->phys;
662 input->dev.parent = tsdev->dev;
664 input->id.vendor = tsdev->vendor;
665 input->id.version = tsdev->rev;
667 input->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS);
668 input->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH);
670 input_set_abs_params(tsdev->input, ABS_X,
671 MRST_X_MIN, MRST_X_MAX, MRST_X_FUZZ, 0);
672 input_set_abs_params(tsdev->input, ABS_Y,
673 MRST_Y_MIN, MRST_Y_MAX, MRST_Y_FUZZ, 0);
674 input_set_abs_params(tsdev->input, ABS_PRESSURE,
675 MRST_PRESSURE_MIN, MRST_PRESSURE_MAX, 0, 0);
677 err = request_threaded_irq(tsdev->irq, NULL, mrstouch_pendet_irq,
678 0, "mrstouch", tsdev);
680 dev_err(tsdev->dev, "unable to allocate irq\n");
684 err = input_register_device(tsdev->input);
686 dev_err(tsdev->dev, "unable to register input device\n");
690 platform_set_drvdata(pdev, tsdev);
694 free_irq(tsdev->irq, tsdev);
696 input_free_device(input);
701 static int __devexit mrstouch_remove(struct platform_device *pdev)
703 struct mrstouch_dev *tsdev = platform_get_drvdata(pdev);
705 free_irq(tsdev->irq, tsdev);
706 input_unregister_device(tsdev->input);
709 platform_set_drvdata(pdev, NULL);
714 static struct platform_driver mrstouch_driver = {
716 .name = "pmic_touch",
717 .owner = THIS_MODULE,
719 .probe = mrstouch_probe,
720 .remove = __devexit_p(mrstouch_remove),
723 static int __init mrstouch_init(void)
725 return platform_driver_register(&mrstouch_driver);
727 module_init(mrstouch_init);
729 static void __exit mrstouch_exit(void)
731 platform_driver_unregister(&mrstouch_driver);
733 module_exit(mrstouch_exit);
735 MODULE_AUTHOR("Sreedhara Murthy. D.S, sreedhara.ds@intel.com");
736 MODULE_DESCRIPTION("Intel Moorestown Resistive Touch Screen Driver");
737 MODULE_LICENSE("GPL");