drivers/staging/mt29f_spinand/mt29f_spinand.c

   1 /*
   2  * Copyright (c) 2003-2013 Broadcom Corporation
   3  *
   4  * Copyright (c) 2009-2010 Micron Technology, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/delay.h>
  19 #include <linux/mtd/mtd.h>
  20 #include <linux/mtd/partitions.h>
  21 #include <linux/mtd/nand.h>
  22 #include <linux/spi/spi.h>
  23
  24 #include "mt29f_spinand.h"
  25
  26 #define BUFSIZE (10 * 64 * 2048)
  27 #define CACHE_BUF 2112
  28 /*
  29  * OOB area specification layout:  Total 32 available free bytes.
  30  */
  31
  32 static inline struct spinand_state *mtd_to_state(struct mtd_info *mtd)
  33 {
  34         struct nand_chip *chip = (struct nand_chip *)mtd->priv;
  35         struct spinand_info *info = (struct spinand_info *)chip->priv;
  36         struct spinand_state *state = (struct spinand_state *)info->priv;
  37
  38         return state;
  39 }
  40
  41 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
  42 static int enable_hw_ecc;
  43 static int enable_read_hw_ecc;
  44
  45 static struct nand_ecclayout spinand_oob_64 = {
  46         .eccbytes = 24,
  47         .eccpos = {
  48                 1, 2, 3, 4, 5, 6,
  49                 17, 18, 19, 20, 21, 22,
  50                 33, 34, 35, 36, 37, 38,
  51                 49, 50, 51, 52, 53, 54, },
  52         .oobavail = 32,
  53         .oobfree = {
  54                 {.offset = 8,
  55                         .length = 8},
  56                 {.offset = 24,
  57                         .length = 8},
  58                 {.offset = 40,
  59                         .length = 8},
  60                 {.offset = 56,
  61                         .length = 8},
  62         }
  63 };
  64 #endif
  65
  66 /*
  67  * spinand_cmd - to process a command to send to the SPI Nand
  68  * Description:
  69  *    Set up the command buffer to send to the SPI controller.
  70  *    The command buffer has to initialized to 0.
  71  */
  72
  73 static int spinand_cmd(struct spi_device *spi, struct spinand_cmd *cmd)
  74 {
  75         struct spi_message message;
  76         struct spi_transfer x[4];
  77         u8 dummy = 0xff;
  78
  79         spi_message_init(&message);
  80         memset(x, 0, sizeof(x));
  81
  82         x[0].len = 1;
  83         x[0].tx_buf = &cmd->cmd;
  84         spi_message_add_tail(&x[0], &message);
  85
  86         if (cmd->n_addr) {
  87                 x[1].len = cmd->n_addr;
  88                 x[1].tx_buf = cmd->addr;
  89                 spi_message_add_tail(&x[1], &message);
  90         }
  91
  92         if (cmd->n_dummy) {
  93                 x[2].len = cmd->n_dummy;
  94                 x[2].tx_buf = &dummy;
  95                 spi_message_add_tail(&x[2], &message);
  96         }
  97
  98         if (cmd->n_tx) {
  99                 x[3].len = cmd->n_tx;
 100                 x[3].tx_buf = cmd->tx_buf;
 101                 spi_message_add_tail(&x[3], &message);
 102         }
 103
 104         if (cmd->n_rx) {
 105                 x[3].len = cmd->n_rx;
 106                 x[3].rx_buf = cmd->rx_buf;
 107                 spi_message_add_tail(&x[3], &message);
 108         }
 109
 110         return spi_sync(spi, &message);
 111 }
 112
 113 /*
 114  * spinand_read_id- Read SPI Nand ID
 115  * Description:
 116  *    Read ID: read two ID bytes from the SPI Nand device
 117  */
 118 static int spinand_read_id(struct spi_device *spi_nand, u8 *id)
 119 {
 120         int retval;
 121         u8 nand_id[3];
 122         struct spinand_cmd cmd = {0};
 123
 124         cmd.cmd = CMD_READ_ID;
 125         cmd.n_rx = 3;
 126         cmd.rx_buf = &nand_id[0];
 127
 128         retval = spinand_cmd(spi_nand, &cmd);
 129         if (retval < 0) {
 130                 dev_err(&spi_nand->dev, "error %d reading id\n", retval);
 131                 return retval;
 132         }
 133         id[0] = nand_id[1];
 134         id[1] = nand_id[2];
 135         return retval;
 136 }
 137
 138 /*
 139  * spinand_read_status- send command 0xf to the SPI Nand status register
 140  * Description:
 141  *    After read, write, or erase, the Nand device is expected to set the
 142  *    busy status.
 143  *    This function is to allow reading the status of the command: read,
 144  *    write, and erase.
 145  *    Once the status turns to be ready, the other status bits also are
 146  *    valid status bits.
 147  */
 148 static int spinand_read_status(struct spi_device *spi_nand, uint8_t *status)
 149 {
 150         struct spinand_cmd cmd = {0};
 151         int ret;
 152
 153         cmd.cmd = CMD_READ_REG;
 154         cmd.n_addr = 1;
 155         cmd.addr[0] = REG_STATUS;
 156         cmd.n_rx = 1;
 157         cmd.rx_buf = status;
 158
 159         ret = spinand_cmd(spi_nand, &cmd);
 160         if (ret < 0)
 161                 dev_err(&spi_nand->dev, "err: %d read status register\n", ret);
 162
 163         return ret;
 164 }
 165
 166 #define MAX_WAIT_JIFFIES  (40 * HZ)
 167 static int wait_till_ready(struct spi_device *spi_nand)
 168 {
 169         unsigned long deadline;
 170         int retval;
 171         u8 stat = 0;
 172
 173         deadline = jiffies + MAX_WAIT_JIFFIES;
 174         do {
 175                 retval = spinand_read_status(spi_nand, &stat);
 176                 if (retval < 0)
 177                         return -1;
 178                 else if (!(stat & 0x1))
 179                         break;
 180
 181                 cond_resched();
 182         } while (!time_after_eq(jiffies, deadline));
 183
 184         if ((stat & 0x1) == 0)
 185                 return 0;
 186
 187         return -1;
 188 }
 189
 190 /**
 191  * spinand_get_otp- send command 0xf to read the SPI Nand OTP register
 192  * Description:
 193  *   There is one bit( bit 0x10 ) to set or to clear the internal ECC.
 194  *   Enable chip internal ECC, set the bit to 1
 195  *   Disable chip internal ECC, clear the bit to 0
 196  */
 197 static int spinand_get_otp(struct spi_device *spi_nand, u8 *otp)
 198 {
 199         struct spinand_cmd cmd = {0};
 200         int retval;
 201
 202         cmd.cmd = CMD_READ_REG;
 203         cmd.n_addr = 1;
 204         cmd.addr[0] = REG_OTP;
 205         cmd.n_rx = 1;
 206         cmd.rx_buf = otp;
 207
 208         retval = spinand_cmd(spi_nand, &cmd);
 209         if (retval < 0)
 210                 dev_err(&spi_nand->dev, "error %d get otp\n", retval);
 211         return retval;
 212 }
 213
 214 /**
 215  * spinand_set_otp- send command 0x1f to write the SPI Nand OTP register
 216  * Description:
 217  *   There is one bit( bit 0x10 ) to set or to clear the internal ECC.
 218  *   Enable chip internal ECC, set the bit to 1
 219  *   Disable chip internal ECC, clear the bit to 0
 220  */
 221 static int spinand_set_otp(struct spi_device *spi_nand, u8 *otp)
 222 {
 223         int retval;
 224         struct spinand_cmd cmd = {0};
 225
 226         cmd.cmd = CMD_WRITE_REG,
 227         cmd.n_addr = 1,
 228         cmd.addr[0] = REG_OTP,
 229         cmd.n_tx = 1,
 230         cmd.tx_buf = otp,
 231
 232         retval = spinand_cmd(spi_nand, &cmd);
 233         if (retval < 0)
 234                 dev_err(&spi_nand->dev, "error %d set otp\n", retval);
 235
 236         return retval;
 237 }
 238
 239 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
 240 /**
 241  * spinand_enable_ecc- send command 0x1f to write the SPI Nand OTP register
 242  * Description:
 243  *   There is one bit( bit 0x10 ) to set or to clear the internal ECC.
 244  *   Enable chip internal ECC, set the bit to 1
 245  *   Disable chip internal ECC, clear the bit to 0
 246  */
 247 static int spinand_enable_ecc(struct spi_device *spi_nand)
 248 {
 249         int retval;
 250         u8 otp = 0;
 251
 252         retval = spinand_get_otp(spi_nand, &otp);
 253         if (retval < 0)
 254                 return retval;
 255
 256         if ((otp & OTP_ECC_MASK) == OTP_ECC_MASK)
 257                 return 0;
 258         otp |= OTP_ECC_MASK;
 259         retval = spinand_set_otp(spi_nand, &otp);
 260         if (retval < 0)
 261                 return retval;
 262         return spinand_get_otp(spi_nand, &otp);
 263 }
 264 #endif
 265
 266 static int spinand_disable_ecc(struct spi_device *spi_nand)
 267 {
 268         int retval;
 269         u8 otp = 0;
 270
 271         retval = spinand_get_otp(spi_nand, &otp);
 272         if (retval < 0)
 273                 return retval;
 274
 275         if ((otp & OTP_ECC_MASK) == OTP_ECC_MASK) {
 276                 otp &= ~OTP_ECC_MASK;
 277                 retval = spinand_set_otp(spi_nand, &otp);
 278                 if (retval < 0)
 279                         return retval;
 280                 return spinand_get_otp(spi_nand, &otp);
 281         }
 282         return 0;
 283 }
 284
 285 /**
 286  * spinand_write_enable- send command 0x06 to enable write or erase the
 287  * Nand cells
 288  * Description:
 289  *   Before write and erase the Nand cells, the write enable has to be set.
 290  *   After the write or erase, the write enable bit is automatically
 291  *   cleared (status register bit 2)
 292  *   Set the bit 2 of the status register has the same effect
 293  */
 294 static int spinand_write_enable(struct spi_device *spi_nand)
 295 {
 296         struct spinand_cmd cmd = {0};
 297
 298         cmd.cmd = CMD_WR_ENABLE;
 299         return spinand_cmd(spi_nand, &cmd);
 300 }
 301
 302 static int spinand_read_page_to_cache(struct spi_device *spi_nand, u16 page_id)
 303 {
 304         struct spinand_cmd cmd = {0};
 305         u16 row;
 306
 307         row = page_id;
 308         cmd.cmd = CMD_READ;
 309         cmd.n_addr = 3;
 310         cmd.addr[1] = (u8)((row & 0xff00) >> 8);
 311         cmd.addr[2] = (u8)(row & 0x00ff);
 312
 313         return spinand_cmd(spi_nand, &cmd);
 314 }
 315
 316 /*
 317  * spinand_read_from_cache- send command 0x03 to read out the data from the
 318  * cache register(2112 bytes max)
 319  * Description:
 320  *   The read can specify 1 to 2112 bytes of data read at the corresponding
 321  *   locations.
 322  *   No tRd delay.
 323  */
 324 static int spinand_read_from_cache(struct spi_device *spi_nand, u16 page_id,
 325                 u16 byte_id, u16 len, u8 *rbuf)
 326 {
 327         struct spinand_cmd cmd = {0};
 328         u16 column;
 329
 330         column = byte_id;
 331         cmd.cmd = CMD_READ_RDM;
 332         cmd.n_addr = 3;
 333         cmd.addr[0] = (u8)((column & 0xff00) >> 8);
 334         cmd.addr[0] |= (u8)(((page_id >> 6) & 0x1) << 4);
 335         cmd.addr[1] = (u8)(column & 0x00ff);
 336         cmd.addr[2] = (u8)(0xff);
 337         cmd.n_dummy = 0;
 338         cmd.n_rx = len;
 339         cmd.rx_buf = rbuf;
 340
 341         return spinand_cmd(spi_nand, &cmd);
 342 }
 343
 344 /*
 345  * spinand_read_page-to read a page with:
 346  * @page_id: the physical page number
 347  * @offset:  the location from 0 to 2111
 348  * @len:     number of bytes to read
 349  * @rbuf:    read buffer to hold @len bytes
 350  *
 351  * Description:
 352  *   The read includes two commands to the Nand: 0x13 and 0x03 commands
 353  *   Poll to read status to wait for tRD time.
 354  */
 355 static int spinand_read_page(struct spi_device *spi_nand, u16 page_id,
 356                 u16 offset, u16 len, u8 *rbuf)
 357 {
 358         int ret;
 359         u8 status = 0;
 360
 361 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
 362         if (enable_read_hw_ecc) {
 363                 if (spinand_enable_ecc(spi_nand) < 0)
 364                         dev_err(&spi_nand->dev, "enable HW ECC failed!");
 365         }
 366 #endif
 367         ret = spinand_read_page_to_cache(spi_nand, page_id);
 368         if (ret < 0)
 369                 return ret;
 370
 371         if (wait_till_ready(spi_nand))
 372                 dev_err(&spi_nand->dev, "WAIT timedout!!!\n");
 373
 374         while (1) {
 375                 ret = spinand_read_status(spi_nand, &status);
 376                 if (ret < 0) {
 377                         dev_err(&spi_nand->dev,
 378                                         "err %d read status register\n", ret);
 379                         return ret;
 380                 }
 381
 382                 if ((status & STATUS_OIP_MASK) == STATUS_READY) {
 383                         if ((status & STATUS_ECC_MASK) == STATUS_ECC_ERROR) {
 384                                 dev_err(&spi_nand->dev, "ecc error, page=%d\n",
 385                                                 page_id);
 386                                 return 0;
 387                         }
 388                         break;
 389                 }
 390         }
 391
 392         ret = spinand_read_from_cache(spi_nand, page_id, offset, len, rbuf);
 393         if (ret < 0) {
 394                 dev_err(&spi_nand->dev, "read from cache failed!!\n");
 395                 return ret;
 396         }
 397
 398 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
 399         if (enable_read_hw_ecc) {
 400                 ret = spinand_disable_ecc(spi_nand);
 401                 if (ret < 0) {
 402                         dev_err(&spi_nand->dev, "disable ecc failed!!\n");
 403                         return ret;
 404                 }
 405                 enable_read_hw_ecc = 0;
 406         }
 407 #endif
 408         return ret;
 409 }
 410
 411 /*
 412  * spinand_program_data_to_cache--to write a page to cache with:
 413  * @byte_id: the location to write to the cache
 414  * @len:     number of bytes to write
 415  * @rbuf:    read buffer to hold @len bytes
 416  *
 417  * Description:
 418  *   The write command used here is 0x84--indicating that the cache is
 419  *   not cleared first.
 420  *   Since it is writing the data to cache, there is no tPROG time.
 421  */
 422 static int spinand_program_data_to_cache(struct spi_device *spi_nand,
 423                 u16 page_id, u16 byte_id, u16 len, u8 *wbuf)
 424 {
 425         struct spinand_cmd cmd = {0};
 426         u16 column;
 427
 428         column = byte_id;
 429         cmd.cmd = CMD_PROG_PAGE_CLRCACHE;
 430         cmd.n_addr = 2;
 431         cmd.addr[0] = (u8)((column & 0xff00) >> 8);
 432         cmd.addr[0] |= (u8)(((page_id >> 6) & 0x1) << 4);
 433         cmd.addr[1] = (u8)(column & 0x00ff);
 434         cmd.n_tx = len;
 435         cmd.tx_buf = wbuf;
 436
 437         return spinand_cmd(spi_nand, &cmd);
 438 }
 439
 440 /**
 441  * spinand_program_execute--to write a page from cache to the Nand array with
 442  * @page_id: the physical page location to write the page.
 443  *
 444  * Description:
 445  *   The write command used here is 0x10--indicating the cache is writing to
 446  *   the Nand array.
 447  *   Need to wait for tPROG time to finish the transaction.
 448  */
 449 static int spinand_program_execute(struct spi_device *spi_nand, u16 page_id)
 450 {
 451         struct spinand_cmd cmd = {0};
 452         u16 row;
 453
 454         row = page_id;
 455         cmd.cmd = CMD_PROG_PAGE_EXC;
 456         cmd.n_addr = 3;
 457         cmd.addr[1] = (u8)((row & 0xff00) >> 8);
 458         cmd.addr[2] = (u8)(row & 0x00ff);
 459
 460         return spinand_cmd(spi_nand, &cmd);
 461 }
 462
 463 /**
 464  * spinand_program_page--to write a page with:
 465  * @page_id: the physical page location to write the page.
 466  * @offset:  the location from the cache starting from 0 to 2111
 467  * @len:     the number of bytes to write
 468  * @wbuf:    the buffer to hold the number of bytes
 469  *
 470  * Description:
 471  *   The commands used here are 0x06, 0x84, and 0x10--indicating that
 472  *   the write enable is first sent, the write cache command, and the
 473  *   write execute command.
 474  *   Poll to wait for the tPROG time to finish the transaction.
 475  */
 476 static int spinand_program_page(struct spi_device *spi_nand,
 477                 u16 page_id, u16 offset, u16 len, u8 *buf)
 478 {
 479         int retval;
 480         u8 status = 0;
 481         uint8_t *wbuf;
 482 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
 483         unsigned int i, j;
 484
 485         enable_read_hw_ecc = 0;
 486         wbuf = devm_kzalloc(&spi_nand->dev, CACHE_BUF, GFP_KERNEL);
 487         spinand_read_page(spi_nand, page_id, 0, CACHE_BUF, wbuf);
 488
 489         for (i = offset, j = 0; i < len; i++, j++)
 490                 wbuf[i] &= buf[j];
 491
 492         if (enable_hw_ecc) {
 493                 retval = spinand_enable_ecc(spi_nand);
 494                 if (retval < 0) {
 495                         dev_err(&spi_nand->dev, "enable ecc failed!!\n");
 496                         return retval;
 497                 }
 498         }
 499 #else
 500         wbuf = buf;
 501 #endif
 502         retval = spinand_write_enable(spi_nand);
 503         if (retval < 0) {
 504                 dev_err(&spi_nand->dev, "write enable failed!!\n");
 505                 return retval;
 506         }
 507         if (wait_till_ready(spi_nand))
 508                 dev_err(&spi_nand->dev, "wait timedout!!!\n");
 509
 510         retval = spinand_program_data_to_cache(spi_nand, page_id,
 511                         offset, len, wbuf);
 512         if (retval < 0)
 513                 return retval;
 514         retval = spinand_program_execute(spi_nand, page_id);
 515         if (retval < 0)
 516                 return retval;
 517         while (1) {
 518                 retval = spinand_read_status(spi_nand, &status);
 519                 if (retval < 0) {
 520                         dev_err(&spi_nand->dev,
 521                                         "error %d reading status register\n",
 522                                         retval);
 523                         return retval;
 524                 }
 525
 526                 if ((status & STATUS_OIP_MASK) == STATUS_READY) {
 527                         if ((status & STATUS_P_FAIL_MASK) == STATUS_P_FAIL) {
 528                                 dev_err(&spi_nand->dev,
 529                                         "program error, page %d\n", page_id);
 530                                 return -1;
 531                         }
 532                         break;
 533                 }
 534         }
 535 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
 536         if (enable_hw_ecc) {
 537                 retval = spinand_disable_ecc(spi_nand);
 538                 if (retval < 0) {
 539                         dev_err(&spi_nand->dev, "disable ecc failed!!\n");
 540                         return retval;
 541                 }
 542                 enable_hw_ecc = 0;
 543         }
 544 #endif
 545
 546         return 0;
 547 }
 548
 549 /**
 550  * spinand_erase_block_erase--to erase a page with:
 551  * @block_id: the physical block location to erase.
 552  *
 553  * Description:
 554  *   The command used here is 0xd8--indicating an erase command to erase
 555  *   one block--64 pages
 556  *   Need to wait for tERS.
 557  */
 558 static int spinand_erase_block_erase(struct spi_device *spi_nand, u16 block_id)
 559 {
 560         struct spinand_cmd cmd = {0};
 561         u16 row;
 562
 563         row = block_id;
 564         cmd.cmd = CMD_ERASE_BLK;
 565         cmd.n_addr = 3;
 566         cmd.addr[1] = (u8)((row & 0xff00) >> 8);
 567         cmd.addr[2] = (u8)(row & 0x00ff);
 568
 569         return spinand_cmd(spi_nand, &cmd);
 570 }
 571
 572 /**
 573  * spinand_erase_block--to erase a page with:
 574  * @block_id: the physical block location to erase.
 575  *
 576  * Description:
 577  *   The commands used here are 0x06 and 0xd8--indicating an erase
 578  *   command to erase one block--64 pages
 579  *   It will first to enable the write enable bit (0x06 command),
 580  *   and then send the 0xd8 erase command
 581  *   Poll to wait for the tERS time to complete the tranaction.
 582  */
 583 static int spinand_erase_block(struct spi_device *spi_nand, u16 block_id)
 584 {
 585         int retval;
 586         u8 status = 0;
 587
 588         retval = spinand_write_enable(spi_nand);
 589         if (wait_till_ready(spi_nand))
 590                 dev_err(&spi_nand->dev, "wait timedout!!!\n");
 591
 592         retval = spinand_erase_block_erase(spi_nand, block_id);
 593         while (1) {
 594                 retval = spinand_read_status(spi_nand, &status);
 595                 if (retval < 0) {
 596                         dev_err(&spi_nand->dev,
 597                                         "error %d reading status register\n",
 598                                         (int)retval);
 599                         return retval;
 600                 }
 601
 602                 if ((status & STATUS_OIP_MASK) == STATUS_READY) {
 603                         if ((status & STATUS_E_FAIL_MASK) == STATUS_E_FAIL) {
 604                                 dev_err(&spi_nand->dev,
 605                                         "erase error, block %d\n", block_id);
 606                                 return -1;
 607                         }
 608                         break;
 609                 }
 610         }
 611         return 0;
 612 }
 613
 614 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
 615 static int spinand_write_page_hwecc(struct mtd_info *mtd,
 616                 struct nand_chip *chip, const uint8_t *buf, int oob_required)
 617 {
 618         const uint8_t *p = buf;
 619         int eccsize = chip->ecc.size;
 620         int eccsteps = chip->ecc.steps;
 621
 622         enable_hw_ecc = 1;
 623         chip->write_buf(mtd, p, eccsize * eccsteps);
 624         return 0;
 625 }
 626
 627 static int spinand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
 628                 uint8_t *buf, int oob_required, int page)
 629 {
 630         int retval;
 631         u8 status;
 632         uint8_t *p = buf;
 633         int eccsize = chip->ecc.size;
 634         int eccsteps = chip->ecc.steps;
 635         struct spinand_info *info = (struct spinand_info *)chip->priv;
 636
 637         enable_read_hw_ecc = 1;
 638
 639         chip->read_buf(mtd, p, eccsize * eccsteps);
 640         if (oob_required)
 641                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 642
 643         while (1) {
 644                 retval = spinand_read_status(info->spi, &status);
 645                 if (retval < 0) {
 646                         dev_err(&mtd->dev,
 647                                         "error %d reading status register\n",
 648                                         retval);
 649                         return retval;
 650                 }
 651
 652                 if ((status & STATUS_OIP_MASK) == STATUS_READY) {
 653                         if ((status & STATUS_ECC_MASK) == STATUS_ECC_ERROR) {
 654                                 pr_info("spinand: ECC error\n");
 655                                 mtd->ecc_stats.failed++;
 656                         } else if ((status & STATUS_ECC_MASK) ==
 657                                         STATUS_ECC_1BIT_CORRECTED)
 658                                 mtd->ecc_stats.corrected++;
 659                         break;
 660                 }
 661         }
 662         return 0;
 663 }
 664 #endif
 665
 666 static void spinand_select_chip(struct mtd_info *mtd, int dev)
 667 {
 668 }
 669
 670 static uint8_t spinand_read_byte(struct mtd_info *mtd)
 671 {
 672         struct spinand_state *state = mtd_to_state(mtd);
 673         u8 data;
 674
 675         data = state->buf[state->buf_ptr];
 676         state->buf_ptr++;
 677         return data;
 678 }
 679
 680
 681 static int spinand_wait(struct mtd_info *mtd, struct nand_chip *chip)
 682 {
 683         struct spinand_info *info = (struct spinand_info *)chip->priv;
 684
 685         unsigned long timeo = jiffies;
 686         int retval, state = chip->state;
 687         u8 status;
 688
 689         if (state == FL_ERASING)
 690                 timeo += (HZ * 400) / 1000;
 691         else
 692                 timeo += (HZ * 20) / 1000;
 693
 694         while (time_before(jiffies, timeo)) {
 695                 retval = spinand_read_status(info->spi, &status);
 696                 if (retval < 0) {
 697                         dev_err(&mtd->dev,
 698                                         "error %d reading status register\n",
 699                                         retval);
 700                         return retval;
 701                 }
 702
 703                 if ((status & STATUS_OIP_MASK) == STATUS_READY)
 704                         return 0;
 705
 706                 cond_resched();
 707         }
 708         return 0;
 709 }
 710
 711 static void spinand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 712 {
 713         struct spinand_state *state = mtd_to_state(mtd);
 714
 715         memcpy(state->buf + state->buf_ptr, buf, len);
 716         state->buf_ptr += len;
 717 }
 718
 719 static void spinand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 720 {
 721         struct spinand_state *state = mtd_to_state(mtd);
 722
 723         memcpy(buf, state->buf + state->buf_ptr, len);
 724         state->buf_ptr += len;
 725 }
 726
 727 /*
 728  * spinand_reset- send RESET command "0xff" to the Nand device.
 729  */
 730 static void spinand_reset(struct spi_device *spi_nand)
 731 {
 732         struct spinand_cmd cmd = {0};
 733
 734         cmd.cmd = CMD_RESET;
 735
 736         if (spinand_cmd(spi_nand, &cmd) < 0)
 737                 pr_info("spinand reset failed!\n");
 738
 739         /* elapse 1ms before issuing any other command */
 740         udelay(1000);
 741
 742         if (wait_till_ready(spi_nand))
 743                 dev_err(&spi_nand->dev, "wait timedout!\n");
 744 }
 745
 746 static void spinand_cmdfunc(struct mtd_info *mtd, unsigned int command,
 747                 int column, int page)
 748 {
 749         struct nand_chip *chip = (struct nand_chip *)mtd->priv;
 750         struct spinand_info *info = (struct spinand_info *)chip->priv;
 751         struct spinand_state *state = (struct spinand_state *)info->priv;
 752
 753         switch (command) {
 754         /*
 755          * READ0 - read in first  0x800 bytes
 756          */
 757         case NAND_CMD_READ1:
 758         case NAND_CMD_READ0:
 759                 state->buf_ptr = 0;
 760                 spinand_read_page(info->spi, page, 0x0, 0x840, state->buf);
 761                 break;
 762         /* READOOB reads only the OOB because no ECC is performed. */
 763         case NAND_CMD_READOOB:
 764                 state->buf_ptr = 0;
 765                 spinand_read_page(info->spi, page, 0x800, 0x40, state->buf);
 766                 break;
 767         case NAND_CMD_RNDOUT:
 768                 state->buf_ptr = column;
 769                 break;
 770         case NAND_CMD_READID:
 771                 state->buf_ptr = 0;
 772                 spinand_read_id(info->spi, state->buf);
 773                 break;
 774         case NAND_CMD_PARAM:
 775                 state->buf_ptr = 0;
 776                 break;
 777         /* ERASE1 stores the block and page address */
 778         case NAND_CMD_ERASE1:
 779                 spinand_erase_block(info->spi, page);
 780                 break;
 781         /* ERASE2 uses the block and page address from ERASE1 */
 782         case NAND_CMD_ERASE2:
 783                 break;
 784         /* SEQIN sets up the addr buffer and all registers except the length */
 785         case NAND_CMD_SEQIN:
 786                 state->col = column;
 787                 state->row = page;
 788                 state->buf_ptr = 0;
 789                 break;
 790         /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
 791         case NAND_CMD_PAGEPROG:
 792                 spinand_program_page(info->spi, state->row, state->col,
 793                                 state->buf_ptr, state->buf);
 794                 break;
 795         case NAND_CMD_STATUS:
 796                 spinand_get_otp(info->spi, state->buf);
 797                 if (!(state->buf[0] & 0x80))
 798                         state->buf[0] = 0x80;
 799                 state->buf_ptr = 0;
 800                 break;
 801         /* RESET command */
 802         case NAND_CMD_RESET:
 803                 if (wait_till_ready(info->spi))
 804                         dev_err(&info->spi->dev, "WAIT timedout!!!\n");
 805                 /* a minimum of 250us must elapse before issuing RESET cmd*/
 806                 udelay(250);
 807                 spinand_reset(info->spi);
 808                 break;
 809         default:
 810                 dev_err(&mtd->dev, "Unknown CMD: 0x%x\n", command);
 811         }
 812 }
 813
 814 /**
 815  * spinand_lock_block- send write register 0x1f command to the Nand device
 816  *
 817  * Description:
 818  *    After power up, all the Nand blocks are locked.  This function allows
 819  *    one to unlock the blocks, and so it can be written or erased.
 820  */
 821 static int spinand_lock_block(struct spi_device *spi_nand, u8 lock)
 822 {
 823         struct spinand_cmd cmd = {0};
 824         int ret;
 825         u8 otp = 0;
 826
 827         ret = spinand_get_otp(spi_nand, &otp);
 828
 829         cmd.cmd = CMD_WRITE_REG;
 830         cmd.n_addr = 1;
 831         cmd.addr[0] = REG_BLOCK_LOCK;
 832         cmd.n_tx = 1;
 833         cmd.tx_buf = &lock;
 834
 835         ret = spinand_cmd(spi_nand, &cmd);
 836         if (ret < 0)
 837                 dev_err(&spi_nand->dev, "error %d lock block\n", ret);
 838
 839         return ret;
 840 }
 841
 842 /*
 843  * spinand_probe - [spinand Interface]
 844  * @spi_nand: registered device driver.
 845  *
 846  * Description:
 847  *   To set up the device driver parameters to make the device available.
 848  */
 849 static int spinand_probe(struct spi_device *spi_nand)
 850 {
 851         struct mtd_info *mtd;
 852         struct nand_chip *chip;
 853         struct spinand_info *info;
 854         struct spinand_state *state;
 855         struct mtd_part_parser_data ppdata;
 856
 857         info  = devm_kzalloc(&spi_nand->dev, sizeof(struct spinand_info),
 858                         GFP_KERNEL);
 859         if (!info)
 860                 return -ENOMEM;
 861
 862         info->spi = spi_nand;
 863
 864         spinand_lock_block(spi_nand, BL_ALL_UNLOCKED);
 865
 866         state = devm_kzalloc(&spi_nand->dev, sizeof(struct spinand_state),
 867                         GFP_KERNEL);
 868         if (!state)
 869                 return -ENOMEM;
 870
 871         info->priv      = state;
 872         state->buf_ptr  = 0;
 873         state->buf      = devm_kzalloc(&spi_nand->dev, BUFSIZE, GFP_KERNEL);
 874         if (!state->buf)
 875                 return -ENOMEM;
 876
 877         chip = devm_kzalloc(&spi_nand->dev, sizeof(struct nand_chip),
 878                         GFP_KERNEL);
 879         if (!chip)
 880                 return -ENOMEM;
 881
 882 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
 883         chip->ecc.mode  = NAND_ECC_HW;
 884         chip->ecc.size  = 0x200;
 885         chip->ecc.bytes = 0x6;
 886         chip->ecc.steps = 0x4;
 887
 888         chip->ecc.strength = 1;
 889         chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
 890         chip->ecc.layout = &spinand_oob_64;
 891         chip->ecc.read_page = spinand_read_page_hwecc;
 892         chip->ecc.write_page = spinand_write_page_hwecc;
 893 #else
 894         chip->ecc.mode  = NAND_ECC_SOFT;
 895         if (spinand_disable_ecc(spi_nand) < 0)
 896                 pr_info("%s: disable ecc failed!\n", __func__);
 897 #endif
 898
 899         chip->priv      = info;
 900         chip->read_buf  = spinand_read_buf;
 901         chip->write_buf = spinand_write_buf;
 902         chip->read_byte = spinand_read_byte;
 903         chip->cmdfunc   = spinand_cmdfunc;
 904         chip->waitfunc  = spinand_wait;
 905         chip->options   |= NAND_CACHEPRG;
 906         chip->select_chip = spinand_select_chip;
 907
 908         mtd = devm_kzalloc(&spi_nand->dev, sizeof(struct mtd_info), GFP_KERNEL);
 909         if (!mtd)
 910                 return -ENOMEM;
 911
 912         dev_set_drvdata(&spi_nand->dev, mtd);
 913
 914         mtd->priv = chip;
 915         mtd->name = dev_name(&spi_nand->dev);
 916         mtd->owner = THIS_MODULE;
 917         mtd->oobsize = 64;
 918
 919         if (nand_scan(mtd, 1))
 920                 return -ENXIO;
 921
 922         ppdata.of_node = spi_nand->dev.of_node;
 923         return mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
 924 }
 925
 926 /*
 927  * spinand_remove: Remove the device driver
 928  * @spi: the spi device.
 929  *
 930  * Description:
 931  *   To remove the device driver parameters and free up allocated memories.
 932  */
 933 static int spinand_remove(struct spi_device *spi)
 934 {
 935         mtd_device_unregister(dev_get_drvdata(&spi->dev));
 936
 937         return 0;
 938 }
 939
 940 static const struct of_device_id spinand_dt[] = {
 941         { .compatible = "spinand,mt29f", },
 942         {}
 943 };
 944 MODULE_DEVICE_TABLE(of, spinand_dt);
 945
 946 /*
 947  * Device name structure description
 948  */
 949 static struct spi_driver spinand_driver = {
 950         .driver = {
 951                 .name           = "mt29f",
 952                 .owner          = THIS_MODULE,
 953                 .of_match_table = spinand_dt,
 954         },
 955         .probe          = spinand_probe,
 956         .remove         = spinand_remove,
 957 };
 958
 959 module_spi_driver(spinand_driver);
 960
 961 MODULE_DESCRIPTION("SPI NAND driver for Micron");
 962 MODULE_AUTHOR("Henry Pan <hspan@micron.com>, Kamlakant Patel <kamlakant.patel@broadcom.com>");
 963 MODULE_LICENSE("GPL v2");