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44 * "cvmx-usb.c" defines a set of low level USB functions to help
45 * developers create Octeon USB drivers for various operating
46 * systems. These functions provide a generic API to the Octeon
47 * USB blocks, hiding the internal hardware specific
50 * <hr>$Revision: 32636 $<hr>
52 #include <linux/delay.h>
53 #include <asm/octeon/cvmx.h>
54 #include <asm/octeon/octeon.h>
55 #include <asm/octeon/cvmx-sysinfo.h>
56 #include "cvmx-usbnx-defs.h"
57 #include "cvmx-usbcx-defs.h"
59 #include <asm/octeon/cvmx-helper.h>
60 #include <asm/octeon/cvmx-helper-board.h>
62 #define CVMX_PREFETCH0(address) CVMX_PREFETCH(address, 0)
63 #define CVMX_PREFETCH128(address) CVMX_PREFETCH(address, 128)
65 #define CVMX_PREFETCH(address, offset) CVMX_PREFETCH_PREF0(address, offset)
66 // normal prefetches that use the pref instruction
67 #define CVMX_PREFETCH_PREFX(X, address, offset) asm volatile ("pref %[type], %[off](%[rbase])" : : [rbase] "d" (address), [off] "I" (offset), [type] "n" (X))
68 #define CVMX_PREFETCH_PREF0(address, offset) CVMX_PREFETCH_PREFX(0, address, offset)
69 #define CVMX_CLZ(result, input) asm ("clz %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input))
71 #define cvmx_wait_usec udelay
72 #define cvmx_le16_to_cpu le16_to_cpu
74 #define MAX_RETRIES 3 /* Maximum number of times to retry failed transactions */
75 #define MAX_PIPES 32 /* Maximum number of pipes that can be open at once */
76 #define MAX_TRANSACTIONS 256 /* Maximum number of outstanding transactions across all pipes */
77 #define MAX_CHANNELS 8 /* Maximum number of hardware channels supported by the USB block */
78 #define MAX_USB_ADDRESS 127 /* The highest valid USB device address */
79 #define MAX_USB_ENDPOINT 15 /* The highest valid USB endpoint number */
80 #define MAX_USB_HUB_PORT 15 /* The highest valid port number on a hub */
81 #define MAX_TRANSFER_BYTES ((1<<19)-1) /* The low level hardware can transfer a maximum of this number of bytes in each transfer. The field is 19 bits wide */
82 #define MAX_TRANSFER_PACKETS ((1<<10)-1) /* The low level hardware can transfer a maximum of this number of packets in each transfer. The field is 10 bits wide */
84 /* These defines disable the normal read and write csr. This is so I can add
85 extra debug stuff to the usb specific version and I won't use the normal
87 #define cvmx_read_csr use_cvmx_usb_read_csr64_instead_of_cvmx_read_csr
88 #define cvmx_write_csr use_cvmx_usb_write_csr64_instead_of_cvmx_write_csr
91 __CVMX_USB_TRANSACTION_FLAGS_IN_USE = 1<<16,
92 } cvmx_usb_transaction_flags_t;
95 USB_CLOCK_TYPE_REF_12,
96 USB_CLOCK_TYPE_REF_24,
97 USB_CLOCK_TYPE_REF_48,
98 USB_CLOCK_TYPE_CRYSTAL_12,
102 * Logical transactions may take numerous low level
103 * transactions, especially when splits are concerned. This
104 * enum represents all of the possible stages a transaction can
105 * be in. Note that split completes are always even. This is so
106 * the NAK handler can backup to the previous low level
107 * transaction with a simple clearing of bit 0.
110 CVMX_USB_STAGE_NON_CONTROL,
111 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE,
112 CVMX_USB_STAGE_SETUP,
113 CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE,
115 CVMX_USB_STAGE_DATA_SPLIT_COMPLETE,
116 CVMX_USB_STAGE_STATUS,
117 CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE,
121 * This structure describes each pending USB transaction
122 * regardless of type. These are linked together to form a list
123 * of pending requests for a pipe.
125 typedef struct cvmx_usb_transaction {
126 struct cvmx_usb_transaction *prev; /**< Transaction before this one in the pipe */
127 struct cvmx_usb_transaction *next; /**< Transaction after this one in the pipe */
128 cvmx_usb_transfer_t type; /**< Type of transaction, duplicated of the pipe */
129 cvmx_usb_transaction_flags_t flags; /**< State flags for this transaction */
130 uint64_t buffer; /**< User's physical buffer address to read/write */
131 int buffer_length; /**< Size of the user's buffer in bytes */
132 uint64_t control_header; /**< For control transactions, physical address of the 8 byte standard header */
133 int iso_start_frame; /**< For ISO transactions, the starting frame number */
134 int iso_number_packets; /**< For ISO transactions, the number of packets in the request */
135 cvmx_usb_iso_packet_t *iso_packets; /**< For ISO transactions, the sub packets in the request */
139 int actual_bytes; /**< Actual bytes transfer for this transaction */
140 cvmx_usb_stage_t stage; /**< For control transactions, the current stage */
141 cvmx_usb_callback_func_t callback; /**< User's callback function when complete */
142 void *callback_data; /**< User's data */
143 } cvmx_usb_transaction_t;
146 * A pipe represents a virtual connection between Octeon and some
147 * USB device. It contains a list of pending request to the device.
149 typedef struct cvmx_usb_pipe {
150 struct cvmx_usb_pipe *prev; /**< Pipe before this one in the list */
151 struct cvmx_usb_pipe *next; /**< Pipe after this one in the list */
152 cvmx_usb_transaction_t *head; /**< The first pending transaction */
153 cvmx_usb_transaction_t *tail; /**< The last pending transaction */
154 uint64_t interval; /**< For periodic pipes, the interval between packets in frames */
155 uint64_t next_tx_frame; /**< The next frame this pipe is allowed to transmit on */
156 cvmx_usb_pipe_flags_t flags; /**< State flags for this pipe */
157 cvmx_usb_speed_t device_speed; /**< Speed of device connected to this pipe */
158 cvmx_usb_transfer_t transfer_type; /**< Type of transaction supported by this pipe */
159 cvmx_usb_direction_t transfer_dir; /**< IN or OUT. Ignored for Control */
160 int multi_count; /**< Max packet in a row for the device */
161 uint16_t max_packet; /**< The device's maximum packet size in bytes */
162 uint8_t device_addr; /**< USB device address at other end of pipe */
163 uint8_t endpoint_num; /**< USB endpoint number at other end of pipe */
164 uint8_t hub_device_addr; /**< Hub address this device is connected to */
165 uint8_t hub_port; /**< Hub port this device is connected to */
166 uint8_t pid_toggle; /**< This toggles between 0/1 on every packet send to track the data pid needed */
167 uint8_t channel; /**< Hardware DMA channel for this pipe */
168 int8_t split_sc_frame; /**< The low order bits of the frame number the split complete should be sent on */
172 cvmx_usb_pipe_t *head; /**< Head of the list, or NULL if empty */
173 cvmx_usb_pipe_t *tail; /**< Tail if the list, or NULL if empty */
174 } cvmx_usb_pipe_list_t;
181 } entry[MAX_CHANNELS+1];
184 } cvmx_usb_tx_fifo_t;
187 * The state of the USB block is stored in this structure
190 int init_flags; /**< Flags passed to initialize */
191 int index; /**< Which USB block this is for */
192 int idle_hardware_channels; /**< Bit set for every idle hardware channel */
193 cvmx_usbcx_hprt_t usbcx_hprt; /**< Stored port status so we don't need to read a CSR to determine splits */
194 cvmx_usb_pipe_t *pipe_for_channel[MAX_CHANNELS]; /**< Map channels to pipes */
195 cvmx_usb_transaction_t *free_transaction_head; /**< List of free transactions head */
196 cvmx_usb_transaction_t *free_transaction_tail; /**< List of free transactions tail */
197 cvmx_usb_pipe_t pipe[MAX_PIPES]; /**< Storage for pipes */
198 cvmx_usb_transaction_t transaction[MAX_TRANSACTIONS]; /**< Storage for transactions */
199 cvmx_usb_callback_func_t callback[__CVMX_USB_CALLBACK_END]; /**< User global callbacks */
200 void *callback_data[__CVMX_USB_CALLBACK_END]; /**< User data for each callback */
201 int indent; /**< Used by debug output to indent functions */
202 cvmx_usb_port_status_t port_status; /**< Last port status used for change notification */
203 cvmx_usb_pipe_list_t free_pipes; /**< List of all pipes that are currently closed */
204 cvmx_usb_pipe_list_t idle_pipes; /**< List of open pipes that have no transactions */
205 cvmx_usb_pipe_list_t active_pipes[4]; /**< Active pipes indexed by transfer type */
206 uint64_t frame_number; /**< Increments every SOF interrupt for time keeping */
207 cvmx_usb_transaction_t *active_split; /**< Points to the current active split, or NULL */
208 cvmx_usb_tx_fifo_t periodic;
209 cvmx_usb_tx_fifo_t nonperiodic;
210 } cvmx_usb_internal_state_t;
212 /* This macro spins on a field waiting for it to reach a value */
213 #define CVMX_WAIT_FOR_FIELD32(address, type, field, op, value, timeout_usec)\
216 uint64_t done = cvmx_get_cycle() + (uint64_t)timeout_usec * \
217 octeon_get_clock_rate() / 1000000; \
221 c.u32 = __cvmx_usb_read_csr32(usb, address); \
222 if (c.s.field op (value)) { \
225 } else if (cvmx_get_cycle() > done) { \
234 /* This macro logically sets a single field in a CSR. It does the sequence
235 read, modify, and write */
236 #define USB_SET_FIELD32(address, type, field, value)\
239 c.u32 = __cvmx_usb_read_csr32(usb, address);\
241 __cvmx_usb_write_csr32(usb, address, c.u32);\
244 /* Returns the IO address to push/pop stuff data from the FIFOs */
245 #define USB_FIFO_ADDRESS(channel, usb_index) (CVMX_USBCX_GOTGCTL(usb_index) + ((channel)+1)*0x1000)
247 static int octeon_usb_get_clock_type(void)
249 switch (cvmx_sysinfo_get()->board_type) {
250 case CVMX_BOARD_TYPE_BBGW_REF:
251 case CVMX_BOARD_TYPE_LANAI2_A:
252 case CVMX_BOARD_TYPE_LANAI2_U:
253 case CVMX_BOARD_TYPE_LANAI2_G:
254 case CVMX_BOARD_TYPE_UBNT_E100:
255 return USB_CLOCK_TYPE_CRYSTAL_12;
257 return USB_CLOCK_TYPE_REF_48;
262 * Read a USB 32bit CSR. It performs the necessary address swizzle
263 * for 32bit CSRs and logs the value in a readable format if
266 * @param usb USB block this access is for
267 * @param address 64bit address to read
269 * @return Result of the read
271 static inline uint32_t __cvmx_usb_read_csr32(cvmx_usb_internal_state_t *usb,
274 uint32_t result = cvmx_read64_uint32(address ^ 4);
281 * Write a USB 32bit CSR. It performs the necessary address
282 * swizzle for 32bit CSRs and logs the value in a readable format
283 * if debugging is on.
285 * @param usb USB block this access is for
286 * @param address 64bit address to write
287 * @param value Value to write
289 static inline void __cvmx_usb_write_csr32(cvmx_usb_internal_state_t *usb,
290 uint64_t address, uint32_t value)
292 cvmx_write64_uint32(address ^ 4, value);
293 cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index));
299 * Read a USB 64bit CSR. It logs the value in a readable format if
302 * @param usb USB block this access is for
303 * @param address 64bit address to read
305 * @return Result of the read
307 static inline uint64_t __cvmx_usb_read_csr64(cvmx_usb_internal_state_t *usb,
310 uint64_t result = cvmx_read64_uint64(address);
317 * Write a USB 64bit CSR. It logs the value in a readable format
318 * if debugging is on.
320 * @param usb USB block this access is for
321 * @param address 64bit address to write
322 * @param value Value to write
324 static inline void __cvmx_usb_write_csr64(cvmx_usb_internal_state_t *usb,
325 uint64_t address, uint64_t value)
327 cvmx_write64_uint64(address, value);
333 * Utility function to convert complete codes into strings
335 * @param complete_code
338 * @return Human readable string
340 static const char *__cvmx_usb_complete_to_string(cvmx_usb_complete_t complete_code)
342 switch (complete_code)
344 case CVMX_USB_COMPLETE_SUCCESS: return "SUCCESS";
345 case CVMX_USB_COMPLETE_SHORT: return "SHORT";
346 case CVMX_USB_COMPLETE_CANCEL: return "CANCEL";
347 case CVMX_USB_COMPLETE_ERROR: return "ERROR";
348 case CVMX_USB_COMPLETE_STALL: return "STALL";
349 case CVMX_USB_COMPLETE_XACTERR: return "XACTERR";
350 case CVMX_USB_COMPLETE_DATATGLERR: return "DATATGLERR";
351 case CVMX_USB_COMPLETE_BABBLEERR: return "BABBLEERR";
352 case CVMX_USB_COMPLETE_FRAMEERR: return "FRAMEERR";
354 return "Update __cvmx_usb_complete_to_string";
360 * Return non zero if this pipe connects to a non HIGH speed
361 * device through a high speed hub.
363 * @param usb USB block this access is for
364 * @param pipe Pipe to check
366 * @return Non zero if we need to do split transactions
368 static inline int __cvmx_usb_pipe_needs_split(cvmx_usb_internal_state_t *usb, cvmx_usb_pipe_t *pipe)
370 return ((pipe->device_speed != CVMX_USB_SPEED_HIGH) && (usb->usbcx_hprt.s.prtspd == CVMX_USB_SPEED_HIGH));
376 * Trivial utility function to return the correct PID for a pipe
378 * @param pipe pipe to check
380 * @return PID for pipe
382 static inline int __cvmx_usb_get_data_pid(cvmx_usb_pipe_t *pipe)
384 if (pipe->pid_toggle)
385 return 2; /* Data1 */
387 return 0; /* Data0 */
392 * Return the number of USB ports supported by this Octeon
393 * chip. If the chip doesn't support USB, or is not supported
394 * by this API, a zero will be returned. Most Octeon chips
395 * support one usb port, but some support two ports.
396 * cvmx_usb_initialize() must be called on independent
397 * cvmx_usb_state_t structures.
399 * @return Number of port, zero if usb isn't supported
401 int cvmx_usb_get_num_ports(void)
405 if (OCTEON_IS_MODEL(OCTEON_CN56XX))
407 else if (OCTEON_IS_MODEL(OCTEON_CN52XX))
409 else if (OCTEON_IS_MODEL(OCTEON_CN50XX))
411 else if (OCTEON_IS_MODEL(OCTEON_CN31XX))
413 else if (OCTEON_IS_MODEL(OCTEON_CN30XX))
424 * Allocate a usb transaction for use
426 * @param usb USB device state populated by
427 * cvmx_usb_initialize().
429 * @return Transaction or NULL
431 static inline cvmx_usb_transaction_t *__cvmx_usb_alloc_transaction(cvmx_usb_internal_state_t *usb)
433 cvmx_usb_transaction_t *t;
434 t = usb->free_transaction_head;
436 usb->free_transaction_head = t->next;
437 if (!usb->free_transaction_head)
438 usb->free_transaction_tail = NULL;
441 memset(t, 0, sizeof(*t));
442 t->flags = __CVMX_USB_TRANSACTION_FLAGS_IN_USE;
450 * Free a usb transaction
452 * @param usb USB device state populated by
453 * cvmx_usb_initialize().
455 * Transaction to free
457 static inline void __cvmx_usb_free_transaction(cvmx_usb_internal_state_t *usb,
458 cvmx_usb_transaction_t *transaction)
460 transaction->flags = 0;
461 transaction->prev = NULL;
462 transaction->next = NULL;
463 if (usb->free_transaction_tail)
464 usb->free_transaction_tail->next = transaction;
466 usb->free_transaction_head = transaction;
467 usb->free_transaction_tail = transaction;
473 * Add a pipe to the tail of a list
474 * @param list List to add pipe to
475 * @param pipe Pipe to add
477 static inline void __cvmx_usb_append_pipe(cvmx_usb_pipe_list_t *list, cvmx_usb_pipe_t *pipe)
480 pipe->prev = list->tail;
482 list->tail->next = pipe;
491 * Remove a pipe from a list
492 * @param list List to remove pipe from
493 * @param pipe Pipe to remove
495 static inline void __cvmx_usb_remove_pipe(cvmx_usb_pipe_list_t *list, cvmx_usb_pipe_t *pipe)
497 if (list->head == pipe) {
498 list->head = pipe->next;
501 list->head->prev = NULL;
505 else if (list->tail == pipe) {
506 list->tail = pipe->prev;
507 list->tail->next = NULL;
511 pipe->prev->next = pipe->next;
512 pipe->next->prev = pipe->prev;
520 * Initialize a USB port for use. This must be called before any
521 * other access to the Octeon USB port is made. The port starts
522 * off in the disabled state.
524 * @param state Pointer to an empty cvmx_usb_state_t structure
525 * that will be populated by the initialize call.
526 * This structure is then passed to all other USB
528 * @param usb_port_number
529 * Which Octeon USB port to initialize.
530 * @param flags Flags to control hardware initialization. See
531 * cvmx_usb_initialize_flags_t for the flag
532 * definitions. Some flags are mandatory.
534 * @return 0 or a negative error code.
536 int cvmx_usb_initialize(cvmx_usb_state_t *state, int usb_port_number,
537 cvmx_usb_initialize_flags_t flags)
539 cvmx_usbnx_clk_ctl_t usbn_clk_ctl;
540 cvmx_usbnx_usbp_ctl_status_t usbn_usbp_ctl_status;
541 cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
543 usb->init_flags = flags;
545 /* Make sure that state is large enough to store the internal state */
546 if (sizeof(*state) < sizeof(*usb))
548 /* At first allow 0-1 for the usb port number */
549 if ((usb_port_number < 0) || (usb_port_number > 1))
551 /* For all chips except 52XX there is only one port */
552 if (!OCTEON_IS_MODEL(OCTEON_CN52XX) && (usb_port_number > 0))
554 /* Try to determine clock type automatically */
555 if ((flags & (CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI |
556 CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND)) == 0) {
557 if (octeon_usb_get_clock_type() == USB_CLOCK_TYPE_CRYSTAL_12)
558 flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI; /* Only 12 MHZ crystals are supported */
560 flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND;
563 if (flags & CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND) {
564 /* Check for auto ref clock frequency */
565 if (!(flags & CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK))
566 switch (octeon_usb_get_clock_type()) {
567 case USB_CLOCK_TYPE_REF_12:
568 flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ;
570 case USB_CLOCK_TYPE_REF_24:
571 flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ;
573 case USB_CLOCK_TYPE_REF_48:
574 flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ;
582 memset(usb, 0, sizeof(usb));
583 usb->init_flags = flags;
585 /* Initialize the USB state structure */
588 usb->index = usb_port_number;
590 /* Initialize the transaction double linked list */
591 usb->free_transaction_head = NULL;
592 usb->free_transaction_tail = NULL;
593 for (i=0; i<MAX_TRANSACTIONS; i++)
594 __cvmx_usb_free_transaction(usb, usb->transaction + i);
595 for (i=0; i<MAX_PIPES; i++)
596 __cvmx_usb_append_pipe(&usb->free_pipes, usb->pipe + i);
599 /* Power On Reset and PHY Initialization */
601 /* 1. Wait for DCOK to assert (nothing to do) */
602 /* 2a. Write USBN0/1_CLK_CTL[POR] = 1 and
603 USBN0/1_CLK_CTL[HRST,PRST,HCLK_RST] = 0 */
604 usbn_clk_ctl.u64 = __cvmx_usb_read_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index));
605 usbn_clk_ctl.s.por = 1;
606 usbn_clk_ctl.s.hrst = 0;
607 usbn_clk_ctl.s.prst = 0;
608 usbn_clk_ctl.s.hclk_rst = 0;
609 usbn_clk_ctl.s.enable = 0;
610 /* 2b. Select the USB reference clock/crystal parameters by writing
611 appropriate values to USBN0/1_CLK_CTL[P_C_SEL, P_RTYPE, P_COM_ON] */
612 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND) {
613 /* The USB port uses 12/24/48MHz 2.5V board clock
614 source at USB_XO. USB_XI should be tied to GND.
615 Most Octeon evaluation boards require this setting */
616 if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) {
617 usbn_clk_ctl.cn31xx.p_rclk = 1; /* From CN31XX,CN30XX manual */
618 usbn_clk_ctl.cn31xx.p_xenbn = 0;
620 else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN50XX))
621 usbn_clk_ctl.cn56xx.p_rtype = 2; /* From CN56XX,CN50XX manual */
623 usbn_clk_ctl.cn52xx.p_rtype = 1; /* From CN52XX manual */
625 switch (flags & CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK) {
626 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ:
627 usbn_clk_ctl.s.p_c_sel = 0;
629 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ:
630 usbn_clk_ctl.s.p_c_sel = 1;
632 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ:
633 usbn_clk_ctl.s.p_c_sel = 2;
638 /* The USB port uses a 12MHz crystal as clock source
639 at USB_XO and USB_XI */
640 if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) {
641 usbn_clk_ctl.cn31xx.p_rclk = 1; /* From CN31XX,CN30XX manual */
642 usbn_clk_ctl.cn31xx.p_xenbn = 1;
644 else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN50XX))
645 usbn_clk_ctl.cn56xx.p_rtype = 0; /* From CN56XX,CN50XX manual */
647 usbn_clk_ctl.cn52xx.p_rtype = 0; /* From CN52XX manual */
649 usbn_clk_ctl.s.p_c_sel = 0;
651 /* 2c. Select the HCLK via writing USBN0/1_CLK_CTL[DIVIDE, DIVIDE2] and
652 setting USBN0/1_CLK_CTL[ENABLE] = 1. Divide the core clock down such
653 that USB is as close as possible to 125Mhz */
655 int divisor = (octeon_get_clock_rate()+125000000-1)/125000000;
656 if (divisor < 4) /* Lower than 4 doesn't seem to work properly */
658 usbn_clk_ctl.s.divide = divisor;
659 usbn_clk_ctl.s.divide2 = 0;
661 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
663 /* 2d. Write USBN0/1_CLK_CTL[HCLK_RST] = 1 */
664 usbn_clk_ctl.s.hclk_rst = 1;
665 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
667 /* 2e. Wait 64 core-clock cycles for HCLK to stabilize */
669 /* 3. Program the power-on reset field in the USBN clock-control register:
670 USBN_CLK_CTL[POR] = 0 */
671 usbn_clk_ctl.s.por = 0;
672 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
674 /* 4. Wait 1 ms for PHY clock to start */
676 /* 5. Program the Reset input from automatic test equipment field in the
677 USBP control and status register: USBN_USBP_CTL_STATUS[ATE_RESET] = 1 */
678 usbn_usbp_ctl_status.u64 = __cvmx_usb_read_csr64(usb, CVMX_USBNX_USBP_CTL_STATUS(usb->index));
679 usbn_usbp_ctl_status.s.ate_reset = 1;
680 __cvmx_usb_write_csr64(usb, CVMX_USBNX_USBP_CTL_STATUS(usb->index),
681 usbn_usbp_ctl_status.u64);
682 /* 6. Wait 10 cycles */
684 /* 7. Clear ATE_RESET field in the USBN clock-control register:
685 USBN_USBP_CTL_STATUS[ATE_RESET] = 0 */
686 usbn_usbp_ctl_status.s.ate_reset = 0;
687 __cvmx_usb_write_csr64(usb, CVMX_USBNX_USBP_CTL_STATUS(usb->index),
688 usbn_usbp_ctl_status.u64);
689 /* 8. Program the PHY reset field in the USBN clock-control register:
690 USBN_CLK_CTL[PRST] = 1 */
691 usbn_clk_ctl.s.prst = 1;
692 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
694 /* 9. Program the USBP control and status register to select host or
695 device mode. USBN_USBP_CTL_STATUS[HST_MODE] = 0 for host, = 1 for
697 usbn_usbp_ctl_status.s.hst_mode = 0;
698 __cvmx_usb_write_csr64(usb, CVMX_USBNX_USBP_CTL_STATUS(usb->index),
699 usbn_usbp_ctl_status.u64);
702 /* 11. Program the hreset_n field in the USBN clock-control register:
703 USBN_CLK_CTL[HRST] = 1 */
704 usbn_clk_ctl.s.hrst = 1;
705 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
707 /* 12. Proceed to USB core initialization */
708 usbn_clk_ctl.s.enable = 1;
709 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
713 /* USB Core Initialization */
715 /* 1. Read USBC_GHWCFG1, USBC_GHWCFG2, USBC_GHWCFG3, USBC_GHWCFG4 to
716 determine USB core configuration parameters. */
718 /* 2. Program the following fields in the global AHB configuration
719 register (USBC_GAHBCFG)
720 DMA mode, USBC_GAHBCFG[DMAEn]: 1 = DMA mode, 0 = slave mode
721 Burst length, USBC_GAHBCFG[HBSTLEN] = 0
722 Nonperiodic TxFIFO empty level (slave mode only),
723 USBC_GAHBCFG[NPTXFEMPLVL]
724 Periodic TxFIFO empty level (slave mode only),
725 USBC_GAHBCFG[PTXFEMPLVL]
726 Global interrupt mask, USBC_GAHBCFG[GLBLINTRMSK] = 1 */
728 cvmx_usbcx_gahbcfg_t usbcx_gahbcfg;
729 /* Due to an errata, CN31XX doesn't support DMA */
730 if (OCTEON_IS_MODEL(OCTEON_CN31XX))
731 usb->init_flags |= CVMX_USB_INITIALIZE_FLAGS_NO_DMA;
732 usbcx_gahbcfg.u32 = 0;
733 usbcx_gahbcfg.s.dmaen = !(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA);
734 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
735 usb->idle_hardware_channels = 0x1; /* Only use one channel with non DMA */
736 else if (OCTEON_IS_MODEL(OCTEON_CN5XXX))
737 usb->idle_hardware_channels = 0xf7; /* CN5XXX have an errata with channel 3 */
739 usb->idle_hardware_channels = 0xff;
740 usbcx_gahbcfg.s.hbstlen = 0;
741 usbcx_gahbcfg.s.nptxfemplvl = 1;
742 usbcx_gahbcfg.s.ptxfemplvl = 1;
743 usbcx_gahbcfg.s.glblintrmsk = 1;
744 __cvmx_usb_write_csr32(usb, CVMX_USBCX_GAHBCFG(usb->index),
747 /* 3. Program the following fields in USBC_GUSBCFG register.
748 HS/FS timeout calibration, USBC_GUSBCFG[TOUTCAL] = 0
749 ULPI DDR select, USBC_GUSBCFG[DDRSEL] = 0
750 USB turnaround time, USBC_GUSBCFG[USBTRDTIM] = 0x5
751 PHY low-power clock select, USBC_GUSBCFG[PHYLPWRCLKSEL] = 0 */
753 cvmx_usbcx_gusbcfg_t usbcx_gusbcfg;
754 usbcx_gusbcfg.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GUSBCFG(usb->index));
755 usbcx_gusbcfg.s.toutcal = 0;
756 usbcx_gusbcfg.s.ddrsel = 0;
757 usbcx_gusbcfg.s.usbtrdtim = 0x5;
758 usbcx_gusbcfg.s.phylpwrclksel = 0;
759 __cvmx_usb_write_csr32(usb, CVMX_USBCX_GUSBCFG(usb->index),
762 /* 4. The software must unmask the following bits in the USBC_GINTMSK
764 OTG interrupt mask, USBC_GINTMSK[OTGINTMSK] = 1
765 Mode mismatch interrupt mask, USBC_GINTMSK[MODEMISMSK] = 1 */
767 cvmx_usbcx_gintmsk_t usbcx_gintmsk;
770 usbcx_gintmsk.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GINTMSK(usb->index));
771 usbcx_gintmsk.s.otgintmsk = 1;
772 usbcx_gintmsk.s.modemismsk = 1;
773 usbcx_gintmsk.s.hchintmsk = 1;
774 usbcx_gintmsk.s.sofmsk = 0;
775 /* We need RX FIFO interrupts if we don't have DMA */
776 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
777 usbcx_gintmsk.s.rxflvlmsk = 1;
778 __cvmx_usb_write_csr32(usb, CVMX_USBCX_GINTMSK(usb->index),
781 /* Disable all channel interrupts. We'll enable them per channel later */
782 for (channel=0; channel<8; channel++)
783 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTMSKX(channel, usb->index), 0);
787 /* Host Port Initialization */
789 /* 1. Program the host-port interrupt-mask field to unmask,
790 USBC_GINTMSK[PRTINT] = 1 */
791 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), cvmx_usbcx_gintmsk_t,
793 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), cvmx_usbcx_gintmsk_t,
795 /* 2. Program the USBC_HCFG register to select full-speed host or
798 cvmx_usbcx_hcfg_t usbcx_hcfg;
799 usbcx_hcfg.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCFG(usb->index));
800 usbcx_hcfg.s.fslssupp = 0;
801 usbcx_hcfg.s.fslspclksel = 0;
802 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCFG(usb->index), usbcx_hcfg.u32);
804 /* 3. Program the port power bit to drive VBUS on the USB,
805 USBC_HPRT[PRTPWR] = 1 */
806 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), cvmx_usbcx_hprt_t, prtpwr, 1);
808 /* Steps 4-15 from the manual are done later in the port enable */
816 * Shutdown a USB port after a call to cvmx_usb_initialize().
817 * The port should be disabled with all pipes closed when this
818 * function is called.
820 * @param state USB device state populated by
821 * cvmx_usb_initialize().
823 * @return 0 or a negative error code.
825 int cvmx_usb_shutdown(cvmx_usb_state_t *state)
827 cvmx_usbnx_clk_ctl_t usbn_clk_ctl;
828 cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
830 /* Make sure all pipes are closed */
831 if (usb->idle_pipes.head ||
832 usb->active_pipes[CVMX_USB_TRANSFER_ISOCHRONOUS].head ||
833 usb->active_pipes[CVMX_USB_TRANSFER_INTERRUPT].head ||
834 usb->active_pipes[CVMX_USB_TRANSFER_CONTROL].head ||
835 usb->active_pipes[CVMX_USB_TRANSFER_BULK].head)
838 /* Disable the clocks and put them in power on reset */
839 usbn_clk_ctl.u64 = __cvmx_usb_read_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index));
840 usbn_clk_ctl.s.enable = 1;
841 usbn_clk_ctl.s.por = 1;
842 usbn_clk_ctl.s.hclk_rst = 1;
843 usbn_clk_ctl.s.prst = 0;
844 usbn_clk_ctl.s.hrst = 0;
845 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
852 * Enable a USB port. After this call succeeds, the USB port is
853 * online and servicing requests.
855 * @param state USB device state populated by
856 * cvmx_usb_initialize().
858 * @return 0 or a negative error code.
860 int cvmx_usb_enable(cvmx_usb_state_t *state)
862 cvmx_usbcx_ghwcfg3_t usbcx_ghwcfg3;
863 cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
865 usb->usbcx_hprt.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPRT(usb->index));
867 /* If the port is already enabled the just return. We don't need to do
869 if (usb->usbcx_hprt.s.prtena)
872 /* If there is nothing plugged into the port then fail immediately */
873 if (!usb->usbcx_hprt.s.prtconnsts) {
877 /* Program the port reset bit to start the reset process */
878 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), cvmx_usbcx_hprt_t, prtrst, 1);
880 /* Wait at least 50ms (high speed), or 10ms (full speed) for the reset
881 process to complete. */
884 /* Program the port reset bit to 0, USBC_HPRT[PRTRST] = 0 */
885 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), cvmx_usbcx_hprt_t, prtrst, 0);
887 /* Wait for the USBC_HPRT[PRTENA]. */
888 if (CVMX_WAIT_FOR_FIELD32(CVMX_USBCX_HPRT(usb->index), cvmx_usbcx_hprt_t,
889 prtena, ==, 1, 100000))
892 /* Read the port speed field to get the enumerated speed, USBC_HPRT[PRTSPD]. */
893 usb->usbcx_hprt.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPRT(usb->index));
894 usbcx_ghwcfg3.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GHWCFG3(usb->index));
896 /* 13. Program the USBC_GRXFSIZ register to select the size of the receive
898 USB_SET_FIELD32(CVMX_USBCX_GRXFSIZ(usb->index), cvmx_usbcx_grxfsiz_t,
899 rxfdep, usbcx_ghwcfg3.s.dfifodepth / 4);
900 /* 14. Program the USBC_GNPTXFSIZ register to select the size and the
901 start address of the non- periodic transmit FIFO for nonperiodic
902 transactions (50%). */
904 cvmx_usbcx_gnptxfsiz_t siz;
905 siz.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GNPTXFSIZ(usb->index));
906 siz.s.nptxfdep = usbcx_ghwcfg3.s.dfifodepth / 2;
907 siz.s.nptxfstaddr = usbcx_ghwcfg3.s.dfifodepth / 4;
908 __cvmx_usb_write_csr32(usb, CVMX_USBCX_GNPTXFSIZ(usb->index), siz.u32);
910 /* 15. Program the USBC_HPTXFSIZ register to select the size and start
911 address of the periodic transmit FIFO for periodic transactions (25%). */
913 cvmx_usbcx_hptxfsiz_t siz;
914 siz.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPTXFSIZ(usb->index));
915 siz.s.ptxfsize = usbcx_ghwcfg3.s.dfifodepth / 4;
916 siz.s.ptxfstaddr = 3 * usbcx_ghwcfg3.s.dfifodepth / 4;
917 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HPTXFSIZ(usb->index), siz.u32);
919 /* Flush all FIFOs */
920 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), cvmx_usbcx_grstctl_t, txfnum, 0x10);
921 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), cvmx_usbcx_grstctl_t, txfflsh, 1);
922 CVMX_WAIT_FOR_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), cvmx_usbcx_grstctl_t,
923 txfflsh, ==, 0, 100);
924 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), cvmx_usbcx_grstctl_t, rxfflsh, 1);
925 CVMX_WAIT_FOR_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), cvmx_usbcx_grstctl_t,
926 rxfflsh, ==, 0, 100);
933 * Disable a USB port. After this call the USB port will not
934 * generate data transfers and will not generate events.
935 * Transactions in process will fail and call their
936 * associated callbacks.
938 * @param state USB device state populated by
939 * cvmx_usb_initialize().
941 * @return 0 or a negative error code.
943 int cvmx_usb_disable(cvmx_usb_state_t *state)
945 cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
947 /* Disable the port */
948 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), cvmx_usbcx_hprt_t, prtena, 1);
954 * Get the current state of the USB port. Use this call to
955 * determine if the usb port has anything connected, is enabled,
956 * or has some sort of error condition. The return value of this
957 * call has "changed" bits to signal of the value of some fields
958 * have changed between calls. These "changed" fields are based
959 * on the last call to cvmx_usb_set_status(). In order to clear
960 * them, you must update the status through cvmx_usb_set_status().
962 * @param state USB device state populated by
963 * cvmx_usb_initialize().
965 * @return Port status information
967 cvmx_usb_port_status_t cvmx_usb_get_status(cvmx_usb_state_t *state)
969 cvmx_usbcx_hprt_t usbc_hprt;
970 cvmx_usb_port_status_t result;
971 cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
973 memset(&result, 0, sizeof(result));
975 usbc_hprt.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPRT(usb->index));
976 result.port_enabled = usbc_hprt.s.prtena;
977 result.port_over_current = usbc_hprt.s.prtovrcurract;
978 result.port_powered = usbc_hprt.s.prtpwr;
979 result.port_speed = usbc_hprt.s.prtspd;
980 result.connected = usbc_hprt.s.prtconnsts;
981 result.connect_change = (result.connected != usb->port_status.connected);
988 * Set the current state of the USB port. The status is used as
989 * a reference for the "changed" bits returned by
990 * cvmx_usb_get_status(). Other than serving as a reference, the
991 * status passed to this function is not used. No fields can be
992 * changed through this call.
994 * @param state USB device state populated by
995 * cvmx_usb_initialize().
997 * Port status to set, most like returned by cvmx_usb_get_status()
999 void cvmx_usb_set_status(cvmx_usb_state_t *state, cvmx_usb_port_status_t port_status)
1001 cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
1002 usb->port_status = port_status;
1009 * Convert a USB transaction into a handle
1011 * @param usb USB device state populated by
1012 * cvmx_usb_initialize().
1013 * @param transaction
1014 * Transaction to get handle for
1018 static inline int __cvmx_usb_get_submit_handle(cvmx_usb_internal_state_t *usb,
1019 cvmx_usb_transaction_t *transaction)
1021 return ((unsigned long)transaction - (unsigned long)usb->transaction) /
1022 sizeof(*transaction);
1028 * Convert a USB pipe into a handle
1030 * @param usb USB device state populated by
1031 * cvmx_usb_initialize().
1032 * @param pipe Pipe to get handle for
1036 static inline int __cvmx_usb_get_pipe_handle(cvmx_usb_internal_state_t *usb,
1037 cvmx_usb_pipe_t *pipe)
1039 return ((unsigned long)pipe - (unsigned long)usb->pipe) / sizeof(*pipe);
1044 * Open a virtual pipe between the host and a USB device. A pipe
1045 * must be opened before data can be transferred between a device
1048 * @param state USB device state populated by
1049 * cvmx_usb_initialize().
1050 * @param flags Optional pipe flags defined in
1051 * cvmx_usb_pipe_flags_t.
1052 * @param device_addr
1053 * USB device address to open the pipe to
1055 * @param endpoint_num
1056 * USB endpoint number to open the pipe to
1058 * @param device_speed
1059 * The speed of the device the pipe is going
1060 * to. This must match the device's speed,
1061 * which may be different than the port speed.
1062 * @param max_packet The maximum packet length the device can
1063 * transmit/receive (low speed=0-8, full
1064 * speed=0-1023, high speed=0-1024). This value
1065 * comes from the standard endpoint descriptor
1066 * field wMaxPacketSize bits <10:0>.
1067 * @param transfer_type
1068 * The type of transfer this pipe is for.
1069 * @param transfer_dir
1070 * The direction the pipe is in. This is not
1071 * used for control pipes.
1072 * @param interval For ISOCHRONOUS and INTERRUPT transfers,
1073 * this is how often the transfer is scheduled
1074 * for. All other transfers should specify
1075 * zero. The units are in frames (8000/sec at
1076 * high speed, 1000/sec for full speed).
1077 * @param multi_count
1078 * For high speed devices, this is the maximum
1079 * allowed number of packet per microframe.
1080 * Specify zero for non high speed devices. This
1081 * value comes from the standard endpoint descriptor
1082 * field wMaxPacketSize bits <12:11>.
1083 * @param hub_device_addr
1084 * Hub device address this device is connected
1085 * to. Devices connected directly to Octeon
1086 * use zero. This is only used when the device
1087 * is full/low speed behind a high speed hub.
1088 * The address will be of the high speed hub,
1089 * not and full speed hubs after it.
1090 * @param hub_port Which port on the hub the device is
1091 * connected. Use zero for devices connected
1092 * directly to Octeon. Like hub_device_addr,
1093 * this is only used for full/low speed
1094 * devices behind a high speed hub.
1096 * @return A non negative value is a pipe handle. Negative
1097 * values are error codes.
1099 int cvmx_usb_open_pipe(cvmx_usb_state_t *state, cvmx_usb_pipe_flags_t flags,
1100 int device_addr, int endpoint_num,
1101 cvmx_usb_speed_t device_speed, int max_packet,
1102 cvmx_usb_transfer_t transfer_type,
1103 cvmx_usb_direction_t transfer_dir, int interval,
1104 int multi_count, int hub_device_addr, int hub_port)
1106 cvmx_usb_pipe_t *pipe;
1107 cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
1109 if (unlikely((device_addr < 0) || (device_addr > MAX_USB_ADDRESS)))
1111 if (unlikely((endpoint_num < 0) || (endpoint_num > MAX_USB_ENDPOINT)))
1113 if (unlikely(device_speed > CVMX_USB_SPEED_LOW))
1115 if (unlikely((max_packet <= 0) || (max_packet > 1024)))
1117 if (unlikely(transfer_type > CVMX_USB_TRANSFER_INTERRUPT))
1119 if (unlikely((transfer_dir != CVMX_USB_DIRECTION_OUT) &&
1120 (transfer_dir != CVMX_USB_DIRECTION_IN)))
1122 if (unlikely(interval < 0))
1124 if (unlikely((transfer_type == CVMX_USB_TRANSFER_CONTROL) && interval))
1126 if (unlikely(multi_count < 0))
1128 if (unlikely((device_speed != CVMX_USB_SPEED_HIGH) &&
1129 (multi_count != 0)))
1131 if (unlikely((hub_device_addr < 0) || (hub_device_addr > MAX_USB_ADDRESS)))
1133 if (unlikely((hub_port < 0) || (hub_port > MAX_USB_HUB_PORT)))
1136 /* Find a free pipe */
1137 pipe = usb->free_pipes.head;
1140 __cvmx_usb_remove_pipe(&usb->free_pipes, pipe);
1141 pipe->flags = flags | __CVMX_USB_PIPE_FLAGS_OPEN;
1142 if ((device_speed == CVMX_USB_SPEED_HIGH) &&
1143 (transfer_dir == CVMX_USB_DIRECTION_OUT) &&
1144 (transfer_type == CVMX_USB_TRANSFER_BULK))
1145 pipe->flags |= __CVMX_USB_PIPE_FLAGS_NEED_PING;
1146 pipe->device_addr = device_addr;
1147 pipe->endpoint_num = endpoint_num;
1148 pipe->device_speed = device_speed;
1149 pipe->max_packet = max_packet;
1150 pipe->transfer_type = transfer_type;
1151 pipe->transfer_dir = transfer_dir;
1152 /* All pipes use interval to rate limit NAK processing. Force an interval
1153 if one wasn't supplied */
1156 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
1157 pipe->interval = interval*8;
1158 /* Force start splits to be schedule on uFrame 0 */
1159 pipe->next_tx_frame = ((usb->frame_number+7)&~7) + pipe->interval;
1162 pipe->interval = interval;
1163 pipe->next_tx_frame = usb->frame_number + pipe->interval;
1165 pipe->multi_count = multi_count;
1166 pipe->hub_device_addr = hub_device_addr;
1167 pipe->hub_port = hub_port;
1168 pipe->pid_toggle = 0;
1169 pipe->split_sc_frame = -1;
1170 __cvmx_usb_append_pipe(&usb->idle_pipes, pipe);
1172 /* We don't need to tell the hardware about this pipe yet since
1173 it doesn't have any submitted requests */
1175 return __cvmx_usb_get_pipe_handle(usb, pipe);
1181 * Poll the RX FIFOs and remove data as needed. This function is only used
1182 * in non DMA mode. It is very important that this function be called quickly
1183 * enough to prevent FIFO overflow.
1185 * @param usb USB device state populated by
1186 * cvmx_usb_initialize().
1188 static void __cvmx_usb_poll_rx_fifo(cvmx_usb_internal_state_t *usb)
1190 cvmx_usbcx_grxstsph_t rx_status;
1196 rx_status.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GRXSTSPH(usb->index));
1197 /* Only read data if IN data is there */
1198 if (rx_status.s.pktsts != 2)
1200 /* Check if no data is available */
1201 if (!rx_status.s.bcnt)
1204 channel = rx_status.s.chnum;
1205 bytes = rx_status.s.bcnt;
1209 /* Get where the DMA engine would have written this data */
1210 address = __cvmx_usb_read_csr64(usb, CVMX_USBNX_DMA0_INB_CHN0(usb->index) + channel*8);
1211 ptr = cvmx_phys_to_ptr(address);
1212 __cvmx_usb_write_csr64(usb, CVMX_USBNX_DMA0_INB_CHN0(usb->index) + channel*8, address + bytes);
1214 /* Loop writing the FIFO data for this packet into memory */
1216 *ptr++ = __cvmx_usb_read_csr32(usb, USB_FIFO_ADDRESS(channel, usb->index));
1226 * Fill the TX hardware fifo with data out of the software
1229 * @param usb USB device state populated by
1230 * cvmx_usb_initialize().
1231 * @param fifo Software fifo to use
1232 * @param available Amount of space in the hardware fifo
1234 * @return Non zero if the hardware fifo was too small and needs
1235 * to be serviced again.
1237 static int __cvmx_usb_fill_tx_hw(cvmx_usb_internal_state_t *usb, cvmx_usb_tx_fifo_t *fifo, int available)
1239 /* We're done either when there isn't anymore space or the software FIFO
1241 while (available && (fifo->head != fifo->tail)) {
1243 const uint32_t *ptr = cvmx_phys_to_ptr(fifo->entry[i].address);
1244 uint64_t csr_address = USB_FIFO_ADDRESS(fifo->entry[i].channel, usb->index) ^ 4;
1245 int words = available;
1247 /* Limit the amount of data to waht the SW fifo has */
1248 if (fifo->entry[i].size <= available) {
1249 words = fifo->entry[i].size;
1251 if (fifo->tail > MAX_CHANNELS)
1255 /* Update the next locations and counts */
1257 fifo->entry[i].address += words * 4;
1258 fifo->entry[i].size -= words;
1260 /* Write the HW fifo data. The read every three writes is due
1261 to an errata on CN3XXX chips */
1263 cvmx_write64_uint32(csr_address, *ptr++);
1264 cvmx_write64_uint32(csr_address, *ptr++);
1265 cvmx_write64_uint32(csr_address, *ptr++);
1266 cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index));
1269 cvmx_write64_uint32(csr_address, *ptr++);
1271 cvmx_write64_uint32(csr_address, *ptr++);
1273 cvmx_write64_uint32(csr_address, *ptr++);
1275 cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index));
1277 return fifo->head != fifo->tail;
1282 * Check the hardware FIFOs and fill them as needed
1284 * @param usb USB device state populated by
1285 * cvmx_usb_initialize().
1287 static void __cvmx_usb_poll_tx_fifo(cvmx_usb_internal_state_t *usb)
1289 if (usb->periodic.head != usb->periodic.tail) {
1290 cvmx_usbcx_hptxsts_t tx_status;
1291 tx_status.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPTXSTS(usb->index));
1292 if (__cvmx_usb_fill_tx_hw(usb, &usb->periodic, tx_status.s.ptxfspcavail))
1293 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), cvmx_usbcx_gintmsk_t, ptxfempmsk, 1);
1295 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), cvmx_usbcx_gintmsk_t, ptxfempmsk, 0);
1298 if (usb->nonperiodic.head != usb->nonperiodic.tail) {
1299 cvmx_usbcx_gnptxsts_t tx_status;
1300 tx_status.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GNPTXSTS(usb->index));
1301 if (__cvmx_usb_fill_tx_hw(usb, &usb->nonperiodic, tx_status.s.nptxfspcavail))
1302 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), cvmx_usbcx_gintmsk_t, nptxfempmsk, 1);
1304 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), cvmx_usbcx_gintmsk_t, nptxfempmsk, 0);
1313 * Fill the TX FIFO with an outgoing packet
1315 * @param usb USB device state populated by
1316 * cvmx_usb_initialize().
1317 * @param channel Channel number to get packet from
1319 static void __cvmx_usb_fill_tx_fifo(cvmx_usb_internal_state_t *usb, int channel)
1321 cvmx_usbcx_hccharx_t hcchar;
1322 cvmx_usbcx_hcspltx_t usbc_hcsplt;
1323 cvmx_usbcx_hctsizx_t usbc_hctsiz;
1324 cvmx_usb_tx_fifo_t *fifo;
1326 /* We only need to fill data on outbound channels */
1327 hcchar.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index));
1328 if (hcchar.s.epdir != CVMX_USB_DIRECTION_OUT)
1331 /* OUT Splits only have data on the start and not the complete */
1332 usbc_hcsplt.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCSPLTX(channel, usb->index));
1333 if (usbc_hcsplt.s.spltena && usbc_hcsplt.s.compsplt)
1336 /* Find out how many bytes we need to fill and convert it into 32bit words */
1337 usbc_hctsiz.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index));
1338 if (!usbc_hctsiz.s.xfersize)
1341 if ((hcchar.s.eptype == CVMX_USB_TRANSFER_INTERRUPT) ||
1342 (hcchar.s.eptype == CVMX_USB_TRANSFER_ISOCHRONOUS))
1343 fifo = &usb->periodic;
1345 fifo = &usb->nonperiodic;
1347 fifo->entry[fifo->head].channel = channel;
1348 fifo->entry[fifo->head].address = __cvmx_usb_read_csr64(usb, CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) + channel*8);
1349 fifo->entry[fifo->head].size = (usbc_hctsiz.s.xfersize+3)>>2;
1351 if (fifo->head > MAX_CHANNELS)
1354 __cvmx_usb_poll_tx_fifo(usb);
1361 * Perform channel specific setup for Control transactions. All
1362 * the generic stuff will already have been done in
1363 * __cvmx_usb_start_channel()
1365 * @param usb USB device state populated by
1366 * cvmx_usb_initialize().
1367 * @param channel Channel to setup
1368 * @param pipe Pipe for control transaction
1370 static void __cvmx_usb_start_channel_control(cvmx_usb_internal_state_t *usb,
1372 cvmx_usb_pipe_t *pipe)
1374 cvmx_usb_transaction_t *transaction = pipe->head;
1375 cvmx_usb_control_header_t *header = cvmx_phys_to_ptr(transaction->control_header);
1376 int bytes_to_transfer = transaction->buffer_length - transaction->actual_bytes;
1377 int packets_to_transfer;
1378 cvmx_usbcx_hctsizx_t usbc_hctsiz;
1380 usbc_hctsiz.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index));
1382 switch (transaction->stage) {
1383 case CVMX_USB_STAGE_NON_CONTROL:
1384 case CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE:
1385 cvmx_dprintf("%s: ERROR - Non control stage\n", __FUNCTION__);
1387 case CVMX_USB_STAGE_SETUP:
1388 usbc_hctsiz.s.pid = 3; /* Setup */
1389 bytes_to_transfer = sizeof(*header);
1390 /* All Control operations start with a setup going OUT */
1391 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), cvmx_usbcx_hccharx_t, epdir, CVMX_USB_DIRECTION_OUT);
1392 /* Setup send the control header instead of the buffer data. The
1393 buffer data will be used in the next stage */
1394 __cvmx_usb_write_csr64(usb, CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) + channel*8, transaction->control_header);
1396 case CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE:
1397 usbc_hctsiz.s.pid = 3; /* Setup */
1398 bytes_to_transfer = 0;
1399 /* All Control operations start with a setup going OUT */
1400 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), cvmx_usbcx_hccharx_t, epdir, CVMX_USB_DIRECTION_OUT);
1401 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel, usb->index), cvmx_usbcx_hcspltx_t, compsplt, 1);
1403 case CVMX_USB_STAGE_DATA:
1404 usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
1405 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
1406 if (header->s.request_type & 0x80)
1407 bytes_to_transfer = 0;
1408 else if (bytes_to_transfer > pipe->max_packet)
1409 bytes_to_transfer = pipe->max_packet;
1411 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index),
1412 cvmx_usbcx_hccharx_t, epdir,
1413 ((header->s.request_type & 0x80) ?
1414 CVMX_USB_DIRECTION_IN :
1415 CVMX_USB_DIRECTION_OUT));
1417 case CVMX_USB_STAGE_DATA_SPLIT_COMPLETE:
1418 usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
1419 if (!(header->s.request_type & 0x80))
1420 bytes_to_transfer = 0;
1421 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index),
1422 cvmx_usbcx_hccharx_t, epdir,
1423 ((header->s.request_type & 0x80) ?
1424 CVMX_USB_DIRECTION_IN :
1425 CVMX_USB_DIRECTION_OUT));
1426 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel, usb->index), cvmx_usbcx_hcspltx_t, compsplt, 1);
1428 case CVMX_USB_STAGE_STATUS:
1429 usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
1430 bytes_to_transfer = 0;
1431 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), cvmx_usbcx_hccharx_t, epdir,
1432 ((header->s.request_type & 0x80) ?
1433 CVMX_USB_DIRECTION_OUT :
1434 CVMX_USB_DIRECTION_IN));
1436 case CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE:
1437 usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
1438 bytes_to_transfer = 0;
1439 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), cvmx_usbcx_hccharx_t, epdir,
1440 ((header->s.request_type & 0x80) ?
1441 CVMX_USB_DIRECTION_OUT :
1442 CVMX_USB_DIRECTION_IN));
1443 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel, usb->index), cvmx_usbcx_hcspltx_t, compsplt, 1);
1447 /* Make sure the transfer never exceeds the byte limit of the hardware.
1448 Further bytes will be sent as continued transactions */
1449 if (bytes_to_transfer > MAX_TRANSFER_BYTES) {
1450 /* Round MAX_TRANSFER_BYTES to a multiple of out packet size */
1451 bytes_to_transfer = MAX_TRANSFER_BYTES / pipe->max_packet;
1452 bytes_to_transfer *= pipe->max_packet;
1455 /* Calculate the number of packets to transfer. If the length is zero
1456 we still need to transfer one packet */
1457 packets_to_transfer = (bytes_to_transfer + pipe->max_packet - 1) / pipe->max_packet;
1458 if (packets_to_transfer == 0)
1459 packets_to_transfer = 1;
1460 else if ((packets_to_transfer>1) && (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)) {
1461 /* Limit to one packet when not using DMA. Channels must be restarted
1462 between every packet for IN transactions, so there is no reason to
1463 do multiple packets in a row */
1464 packets_to_transfer = 1;
1465 bytes_to_transfer = packets_to_transfer * pipe->max_packet;
1467 else if (packets_to_transfer > MAX_TRANSFER_PACKETS) {
1468 /* Limit the number of packet and data transferred to what the
1469 hardware can handle */
1470 packets_to_transfer = MAX_TRANSFER_PACKETS;
1471 bytes_to_transfer = packets_to_transfer * pipe->max_packet;
1474 usbc_hctsiz.s.xfersize = bytes_to_transfer;
1475 usbc_hctsiz.s.pktcnt = packets_to_transfer;
1477 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index), usbc_hctsiz.u32);
1484 * Start a channel to perform the pipe's head transaction
1486 * @param usb USB device state populated by
1487 * cvmx_usb_initialize().
1488 * @param channel Channel to setup
1489 * @param pipe Pipe to start
1491 static void __cvmx_usb_start_channel(cvmx_usb_internal_state_t *usb,
1493 cvmx_usb_pipe_t *pipe)
1495 cvmx_usb_transaction_t *transaction = pipe->head;
1497 /* Make sure all writes to the DMA region get flushed */
1500 /* Attach the channel to the pipe */
1501 usb->pipe_for_channel[channel] = pipe;
1502 pipe->channel = channel;
1503 pipe->flags |= __CVMX_USB_PIPE_FLAGS_SCHEDULED;
1505 /* Mark this channel as in use */
1506 usb->idle_hardware_channels &= ~(1<<channel);
1508 /* Enable the channel interrupt bits */
1510 cvmx_usbcx_hcintx_t usbc_hcint;
1511 cvmx_usbcx_hcintmskx_t usbc_hcintmsk;
1512 cvmx_usbcx_haintmsk_t usbc_haintmsk;
1514 /* Clear all channel status bits */
1515 usbc_hcint.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCINTX(channel, usb->index));
1516 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTX(channel, usb->index), usbc_hcint.u32);
1518 usbc_hcintmsk.u32 = 0;
1519 usbc_hcintmsk.s.chhltdmsk = 1;
1520 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) {
1521 /* Channels need these extra interrupts when we aren't in DMA mode */
1522 usbc_hcintmsk.s.datatglerrmsk = 1;
1523 usbc_hcintmsk.s.frmovrunmsk = 1;
1524 usbc_hcintmsk.s.bblerrmsk = 1;
1525 usbc_hcintmsk.s.xacterrmsk = 1;
1526 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
1527 /* Splits don't generate xfercompl, so we need ACK and NYET */
1528 usbc_hcintmsk.s.nyetmsk = 1;
1529 usbc_hcintmsk.s.ackmsk = 1;
1531 usbc_hcintmsk.s.nakmsk = 1;
1532 usbc_hcintmsk.s.stallmsk = 1;
1533 usbc_hcintmsk.s.xfercomplmsk = 1;
1535 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTMSKX(channel, usb->index), usbc_hcintmsk.u32);
1537 /* Enable the channel interrupt to propagate */
1538 usbc_haintmsk.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HAINTMSK(usb->index));
1539 usbc_haintmsk.s.haintmsk |= 1<<channel;
1540 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HAINTMSK(usb->index), usbc_haintmsk.u32);
1543 /* Setup the locations the DMA engines use */
1545 uint64_t dma_address = transaction->buffer + transaction->actual_bytes;
1546 if (transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)
1547 dma_address = transaction->buffer + transaction->iso_packets[0].offset + transaction->actual_bytes;
1548 __cvmx_usb_write_csr64(usb, CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) + channel*8, dma_address);
1549 __cvmx_usb_write_csr64(usb, CVMX_USBNX_DMA0_INB_CHN0(usb->index) + channel*8, dma_address);
1552 /* Setup both the size of the transfer and the SPLIT characteristics */
1554 cvmx_usbcx_hcspltx_t usbc_hcsplt = {.u32 = 0};
1555 cvmx_usbcx_hctsizx_t usbc_hctsiz = {.u32 = 0};
1556 int packets_to_transfer;
1557 int bytes_to_transfer = transaction->buffer_length - transaction->actual_bytes;
1559 /* ISOCHRONOUS transactions store each individual transfer size in the
1560 packet structure, not the global buffer_length */
1561 if (transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)
1562 bytes_to_transfer = transaction->iso_packets[0].length - transaction->actual_bytes;
1564 /* We need to do split transactions when we are talking to non high
1565 speed devices that are behind a high speed hub */
1566 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
1567 /* On the start split phase (stage is even) record the frame number we
1568 will need to send the split complete. We only store the lower two bits
1569 since the time ahead can only be two frames */
1570 if ((transaction->stage&1) == 0) {
1571 if (transaction->type == CVMX_USB_TRANSFER_BULK)
1572 pipe->split_sc_frame = (usb->frame_number + 1) & 0x7f;
1574 pipe->split_sc_frame = (usb->frame_number + 2) & 0x7f;
1577 pipe->split_sc_frame = -1;
1579 usbc_hcsplt.s.spltena = 1;
1580 usbc_hcsplt.s.hubaddr = pipe->hub_device_addr;
1581 usbc_hcsplt.s.prtaddr = pipe->hub_port;
1582 usbc_hcsplt.s.compsplt = (transaction->stage == CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE);
1584 /* SPLIT transactions can only ever transmit one data packet so
1585 limit the transfer size to the max packet size */
1586 if (bytes_to_transfer > pipe->max_packet)
1587 bytes_to_transfer = pipe->max_packet;
1589 /* ISOCHRONOUS OUT splits are unique in that they limit
1590 data transfers to 188 byte chunks representing the
1591 begin/middle/end of the data or all */
1592 if (!usbc_hcsplt.s.compsplt &&
1593 (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) &&
1594 (pipe->transfer_type == CVMX_USB_TRANSFER_ISOCHRONOUS)) {
1595 /* Clear the split complete frame number as there isn't going
1596 to be a split complete */
1597 pipe->split_sc_frame = -1;
1598 /* See if we've started this transfer and sent data */
1599 if (transaction->actual_bytes == 0) {
1600 /* Nothing sent yet, this is either a begin or the
1602 if (bytes_to_transfer <= 188)
1603 usbc_hcsplt.s.xactpos = 3; /* Entire payload in one go */
1605 usbc_hcsplt.s.xactpos = 2; /* First part of payload */
1608 /* Continuing the previous data, we must either be
1609 in the middle or at the end */
1610 if (bytes_to_transfer <= 188)
1611 usbc_hcsplt.s.xactpos = 1; /* End of payload */
1613 usbc_hcsplt.s.xactpos = 0; /* Middle of payload */
1615 /* Again, the transfer size is limited to 188 bytes */
1616 if (bytes_to_transfer > 188)
1617 bytes_to_transfer = 188;
1621 /* Make sure the transfer never exceeds the byte limit of the hardware.
1622 Further bytes will be sent as continued transactions */
1623 if (bytes_to_transfer > MAX_TRANSFER_BYTES) {
1624 /* Round MAX_TRANSFER_BYTES to a multiple of out packet size */
1625 bytes_to_transfer = MAX_TRANSFER_BYTES / pipe->max_packet;
1626 bytes_to_transfer *= pipe->max_packet;
1629 /* Calculate the number of packets to transfer. If the length is zero
1630 we still need to transfer one packet */
1631 packets_to_transfer = (bytes_to_transfer + pipe->max_packet - 1) / pipe->max_packet;
1632 if (packets_to_transfer == 0)
1633 packets_to_transfer = 1;
1634 else if ((packets_to_transfer>1) && (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)) {
1635 /* Limit to one packet when not using DMA. Channels must be restarted
1636 between every packet for IN transactions, so there is no reason to
1637 do multiple packets in a row */
1638 packets_to_transfer = 1;
1639 bytes_to_transfer = packets_to_transfer * pipe->max_packet;
1641 else if (packets_to_transfer > MAX_TRANSFER_PACKETS) {
1642 /* Limit the number of packet and data transferred to what the
1643 hardware can handle */
1644 packets_to_transfer = MAX_TRANSFER_PACKETS;
1645 bytes_to_transfer = packets_to_transfer * pipe->max_packet;
1648 usbc_hctsiz.s.xfersize = bytes_to_transfer;
1649 usbc_hctsiz.s.pktcnt = packets_to_transfer;
1651 /* Update the DATA0/DATA1 toggle */
1652 usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
1653 /* High speed pipes may need a hardware ping before they start */
1654 if (pipe->flags & __CVMX_USB_PIPE_FLAGS_NEED_PING)
1655 usbc_hctsiz.s.dopng = 1;
1657 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCSPLTX(channel, usb->index), usbc_hcsplt.u32);
1658 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index), usbc_hctsiz.u32);
1661 /* Setup the Host Channel Characteristics Register */
1663 cvmx_usbcx_hccharx_t usbc_hcchar = {.u32 = 0};
1665 /* Set the startframe odd/even properly. This is only used for periodic */
1666 usbc_hcchar.s.oddfrm = usb->frame_number&1;
1668 /* Set the number of back to back packets allowed by this endpoint.
1669 Split transactions interpret "ec" as the number of immediate
1670 retries of failure. These retries happen too quickly, so we
1671 disable these entirely for splits */
1672 if (__cvmx_usb_pipe_needs_split(usb, pipe))
1673 usbc_hcchar.s.ec = 1;
1674 else if (pipe->multi_count < 1)
1675 usbc_hcchar.s.ec = 1;
1676 else if (pipe->multi_count > 3)
1677 usbc_hcchar.s.ec = 3;
1679 usbc_hcchar.s.ec = pipe->multi_count;
1681 /* Set the rest of the endpoint specific settings */
1682 usbc_hcchar.s.devaddr = pipe->device_addr;
1683 usbc_hcchar.s.eptype = transaction->type;
1684 usbc_hcchar.s.lspddev = (pipe->device_speed == CVMX_USB_SPEED_LOW);
1685 usbc_hcchar.s.epdir = pipe->transfer_dir;
1686 usbc_hcchar.s.epnum = pipe->endpoint_num;
1687 usbc_hcchar.s.mps = pipe->max_packet;
1688 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index), usbc_hcchar.u32);
1691 /* Do transaction type specific fixups as needed */
1692 switch (transaction->type) {
1693 case CVMX_USB_TRANSFER_CONTROL:
1694 __cvmx_usb_start_channel_control(usb, channel, pipe);
1696 case CVMX_USB_TRANSFER_BULK:
1697 case CVMX_USB_TRANSFER_INTERRUPT:
1699 case CVMX_USB_TRANSFER_ISOCHRONOUS:
1700 if (!__cvmx_usb_pipe_needs_split(usb, pipe)) {
1701 /* ISO transactions require different PIDs depending on direction
1702 and how many packets are needed */
1703 if (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) {
1704 if (pipe->multi_count < 2) /* Need DATA0 */
1705 USB_SET_FIELD32(CVMX_USBCX_HCTSIZX(channel, usb->index), cvmx_usbcx_hctsizx_t, pid, 0);
1706 else /* Need MDATA */
1707 USB_SET_FIELD32(CVMX_USBCX_HCTSIZX(channel, usb->index), cvmx_usbcx_hctsizx_t, pid, 3);
1713 cvmx_usbcx_hctsizx_t usbc_hctsiz = {.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index))};
1714 transaction->xfersize = usbc_hctsiz.s.xfersize;
1715 transaction->pktcnt = usbc_hctsiz.s.pktcnt;
1717 /* Remeber when we start a split transaction */
1718 if (__cvmx_usb_pipe_needs_split(usb, pipe))
1719 usb->active_split = transaction;
1720 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), cvmx_usbcx_hccharx_t, chena, 1);
1721 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
1722 __cvmx_usb_fill_tx_fifo(usb, channel);
1729 * Find a pipe that is ready to be scheduled to hardware.
1730 * @param usb USB device state populated by
1731 * cvmx_usb_initialize().
1732 * @param list Pipe list to search
1733 * @param current_frame
1734 * Frame counter to use as a time reference.
1736 * @return Pipe or NULL if none are ready
1738 static cvmx_usb_pipe_t *__cvmx_usb_find_ready_pipe(cvmx_usb_internal_state_t *usb, cvmx_usb_pipe_list_t *list, uint64_t current_frame)
1740 cvmx_usb_pipe_t *pipe = list->head;
1742 if (!(pipe->flags & __CVMX_USB_PIPE_FLAGS_SCHEDULED) && pipe->head &&
1743 (pipe->next_tx_frame <= current_frame) &&
1744 ((pipe->split_sc_frame == -1) || ((((int)current_frame - (int)pipe->split_sc_frame) & 0x7f) < 0x40)) &&
1745 (!usb->active_split || (usb->active_split == pipe->head))) {
1746 CVMX_PREFETCH(pipe, 128);
1747 CVMX_PREFETCH(pipe->head, 0);
1758 * Called whenever a pipe might need to be scheduled to the
1761 * @param usb USB device state populated by
1762 * cvmx_usb_initialize().
1763 * @param is_sof True if this schedule was called on a SOF interrupt.
1765 static void __cvmx_usb_schedule(cvmx_usb_internal_state_t *usb, int is_sof)
1768 cvmx_usb_pipe_t *pipe;
1770 cvmx_usb_transfer_t ttype;
1772 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) {
1773 /* Without DMA we need to be careful to not schedule something at the end of a frame and cause an overrun */
1774 cvmx_usbcx_hfnum_t hfnum = {.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HFNUM(usb->index))};
1775 cvmx_usbcx_hfir_t hfir = {.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HFIR(usb->index))};
1776 if (hfnum.s.frrem < hfir.s.frint/4)
1780 while (usb->idle_hardware_channels) {
1781 /* Find an idle channel */
1782 CVMX_CLZ(channel, usb->idle_hardware_channels);
1783 channel = 31 - channel;
1784 if (unlikely(channel > 7))
1787 /* Find a pipe needing service */
1790 /* Only process periodic pipes on SOF interrupts. This way we are
1791 sure that the periodic data is sent in the beginning of the
1793 pipe = __cvmx_usb_find_ready_pipe(usb, usb->active_pipes + CVMX_USB_TRANSFER_ISOCHRONOUS, usb->frame_number);
1795 pipe = __cvmx_usb_find_ready_pipe(usb, usb->active_pipes + CVMX_USB_TRANSFER_INTERRUPT, usb->frame_number);
1797 if (likely(!pipe)) {
1798 pipe = __cvmx_usb_find_ready_pipe(usb, usb->active_pipes + CVMX_USB_TRANSFER_CONTROL, usb->frame_number);
1800 pipe = __cvmx_usb_find_ready_pipe(usb, usb->active_pipes + CVMX_USB_TRANSFER_BULK, usb->frame_number);
1805 __cvmx_usb_start_channel(usb, channel, pipe);
1809 /* Only enable SOF interrupts when we have transactions pending in the
1810 future that might need to be scheduled */
1812 for (ttype=CVMX_USB_TRANSFER_CONTROL; ttype<=CVMX_USB_TRANSFER_INTERRUPT; ttype++) {
1813 pipe = usb->active_pipes[ttype].head;
1815 if (pipe->next_tx_frame > usb->frame_number) {
1822 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), cvmx_usbcx_gintmsk_t, sofmsk, need_sof);
1829 * Call a user's callback for a specific reason.
1831 * @param usb USB device state populated by
1832 * cvmx_usb_initialize().
1833 * @param pipe Pipe the callback is for or NULL
1834 * @param transaction
1835 * Transaction the callback is for or NULL
1836 * @param reason Reason this callback is being called
1837 * @param complete_code
1838 * Completion code for the transaction, if any
1840 static void __cvmx_usb_perform_callback(cvmx_usb_internal_state_t *usb,
1841 cvmx_usb_pipe_t *pipe,
1842 cvmx_usb_transaction_t *transaction,
1843 cvmx_usb_callback_t reason,
1844 cvmx_usb_complete_t complete_code)
1846 cvmx_usb_callback_func_t callback = usb->callback[reason];
1847 void *user_data = usb->callback_data[reason];
1848 int submit_handle = -1;
1849 int pipe_handle = -1;
1850 int bytes_transferred = 0;
1853 pipe_handle = __cvmx_usb_get_pipe_handle(usb, pipe);
1856 submit_handle = __cvmx_usb_get_submit_handle(usb, transaction);
1857 bytes_transferred = transaction->actual_bytes;
1858 /* Transactions are allowed to override the default callback */
1859 if ((reason == CVMX_USB_CALLBACK_TRANSFER_COMPLETE) && transaction->callback) {
1860 callback = transaction->callback;
1861 user_data = transaction->callback_data;
1868 callback((cvmx_usb_state_t *)usb, reason, complete_code, pipe_handle, submit_handle,
1869 bytes_transferred, user_data);
1875 * Signal the completion of a transaction and free it. The
1876 * transaction will be removed from the pipe transaction list.
1878 * @param usb USB device state populated by
1879 * cvmx_usb_initialize().
1880 * @param pipe Pipe the transaction is on
1881 * @param transaction
1882 * Transaction that completed
1883 * @param complete_code
1886 static void __cvmx_usb_perform_complete(cvmx_usb_internal_state_t * usb,
1887 cvmx_usb_pipe_t *pipe,
1888 cvmx_usb_transaction_t *transaction,
1889 cvmx_usb_complete_t complete_code)
1891 /* If this was a split then clear our split in progress marker */
1892 if (usb->active_split == transaction)
1893 usb->active_split = NULL;
1895 /* Isochronous transactions need extra processing as they might not be done
1896 after a single data transfer */
1897 if (unlikely(transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)) {
1898 /* Update the number of bytes transferred in this ISO packet */
1899 transaction->iso_packets[0].length = transaction->actual_bytes;
1900 transaction->iso_packets[0].status = complete_code;
1902 /* If there are more ISOs pending and we succeeded, schedule the next
1904 if ((transaction->iso_number_packets > 1) && (complete_code == CVMX_USB_COMPLETE_SUCCESS)) {
1905 transaction->actual_bytes = 0; /* No bytes transferred for this packet as of yet */
1906 transaction->iso_number_packets--; /* One less ISO waiting to transfer */
1907 transaction->iso_packets++; /* Increment to the next location in our packet array */
1908 transaction->stage = CVMX_USB_STAGE_NON_CONTROL;
1913 /* Remove the transaction from the pipe list */
1914 if (transaction->next)
1915 transaction->next->prev = transaction->prev;
1917 pipe->tail = transaction->prev;
1918 if (transaction->prev)
1919 transaction->prev->next = transaction->next;
1921 pipe->head = transaction->next;
1923 __cvmx_usb_remove_pipe(usb->active_pipes + pipe->transfer_type, pipe);
1924 __cvmx_usb_append_pipe(&usb->idle_pipes, pipe);
1927 __cvmx_usb_perform_callback(usb, pipe, transaction,
1928 CVMX_USB_CALLBACK_TRANSFER_COMPLETE,
1930 __cvmx_usb_free_transaction(usb, transaction);
1938 * Submit a usb transaction to a pipe. Called for all types
1942 * @param pipe_handle
1943 * Which pipe to submit to. Will be validated in this function.
1944 * @param type Transaction type
1945 * @param flags Flags for the transaction
1946 * @param buffer User buffer for the transaction
1947 * @param buffer_length
1948 * User buffer's length in bytes
1949 * @param control_header
1950 * For control transactions, the 8 byte standard header
1951 * @param iso_start_frame
1952 * For ISO transactions, the start frame
1953 * @param iso_number_packets
1954 * For ISO, the number of packet in the transaction.
1955 * @param iso_packets
1956 * A description of each ISO packet
1957 * @param callback User callback to call when the transaction completes
1958 * @param user_data User's data for the callback
1960 * @return Submit handle or negative on failure. Matches the result
1961 * in the external API.
1963 static int __cvmx_usb_submit_transaction(cvmx_usb_internal_state_t *usb,
1965 cvmx_usb_transfer_t type,
1969 uint64_t control_header,
1970 int iso_start_frame,
1971 int iso_number_packets,
1972 cvmx_usb_iso_packet_t *iso_packets,
1973 cvmx_usb_callback_func_t callback,
1977 cvmx_usb_transaction_t *transaction;
1978 cvmx_usb_pipe_t *pipe = usb->pipe + pipe_handle;
1980 if (unlikely((pipe_handle < 0) || (pipe_handle >= MAX_PIPES)))
1982 /* Fail if the pipe isn't open */
1983 if (unlikely((pipe->flags & __CVMX_USB_PIPE_FLAGS_OPEN) == 0))
1985 if (unlikely(pipe->transfer_type != type))
1988 transaction = __cvmx_usb_alloc_transaction(usb);
1989 if (unlikely(!transaction))
1992 transaction->type = type;
1993 transaction->flags |= flags;
1994 transaction->buffer = buffer;
1995 transaction->buffer_length = buffer_length;
1996 transaction->control_header = control_header;
1997 transaction->iso_start_frame = iso_start_frame; // FIXME: This is not used, implement it
1998 transaction->iso_number_packets = iso_number_packets;
1999 transaction->iso_packets = iso_packets;
2000 transaction->callback = callback;
2001 transaction->callback_data = user_data;
2002 if (transaction->type == CVMX_USB_TRANSFER_CONTROL)
2003 transaction->stage = CVMX_USB_STAGE_SETUP;
2005 transaction->stage = CVMX_USB_STAGE_NON_CONTROL;
2007 transaction->next = NULL;
2009 transaction->prev = pipe->tail;
2010 transaction->prev->next = transaction;
2013 if (pipe->next_tx_frame < usb->frame_number)
2014 pipe->next_tx_frame = usb->frame_number + pipe->interval -
2015 (usb->frame_number - pipe->next_tx_frame) % pipe->interval;
2016 transaction->prev = NULL;
2017 pipe->head = transaction;
2018 __cvmx_usb_remove_pipe(&usb->idle_pipes, pipe);
2019 __cvmx_usb_append_pipe(usb->active_pipes + pipe->transfer_type, pipe);
2021 pipe->tail = transaction;
2023 submit_handle = __cvmx_usb_get_submit_handle(usb, transaction);
2025 /* We may need to schedule the pipe if this was the head of the pipe */
2026 if (!transaction->prev)
2027 __cvmx_usb_schedule(usb, 0);
2029 return submit_handle;
2034 * Call to submit a USB Bulk transfer to a pipe.
2036 * @param state USB device state populated by
2037 * cvmx_usb_initialize().
2038 * @param pipe_handle
2039 * Handle to the pipe for the transfer.
2040 * @param buffer Physical address of the data buffer in
2041 * memory. Note that this is NOT A POINTER, but
2042 * the full 64bit physical address of the
2043 * buffer. This may be zero if buffer_length is
2045 * @param buffer_length
2046 * Length of buffer in bytes.
2047 * @param callback Function to call when this transaction
2048 * completes. If the return value of this
2049 * function isn't an error, then this function
2050 * is guaranteed to be called when the
2051 * transaction completes. If this parameter is
2052 * NULL, then the generic callback registered
2053 * through cvmx_usb_register_callback is
2054 * called. If both are NULL, then there is no
2055 * way to know when a transaction completes.
2056 * @param user_data User supplied data returned when the
2057 * callback is called. This is only used if
2058 * callback in not NULL.
2060 * @return A submitted transaction handle or negative on
2061 * failure. Negative values are error codes.
2063 int cvmx_usb_submit_bulk(cvmx_usb_state_t *state, int pipe_handle,
2064 uint64_t buffer, int buffer_length,
2065 cvmx_usb_callback_func_t callback,
2069 cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
2071 /* Pipe handle checking is done later in a common place */
2072 if (unlikely(!buffer))
2074 if (unlikely(buffer_length < 0))
2077 submit_handle = __cvmx_usb_submit_transaction(usb, pipe_handle,
2078 CVMX_USB_TRANSFER_BULK,
2082 0, /* control_header */
2083 0, /* iso_start_frame */
2084 0, /* iso_number_packets */
2085 NULL, /* iso_packets */
2088 return submit_handle;
2093 * Call to submit a USB Interrupt transfer to a pipe.
2095 * @param state USB device state populated by
2096 * cvmx_usb_initialize().
2097 * @param pipe_handle
2098 * Handle to the pipe for the transfer.
2099 * @param buffer Physical address of the data buffer in
2100 * memory. Note that this is NOT A POINTER, but
2101 * the full 64bit physical address of the
2102 * buffer. This may be zero if buffer_length is
2104 * @param buffer_length
2105 * Length of buffer in bytes.
2106 * @param callback Function to call when this transaction
2107 * completes. If the return value of this
2108 * function isn't an error, then this function
2109 * is guaranteed to be called when the
2110 * transaction completes. If this parameter is
2111 * NULL, then the generic callback registered
2112 * through cvmx_usb_register_callback is
2113 * called. If both are NULL, then there is no
2114 * way to know when a transaction completes.
2115 * @param user_data User supplied data returned when the
2116 * callback is called. This is only used if
2117 * callback in not NULL.
2119 * @return A submitted transaction handle or negative on
2120 * failure. Negative values are error codes.
2122 int cvmx_usb_submit_interrupt(cvmx_usb_state_t *state, int pipe_handle,
2123 uint64_t buffer, int buffer_length,
2124 cvmx_usb_callback_func_t callback,
2128 cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
2130 /* Pipe handle checking is done later in a common place */
2131 if (unlikely(!buffer))
2133 if (unlikely(buffer_length < 0))
2136 submit_handle = __cvmx_usb_submit_transaction(usb, pipe_handle,
2137 CVMX_USB_TRANSFER_INTERRUPT,
2141 0, /* control_header */
2142 0, /* iso_start_frame */
2143 0, /* iso_number_packets */
2144 NULL, /* iso_packets */
2147 return submit_handle;
2152 * Call to submit a USB Control transfer to a pipe.
2154 * @param state USB device state populated by
2155 * cvmx_usb_initialize().
2156 * @param pipe_handle
2157 * Handle to the pipe for the transfer.
2158 * @param control_header
2159 * USB 8 byte control header physical address.
2160 * Note that this is NOT A POINTER, but the
2161 * full 64bit physical address of the buffer.
2162 * @param buffer Physical address of the data buffer in
2163 * memory. Note that this is NOT A POINTER, but
2164 * the full 64bit physical address of the
2165 * buffer. This may be zero if buffer_length is
2167 * @param buffer_length
2168 * Length of buffer in bytes.
2169 * @param callback Function to call when this transaction
2170 * completes. If the return value of this
2171 * function isn't an error, then this function
2172 * is guaranteed to be called when the
2173 * transaction completes. If this parameter is
2174 * NULL, then the generic callback registered
2175 * through cvmx_usb_register_callback is
2176 * called. If both are NULL, then there is no
2177 * way to know when a transaction completes.
2178 * @param user_data User supplied data returned when the
2179 * callback is called. This is only used if
2180 * callback in not NULL.
2182 * @return A submitted transaction handle or negative on
2183 * failure. Negative values are error codes.
2185 int cvmx_usb_submit_control(cvmx_usb_state_t *state, int pipe_handle,
2186 uint64_t control_header,
2187 uint64_t buffer, int buffer_length,
2188 cvmx_usb_callback_func_t callback,
2192 cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
2193 cvmx_usb_control_header_t *header = cvmx_phys_to_ptr(control_header);
2195 /* Pipe handle checking is done later in a common place */
2196 if (unlikely(!control_header))
2198 /* Some drivers send a buffer with a zero length. God only knows why */
2199 if (unlikely(buffer && (buffer_length < 0)))
2201 if (unlikely(!buffer && (buffer_length != 0)))
2203 if ((header->s.request_type & 0x80) == 0)
2204 buffer_length = cvmx_le16_to_cpu(header->s.length);
2206 submit_handle = __cvmx_usb_submit_transaction(usb, pipe_handle,
2207 CVMX_USB_TRANSFER_CONTROL,
2212 0, /* iso_start_frame */
2213 0, /* iso_number_packets */
2214 NULL, /* iso_packets */
2217 return submit_handle;
2222 * Call to submit a USB Isochronous transfer to a pipe.
2224 * @param state USB device state populated by
2225 * cvmx_usb_initialize().
2226 * @param pipe_handle
2227 * Handle to the pipe for the transfer.
2228 * @param start_frame
2229 * Number of frames into the future to schedule
2231 * @param flags Flags to control the transfer. See
2232 * cvmx_usb_isochronous_flags_t for the flag
2234 * @param number_packets
2235 * Number of sequential packets to transfer.
2236 * "packets" is a pointer to an array of this
2237 * many packet structures.
2238 * @param packets Description of each transfer packet as
2239 * defined by cvmx_usb_iso_packet_t. The array
2240 * pointed to here must stay valid until the
2241 * complete callback is called.
2242 * @param buffer Physical address of the data buffer in
2243 * memory. Note that this is NOT A POINTER, but
2244 * the full 64bit physical address of the
2245 * buffer. This may be zero if buffer_length is
2247 * @param buffer_length
2248 * Length of buffer in bytes.
2249 * @param callback Function to call when this transaction
2250 * completes. If the return value of this
2251 * function isn't an error, then this function
2252 * is guaranteed to be called when the
2253 * transaction completes. If this parameter is
2254 * NULL, then the generic callback registered
2255 * through cvmx_usb_register_callback is
2256 * called. If both are NULL, then there is no
2257 * way to know when a transaction completes.
2258 * @param user_data User supplied data returned when the
2259 * callback is called. This is only used if
2260 * callback in not NULL.
2262 * @return A submitted transaction handle or negative on
2263 * failure. Negative values are error codes.
2265 int cvmx_usb_submit_isochronous(cvmx_usb_state_t *state, int pipe_handle,
2266 int start_frame, int flags,
2268 cvmx_usb_iso_packet_t packets[],
2269 uint64_t buffer, int buffer_length,
2270 cvmx_usb_callback_func_t callback,
2274 cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
2276 /* Pipe handle checking is done later in a common place */
2277 if (unlikely(start_frame < 0))
2279 if (unlikely(flags & ~(CVMX_USB_ISOCHRONOUS_FLAGS_ALLOW_SHORT | CVMX_USB_ISOCHRONOUS_FLAGS_ASAP)))
2281 if (unlikely(number_packets < 1))
2283 if (unlikely(!packets))
2285 if (unlikely(!buffer))
2287 if (unlikely(buffer_length < 0))
2290 submit_handle = __cvmx_usb_submit_transaction(usb, pipe_handle,
2291 CVMX_USB_TRANSFER_ISOCHRONOUS,
2295 0, /* control_header */
2301 return submit_handle;
2306 * Cancel one outstanding request in a pipe. Canceling a request
2307 * can fail if the transaction has already completed before cancel
2308 * is called. Even after a successful cancel call, it may take
2309 * a frame or two for the cvmx_usb_poll() function to call the
2310 * associated callback.
2312 * @param state USB device state populated by
2313 * cvmx_usb_initialize().
2314 * @param pipe_handle
2315 * Pipe handle to cancel requests in.
2316 * @param submit_handle
2317 * Handle to transaction to cancel, returned by the submit function.
2319 * @return 0 or a negative error code.
2321 int cvmx_usb_cancel(cvmx_usb_state_t *state, int pipe_handle, int submit_handle)
2323 cvmx_usb_transaction_t *transaction;
2324 cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
2325 cvmx_usb_pipe_t *pipe = usb->pipe + pipe_handle;
2327 if (unlikely((pipe_handle < 0) || (pipe_handle >= MAX_PIPES)))
2329 if (unlikely((submit_handle < 0) || (submit_handle >= MAX_TRANSACTIONS)))
2332 /* Fail if the pipe isn't open */
2333 if (unlikely((pipe->flags & __CVMX_USB_PIPE_FLAGS_OPEN) == 0))
2336 transaction = usb->transaction + submit_handle;
2338 /* Fail if this transaction already completed */
2339 if (unlikely((transaction->flags & __CVMX_USB_TRANSACTION_FLAGS_IN_USE) == 0))
2342 /* If the transaction is the HEAD of the queue and scheduled. We need to
2344 if ((pipe->head == transaction) &&
2345 (pipe->flags & __CVMX_USB_PIPE_FLAGS_SCHEDULED)) {
2346 cvmx_usbcx_hccharx_t usbc_hcchar;
2348 usb->pipe_for_channel[pipe->channel] = NULL;
2349 pipe->flags &= ~__CVMX_USB_PIPE_FLAGS_SCHEDULED;
2353 usbc_hcchar.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCCHARX(pipe->channel, usb->index));
2354 /* If the channel isn't enabled then the transaction already completed */
2355 if (usbc_hcchar.s.chena) {
2356 usbc_hcchar.s.chdis = 1;
2357 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCCHARX(pipe->channel, usb->index), usbc_hcchar.u32);
2360 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_CANCEL);
2366 * Cancel all outstanding requests in a pipe. Logically all this
2367 * does is call cvmx_usb_cancel() in a loop.
2369 * @param state USB device state populated by
2370 * cvmx_usb_initialize().
2371 * @param pipe_handle
2372 * Pipe handle to cancel requests in.
2374 * @return 0 or a negative error code.
2376 int cvmx_usb_cancel_all(cvmx_usb_state_t *state, int pipe_handle)
2378 cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
2379 cvmx_usb_pipe_t *pipe = usb->pipe + pipe_handle;
2381 if (unlikely((pipe_handle < 0) || (pipe_handle >= MAX_PIPES)))
2384 /* Fail if the pipe isn't open */
2385 if (unlikely((pipe->flags & __CVMX_USB_PIPE_FLAGS_OPEN) == 0))
2388 /* Simply loop through and attempt to cancel each transaction */
2389 while (pipe->head) {
2390 int result = cvmx_usb_cancel(state, pipe_handle,
2391 __cvmx_usb_get_submit_handle(usb, pipe->head));
2392 if (unlikely(result != 0))
2400 * Close a pipe created with cvmx_usb_open_pipe().
2402 * @param state USB device state populated by
2403 * cvmx_usb_initialize().
2404 * @param pipe_handle
2405 * Pipe handle to close.
2407 * @return 0 or a negative error code. EBUSY is returned if the pipe has
2408 * outstanding transfers.
2410 int cvmx_usb_close_pipe(cvmx_usb_state_t *state, int pipe_handle)
2412 cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
2413 cvmx_usb_pipe_t *pipe = usb->pipe + pipe_handle;
2415 if (unlikely((pipe_handle < 0) || (pipe_handle >= MAX_PIPES)))
2418 /* Fail if the pipe isn't open */
2419 if (unlikely((pipe->flags & __CVMX_USB_PIPE_FLAGS_OPEN) == 0))
2422 /* Fail if the pipe has pending transactions */
2423 if (unlikely(pipe->head))
2427 __cvmx_usb_remove_pipe(&usb->idle_pipes, pipe);
2428 __cvmx_usb_append_pipe(&usb->free_pipes, pipe);
2435 * Register a function to be called when various USB events occur.
2437 * @param state USB device state populated by
2438 * cvmx_usb_initialize().
2439 * @param reason Which event to register for.
2440 * @param callback Function to call when the event occurs.
2441 * @param user_data User data parameter to the function.
2443 * @return 0 or a negative error code.
2445 int cvmx_usb_register_callback(cvmx_usb_state_t *state,
2446 cvmx_usb_callback_t reason,
2447 cvmx_usb_callback_func_t callback,
2450 cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
2452 if (unlikely(reason >= __CVMX_USB_CALLBACK_END))
2454 if (unlikely(!callback))
2457 usb->callback[reason] = callback;
2458 usb->callback_data[reason] = user_data;
2465 * Get the current USB protocol level frame number. The frame
2466 * number is always in the range of 0-0x7ff.
2468 * @param state USB device state populated by
2469 * cvmx_usb_initialize().
2471 * @return USB frame number
2473 int cvmx_usb_get_frame_number(cvmx_usb_state_t *state)
2476 cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
2477 cvmx_usbcx_hfnum_t usbc_hfnum;
2479 usbc_hfnum.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HFNUM(usb->index));
2480 frame_number = usbc_hfnum.s.frnum;
2482 return frame_number;
2488 * Poll a channel for status
2490 * @param usb USB device
2491 * @param channel Channel to poll
2493 * @return Zero on success
2495 static int __cvmx_usb_poll_channel(cvmx_usb_internal_state_t *usb, int channel)
2497 cvmx_usbcx_hcintx_t usbc_hcint;
2498 cvmx_usbcx_hctsizx_t usbc_hctsiz;
2499 cvmx_usbcx_hccharx_t usbc_hcchar;
2500 cvmx_usb_pipe_t *pipe;
2501 cvmx_usb_transaction_t *transaction;
2502 int bytes_this_transfer;
2503 int bytes_in_last_packet;
2504 int packets_processed;
2505 int buffer_space_left;
2507 /* Read the interrupt status bits for the channel */
2508 usbc_hcint.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCINTX(channel, usb->index));
2510 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) {
2511 usbc_hcchar.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index));
2513 if (usbc_hcchar.s.chena && usbc_hcchar.s.chdis) {
2514 /* There seems to be a bug in CN31XX which can cause interrupt
2515 IN transfers to get stuck until we do a write of HCCHARX
2516 without changing things */
2517 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index), usbc_hcchar.u32);
2521 /* In non DMA mode the channels don't halt themselves. We need to
2522 manually disable channels that are left running */
2523 if (!usbc_hcint.s.chhltd) {
2524 if (usbc_hcchar.s.chena) {
2525 cvmx_usbcx_hcintmskx_t hcintmsk;
2526 /* Disable all interrupts except CHHLTD */
2528 hcintmsk.s.chhltdmsk = 1;
2529 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTMSKX(channel, usb->index), hcintmsk.u32);
2530 usbc_hcchar.s.chdis = 1;
2531 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index), usbc_hcchar.u32);
2534 else if (usbc_hcint.s.xfercompl) {
2535 /* Successful IN/OUT with transfer complete. Channel halt isn't needed */
2538 cvmx_dprintf("USB%d: Channel %d interrupt without halt\n", usb->index, channel);
2544 /* There is are no interrupts that we need to process when the channel is
2546 if (!usbc_hcint.s.chhltd)
2550 /* Disable the channel interrupts now that it is done */
2551 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTMSKX(channel, usb->index), 0);
2552 usb->idle_hardware_channels |= (1<<channel);
2554 /* Make sure this channel is tied to a valid pipe */
2555 pipe = usb->pipe_for_channel[channel];
2556 CVMX_PREFETCH(pipe, 0);
2557 CVMX_PREFETCH(pipe, 128);
2560 transaction = pipe->head;
2561 CVMX_PREFETCH0(transaction);
2563 /* Disconnect this pipe from the HW channel. Later the schedule function will
2564 figure out which pipe needs to go */
2565 usb->pipe_for_channel[channel] = NULL;
2566 pipe->flags &= ~__CVMX_USB_PIPE_FLAGS_SCHEDULED;
2568 /* Read the channel config info so we can figure out how much data
2570 usbc_hcchar.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index));
2571 usbc_hctsiz.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index));
2573 /* Calculating the number of bytes successfully transferred is dependent on
2574 the transfer direction */
2575 packets_processed = transaction->pktcnt - usbc_hctsiz.s.pktcnt;
2576 if (usbc_hcchar.s.epdir) {
2577 /* IN transactions are easy. For every byte received the hardware
2578 decrements xfersize. All we need to do is subtract the current
2579 value of xfersize from its starting value and we know how many
2580 bytes were written to the buffer */
2581 bytes_this_transfer = transaction->xfersize - usbc_hctsiz.s.xfersize;
2584 /* OUT transaction don't decrement xfersize. Instead pktcnt is
2585 decremented on every successful packet send. The hardware does
2586 this when it receives an ACK, or NYET. If it doesn't
2587 receive one of these responses pktcnt doesn't change */
2588 bytes_this_transfer = packets_processed * usbc_hcchar.s.mps;
2589 /* The last packet may not be a full transfer if we didn't have
2591 if (bytes_this_transfer > transaction->xfersize)
2592 bytes_this_transfer = transaction->xfersize;
2594 /* Figure out how many bytes were in the last packet of the transfer */
2595 if (packets_processed)
2596 bytes_in_last_packet = bytes_this_transfer - (packets_processed-1) * usbc_hcchar.s.mps;
2598 bytes_in_last_packet = bytes_this_transfer;
2600 /* As a special case, setup transactions output the setup header, not
2601 the user's data. For this reason we don't count setup data as bytes
2603 if ((transaction->stage == CVMX_USB_STAGE_SETUP) ||
2604 (transaction->stage == CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE))
2605 bytes_this_transfer = 0;
2607 /* Add the bytes transferred to the running total. It is important that
2608 bytes_this_transfer doesn't count any data that needs to be
2610 transaction->actual_bytes += bytes_this_transfer;
2611 if (transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)
2612 buffer_space_left = transaction->iso_packets[0].length - transaction->actual_bytes;
2614 buffer_space_left = transaction->buffer_length - transaction->actual_bytes;
2616 /* We need to remember the PID toggle state for the next transaction. The
2617 hardware already updated it for the next transaction */
2618 pipe->pid_toggle = !(usbc_hctsiz.s.pid == 0);
2620 /* For high speed bulk out, assume the next transaction will need to do a
2621 ping before proceeding. If this isn't true the ACK processing below
2622 will clear this flag */
2623 if ((pipe->device_speed == CVMX_USB_SPEED_HIGH) &&
2624 (pipe->transfer_type == CVMX_USB_TRANSFER_BULK) &&
2625 (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT))
2626 pipe->flags |= __CVMX_USB_PIPE_FLAGS_NEED_PING;
2628 if (usbc_hcint.s.stall) {
2629 /* STALL as a response means this transaction cannot be completed
2630 because the device can't process transactions. Tell the user. Any
2631 data that was transferred will be counted on the actual bytes
2633 pipe->pid_toggle = 0;
2634 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_STALL);
2636 else if (usbc_hcint.s.xacterr) {
2637 /* We know at least one packet worked if we get a ACK or NAK. Reset the retry counter */
2638 if (usbc_hcint.s.nak || usbc_hcint.s.ack)
2639 transaction->retries = 0;
2640 transaction->retries++;
2641 if (transaction->retries > MAX_RETRIES) {
2642 /* XactErr as a response means the device signaled something wrong with
2643 the transfer. For example, PID toggle errors cause these */
2644 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_XACTERR);
2647 /* If this was a split then clear our split in progress marker */
2648 if (usb->active_split == transaction)
2649 usb->active_split = NULL;
2650 /* Rewind to the beginning of the transaction by anding off the
2651 split complete bit */
2652 transaction->stage &= ~1;
2653 pipe->split_sc_frame = -1;
2654 pipe->next_tx_frame += pipe->interval;
2655 if (pipe->next_tx_frame < usb->frame_number)
2656 pipe->next_tx_frame = usb->frame_number + pipe->interval -
2657 (usb->frame_number - pipe->next_tx_frame) % pipe->interval;
2660 else if (usbc_hcint.s.bblerr)
2662 /* Babble Error (BblErr) */
2663 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_BABBLEERR);
2665 else if (usbc_hcint.s.datatglerr)
2667 /* We'll retry the exact same transaction again */
2668 transaction->retries++;
2670 else if (usbc_hcint.s.nyet) {
2671 /* NYET as a response is only allowed in three cases: as a response to
2672 a ping, as a response to a split transaction, and as a response to
2673 a bulk out. The ping case is handled by hardware, so we only have
2674 splits and bulk out */
2675 if (!__cvmx_usb_pipe_needs_split(usb, pipe)) {
2676 transaction->retries = 0;
2677 /* If there is more data to go then we need to try again. Otherwise
2678 this transaction is complete */
2679 if ((buffer_space_left == 0) || (bytes_in_last_packet < pipe->max_packet))
2680 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2683 /* Split transactions retry the split complete 4 times then rewind
2684 to the start split and do the entire transactions again */
2685 transaction->retries++;
2686 if ((transaction->retries & 0x3) == 0) {
2687 /* Rewind to the beginning of the transaction by anding off the
2688 split complete bit */
2689 transaction->stage &= ~1;
2690 pipe->split_sc_frame = -1;
2694 else if (usbc_hcint.s.ack) {
2695 transaction->retries = 0;
2696 /* The ACK bit can only be checked after the other error bits. This is
2697 because a multi packet transfer may succeed in a number of packets
2698 and then get a different response on the last packet. In this case
2699 both ACK and the last response bit will be set. If none of the
2700 other response bits is set, then the last packet must have been an
2703 /* Since we got an ACK, we know we don't need to do a ping on this
2705 pipe->flags &= ~__CVMX_USB_PIPE_FLAGS_NEED_PING;
2707 switch (transaction->type)
2709 case CVMX_USB_TRANSFER_CONTROL:
2710 switch (transaction->stage)
2712 case CVMX_USB_STAGE_NON_CONTROL:
2713 case CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE:
2714 /* This should be impossible */
2715 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_ERROR);
2717 case CVMX_USB_STAGE_SETUP:
2718 pipe->pid_toggle = 1;
2719 if (__cvmx_usb_pipe_needs_split(usb, pipe))
2720 transaction->stage = CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE;
2722 cvmx_usb_control_header_t *header = cvmx_phys_to_ptr(transaction->control_header);
2723 if (header->s.length)
2724 transaction->stage = CVMX_USB_STAGE_DATA;
2726 transaction->stage = CVMX_USB_STAGE_STATUS;
2729 case CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE:
2731 cvmx_usb_control_header_t *header = cvmx_phys_to_ptr(transaction->control_header);
2732 if (header->s.length)
2733 transaction->stage = CVMX_USB_STAGE_DATA;
2735 transaction->stage = CVMX_USB_STAGE_STATUS;
2738 case CVMX_USB_STAGE_DATA:
2739 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
2740 transaction->stage = CVMX_USB_STAGE_DATA_SPLIT_COMPLETE;
2741 /* For setup OUT data that are splits, the hardware
2742 doesn't appear to count transferred data. Here
2743 we manually update the data transferred */
2744 if (!usbc_hcchar.s.epdir) {
2745 if (buffer_space_left < pipe->max_packet)
2746 transaction->actual_bytes += buffer_space_left;
2748 transaction->actual_bytes += pipe->max_packet;
2751 else if ((buffer_space_left == 0) || (bytes_in_last_packet < pipe->max_packet)) {
2752 pipe->pid_toggle = 1;
2753 transaction->stage = CVMX_USB_STAGE_STATUS;
2756 case CVMX_USB_STAGE_DATA_SPLIT_COMPLETE:
2757 if ((buffer_space_left == 0) || (bytes_in_last_packet < pipe->max_packet)) {
2758 pipe->pid_toggle = 1;
2759 transaction->stage = CVMX_USB_STAGE_STATUS;
2762 transaction->stage = CVMX_USB_STAGE_DATA;
2765 case CVMX_USB_STAGE_STATUS:
2766 if (__cvmx_usb_pipe_needs_split(usb, pipe))
2767 transaction->stage = CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE;
2769 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2771 case CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE:
2772 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2776 case CVMX_USB_TRANSFER_BULK:
2777 case CVMX_USB_TRANSFER_INTERRUPT:
2778 /* The only time a bulk transfer isn't complete when
2779 it finishes with an ACK is during a split transaction. For
2780 splits we need to continue the transfer if more data is
2782 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
2783 if (transaction->stage == CVMX_USB_STAGE_NON_CONTROL)
2784 transaction->stage = CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE;
2786 if (buffer_space_left && (bytes_in_last_packet == pipe->max_packet))
2787 transaction->stage = CVMX_USB_STAGE_NON_CONTROL;
2789 if (transaction->type == CVMX_USB_TRANSFER_INTERRUPT)
2790 pipe->next_tx_frame += pipe->interval;
2791 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2796 if ((pipe->device_speed == CVMX_USB_SPEED_HIGH) &&
2797 (pipe->transfer_type == CVMX_USB_TRANSFER_BULK) &&
2798 (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) &&
2800 pipe->flags |= __CVMX_USB_PIPE_FLAGS_NEED_PING;
2801 if (!buffer_space_left || (bytes_in_last_packet < pipe->max_packet)) {
2802 if (transaction->type == CVMX_USB_TRANSFER_INTERRUPT)
2803 pipe->next_tx_frame += pipe->interval;
2804 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2808 case CVMX_USB_TRANSFER_ISOCHRONOUS:
2809 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
2810 /* ISOCHRONOUS OUT splits don't require a complete split stage.
2811 Instead they use a sequence of begin OUT splits to transfer
2812 the data 188 bytes at a time. Once the transfer is complete,
2813 the pipe sleeps until the next schedule interval */
2814 if (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) {
2815 /* If no space left or this wasn't a max size packet then
2816 this transfer is complete. Otherwise start it again
2817 to send the next 188 bytes */
2818 if (!buffer_space_left || (bytes_this_transfer < 188)) {
2819 pipe->next_tx_frame += pipe->interval;
2820 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2824 if (transaction->stage == CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE) {
2825 /* We are in the incoming data phase. Keep getting
2826 data until we run out of space or get a small
2828 if ((buffer_space_left == 0) || (bytes_in_last_packet < pipe->max_packet)) {
2829 pipe->next_tx_frame += pipe->interval;
2830 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2834 transaction->stage = CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE;
2838 pipe->next_tx_frame += pipe->interval;
2839 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2844 else if (usbc_hcint.s.nak) {
2845 /* If this was a split then clear our split in progress marker */
2846 if (usb->active_split == transaction)
2847 usb->active_split = NULL;
2848 /* NAK as a response means the device couldn't accept the transaction,
2849 but it should be retried in the future. Rewind to the beginning of
2850 the transaction by anding off the split complete bit. Retry in the
2852 transaction->retries = 0;
2853 transaction->stage &= ~1;
2854 pipe->next_tx_frame += pipe->interval;
2855 if (pipe->next_tx_frame < usb->frame_number)
2856 pipe->next_tx_frame = usb->frame_number + pipe->interval -
2857 (usb->frame_number - pipe->next_tx_frame) % pipe->interval;
2860 cvmx_usb_port_status_t port;
2861 port = cvmx_usb_get_status((cvmx_usb_state_t *)usb);
2862 if (port.port_enabled)
2864 /* We'll retry the exact same transaction again */
2865 transaction->retries++;
2869 /* We get channel halted interrupts with no result bits sets when the
2870 cable is unplugged */
2871 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_ERROR);
2879 * Poll the USB block for status and call all needed callback
2880 * handlers. This function is meant to be called in the interrupt
2881 * handler for the USB controller. It can also be called
2882 * periodically in a loop for non-interrupt based operation.
2884 * @param state USB device state populated by
2885 * cvmx_usb_initialize().
2887 * @return 0 or a negative error code.
2889 int cvmx_usb_poll(cvmx_usb_state_t *state)
2891 cvmx_usbcx_hfnum_t usbc_hfnum;
2892 cvmx_usbcx_gintsts_t usbc_gintsts;
2893 cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
2895 CVMX_PREFETCH(usb, 0);
2896 CVMX_PREFETCH(usb, 1*128);
2897 CVMX_PREFETCH(usb, 2*128);
2898 CVMX_PREFETCH(usb, 3*128);
2899 CVMX_PREFETCH(usb, 4*128);
2901 /* Update the frame counter */
2902 usbc_hfnum.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HFNUM(usb->index));
2903 if ((usb->frame_number&0x3fff) > usbc_hfnum.s.frnum)
2904 usb->frame_number += 0x4000;
2905 usb->frame_number &= ~0x3fffull;
2906 usb->frame_number |= usbc_hfnum.s.frnum;
2908 /* Read the pending interrupts */
2909 usbc_gintsts.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GINTSTS(usb->index));
2911 /* Clear the interrupts now that we know about them */
2912 __cvmx_usb_write_csr32(usb, CVMX_USBCX_GINTSTS(usb->index), usbc_gintsts.u32);
2914 if (usbc_gintsts.s.rxflvl) {
2915 /* RxFIFO Non-Empty (RxFLvl)
2916 Indicates that there is at least one packet pending to be read
2918 /* In DMA mode this is handled by hardware */
2919 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
2920 __cvmx_usb_poll_rx_fifo(usb);
2922 if (usbc_gintsts.s.ptxfemp || usbc_gintsts.s.nptxfemp) {
2923 /* Fill the Tx FIFOs when not in DMA mode */
2924 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
2925 __cvmx_usb_poll_tx_fifo(usb);
2927 if (usbc_gintsts.s.disconnint || usbc_gintsts.s.prtint) {
2928 cvmx_usbcx_hprt_t usbc_hprt;
2929 /* Disconnect Detected Interrupt (DisconnInt)
2930 Asserted when a device disconnect is detected. */
2932 /* Host Port Interrupt (PrtInt)
2933 The core sets this bit to indicate a change in port status of one
2934 of the O2P USB core ports in Host mode. The application must
2935 read the Host Port Control and Status (HPRT) register to
2936 determine the exact event that caused this interrupt. The
2937 application must clear the appropriate status bit in the Host Port
2938 Control and Status register to clear this bit. */
2940 /* Call the user's port callback */
2941 __cvmx_usb_perform_callback(usb, NULL, NULL,
2942 CVMX_USB_CALLBACK_PORT_CHANGED,
2943 CVMX_USB_COMPLETE_SUCCESS);
2944 /* Clear the port change bits */
2945 usbc_hprt.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPRT(usb->index));
2946 usbc_hprt.s.prtena = 0;
2947 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HPRT(usb->index), usbc_hprt.u32);
2949 if (usbc_gintsts.s.hchint) {
2950 /* Host Channels Interrupt (HChInt)
2951 The core sets this bit to indicate that an interrupt is pending on
2952 one of the channels of the core (in Host mode). The application
2953 must read the Host All Channels Interrupt (HAINT) register to
2954 determine the exact number of the channel on which the
2955 interrupt occurred, and then read the corresponding Host
2956 Channel-n Interrupt (HCINTn) register to determine the exact
2957 cause of the interrupt. The application must clear the
2958 appropriate status bit in the HCINTn register to clear this bit. */
2959 cvmx_usbcx_haint_t usbc_haint;
2960 usbc_haint.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HAINT(usb->index));
2961 while (usbc_haint.u32) {
2963 CVMX_CLZ(channel, usbc_haint.u32);
2964 channel = 31 - channel;
2965 __cvmx_usb_poll_channel(usb, channel);
2966 usbc_haint.u32 ^= 1<<channel;
2970 __cvmx_usb_schedule(usb, usbc_gintsts.s.sof);