2 * Copyright (c) 2009,2010 One Laptop per Child
4 * This program is free software. You can redistribute it and/or
5 * modify it under the terms of version 2 of the GNU General Public
6 * License as published by the Free Software Foundation.
9 #include <linux/acpi.h>
10 #include <linux/delay.h>
11 #include <linux/pci.h>
12 #include <linux/gpio.h>
15 /* TODO: this eventually belongs in linux/vx855.h */
16 #define NR_VX855_GPI 14
17 #define NR_VX855_GPO 13
18 #define NR_VX855_GPIO 15
20 #define VX855_GPI(n) (n)
21 #define VX855_GPO(n) (NR_VX855_GPI + (n))
22 #define VX855_GPIO(n) (NR_VX855_GPI + NR_VX855_GPO + (n))
24 #include "olpc_dcon.h"
26 /* Hardware setup on the XO 1.5:
27 * DCONLOAD connects to
28 * VX855_GPIO1 (not SMBCK2)
29 * DCONBLANK connects to VX855_GPIO8 (not SSPICLK) unused in driver
30 * DCONSTAT0 connects to VX855_GPI10 (not SSPISDI)
31 * DCONSTAT1 connects to VX855_GPI11 (not nSSPISS)
32 * DCONIRQ connects to VX855_GPIO12
33 * DCONSMBDATA connects to VX855 graphics CRTSPD
34 * DCONSMBCLK connects to VX855 graphics CRTSPCLK
37 #define VX855_GENL_PURPOSE_OUTPUT 0x44c // PMIO_Rx4c-4f
38 #define VX855_GPI_STATUS_CHG 0x450 // PMIO_Rx50
39 #define VX855_GPI_SCI_SMI 0x452 // PMIO_Rx52
40 #define BIT_GPIO12 0x40
42 #define PREFIX "OLPC DCON:"
44 static void dcon_clear_irq(void)
46 /* irq status will appear in PMIO_Rx50[6] (RW1C) on gpio12 */
47 outb(BIT_GPIO12, VX855_GPI_STATUS_CHG);
50 static int dcon_was_irq(void)
54 /* irq status will appear in PMIO_Rx50[6] on gpio12 */
55 tmp = inb(VX855_GPI_STATUS_CHG);
56 return !!(tmp & BIT_GPIO12);
61 static int dcon_init_xo_1_5(struct dcon_priv *dcon)
68 pdev = pci_get_device(PCI_VENDOR_ID_VIA,
69 PCI_DEVICE_ID_VIA_VX855, NULL);
71 printk(KERN_ERR "cannot find VX855 PCI ID\n");
75 pci_read_config_byte(pdev, 0x95, &tmp);
76 pci_write_config_byte(pdev, 0x95, tmp|0x0c);
78 /* Set GPIO8 to GPIO mode, not SSPICLK */
79 pci_read_config_byte(pdev, 0xe3, &tmp);
80 pci_write_config_byte(pdev, 0xe3, tmp | 0x04);
82 /* Set GPI10/GPI11 to GPI mode, not SSPISDI/SSPISS */
83 pci_read_config_byte(pdev, 0xe4, &tmp);
84 pci_write_config_byte(pdev, 0xe4, tmp|0x08);
86 /* clear PMU_RxE1[6] to select SCI on GPIO12 */
87 /* clear PMU_RxE0[6] to choose falling edge */
88 pci_read_config_byte(pdev, 0xe1, &tmp);
89 pci_write_config_byte(pdev, 0xe1, tmp & ~BIT_GPIO12);
90 pci_read_config_byte(pdev, 0xe0, &tmp);
91 pci_write_config_byte(pdev, 0xe0, tmp & ~BIT_GPIO12);
95 /* set PMIO_Rx52[6] to enable SCI/SMI on gpio12 */
96 outb(inb(VX855_GPI_SCI_SMI)|BIT_GPIO12, VX855_GPI_SCI_SMI);
98 /* Determine the current state of DCONLOAD, likely set by firmware */
100 dcon->curr_src = (inl(VX855_GENL_PURPOSE_OUTPUT) & 0x1000) ?
101 DCON_SOURCE_CPU : DCON_SOURCE_DCON;
102 dcon->pending_src = dcon->curr_src;
106 /* we're sharing the IRQ with ACPI */
107 irq = acpi_gbl_FADT.sci_interrupt;
108 if (request_irq(irq, &dcon_interrupt, IRQF_SHARED, "DCON", dcon)) {
109 printk(KERN_ERR PREFIX "DCON (IRQ%d) allocation failed\n", irq);
116 static void set_i2c_line(int sda, int scl)
119 unsigned int port = 0x26;
121 /* FIXME: This directly accesses the CRT GPIO controller !!! */
142 static void dcon_wiggle_xo_1_5(void)
147 * According to HiMax, when powering the DCON up we should hold
148 * SMB_DATA high for 8 SMB_CLK cycles. This will force the DCON
149 * state machine to reset to a (sane) initial state. Mitch Bradley
150 * did some testing and discovered that holding for 16 SMB_CLK cycles
151 * worked a lot more reliably, so that's what we do here.
155 for (x = 0; x < 16; x++) {
163 /* set PMIO_Rx52[6] to enable SCI/SMI on gpio12 */
164 outb(inb(VX855_GPI_SCI_SMI)|BIT_GPIO12, VX855_GPI_SCI_SMI);
167 static void dcon_set_dconload_xo_1_5(int val)
169 gpio_set_value(VX855_GPIO(1), val);
172 static u8 dcon_read_status_xo_1_5(void)
179 // i believe this is the same as "inb(0x44b) & 3"
180 status = gpio_get_value(VX855_GPI(10));
181 status |= gpio_get_value(VX855_GPI(11)) << 1;
188 struct dcon_platform_data dcon_pdata_xo_1_5 = {
189 .init = dcon_init_xo_1_5,
190 .bus_stabilize_wiggle = dcon_wiggle_xo_1_5,
191 .set_dconload = dcon_set_dconload_xo_1_5,
192 .read_status = dcon_read_status_xo_1_5,