2 * DMM IOMMU driver support functions for TI OMAP processors.
4 * Author: Rob Clark <rob@ti.com>
5 * Andy Gross <andy.gross@ti.com>
7 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation version 2.
13 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
14 * kind, whether express or implied; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h> /* platform_device() */
21 #include <linux/errno.h>
22 #include <linux/sched.h>
23 #include <linux/wait.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/slab.h>
27 #include <linux/vmalloc.h>
28 #include <linux/delay.h>
30 #include <linux/time.h>
31 #include <linux/list.h>
33 #include "omap_dmm_tiler.h"
34 #include "omap_dmm_priv.h"
36 #define DMM_DRIVER_NAME "dmm"
38 /* mappings for associating views to luts */
39 static struct tcm *containers[TILFMT_NFORMATS];
40 static struct dmm *omap_dmm;
42 /* global spinlock for protecting lists */
43 static DEFINE_SPINLOCK(list_lock);
46 #define GEOM(xshift, yshift, bytes_per_pixel) { \
49 .cpp = (bytes_per_pixel), \
50 .slot_w = 1 << (SLOT_WIDTH_BITS - (xshift)), \
51 .slot_h = 1 << (SLOT_HEIGHT_BITS - (yshift)), \
55 uint32_t x_shft; /* unused X-bits (as part of bpp) */
56 uint32_t y_shft; /* unused Y-bits (as part of bpp) */
57 uint32_t cpp; /* bytes/chars per pixel */
58 uint32_t slot_w; /* width of each slot (in pixels) */
59 uint32_t slot_h; /* height of each slot (in pixels) */
60 } geom[TILFMT_NFORMATS] = {
61 [TILFMT_8BIT] = GEOM(0, 0, 1),
62 [TILFMT_16BIT] = GEOM(0, 1, 2),
63 [TILFMT_32BIT] = GEOM(1, 1, 4),
64 [TILFMT_PAGE] = GEOM(SLOT_WIDTH_BITS, SLOT_HEIGHT_BITS, 1),
68 /* lookup table for registers w/ per-engine instances */
69 static const uint32_t reg[][4] = {
70 [PAT_STATUS] = {DMM_PAT_STATUS__0, DMM_PAT_STATUS__1,
71 DMM_PAT_STATUS__2, DMM_PAT_STATUS__3},
72 [PAT_DESCR] = {DMM_PAT_DESCR__0, DMM_PAT_DESCR__1,
73 DMM_PAT_DESCR__2, DMM_PAT_DESCR__3},
76 /* simple allocator to grab next 16 byte aligned memory from txn */
77 static void *alloc_dma(struct dmm_txn *txn, size_t sz, dma_addr_t *pa)
80 struct refill_engine *engine = txn->engine_handle;
82 /* dmm programming requires 16 byte aligned addresses */
83 txn->current_pa = round_up(txn->current_pa, 16);
84 txn->current_va = (void *)round_up((long)txn->current_va, 16);
86 ptr = txn->current_va;
87 *pa = txn->current_pa;
89 txn->current_pa += sz;
90 txn->current_va += sz;
92 BUG_ON((txn->current_va - engine->refill_va) > REFILL_BUFFER_SIZE);
97 /* check status and spin until wait_mask comes true */
98 static int wait_status(struct refill_engine *engine, uint32_t wait_mask)
100 struct dmm *dmm = engine->dmm;
101 uint32_t r = 0, err, i;
103 i = DMM_FIXED_RETRY_COUNT;
105 r = readl(dmm->base + reg[PAT_STATUS][engine->id]);
106 err = r & DMM_PATSTATUS_ERR;
110 if ((r & wait_mask) == wait_mask)
122 static void release_engine(struct refill_engine *engine)
126 spin_lock_irqsave(&list_lock, flags);
127 list_add(&engine->idle_node, &omap_dmm->idle_head);
128 spin_unlock_irqrestore(&list_lock, flags);
130 atomic_inc(&omap_dmm->engine_counter);
131 wake_up_interruptible(&omap_dmm->engine_queue);
134 static irqreturn_t omap_dmm_irq_handler(int irq, void *arg)
136 struct dmm *dmm = arg;
137 uint32_t status = readl(dmm->base + DMM_PAT_IRQSTATUS);
141 writel(status, dmm->base + DMM_PAT_IRQSTATUS);
143 for (i = 0; i < dmm->num_engines; i++) {
144 if (status & DMM_IRQSTAT_LST) {
145 wake_up_interruptible(&dmm->engines[i].wait_for_refill);
147 if (dmm->engines[i].async)
148 release_engine(&dmm->engines[i]);
158 * Get a handle for a DMM transaction
160 static struct dmm_txn *dmm_txn_init(struct dmm *dmm, struct tcm *tcm)
162 struct dmm_txn *txn = NULL;
163 struct refill_engine *engine = NULL;
168 /* wait until an engine is available */
169 ret = wait_event_interruptible(omap_dmm->engine_queue,
170 atomic_add_unless(&omap_dmm->engine_counter, -1, 0));
174 /* grab an idle engine */
175 spin_lock_irqsave(&list_lock, flags);
176 if (!list_empty(&dmm->idle_head)) {
177 engine = list_entry(dmm->idle_head.next, struct refill_engine,
179 list_del(&engine->idle_node);
181 spin_unlock_irqrestore(&list_lock, flags);
187 txn->engine_handle = engine;
188 txn->last_pat = NULL;
189 txn->current_va = engine->refill_va;
190 txn->current_pa = engine->refill_pa;
196 * Add region to DMM transaction. If pages or pages[i] is NULL, then the
197 * corresponding slot is cleared (ie. dummy_pa is programmed)
199 static void dmm_txn_append(struct dmm_txn *txn, struct pat_area *area,
200 struct page **pages, uint32_t npages, uint32_t roll)
202 dma_addr_t pat_pa = 0;
205 struct refill_engine *engine = txn->engine_handle;
206 int columns = (1 + area->x1 - area->x0);
207 int rows = (1 + area->y1 - area->y0);
208 int i = columns*rows;
210 pat = alloc_dma(txn, sizeof(struct pat), &pat_pa);
213 txn->last_pat->next_pa = (uint32_t)pat_pa;
216 pat->ctrl = (struct pat_ctrl){
218 .lut_id = engine->tcm->lut_id,
221 data = alloc_dma(txn, 4*i, &pat->data_pa);
227 data[i] = (pages && pages[n]) ?
228 page_to_phys(pages[n]) : engine->dmm->dummy_pa;
237 * Commit the DMM transaction.
239 static int dmm_txn_commit(struct dmm_txn *txn, bool wait)
242 struct refill_engine *engine = txn->engine_handle;
243 struct dmm *dmm = engine->dmm;
245 if (!txn->last_pat) {
246 dev_err(engine->dmm->dev, "need at least one txn\n");
251 txn->last_pat->next_pa = 0;
253 /* write to PAT_DESCR to clear out any pending transaction */
254 writel(0x0, dmm->base + reg[PAT_DESCR][engine->id]);
256 /* wait for engine ready: */
257 ret = wait_status(engine, DMM_PATSTATUS_READY);
263 /* mark whether it is async to denote list management in IRQ handler */
264 engine->async = wait ? false : true;
267 writel(engine->refill_pa,
268 dmm->base + reg[PAT_DESCR][engine->id]);
271 if (wait_event_interruptible_timeout(engine->wait_for_refill,
272 wait_status(engine, DMM_PATSTATUS_READY) == 0,
273 msecs_to_jiffies(1)) <= 0) {
274 dev_err(dmm->dev, "timed out waiting for done\n");
280 /* only place engine back on list if we are done with it */
282 release_engine(engine);
290 static int fill(struct tcm_area *area, struct page **pages,
291 uint32_t npages, uint32_t roll, bool wait)
294 struct tcm_area slice, area_s;
297 txn = dmm_txn_init(omap_dmm, area->tcm);
298 if (IS_ERR_OR_NULL(txn))
301 tcm_for_each_slice(slice, *area, area_s) {
302 struct pat_area p_area = {
303 .x0 = slice.p0.x, .y0 = slice.p0.y,
304 .x1 = slice.p1.x, .y1 = slice.p1.y,
307 dmm_txn_append(txn, &p_area, pages, npages, roll);
309 roll += tcm_sizeof(slice);
312 ret = dmm_txn_commit(txn, wait);
321 /* note: slots for which pages[i] == NULL are filled w/ dummy page
323 int tiler_pin(struct tiler_block *block, struct page **pages,
324 uint32_t npages, uint32_t roll, bool wait)
328 ret = fill(&block->area, pages, npages, roll, wait);
336 int tiler_unpin(struct tiler_block *block)
338 return fill(&block->area, NULL, 0, 0, false);
344 struct tiler_block *tiler_reserve_2d(enum tiler_fmt fmt, uint16_t w,
345 uint16_t h, uint16_t align)
347 struct tiler_block *block = kzalloc(sizeof(*block), GFP_KERNEL);
352 BUG_ON(!validfmt(fmt));
354 /* convert width/height to slots */
355 w = DIV_ROUND_UP(w, geom[fmt].slot_w);
356 h = DIV_ROUND_UP(h, geom[fmt].slot_h);
358 /* convert alignment to slots */
359 min_align = max(min_align, (geom[fmt].slot_w * geom[fmt].cpp));
360 align = ALIGN(align, min_align);
361 align /= geom[fmt].slot_w * geom[fmt].cpp;
365 ret = tcm_reserve_2d(containers[fmt], w, h, align, &block->area);
368 return ERR_PTR(-ENOMEM);
371 /* add to allocation list */
372 spin_lock_irqsave(&list_lock, flags);
373 list_add(&block->alloc_node, &omap_dmm->alloc_head);
374 spin_unlock_irqrestore(&list_lock, flags);
379 struct tiler_block *tiler_reserve_1d(size_t size)
381 struct tiler_block *block = kzalloc(sizeof(*block), GFP_KERNEL);
382 int num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
386 return ERR_PTR(-ENOMEM);
388 block->fmt = TILFMT_PAGE;
390 if (tcm_reserve_1d(containers[TILFMT_PAGE], num_pages,
393 return ERR_PTR(-ENOMEM);
396 spin_lock_irqsave(&list_lock, flags);
397 list_add(&block->alloc_node, &omap_dmm->alloc_head);
398 spin_unlock_irqrestore(&list_lock, flags);
403 /* note: if you have pin'd pages, you should have already unpin'd first! */
404 int tiler_release(struct tiler_block *block)
406 int ret = tcm_free(&block->area);
410 dev_err(omap_dmm->dev, "failed to release block\n");
412 spin_lock_irqsave(&list_lock, flags);
413 list_del(&block->alloc_node);
414 spin_unlock_irqrestore(&list_lock, flags);
424 /* calculate the tiler space address of a pixel in a view orientation...
425 * below description copied from the display subsystem section of TRM:
427 * When the TILER is addressed, the bits:
428 * [28:27] = 0x0 for 8-bit tiled
429 * 0x1 for 16-bit tiled
430 * 0x2 for 32-bit tiled
432 * [31:29] = 0x0 for 0-degree view
433 * 0x1 for 180-degree view + mirroring
434 * 0x2 for 0-degree view + mirroring
435 * 0x3 for 180-degree view
436 * 0x4 for 270-degree view + mirroring
437 * 0x5 for 270-degree view
438 * 0x6 for 90-degree view
439 * 0x7 for 90-degree view + mirroring
440 * Otherwise the bits indicated the corresponding bit address to access
443 static u32 tiler_get_address(enum tiler_fmt fmt, u32 orient, u32 x, u32 y)
445 u32 x_bits, y_bits, tmp, x_mask, y_mask, alignment;
447 x_bits = CONT_WIDTH_BITS - geom[fmt].x_shft;
448 y_bits = CONT_HEIGHT_BITS - geom[fmt].y_shft;
449 alignment = geom[fmt].x_shft + geom[fmt].y_shft;
451 /* validate coordinate */
452 x_mask = MASK(x_bits);
453 y_mask = MASK(y_bits);
455 if (x < 0 || x > x_mask || y < 0 || y > y_mask) {
456 DBG("invalid coords: %u < 0 || %u > %u || %u < 0 || %u > %u",
457 x, x, x_mask, y, y, y_mask);
461 /* account for mirroring */
462 if (orient & MASK_X_INVERT)
464 if (orient & MASK_Y_INVERT)
467 /* get coordinate address */
468 if (orient & MASK_XY_FLIP)
469 tmp = ((x << y_bits) + y);
471 tmp = ((y << x_bits) + x);
473 return TIL_ADDR((tmp << alignment), orient, fmt);
476 dma_addr_t tiler_ssptr(struct tiler_block *block)
478 BUG_ON(!validfmt(block->fmt));
480 return TILVIEW_8BIT + tiler_get_address(block->fmt, 0,
481 block->area.p0.x * geom[block->fmt].slot_w,
482 block->area.p0.y * geom[block->fmt].slot_h);
485 dma_addr_t tiler_tsptr(struct tiler_block *block, uint32_t orient,
486 uint32_t x, uint32_t y)
488 struct tcm_pt *p = &block->area.p0;
489 BUG_ON(!validfmt(block->fmt));
491 return tiler_get_address(block->fmt, orient,
492 (p->x * geom[block->fmt].slot_w) + x,
493 (p->y * geom[block->fmt].slot_h) + y);
496 void tiler_align(enum tiler_fmt fmt, uint16_t *w, uint16_t *h)
498 BUG_ON(!validfmt(fmt));
499 *w = round_up(*w, geom[fmt].slot_w);
500 *h = round_up(*h, geom[fmt].slot_h);
503 uint32_t tiler_stride(enum tiler_fmt fmt, uint32_t orient)
505 BUG_ON(!validfmt(fmt));
507 if (orient & MASK_XY_FLIP)
508 return 1 << (CONT_HEIGHT_BITS + geom[fmt].x_shft);
510 return 1 << (CONT_WIDTH_BITS + geom[fmt].y_shft);
513 size_t tiler_size(enum tiler_fmt fmt, uint16_t w, uint16_t h)
515 tiler_align(fmt, &w, &h);
516 return geom[fmt].cpp * w * h;
519 size_t tiler_vsize(enum tiler_fmt fmt, uint16_t w, uint16_t h)
521 BUG_ON(!validfmt(fmt));
522 return round_up(geom[fmt].cpp * w, PAGE_SIZE) * h;
525 bool dmm_is_available(void)
527 return omap_dmm ? true : false;
530 static int omap_dmm_remove(struct platform_device *dev)
532 struct tiler_block *block, *_block;
537 /* free all area regions */
538 spin_lock_irqsave(&list_lock, flags);
539 list_for_each_entry_safe(block, _block, &omap_dmm->alloc_head,
541 list_del(&block->alloc_node);
544 spin_unlock_irqrestore(&list_lock, flags);
546 for (i = 0; i < omap_dmm->num_lut; i++)
547 if (omap_dmm->tcm && omap_dmm->tcm[i])
548 omap_dmm->tcm[i]->deinit(omap_dmm->tcm[i]);
549 kfree(omap_dmm->tcm);
551 kfree(omap_dmm->engines);
552 if (omap_dmm->refill_va)
553 dma_free_writecombine(omap_dmm->dev,
554 REFILL_BUFFER_SIZE * omap_dmm->num_engines,
556 omap_dmm->refill_pa);
557 if (omap_dmm->dummy_page)
558 __free_page(omap_dmm->dummy_page);
560 if (omap_dmm->irq > 0)
561 free_irq(omap_dmm->irq, omap_dmm);
563 iounmap(omap_dmm->base);
571 static int omap_dmm_probe(struct platform_device *dev)
573 int ret = -EFAULT, i;
574 struct tcm_area area = {0};
575 u32 hwinfo, pat_geom;
576 struct resource *mem;
578 omap_dmm = kzalloc(sizeof(*omap_dmm), GFP_KERNEL);
580 dev_err(&dev->dev, "failed to allocate driver data section\n");
584 /* initialize lists */
585 INIT_LIST_HEAD(&omap_dmm->alloc_head);
586 INIT_LIST_HEAD(&omap_dmm->idle_head);
588 init_waitqueue_head(&omap_dmm->engine_queue);
590 /* lookup hwmod data - base address and irq */
591 mem = platform_get_resource(dev, IORESOURCE_MEM, 0);
593 dev_err(&dev->dev, "failed to get base address resource\n");
597 omap_dmm->base = ioremap(mem->start, SZ_2K);
599 if (!omap_dmm->base) {
600 dev_err(&dev->dev, "failed to get dmm base address\n");
604 omap_dmm->irq = platform_get_irq(dev, 0);
605 if (omap_dmm->irq < 0) {
606 dev_err(&dev->dev, "failed to get IRQ resource\n");
610 omap_dmm->dev = &dev->dev;
612 hwinfo = readl(omap_dmm->base + DMM_PAT_HWINFO);
613 omap_dmm->num_engines = (hwinfo >> 24) & 0x1F;
614 omap_dmm->num_lut = (hwinfo >> 16) & 0x1F;
615 omap_dmm->container_width = 256;
616 omap_dmm->container_height = 128;
618 atomic_set(&omap_dmm->engine_counter, omap_dmm->num_engines);
620 /* read out actual LUT width and height */
621 pat_geom = readl(omap_dmm->base + DMM_PAT_GEOMETRY);
622 omap_dmm->lut_width = ((pat_geom >> 16) & 0xF) << 5;
623 omap_dmm->lut_height = ((pat_geom >> 24) & 0xF) << 5;
625 /* initialize DMM registers */
626 writel(0x88888888, omap_dmm->base + DMM_PAT_VIEW__0);
627 writel(0x88888888, omap_dmm->base + DMM_PAT_VIEW__1);
628 writel(0x80808080, omap_dmm->base + DMM_PAT_VIEW_MAP__0);
629 writel(0x80000000, omap_dmm->base + DMM_PAT_VIEW_MAP_BASE);
630 writel(0x88888888, omap_dmm->base + DMM_TILER_OR__0);
631 writel(0x88888888, omap_dmm->base + DMM_TILER_OR__1);
633 ret = request_irq(omap_dmm->irq, omap_dmm_irq_handler, IRQF_SHARED,
634 "omap_dmm_irq_handler", omap_dmm);
637 dev_err(&dev->dev, "couldn't register IRQ %d, error %d\n",
643 /* Enable all interrupts for each refill engine except
644 * ERR_LUT_MISS<n> (which is just advisory, and we don't care
645 * about because we want to be able to refill live scanout
646 * buffers for accelerated pan/scroll) and FILL_DSC<n> which
647 * we just generally don't care about.
649 writel(0x7e7e7e7e, omap_dmm->base + DMM_PAT_IRQENABLE_SET);
651 omap_dmm->dummy_page = alloc_page(GFP_KERNEL | __GFP_DMA32);
652 if (!omap_dmm->dummy_page) {
653 dev_err(&dev->dev, "could not allocate dummy page\n");
658 /* set dma mask for device */
659 /* NOTE: this is a workaround for the hwmod not initializing properly */
660 dev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
662 omap_dmm->dummy_pa = page_to_phys(omap_dmm->dummy_page);
664 /* alloc refill memory */
665 omap_dmm->refill_va = dma_alloc_writecombine(&dev->dev,
666 REFILL_BUFFER_SIZE * omap_dmm->num_engines,
667 &omap_dmm->refill_pa, GFP_KERNEL);
668 if (!omap_dmm->refill_va) {
669 dev_err(&dev->dev, "could not allocate refill memory\n");
674 omap_dmm->engines = kzalloc(
675 omap_dmm->num_engines * sizeof(struct refill_engine),
677 if (!omap_dmm->engines) {
678 dev_err(&dev->dev, "could not allocate engines\n");
683 for (i = 0; i < omap_dmm->num_engines; i++) {
684 omap_dmm->engines[i].id = i;
685 omap_dmm->engines[i].dmm = omap_dmm;
686 omap_dmm->engines[i].refill_va = omap_dmm->refill_va +
687 (REFILL_BUFFER_SIZE * i);
688 omap_dmm->engines[i].refill_pa = omap_dmm->refill_pa +
689 (REFILL_BUFFER_SIZE * i);
690 init_waitqueue_head(&omap_dmm->engines[i].wait_for_refill);
692 list_add(&omap_dmm->engines[i].idle_node, &omap_dmm->idle_head);
695 omap_dmm->tcm = kzalloc(omap_dmm->num_lut * sizeof(*omap_dmm->tcm),
697 if (!omap_dmm->tcm) {
698 dev_err(&dev->dev, "failed to allocate lut ptrs\n");
703 /* init containers */
704 for (i = 0; i < omap_dmm->num_lut; i++) {
705 omap_dmm->tcm[i] = sita_init(omap_dmm->container_width,
706 omap_dmm->container_height,
709 if (!omap_dmm->tcm[i]) {
710 dev_err(&dev->dev, "failed to allocate container\n");
715 omap_dmm->tcm[i]->lut_id = i;
718 /* assign access mode containers to applicable tcm container */
719 /* OMAP 4 has 1 container for all 4 views */
720 containers[TILFMT_8BIT] = omap_dmm->tcm[0];
721 containers[TILFMT_16BIT] = omap_dmm->tcm[0];
722 containers[TILFMT_32BIT] = omap_dmm->tcm[0];
723 containers[TILFMT_PAGE] = omap_dmm->tcm[0];
725 area = (struct tcm_area) {
728 .p1.x = omap_dmm->container_width - 1,
729 .p1.y = omap_dmm->container_height - 1,
732 /* initialize all LUTs to dummy page entries */
733 for (i = 0; i < omap_dmm->num_lut; i++) {
734 area.tcm = omap_dmm->tcm[i];
735 if (fill(&area, NULL, 0, 0, true))
736 dev_err(omap_dmm->dev, "refill failed");
739 dev_info(omap_dmm->dev, "initialized all PAT entries\n");
744 if (omap_dmm_remove(dev))
745 dev_err(&dev->dev, "cleanup failed\n");
753 #ifdef CONFIG_DEBUG_FS
755 static const char *alphabet = "abcdefghijklmnopqrstuvwxyz"
756 "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789";
757 static const char *special = ".,:;'\"`~!^-+";
759 static void fill_map(char **map, int xdiv, int ydiv, struct tcm_area *a,
763 for (y = a->p0.y / ydiv; y <= a->p1.y / ydiv; y++)
764 for (x = a->p0.x / xdiv; x <= a->p1.x / xdiv; x++)
765 if (map[y][x] == ' ' || ovw)
769 static void fill_map_pt(char **map, int xdiv, int ydiv, struct tcm_pt *p,
772 map[p->y / ydiv][p->x / xdiv] = c;
775 static char read_map_pt(char **map, int xdiv, int ydiv, struct tcm_pt *p)
777 return map[p->y / ydiv][p->x / xdiv];
780 static int map_width(int xdiv, int x0, int x1)
782 return (x1 / xdiv) - (x0 / xdiv) + 1;
785 static void text_map(char **map, int xdiv, char *nice, int yd, int x0, int x1)
787 char *p = map[yd] + (x0 / xdiv);
788 int w = (map_width(xdiv, x0, x1) - strlen(nice)) / 2;
796 static void map_1d_info(char **map, int xdiv, int ydiv, char *nice,
799 sprintf(nice, "%dK", tcm_sizeof(*a) * 4);
800 if (a->p0.y + 1 < a->p1.y) {
801 text_map(map, xdiv, nice, (a->p0.y + a->p1.y) / 2 / ydiv, 0,
803 } else if (a->p0.y < a->p1.y) {
804 if (strlen(nice) < map_width(xdiv, a->p0.x, 256 - 1))
805 text_map(map, xdiv, nice, a->p0.y / ydiv,
806 a->p0.x + xdiv, 256 - 1);
807 else if (strlen(nice) < map_width(xdiv, 0, a->p1.x))
808 text_map(map, xdiv, nice, a->p1.y / ydiv,
810 } else if (strlen(nice) + 1 < map_width(xdiv, a->p0.x, a->p1.x)) {
811 text_map(map, xdiv, nice, a->p0.y / ydiv, a->p0.x, a->p1.x);
815 static void map_2d_info(char **map, int xdiv, int ydiv, char *nice,
818 sprintf(nice, "(%d*%d)", tcm_awidth(*a), tcm_aheight(*a));
819 if (strlen(nice) + 1 < map_width(xdiv, a->p0.x, a->p1.x))
820 text_map(map, xdiv, nice, (a->p0.y + a->p1.y) / 2 / ydiv,
824 int tiler_map_show(struct seq_file *s, void *arg)
826 int xdiv = 2, ydiv = 1;
827 char **map = NULL, *global_map;
828 struct tiler_block *block;
829 struct tcm_area a, p;
831 const char *m2d = alphabet;
832 const char *a2d = special;
833 const char *m2dp = m2d, *a2dp = a2d;
840 /* early return if dmm/tiler device is not initialized */
844 h_adj = omap_dmm->lut_height / ydiv;
845 w_adj = omap_dmm->lut_width / xdiv;
847 map = kzalloc(h_adj * sizeof(*map), GFP_KERNEL);
848 global_map = kzalloc((w_adj + 1) * h_adj, GFP_KERNEL);
850 if (!map || !global_map)
853 memset(global_map, ' ', (w_adj + 1) * h_adj);
854 for (i = 0; i < omap_dmm->lut_height; i++) {
855 map[i] = global_map + i * (w_adj + 1);
858 spin_lock_irqsave(&list_lock, flags);
860 list_for_each_entry(block, &omap_dmm->alloc_head, alloc_node) {
861 if (block->fmt != TILFMT_PAGE) {
862 fill_map(map, xdiv, ydiv, &block->area, *m2dp, true);
867 map_2d_info(map, xdiv, ydiv, nice, &block->area);
869 bool start = read_map_pt(map, xdiv, ydiv,
872 bool end = read_map_pt(map, xdiv, ydiv, &block->area.p1)
874 tcm_for_each_slice(a, block->area, p)
875 fill_map(map, xdiv, ydiv, &a, '=', true);
876 fill_map_pt(map, xdiv, ydiv, &block->area.p0,
878 fill_map_pt(map, xdiv, ydiv, &block->area.p1,
880 map_1d_info(map, xdiv, ydiv, nice, &block->area);
884 spin_unlock_irqrestore(&list_lock, flags);
887 seq_printf(s, "BEGIN DMM TILER MAP\n");
888 for (i = 0; i < 128; i++)
889 seq_printf(s, "%03d:%s\n", i, map[i]);
890 seq_printf(s, "END TILER MAP\n");
892 dev_dbg(omap_dmm->dev, "BEGIN DMM TILER MAP\n");
893 for (i = 0; i < 128; i++)
894 dev_dbg(omap_dmm->dev, "%03d:%s\n", i, map[i]);
895 dev_dbg(omap_dmm->dev, "END TILER MAP\n");
906 struct platform_driver omap_dmm_driver = {
907 .probe = omap_dmm_probe,
908 .remove = omap_dmm_remove,
910 .owner = THIS_MODULE,
911 .name = DMM_DRIVER_NAME,
915 MODULE_LICENSE("GPL v2");
916 MODULE_AUTHOR("Andy Gross <andy.gross@ti.com>");
917 MODULE_DESCRIPTION("OMAP DMM/Tiler Driver");
918 MODULE_ALIAS("platform:" DMM_DRIVER_NAME);