drivers/staging/rt2860/common/cmm_asic.c

   1 /*
   2  *************************************************************************
   3  * Ralink Tech Inc.
   4  * 5F., No.36, Taiyuan St., Jhubei City,
   5  * Hsinchu County 302,
   6  * Taiwan, R.O.C.
   7  *
   8  * (c) Copyright 2002-2007, Ralink Technology, Inc.
   9  *
  10  * This program is free software; you can redistribute it and/or modify  *
  11  * it under the terms of the GNU General Public License as published by  *
  12  * the Free Software Foundation; either version 2 of the License, or     *
  13  * (at your option) any later version.                                   *
  14  *                                                                       *
  15  * This program is distributed in the hope that it will be useful,       *
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  18  * GNU General Public License for more details.                          *
  19  *                                                                       *
  20  * You should have received a copy of the GNU General Public License     *
  21  * along with this program; if not, write to the                         *
  22  * Free Software Foundation, Inc.,                                       *
  23  * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  24  *                                                                       *
  25  *************************************************************************
  26
  27         Module Name:
  28         cmm_asic.c
  29
  30         Abstract:
  31         Functions used to communicate with ASIC
  32
  33         Revision History:
  34         Who                     When                    What
  35         --------        ----------              ----------------------------------------------
  36 */
  37
  38 #include "../rt_config.h"
  39
  40
  41 // Reset the RFIC setting to new series
  42 RTMP_RF_REGS RF2850RegTable[] = {
  43 //              ch       R1              R2              R3(TX0~4=0) R4
  44                 {1,  0x98402ecc, 0x984c0786, 0x9816b455, 0x9800510b},
  45                 {2,  0x98402ecc, 0x984c0786, 0x98168a55, 0x9800519f},
  46                 {3,  0x98402ecc, 0x984c078a, 0x98168a55, 0x9800518b},
  47                 {4,  0x98402ecc, 0x984c078a, 0x98168a55, 0x9800519f},
  48                 {5,  0x98402ecc, 0x984c078e, 0x98168a55, 0x9800518b},
  49                 {6,  0x98402ecc, 0x984c078e, 0x98168a55, 0x9800519f},
  50                 {7,  0x98402ecc, 0x984c0792, 0x98168a55, 0x9800518b},
  51                 {8,  0x98402ecc, 0x984c0792, 0x98168a55, 0x9800519f},
  52                 {9,  0x98402ecc, 0x984c0796, 0x98168a55, 0x9800518b},
  53                 {10, 0x98402ecc, 0x984c0796, 0x98168a55, 0x9800519f},
  54                 {11, 0x98402ecc, 0x984c079a, 0x98168a55, 0x9800518b},
  55                 {12, 0x98402ecc, 0x984c079a, 0x98168a55, 0x9800519f},
  56                 {13, 0x98402ecc, 0x984c079e, 0x98168a55, 0x9800518b},
  57                 {14, 0x98402ecc, 0x984c07a2, 0x98168a55, 0x98005193},
  58
  59                 // 802.11 UNI / HyperLan 2
  60                 {36, 0x98402ecc, 0x984c099a, 0x98158a55, 0x980ed1a3},
  61                 {38, 0x98402ecc, 0x984c099e, 0x98158a55, 0x980ed193},
  62                 {40, 0x98402ec8, 0x984c0682, 0x98158a55, 0x980ed183},
  63                 {44, 0x98402ec8, 0x984c0682, 0x98158a55, 0x980ed1a3},
  64                 {46, 0x98402ec8, 0x984c0686, 0x98158a55, 0x980ed18b},
  65                 {48, 0x98402ec8, 0x984c0686, 0x98158a55, 0x980ed19b},
  66                 {52, 0x98402ec8, 0x984c068a, 0x98158a55, 0x980ed193},
  67                 {54, 0x98402ec8, 0x984c068a, 0x98158a55, 0x980ed1a3},
  68                 {56, 0x98402ec8, 0x984c068e, 0x98158a55, 0x980ed18b},
  69                 {60, 0x98402ec8, 0x984c0692, 0x98158a55, 0x980ed183},
  70                 {62, 0x98402ec8, 0x984c0692, 0x98158a55, 0x980ed193},
  71                 {64, 0x98402ec8, 0x984c0692, 0x98158a55, 0x980ed1a3}, // Plugfest#4, Day4, change RFR3 left4th 9->5.
  72
  73                 // 802.11 HyperLan 2
  74                 {100, 0x98402ec8, 0x984c06b2, 0x98178a55, 0x980ed783},
  75
  76                 // 2008.04.30 modified
  77                 // The system team has AN to improve the EVM value
  78                 // for channel 102 to 108 for the RT2850/RT2750 dual band solution.
  79                 {102, 0x98402ec8, 0x985c06b2, 0x98578a55, 0x980ed793},
  80                 {104, 0x98402ec8, 0x985c06b2, 0x98578a55, 0x980ed1a3},
  81                 {108, 0x98402ecc, 0x985c0a32, 0x98578a55, 0x980ed193},
  82
  83                 {110, 0x98402ecc, 0x984c0a36, 0x98178a55, 0x980ed183},
  84                 {112, 0x98402ecc, 0x984c0a36, 0x98178a55, 0x980ed19b},
  85                 {116, 0x98402ecc, 0x984c0a3a, 0x98178a55, 0x980ed1a3},
  86                 {118, 0x98402ecc, 0x984c0a3e, 0x98178a55, 0x980ed193},
  87                 {120, 0x98402ec4, 0x984c0382, 0x98178a55, 0x980ed183},
  88                 {124, 0x98402ec4, 0x984c0382, 0x98178a55, 0x980ed193},
  89                 {126, 0x98402ec4, 0x984c0382, 0x98178a55, 0x980ed15b}, // 0x980ed1bb->0x980ed15b required by Rory 20070927
  90                 {128, 0x98402ec4, 0x984c0382, 0x98178a55, 0x980ed1a3},
  91                 {132, 0x98402ec4, 0x984c0386, 0x98178a55, 0x980ed18b},
  92                 {134, 0x98402ec4, 0x984c0386, 0x98178a55, 0x980ed193},
  93                 {136, 0x98402ec4, 0x984c0386, 0x98178a55, 0x980ed19b},
  94                 {140, 0x98402ec4, 0x984c038a, 0x98178a55, 0x980ed183},
  95
  96                 // 802.11 UNII
  97                 {149, 0x98402ec4, 0x984c038a, 0x98178a55, 0x980ed1a7},
  98                 {151, 0x98402ec4, 0x984c038e, 0x98178a55, 0x980ed187},
  99                 {153, 0x98402ec4, 0x984c038e, 0x98178a55, 0x980ed18f},
 100                 {157, 0x98402ec4, 0x984c038e, 0x98178a55, 0x980ed19f},
 101                 {159, 0x98402ec4, 0x984c038e, 0x98178a55, 0x980ed1a7},
 102                 {161, 0x98402ec4, 0x984c0392, 0x98178a55, 0x980ed187},
 103                 {165, 0x98402ec4, 0x984c0392, 0x98178a55, 0x980ed197},
 104                 {167, 0x98402ec4, 0x984c03d2, 0x98179855, 0x9815531f},
 105                 {169, 0x98402ec4, 0x984c03d2, 0x98179855, 0x98155327},
 106                 {171, 0x98402ec4, 0x984c03d6, 0x98179855, 0x98155307},
 107                 {173, 0x98402ec4, 0x984c03d6, 0x98179855, 0x9815530f},
 108
 109                 // Japan
 110                 {184, 0x95002ccc, 0x9500491e, 0x9509be55, 0x950c0a0b},
 111                 {188, 0x95002ccc, 0x95004922, 0x9509be55, 0x950c0a13},
 112                 {192, 0x95002ccc, 0x95004926, 0x9509be55, 0x950c0a1b},
 113                 {196, 0x95002ccc, 0x9500492a, 0x9509be55, 0x950c0a23},
 114                 {208, 0x95002ccc, 0x9500493a, 0x9509be55, 0x950c0a13},
 115                 {212, 0x95002ccc, 0x9500493e, 0x9509be55, 0x950c0a1b},
 116                 {216, 0x95002ccc, 0x95004982, 0x9509be55, 0x950c0a23},
 117
 118                 // still lack of MMAC(Japan) ch 34,38,42,46
 119 };
 120 UCHAR   NUM_OF_2850_CHNL = (sizeof(RF2850RegTable) / sizeof(RTMP_RF_REGS));
 121
 122 FREQUENCY_ITEM FreqItems3020[] =
 123 {
 124         /**************************************************/
 125         // ISM : 2.4 to 2.483 GHz                         //
 126         /**************************************************/
 127         // 11g
 128         /**************************************************/
 129         //-CH---N-------R---K-----------
 130         {1,    241,  2,  2},
 131         {2,    241,      2,  7},
 132         {3,    242,      2,  2},
 133         {4,    242,      2,  7},
 134         {5,    243,      2,  2},
 135         {6,    243,      2,  7},
 136         {7,    244,      2,  2},
 137         {8,    244,      2,  7},
 138         {9,    245,      2,  2},
 139         {10,   245,      2,  7},
 140         {11,   246,      2,  2},
 141         {12,   246,      2,  7},
 142         {13,   247,      2,  2},
 143         {14,   248,      2,  4},
 144 };
 145 UCHAR   NUM_OF_3020_CHNL = (sizeof(FreqItems3020) / sizeof(FREQUENCY_ITEM));
 146
 147
 148 VOID AsicUpdateAutoFallBackTable(
 149         IN      PRTMP_ADAPTER   pAd,
 150         IN      PUCHAR                  pRateTable)
 151 {
 152         UCHAR                                   i;
 153         HT_FBK_CFG0_STRUC               HtCfg0;
 154         HT_FBK_CFG1_STRUC               HtCfg1;
 155         LG_FBK_CFG0_STRUC               LgCfg0;
 156         LG_FBK_CFG1_STRUC               LgCfg1;
 157         PRTMP_TX_RATE_SWITCH    pCurrTxRate, pNextTxRate;
 158
 159         // set to initial value
 160         HtCfg0.word = 0x65432100;
 161         HtCfg1.word = 0xedcba988;
 162         LgCfg0.word = 0xedcba988;
 163         LgCfg1.word = 0x00002100;
 164
 165         pNextTxRate = (PRTMP_TX_RATE_SWITCH)pRateTable+1;
 166         for (i = 1; i < *((PUCHAR) pRateTable); i++)
 167         {
 168                 pCurrTxRate = (PRTMP_TX_RATE_SWITCH)pRateTable+1+i;
 169                 switch (pCurrTxRate->Mode)
 170                 {
 171                         case 0:         //CCK
 172                                 break;
 173                         case 1:         //OFDM
 174                                 {
 175                                         switch(pCurrTxRate->CurrMCS)
 176                                         {
 177                                                 case 0:
 178                                                         LgCfg0.field.OFDMMCS0FBK = (pNextTxRate->Mode == MODE_OFDM) ? (pNextTxRate->CurrMCS+8): pNextTxRate->CurrMCS;
 179                                                         break;
 180                                                 case 1:
 181                                                         LgCfg0.field.OFDMMCS1FBK = (pNextTxRate->Mode == MODE_OFDM) ? (pNextTxRate->CurrMCS+8): pNextTxRate->CurrMCS;
 182                                                         break;
 183                                                 case 2:
 184                                                         LgCfg0.field.OFDMMCS2FBK = (pNextTxRate->Mode == MODE_OFDM) ? (pNextTxRate->CurrMCS+8): pNextTxRate->CurrMCS;
 185                                                         break;
 186                                                 case 3:
 187                                                         LgCfg0.field.OFDMMCS3FBK = (pNextTxRate->Mode == MODE_OFDM) ? (pNextTxRate->CurrMCS+8): pNextTxRate->CurrMCS;
 188                                                         break;
 189                                                 case 4:
 190                                                         LgCfg0.field.OFDMMCS4FBK = (pNextTxRate->Mode == MODE_OFDM) ? (pNextTxRate->CurrMCS+8): pNextTxRate->CurrMCS;
 191                                                         break;
 192                                                 case 5:
 193                                                         LgCfg0.field.OFDMMCS5FBK = (pNextTxRate->Mode == MODE_OFDM) ? (pNextTxRate->CurrMCS+8): pNextTxRate->CurrMCS;
 194                                                         break;
 195                                                 case 6:
 196                                                         LgCfg0.field.OFDMMCS6FBK = (pNextTxRate->Mode == MODE_OFDM) ? (pNextTxRate->CurrMCS+8): pNextTxRate->CurrMCS;
 197                                                         break;
 198                                                 case 7:
 199                                                         LgCfg0.field.OFDMMCS7FBK = (pNextTxRate->Mode == MODE_OFDM) ? (pNextTxRate->CurrMCS+8): pNextTxRate->CurrMCS;
 200                                                         break;
 201                                         }
 202                                 }
 203                                 break;
 204                         case 2:         //HT-MIX
 205                         case 3:         //HT-GF
 206                                 {
 207                                         if ((pNextTxRate->Mode >= MODE_HTMIX) && (pCurrTxRate->CurrMCS != pNextTxRate->CurrMCS))
 208                                         {
 209                                                 switch(pCurrTxRate->CurrMCS)
 210                                                 {
 211                                                         case 0:
 212                                                                 HtCfg0.field.HTMCS0FBK = pNextTxRate->CurrMCS;
 213                                                                 break;
 214                                                         case 1:
 215                                                                 HtCfg0.field.HTMCS1FBK = pNextTxRate->CurrMCS;
 216                                                                 break;
 217                                                         case 2:
 218                                                                 HtCfg0.field.HTMCS2FBK = pNextTxRate->CurrMCS;
 219                                                                 break;
 220                                                         case 3:
 221                                                                 HtCfg0.field.HTMCS3FBK = pNextTxRate->CurrMCS;
 222                                                                 break;
 223                                                         case 4:
 224                                                                 HtCfg0.field.HTMCS4FBK = pNextTxRate->CurrMCS;
 225                                                                 break;
 226                                                         case 5:
 227                                                                 HtCfg0.field.HTMCS5FBK = pNextTxRate->CurrMCS;
 228                                                                 break;
 229                                                         case 6:
 230                                                                 HtCfg0.field.HTMCS6FBK = pNextTxRate->CurrMCS;
 231                                                                 break;
 232                                                         case 7:
 233                                                                 HtCfg0.field.HTMCS7FBK = pNextTxRate->CurrMCS;
 234                                                                 break;
 235                                                         case 8:
 236                                                                 HtCfg1.field.HTMCS8FBK = pNextTxRate->CurrMCS;
 237                                                                 break;
 238                                                         case 9:
 239                                                                 HtCfg1.field.HTMCS9FBK = pNextTxRate->CurrMCS;
 240                                                                 break;
 241                                                         case 10:
 242                                                                 HtCfg1.field.HTMCS10FBK = pNextTxRate->CurrMCS;
 243                                                                 break;
 244                                                         case 11:
 245                                                                 HtCfg1.field.HTMCS11FBK = pNextTxRate->CurrMCS;
 246                                                                 break;
 247                                                         case 12:
 248                                                                 HtCfg1.field.HTMCS12FBK = pNextTxRate->CurrMCS;
 249                                                                 break;
 250                                                         case 13:
 251                                                                 HtCfg1.field.HTMCS13FBK = pNextTxRate->CurrMCS;
 252                                                                 break;
 253                                                         case 14:
 254                                                                 HtCfg1.field.HTMCS14FBK = pNextTxRate->CurrMCS;
 255                                                                 break;
 256                                                         case 15:
 257                                                                 HtCfg1.field.HTMCS15FBK = pNextTxRate->CurrMCS;
 258                                                                 break;
 259                                                         default:
 260                                                                 DBGPRINT(RT_DEBUG_ERROR, ("AsicUpdateAutoFallBackTable: not support CurrMCS=%d\n", pCurrTxRate->CurrMCS));
 261                                                 }
 262                                         }
 263                                 }
 264                                 break;
 265                 }
 266
 267                 pNextTxRate = pCurrTxRate;
 268         }
 269
 270         RTMP_IO_WRITE32(pAd, HT_FBK_CFG0, HtCfg0.word);
 271         RTMP_IO_WRITE32(pAd, HT_FBK_CFG1, HtCfg1.word);
 272         RTMP_IO_WRITE32(pAd, LG_FBK_CFG0, LgCfg0.word);
 273         RTMP_IO_WRITE32(pAd, LG_FBK_CFG1, LgCfg1.word);
 274 }
 275
 276 /*
 277         ========================================================================
 278
 279         Routine Description:
 280                 Set MAC register value according operation mode.
 281                 OperationMode AND bNonGFExist are for MM and GF Proteciton.
 282                 If MM or GF mask is not set, those passing argument doesn't not take effect.
 283
 284                 Operation mode meaning:
 285                 = 0 : Pure HT, no preotection.
 286                 = 0x01; there may be non-HT devices in both the control and extension channel, protection is optional in BSS.
 287                 = 0x10: No Transmission in 40M is protected.
 288                 = 0x11: Transmission in both 40M and 20M shall be protected
 289                 if (bNonGFExist)
 290                         we should choose not to use GF. But still set correct ASIC registers.
 291         ========================================================================
 292 */
 293 VOID    AsicUpdateProtect(
 294         IN              PRTMP_ADAPTER   pAd,
 295         IN              USHORT                  OperationMode,
 296         IN              UCHAR                   SetMask,
 297         IN              BOOLEAN                 bDisableBGProtect,
 298         IN              BOOLEAN                 bNonGFExist)
 299 {
 300         PROT_CFG_STRUC  ProtCfg, ProtCfg4;
 301         UINT32 Protect[6];
 302         USHORT                  offset;
 303         UCHAR                   i;
 304         UINT32 MacReg = 0;
 305
 306
 307         if (!(pAd->CommonCfg.bHTProtect) && (OperationMode != 8))
 308         {
 309                 return;
 310         }
 311
 312         if (pAd->BATable.numDoneOriginator)
 313         {
 314                 //
 315                 // enable the RTS/CTS to avoid channel collision
 316                 //
 317                 SetMask = ALLN_SETPROTECT;
 318                 OperationMode = 8;
 319         }
 320
 321         // Config ASIC RTS threshold register
 322         RTMP_IO_READ32(pAd, TX_RTS_CFG, &MacReg);
 323         MacReg &= 0xFF0000FF;
 324         // If the user want disable RtsThreshold and enable Amsdu/Ralink-Aggregation, set the RtsThreshold as 4096
 325         if ((
 326                         (pAd->CommonCfg.BACapability.field.AmsduEnable) ||
 327                         (pAd->CommonCfg.bAggregationCapable == TRUE))
 328             && pAd->CommonCfg.RtsThreshold == MAX_RTS_THRESHOLD)
 329         {
 330                         MacReg |= (0x1000 << 8);
 331         }
 332         else
 333         {
 334                         MacReg |= (pAd->CommonCfg.RtsThreshold << 8);
 335         }
 336
 337         RTMP_IO_WRITE32(pAd, TX_RTS_CFG, MacReg);
 338
 339         // Initial common protection settings
 340         RTMPZeroMemory(Protect, sizeof(Protect));
 341         ProtCfg4.word = 0;
 342         ProtCfg.word = 0;
 343         ProtCfg.field.TxopAllowGF40 = 1;
 344         ProtCfg.field.TxopAllowGF20 = 1;
 345         ProtCfg.field.TxopAllowMM40 = 1;
 346         ProtCfg.field.TxopAllowMM20 = 1;
 347         ProtCfg.field.TxopAllowOfdm = 1;
 348         ProtCfg.field.TxopAllowCck = 1;
 349         ProtCfg.field.RTSThEn = 1;
 350         ProtCfg.field.ProtectNav = ASIC_SHORTNAV;
 351
 352         // update PHY mode and rate
 353         if (pAd->CommonCfg.Channel > 14)
 354                 ProtCfg.field.ProtectRate = 0x4000;
 355         ProtCfg.field.ProtectRate |= pAd->CommonCfg.RtsRate;
 356
 357         // Handle legacy(B/G) protection
 358         if (bDisableBGProtect)
 359         {
 360                 //ProtCfg.field.ProtectRate = pAd->CommonCfg.RtsRate;
 361                 ProtCfg.field.ProtectCtrl = 0;
 362                 Protect[0] = ProtCfg.word;
 363                 Protect[1] = ProtCfg.word;
 364                 pAd->FlgCtsEnabled = 0; /* CTS-self is not used */
 365         }
 366         else
 367         {
 368                 //ProtCfg.field.ProtectRate = pAd->CommonCfg.RtsRate;
 369                 ProtCfg.field.ProtectCtrl = 0;                  // CCK do not need to be protected
 370                 Protect[0] = ProtCfg.word;
 371                 ProtCfg.field.ProtectCtrl = ASIC_CTS;   // OFDM needs using CCK to protect
 372                 Protect[1] = ProtCfg.word;
 373                 pAd->FlgCtsEnabled = 1; /* CTS-self is used */
 374         }
 375
 376         // Decide HT frame protection.
 377         if ((SetMask & ALLN_SETPROTECT) != 0)
 378         {
 379                 switch(OperationMode)
 380                 {
 381                         case 0x0:
 382                                 // NO PROTECT
 383                                 // 1.All STAs in the BSS are 20/40 MHz HT
 384                                 // 2. in ai 20/40MHz BSS
 385                                 // 3. all STAs are 20MHz in a 20MHz BSS
 386                                 // Pure HT. no protection.
 387
 388                                 // MM20_PROT_CFG
 389                                 //      Reserved (31:27)
 390                                 //      PROT_TXOP(25:20) -- 010111
 391                                 //      PROT_NAV(19:18)  -- 01 (Short NAV protection)
 392                                 //  PROT_CTRL(17:16) -- 00 (None)
 393                                 //      PROT_RATE(15:0)  -- 0x4004 (OFDM 24M)
 394                                 Protect[2] = 0x01744004;
 395
 396                                 // MM40_PROT_CFG
 397                                 //      Reserved (31:27)
 398                                 //      PROT_TXOP(25:20) -- 111111
 399                                 //      PROT_NAV(19:18)  -- 01 (Short NAV protection)
 400                                 //  PROT_CTRL(17:16) -- 00 (None)
 401                                 //      PROT_RATE(15:0)  -- 0x4084 (duplicate OFDM 24M)
 402                                 Protect[3] = 0x03f44084;
 403
 404                                 // CF20_PROT_CFG
 405                                 //      Reserved (31:27)
 406                                 //      PROT_TXOP(25:20) -- 010111
 407                                 //      PROT_NAV(19:18)  -- 01 (Short NAV protection)
 408                                 //  PROT_CTRL(17:16) -- 00 (None)
 409                                 //      PROT_RATE(15:0)  -- 0x4004 (OFDM 24M)
 410                                 Protect[4] = 0x01744004;
 411
 412                                 // CF40_PROT_CFG
 413                                 //      Reserved (31:27)
 414                                 //      PROT_TXOP(25:20) -- 111111
 415                                 //      PROT_NAV(19:18)  -- 01 (Short NAV protection)
 416                                 //  PROT_CTRL(17:16) -- 00 (None)
 417                                 //      PROT_RATE(15:0)  -- 0x4084 (duplicate OFDM 24M)
 418                                 Protect[5] = 0x03f44084;
 419
 420                                 if (bNonGFExist)
 421                                 {
 422                                         // PROT_NAV(19:18)  -- 01 (Short NAV protectiion)
 423                                         // PROT_CTRL(17:16) -- 01 (RTS/CTS)
 424                                         Protect[4] = 0x01754004;
 425                                         Protect[5] = 0x03f54084;
 426                                 }
 427                                 pAd->CommonCfg.IOTestParm.bRTSLongProtOn = FALSE;
 428                                 break;
 429
 430                         case 1:
 431                                 // This is "HT non-member protection mode."
 432                                 // If there may be non-HT STAs my BSS
 433                                 ProtCfg.word = 0x01744004;      // PROT_CTRL(17:16) : 0 (None)
 434                                 ProtCfg4.word = 0x03f44084; // duplicaet legacy 24M. BW set 1.
 435                                 if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_BG_PROTECTION_INUSED))
 436                                 {
 437                                         ProtCfg.word = 0x01740003;      //ERP use Protection bit is set, use protection rate at Clause 18..
 438                                         ProtCfg4.word = 0x03f40003; // Don't duplicate RTS/CTS in CCK mode. 0x03f40083;
 439                                 }
 440                                 //Assign Protection method for 20&40 MHz packets
 441                                 ProtCfg.field.ProtectCtrl = ASIC_RTS;
 442                                 ProtCfg.field.ProtectNav = ASIC_SHORTNAV;
 443                                 ProtCfg4.field.ProtectCtrl = ASIC_RTS;
 444                                 ProtCfg4.field.ProtectNav = ASIC_SHORTNAV;
 445                                 Protect[2] = ProtCfg.word;
 446                                 Protect[3] = ProtCfg4.word;
 447                                 Protect[4] = ProtCfg.word;
 448                                 Protect[5] = ProtCfg4.word;
 449                                 pAd->CommonCfg.IOTestParm.bRTSLongProtOn = TRUE;
 450                                 break;
 451
 452                         case 2:
 453                                 // If only HT STAs are in BSS. at least one is 20MHz. Only protect 40MHz packets
 454                                 ProtCfg.word = 0x01744004;  // PROT_CTRL(17:16) : 0 (None)
 455                                 ProtCfg4.word = 0x03f44084; // duplicaet legacy 24M. BW set 1.
 456
 457                                 //Assign Protection method for 40MHz packets
 458                                 ProtCfg4.field.ProtectCtrl = ASIC_RTS;
 459                                 ProtCfg4.field.ProtectNav = ASIC_SHORTNAV;
 460                                 Protect[2] = ProtCfg.word;
 461                                 Protect[3] = ProtCfg4.word;
 462                                 if (bNonGFExist)
 463                                 {
 464                                         ProtCfg.field.ProtectCtrl = ASIC_RTS;
 465                                         ProtCfg.field.ProtectNav = ASIC_SHORTNAV;
 466                                 }
 467                                 Protect[4] = ProtCfg.word;
 468                                 Protect[5] = ProtCfg4.word;
 469
 470                                 pAd->CommonCfg.IOTestParm.bRTSLongProtOn = FALSE;
 471                                 break;
 472
 473                         case 3:
 474                                 // HT mixed mode.        PROTECT ALL!
 475                                 // Assign Rate
 476                                 ProtCfg.word = 0x01744004;      //duplicaet legacy 24M. BW set 1.
 477                                 ProtCfg4.word = 0x03f44084;
 478                                 // both 20MHz and 40MHz are protected. Whether use RTS or CTS-to-self depends on the
 479                                 if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_BG_PROTECTION_INUSED))
 480                                 {
 481                                         ProtCfg.word = 0x01740003;      //ERP use Protection bit is set, use protection rate at Clause 18..
 482                                         ProtCfg4.word = 0x03f40003; // Don't duplicate RTS/CTS in CCK mode. 0x03f40083
 483                                 }
 484                                 //Assign Protection method for 20&40 MHz packets
 485                                 ProtCfg.field.ProtectCtrl = ASIC_RTS;
 486                                 ProtCfg.field.ProtectNav = ASIC_SHORTNAV;
 487                                 ProtCfg4.field.ProtectCtrl = ASIC_RTS;
 488                                 ProtCfg4.field.ProtectNav = ASIC_SHORTNAV;
 489                                 Protect[2] = ProtCfg.word;
 490                                 Protect[3] = ProtCfg4.word;
 491                                 Protect[4] = ProtCfg.word;
 492                                 Protect[5] = ProtCfg4.word;
 493                                 pAd->CommonCfg.IOTestParm.bRTSLongProtOn = TRUE;
 494                                 break;
 495
 496                         case 8:
 497                                 // Special on for Atheros problem n chip.
 498                                 Protect[2] = 0x01754004;
 499                                 Protect[3] = 0x03f54084;
 500                                 Protect[4] = 0x01754004;
 501                                 Protect[5] = 0x03f54084;
 502                                 pAd->CommonCfg.IOTestParm.bRTSLongProtOn = TRUE;
 503                                 break;
 504                 }
 505         }
 506
 507         offset = CCK_PROT_CFG;
 508         for (i = 0;i < 6;i++)
 509         {
 510                         if ((SetMask & (1<< i)))
 511                 {
 512                 RTMP_IO_WRITE32(pAd, offset + i*4, Protect[i]);
 513         }
 514 }
 515 }
 516
 517
 518 /*
 519         ==========================================================================
 520         Description:
 521
 522         IRQL = PASSIVE_LEVEL
 523         IRQL = DISPATCH_LEVEL
 524
 525         ==========================================================================
 526  */
 527 VOID AsicSwitchChannel(
 528                                           IN PRTMP_ADAPTER pAd,
 529         IN      UCHAR                   Channel,
 530         IN      BOOLEAN                 bScan)
 531 {
 532         ULONG                   R2 = 0, R3 = DEFAULT_RF_TX_POWER, R4 = 0;
 533         CHAR    TxPwer = 0, TxPwer2 = DEFAULT_RF_TX_POWER; //Bbp94 = BBPR94_DEFAULT, TxPwer2 = DEFAULT_RF_TX_POWER;
 534         UCHAR   index;
 535         UINT32  Value = 0; //BbpReg, Value;
 536         RTMP_RF_REGS *RFRegTable;
 537         UCHAR   RFValue;
 538
 539         RFValue = 0;
 540         // Search Tx power value
 541         // We can't use ChannelList to search channel, since some central channl's txpowr doesn't list
 542         // in ChannelList, so use TxPower array instead.
 543         //
 544         for (index = 0; index < MAX_NUM_OF_CHANNELS; index++)
 545         {
 546                 if (Channel == pAd->TxPower[index].Channel)
 547                 {
 548                         TxPwer = pAd->TxPower[index].Power;
 549                         TxPwer2 = pAd->TxPower[index].Power2;
 550                         break;
 551                 }
 552         }
 553
 554         if (index == MAX_NUM_OF_CHANNELS)
 555         {
 556                 DBGPRINT(RT_DEBUG_ERROR, ("AsicSwitchChannel: Can't find the Channel#%d \n", Channel));
 557         }
 558
 559 #ifdef RT30xx
 560         // The RF programming sequence is difference between 3xxx and 2xxx
 561         if ((IS_RT3070(pAd) || IS_RT3090(pAd)||IS_RT3390(pAd)) && ((pAd->RfIcType == RFIC_3020) || (pAd->RfIcType == RFIC_2020) ||
 562                 (pAd->RfIcType == RFIC_3021) || (pAd->RfIcType == RFIC_3022)))
 563         {
 564                 /* modify by WY for Read RF Reg. error */
 565
 566                 for (index = 0; index < NUM_OF_3020_CHNL; index++)
 567                 {
 568                         if (Channel == FreqItems3020[index].Channel)
 569                         {
 570                                 // Programming channel parameters
 571                                 RT30xxWriteRFRegister(pAd, RF_R02, FreqItems3020[index].N);
 572                                 RT30xxWriteRFRegister(pAd, RF_R03, FreqItems3020[index].K);
 573                                 RT30xxReadRFRegister(pAd, RF_R06, &RFValue);
 574                                 RFValue = (RFValue & 0xFC) | FreqItems3020[index].R;
 575                                 RT30xxWriteRFRegister(pAd, RF_R06, RFValue);
 576
 577                                 // Set Tx0 Power
 578                                 RT30xxReadRFRegister(pAd, RF_R12, &RFValue);
 579                                 RFValue = (RFValue & 0xE0) | TxPwer;
 580                                 RT30xxWriteRFRegister(pAd, RF_R12, RFValue);
 581
 582                                 // Set Tx1 Power
 583                                 RT30xxReadRFRegister(pAd, RF_R13, &RFValue);
 584                                 RFValue = (RFValue & 0xE0) | TxPwer2;
 585                                 RT30xxWriteRFRegister(pAd, RF_R13, RFValue);
 586
 587                                 // Tx/Rx Stream setting
 588                                 RT30xxReadRFRegister(pAd, RF_R01, &RFValue);
 589                                 //if (IS_RT3090(pAd))
 590                                 //      RFValue |= 0x01; // Enable RF block.
 591                                 RFValue &= 0x03;        //clear bit[7~2]
 592                                 if (pAd->Antenna.field.TxPath == 1)
 593                                         RFValue |= 0xA0;
 594                                 else if (pAd->Antenna.field.TxPath == 2)
 595                                         RFValue |= 0x80;
 596                                 if (pAd->Antenna.field.RxPath == 1)
 597                                         RFValue |= 0x50;
 598                                 else if (pAd->Antenna.field.RxPath == 2)
 599                                         RFValue |= 0x40;
 600                                 RT30xxWriteRFRegister(pAd, RF_R01, RFValue);
 601
 602                                 // Set RF offset
 603                                 RT30xxReadRFRegister(pAd, RF_R23, &RFValue);
 604                                 RFValue = (RFValue & 0x80) | pAd->RfFreqOffset;
 605                                 RT30xxWriteRFRegister(pAd, RF_R23, RFValue);
 606
 607                                 // Set BW
 608                                 if (!bScan && (pAd->CommonCfg.BBPCurrentBW == BW_40))
 609                         {
 610                                         RFValue = pAd->Mlme.CaliBW40RfR24;
 611                                         //DISABLE_11N_CHECK(pAd);
 612                                 }
 613                                 else
 614                         {
 615                                         RFValue = pAd->Mlme.CaliBW20RfR24;
 616                                 }
 617                                 RT30xxWriteRFRegister(pAd, RF_R24, RFValue);
 618                                 RT30xxWriteRFRegister(pAd, RF_R31, RFValue);
 619
 620                                 // Enable RF tuning
 621                                 RT30xxReadRFRegister(pAd, RF_R07, &RFValue);
 622                                 RFValue = RFValue | 0x1;
 623                                 RT30xxWriteRFRegister(pAd, RF_R07, RFValue);
 624
 625                                 // latch channel for future usage.
 626                                 pAd->LatchRfRegs.Channel = Channel;
 627
 628                 DBGPRINT(RT_DEBUG_TRACE, ("SwitchChannel#%d(RF=%d, Pwr0=%d, Pwr1=%d, %dT), N=0x%02X, K=0x%02X, R=0x%02X\n",
 629                         Channel,
 630                         pAd->RfIcType,
 631                         TxPwer,
 632                         TxPwer2,
 633                         pAd->Antenna.field.TxPath,
 634                         FreqItems3020[index].N,
 635                         FreqItems3020[index].K,
 636                         FreqItems3020[index].R));
 637
 638                                 break;
 639                         }
 640                 }
 641         }
 642         else
 643 #endif // RT30xx //
 644         {
 645                 RFRegTable = RF2850RegTable;
 646                 switch (pAd->RfIcType)
 647                 {
 648                         case RFIC_2820:
 649                         case RFIC_2850:
 650                         case RFIC_2720:
 651                         case RFIC_2750:
 652
 653                                 for (index = 0; index < NUM_OF_2850_CHNL; index++)
 654                                 {
 655                                         if (Channel == RFRegTable[index].Channel)
 656                                         {
 657                                                 R2 = RFRegTable[index].R2;
 658                                                 if (pAd->Antenna.field.TxPath == 1)
 659                                                 {
 660                                                         R2 |= 0x4000;   // If TXpath is 1, bit 14 = 1;
 661                                                 }
 662
 663                                                 if (pAd->Antenna.field.RxPath == 2)
 664                                                 {
 665                                                         R2 |= 0x40;     // write 1 to off Rxpath.
 666                                                 }
 667                                                 else if (pAd->Antenna.field.RxPath == 1)
 668                                                 {
 669                                                         R2 |= 0x20040;  // write 1 to off RxPath
 670                                                 }
 671
 672                                                 if (Channel > 14)
 673                                                 {
 674                                                         // initialize R3, R4
 675                                                         R3 = (RFRegTable[index].R3 & 0xffffc1ff);
 676                                                         R4 = (RFRegTable[index].R4 & (~0x001f87c0)) | (pAd->RfFreqOffset << 15);
 677
 678                                                         // 5G band power range: 0xF9~0X0F, TX0 Reg3 bit9/TX1 Reg4 bit6="0" means the TX power reduce 7dB
 679                                                         // R3
 680                                                         if ((TxPwer >= -7) && (TxPwer < 0))
 681                                                         {
 682                                                                 TxPwer = (7+TxPwer);
 683                                                                 TxPwer = (TxPwer > 0xF) ? (0xF) : (TxPwer);
 684                                                                 R3 |= (TxPwer << 10);
 685                                                                 DBGPRINT(RT_DEBUG_ERROR, ("AsicSwitchChannel: TxPwer=%d \n", TxPwer));
 686                                                         }
 687                                                         else
 688                                                         {
 689                                                                 TxPwer = (TxPwer > 0xF) ? (0xF) : (TxPwer);
 690                                                                 R3 |= (TxPwer << 10) | (1 << 9);
 691                                                         }
 692
 693                                                         // R4
 694                                                         if ((TxPwer2 >= -7) && (TxPwer2 < 0))
 695                                                         {
 696                                                                 TxPwer2 = (7+TxPwer2);
 697                                                                 TxPwer2 = (TxPwer2 > 0xF) ? (0xF) : (TxPwer2);
 698                                                                 R4 |= (TxPwer2 << 7);
 699                                                                 DBGPRINT(RT_DEBUG_ERROR, ("AsicSwitchChannel: TxPwer2=%d \n", TxPwer2));
 700                                                         }
 701                                                         else
 702                                                         {
 703                                                                 TxPwer2 = (TxPwer2 > 0xF) ? (0xF) : (TxPwer2);
 704                                                                 R4 |= (TxPwer2 << 7) | (1 << 6);
 705                                                         }
 706                                                 }
 707                                                 else
 708                                                 {
 709                                                         R3 = (RFRegTable[index].R3 & 0xffffc1ff) | (TxPwer << 9); // set TX power0
 710                                                 R4 = (RFRegTable[index].R4 & (~0x001f87c0)) | (pAd->RfFreqOffset << 15) | (TxPwer2 <<6);// Set freq Offset & TxPwr1
 711                                                 }
 712
 713                                                 // Based on BBP current mode before changing RF channel.
 714                                                 if (!bScan && (pAd->CommonCfg.BBPCurrentBW == BW_40))
 715                                                 {
 716                                                         R4 |=0x200000;
 717                                                 }
 718
 719                                                 // Update variables
 720                                                 pAd->LatchRfRegs.Channel = Channel;
 721                                                 pAd->LatchRfRegs.R1 = RFRegTable[index].R1;
 722                                                 pAd->LatchRfRegs.R2 = R2;
 723                                                 pAd->LatchRfRegs.R3 = R3;
 724                                                 pAd->LatchRfRegs.R4 = R4;
 725
 726                                                 // Set RF value 1's set R3[bit2] = [0]
 727                                                 RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R1);
 728                                                 RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R2);
 729                                                 RTMP_RF_IO_WRITE32(pAd, (pAd->LatchRfRegs.R3 & (~0x04)));
 730                                                 RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R4);
 731
 732                                                 RTMPusecDelay(200);
 733
 734                                                 // Set RF value 2's set R3[bit2] = [1]
 735                                                 RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R1);
 736                                                 RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R2);
 737                                                 RTMP_RF_IO_WRITE32(pAd, (pAd->LatchRfRegs.R3 | 0x04));
 738                                                 RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R4);
 739
 740                                                 RTMPusecDelay(200);
 741
 742                                                 // Set RF value 3's set R3[bit2] = [0]
 743                                                 RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R1);
 744                                                 RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R2);
 745                                                 RTMP_RF_IO_WRITE32(pAd, (pAd->LatchRfRegs.R3 & (~0x04)));
 746                                                 RTMP_RF_IO_WRITE32(pAd, pAd->LatchRfRegs.R4);
 747
 748                                                 break;
 749                                         }
 750                                 }
 751                                 break;
 752
 753                         default:
 754                                 break;
 755                 }
 756
 757                 DBGPRINT(RT_DEBUG_TRACE, ("SwitchChannel#%d(RF=%d, Pwr0=%lu, Pwr1=%lu, %dT) to , R1=0x%08lx, R2=0x%08lx, R3=0x%08lx, R4=0x%08lx\n",
 758                                                           Channel,
 759                                                           pAd->RfIcType,
 760                                                           (R3 & 0x00003e00) >> 9,
 761                                                           (R4 & 0x000007c0) >> 6,
 762                                                           pAd->Antenna.field.TxPath,
 763                                                           pAd->LatchRfRegs.R1,
 764                                                           pAd->LatchRfRegs.R2,
 765                                                           pAd->LatchRfRegs.R3,
 766                                                           pAd->LatchRfRegs.R4));
 767         }
 768
 769         // Change BBP setting during siwtch from a->g, g->a
 770         if (Channel <= 14)
 771         {
 772                 ULONG   TxPinCfg = 0x00050F0A;//Gary 2007/08/09 0x050A0A
 773
 774                 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - GET_LNA_GAIN(pAd)));
 775                 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - GET_LNA_GAIN(pAd)));
 776                 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - GET_LNA_GAIN(pAd)));
 777                 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0);//(0x44 - GET_LNA_GAIN(pAd)));    // According the Rory's suggestion to solve the middle range issue.
 778                 //RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x62);
 779
 780                 // Rx High power VGA offset for LNA select
 781                 if (pAd->NicConfig2.field.ExternalLNAForG)
 782                 {
 783                         RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x62);
 784                         RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x46);
 785                 }
 786                 else
 787                 {
 788                         RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x84);
 789                         RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x50);
 790                 }
 791
 792                 // 5G band selection PIN, bit1 and bit2 are complement
 793                 RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value);
 794                 Value &= (~0x6);
 795                 Value |= (0x04);
 796                 RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value);
 797
 798                 // Turn off unused PA or LNA when only 1T or 1R
 799                 if (pAd->Antenna.field.TxPath == 1)
 800                 {
 801                         TxPinCfg &= 0xFFFFFFF3;
 802                 }
 803                 if (pAd->Antenna.field.RxPath == 1)
 804                 {
 805                         TxPinCfg &= 0xFFFFF3FF;
 806                 }
 807
 808
 809                 RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
 810
 811         }
 812         else
 813         {
 814                 ULONG   TxPinCfg = 0x00050F05;//Gary 2007/8/9 0x050505
 815
 816                 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - GET_LNA_GAIN(pAd)));
 817                 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - GET_LNA_GAIN(pAd)));
 818                 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - GET_LNA_GAIN(pAd)));
 819                 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0);//(0x44 - GET_LNA_GAIN(pAd)));   // According the Rory's suggestion to solve the middle range issue.
 820                         RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0xF2);
 821
 822                 // Rx High power VGA offset for LNA select
 823                 if (pAd->NicConfig2.field.ExternalLNAForA)
 824                 {
 825                         RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x46);
 826                 }
 827                 else
 828                 {
 829                         RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x50);
 830                 }
 831
 832                 // 5G band selection PIN, bit1 and bit2 are complement
 833                 RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value);
 834                 Value &= (~0x6);
 835                 Value |= (0x02);
 836                 RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value);
 837
 838                 // Turn off unused PA or LNA when only 1T or 1R
 839                 if (pAd->Antenna.field.TxPath == 1)
 840                 {
 841                         TxPinCfg &= 0xFFFFFFF3;
 842                 }
 843                 if (pAd->Antenna.field.RxPath == 1)
 844                 {
 845                         TxPinCfg &= 0xFFFFF3FF;
 846                 }
 847
 848
 849                 RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
 850
 851         }
 852
 853         // R66 should be set according to Channel and use 20MHz when scanning
 854         //RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, (0x2E + GET_LNA_GAIN(pAd)));
 855         if (bScan)
 856                 RTMPSetAGCInitValue(pAd, BW_20);
 857         else
 858                 RTMPSetAGCInitValue(pAd, pAd->CommonCfg.BBPCurrentBW);
 859
 860         //
 861         // On 11A, We should delay and wait RF/BBP to be stable
 862         // and the appropriate time should be 1000 micro seconds
 863         // 2005/06/05 - On 11G, We also need this delay time. Otherwise it's difficult to pass the WHQL.
 864         //
 865         RTMPusecDelay(1000);
 866 }
 867
 868 VOID AsicResetBBPAgent(
 869 IN PRTMP_ADAPTER pAd)
 870 {
 871         BBP_CSR_CFG_STRUC       BbpCsr;
 872         DBGPRINT(RT_DEBUG_ERROR, ("Reset BBP Agent busy bit.!! \n"));
 873         // Still need to find why BBP agent keeps busy, but in fact, hardware still function ok. Now clear busy first.
 874         RTMP_IO_READ32(pAd, H2M_BBP_AGENT, &BbpCsr.word);
 875         BbpCsr.field.Busy = 0;
 876         RTMP_IO_WRITE32(pAd, H2M_BBP_AGENT, BbpCsr.word);
 877 }
 878
 879 /*
 880         ==========================================================================
 881         Description:
 882                 This function is required for 2421 only, and should not be used during
 883                 site survey. It's only required after NIC decided to stay at a channel
 884                 for a longer period.
 885                 When this function is called, it's always after AsicSwitchChannel().
 886
 887         IRQL = PASSIVE_LEVEL
 888         IRQL = DISPATCH_LEVEL
 889
 890         ==========================================================================
 891  */
 892 VOID AsicLockChannel(
 893         IN PRTMP_ADAPTER pAd,
 894         IN UCHAR Channel)
 895 {
 896 }
 897
 898 VOID AsicRfTuningExec(
 899         IN PVOID SystemSpecific1,
 900         IN PVOID FunctionContext,
 901         IN PVOID SystemSpecific2,
 902         IN PVOID SystemSpecific3)
 903 {
 904 }
 905
 906 /*
 907         ==========================================================================
 908         Description:
 909                 Gives CCK TX rate 2 more dB TX power.
 910                 This routine works only in LINK UP in INFRASTRUCTURE mode.
 911
 912                 calculate desired Tx power in RF R3.Tx0~5,      should consider -
 913                 0. if current radio is a noisy environment (pAd->DrsCounters.fNoisyEnvironment)
 914                 1. TxPowerPercentage
 915                 2. auto calibration based on TSSI feedback
 916                 3. extra 2 db for CCK
 917                 4. -10 db upon very-short distance (AvgRSSI >= -40db) to AP
 918
 919         NOTE: Since this routine requires the value of (pAd->DrsCounters.fNoisyEnvironment),
 920                 it should be called AFTER MlmeDynamicTxRatSwitching()
 921         ==========================================================================
 922  */
 923 VOID AsicAdjustTxPower(
 924         IN PRTMP_ADAPTER pAd)
 925 {
 926         INT                     i, j;
 927         CHAR            DeltaPwr = 0;
 928         BOOLEAN         bAutoTxAgc = FALSE;
 929         UCHAR           TssiRef, *pTssiMinusBoundary, *pTssiPlusBoundary, TxAgcStep;
 930         UCHAR           BbpR1 = 0, BbpR49 = 0, idx;
 931         PCHAR           pTxAgcCompensate;
 932         ULONG           TxPwr[5];
 933         CHAR            Value;
 934         CHAR            Rssi = -127;
 935
 936
 937
 938         if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE) ||
 939 #ifdef RTMP_MAC_PCI
 940                 (pAd->bPCIclkOff == TRUE) ||
 941 #endif // RTMP_MAC_PCI //
 942                 RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_IDLE_RADIO_OFF) ||
 943                 RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_BSS_SCAN_IN_PROGRESS))
 944                 return;
 945
 946                 Rssi = RTMPMaxRssi(pAd,
 947                                                    pAd->StaCfg.RssiSample.AvgRssi0,
 948                                                    pAd->StaCfg.RssiSample.AvgRssi1,
 949                                                    pAd->StaCfg.RssiSample.AvgRssi2);
 950
 951         if (pAd->CommonCfg.BBPCurrentBW == BW_40)
 952         {
 953                 if (pAd->CommonCfg.CentralChannel > 14)
 954                 {
 955                         TxPwr[0] = pAd->Tx40MPwrCfgABand[0];
 956                         TxPwr[1] = pAd->Tx40MPwrCfgABand[1];
 957                         TxPwr[2] = pAd->Tx40MPwrCfgABand[2];
 958                         TxPwr[3] = pAd->Tx40MPwrCfgABand[3];
 959                         TxPwr[4] = pAd->Tx40MPwrCfgABand[4];
 960                 }
 961                 else
 962                 {
 963                         TxPwr[0] = pAd->Tx40MPwrCfgGBand[0];
 964                         TxPwr[1] = pAd->Tx40MPwrCfgGBand[1];
 965                         TxPwr[2] = pAd->Tx40MPwrCfgGBand[2];
 966                         TxPwr[3] = pAd->Tx40MPwrCfgGBand[3];
 967                         TxPwr[4] = pAd->Tx40MPwrCfgGBand[4];
 968                 }
 969         }
 970         else
 971         {
 972                 if (pAd->CommonCfg.Channel > 14)
 973                 {
 974                         TxPwr[0] = pAd->Tx20MPwrCfgABand[0];
 975                         TxPwr[1] = pAd->Tx20MPwrCfgABand[1];
 976                         TxPwr[2] = pAd->Tx20MPwrCfgABand[2];
 977                         TxPwr[3] = pAd->Tx20MPwrCfgABand[3];
 978                         TxPwr[4] = pAd->Tx20MPwrCfgABand[4];
 979                 }
 980                 else
 981                 {
 982                         TxPwr[0] = pAd->Tx20MPwrCfgGBand[0];
 983                         TxPwr[1] = pAd->Tx20MPwrCfgGBand[1];
 984                         TxPwr[2] = pAd->Tx20MPwrCfgGBand[2];
 985                         TxPwr[3] = pAd->Tx20MPwrCfgGBand[3];
 986                         TxPwr[4] = pAd->Tx20MPwrCfgGBand[4];
 987                 }
 988         }
 989
 990         // TX power compensation for temperature variation based on TSSI. try every 4 second
 991         if (pAd->Mlme.OneSecPeriodicRound % 4 == 0)
 992         {
 993                 if (pAd->CommonCfg.Channel <= 14)
 994                 {
 995                         /* bg channel */
 996                         bAutoTxAgc         = pAd->bAutoTxAgcG;
 997                         TssiRef            = pAd->TssiRefG;
 998                         pTssiMinusBoundary = &pAd->TssiMinusBoundaryG[0];
 999                         pTssiPlusBoundary  = &pAd->TssiPlusBoundaryG[0];
1000                         TxAgcStep          = pAd->TxAgcStepG;
1001                         pTxAgcCompensate   = &pAd->TxAgcCompensateG;
1002                 }
1003                 else
1004                 {
1005                         /* a channel */
1006                         bAutoTxAgc         = pAd->bAutoTxAgcA;
1007                         TssiRef            = pAd->TssiRefA;
1008                         pTssiMinusBoundary = &pAd->TssiMinusBoundaryA[0];
1009                         pTssiPlusBoundary  = &pAd->TssiPlusBoundaryA[0];
1010                         TxAgcStep          = pAd->TxAgcStepA;
1011                         pTxAgcCompensate   = &pAd->TxAgcCompensateA;
1012                 }
1013
1014                 if (bAutoTxAgc)
1015                 {
1016                         /* BbpR1 is unsigned char */
1017                         RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R49, &BbpR49);
1018
1019                         /* (p) TssiPlusBoundaryG[0] = 0 = (m) TssiMinusBoundaryG[0] */
1020                         /* compensate: +4     +3   +2   +1    0   -1   -2   -3   -4 * steps */
1021                         /* step value is defined in pAd->TxAgcStepG for tx power value */
1022
1023                         /* [4]+1+[4]   p4     p3   p2   p1   o1   m1   m2   m3   m4 */
1024                         /* ex:         0x00 0x15 0x25 0x45 0x88 0xA0 0xB5 0xD0 0xF0
1025                            above value are examined in mass factory production */
1026                         /*             [4]    [3]  [2]  [1]  [0]  [1]  [2]  [3]  [4] */
1027
1028                         /* plus (+) is 0x00 ~ 0x45, minus (-) is 0xa0 ~ 0xf0 */
1029                         /* if value is between p1 ~ o1 or o1 ~ s1, no need to adjust tx power */
1030                         /* if value is 0xa5, tx power will be -= TxAgcStep*(2-1) */
1031
1032                         if (BbpR49 > pTssiMinusBoundary[1])
1033                         {
1034                                 // Reading is larger than the reference value
1035                                 // check for how large we need to decrease the Tx power
1036                                 for (idx = 1; idx < 5; idx++)
1037                                 {
1038                                         if (BbpR49 <= pTssiMinusBoundary[idx])  // Found the range
1039                                                 break;
1040                                 }
1041                                 // The index is the step we should decrease, idx = 0 means there is nothing to compensate
1042 //                              if (R3 > (ULONG) (TxAgcStep * (idx-1)))
1043                                         *pTxAgcCompensate = -(TxAgcStep * (idx-1));
1044 //                              else
1045 //                                      *pTxAgcCompensate = -((UCHAR)R3);
1046
1047                                 DeltaPwr += (*pTxAgcCompensate);
1048                                 DBGPRINT(RT_DEBUG_TRACE, ("-- Tx Power, BBP R1=%x, TssiRef=%x, TxAgcStep=%x, step = -%d\n",
1049                                         BbpR49, TssiRef, TxAgcStep, idx-1));
1050                         }
1051                         else if (BbpR49 < pTssiPlusBoundary[1])
1052                         {
1053                                 // Reading is smaller than the reference value
1054                                 // check for how large we need to increase the Tx power
1055                                 for (idx = 1; idx < 5; idx++)
1056                                 {
1057                                         if (BbpR49 >= pTssiPlusBoundary[idx])   // Found the range
1058                                                 break;
1059                                 }
1060                                 // The index is the step we should increase, idx = 0 means there is nothing to compensate
1061                                 *pTxAgcCompensate = TxAgcStep * (idx-1);
1062                                 DeltaPwr += (*pTxAgcCompensate);
1063                                 DBGPRINT(RT_DEBUG_TRACE, ("++ Tx Power, BBP R1=%x, TssiRef=%x, TxAgcStep=%x, step = +%d\n",
1064                                         BbpR49, TssiRef, TxAgcStep, idx-1));
1065                         }
1066                         else
1067                         {
1068                                 *pTxAgcCompensate = 0;
1069                                 DBGPRINT(RT_DEBUG_TRACE, ("   Tx Power, BBP R49=%x, TssiRef=%x, TxAgcStep=%x, step = +%d\n",
1070                                         BbpR49, TssiRef, TxAgcStep, 0));
1071                         }
1072                 }
1073         }
1074         else
1075         {
1076                 if (pAd->CommonCfg.Channel <= 14)
1077                 {
1078                         bAutoTxAgc         = pAd->bAutoTxAgcG;
1079                         pTxAgcCompensate   = &pAd->TxAgcCompensateG;
1080                 }
1081                 else
1082                 {
1083                         bAutoTxAgc         = pAd->bAutoTxAgcA;
1084                         pTxAgcCompensate   = &pAd->TxAgcCompensateA;
1085                 }
1086
1087                 if (bAutoTxAgc)
1088                         DeltaPwr += (*pTxAgcCompensate);
1089         }
1090
1091         RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R1, &BbpR1);
1092         BbpR1 &= 0xFC;
1093
1094
1095         /* calculate delta power based on the percentage specified from UI */
1096         // E2PROM setting is calibrated for maximum TX power (i.e. 100%)
1097         // We lower TX power here according to the percentage specified from UI
1098         if (pAd->CommonCfg.TxPowerPercentage == 0xffffffff)       // AUTO TX POWER control
1099         {
1100                 {
1101                         // to patch high power issue with some APs, like Belkin N1.
1102                         if (Rssi > -35)
1103                         {
1104                                 BbpR1 |= 0x02;          // DeltaPwr -= 12;
1105                         }
1106                         else if (Rssi > -40)
1107                         {
1108                                 BbpR1 |= 0x01;          // DeltaPwr -= 6;
1109                         }
1110                         else
1111                 ;
1112                 }
1113         }
1114         else if (pAd->CommonCfg.TxPowerPercentage > 90)  // 91 ~ 100% & AUTO, treat as 100% in terms of mW
1115                 ;
1116         else if (pAd->CommonCfg.TxPowerPercentage > 60)  // 61 ~ 90%, treat as 75% in terms of mW               // DeltaPwr -= 1;
1117         {
1118                 DeltaPwr -= 1;
1119         }
1120         else if (pAd->CommonCfg.TxPowerPercentage > 30)  // 31 ~ 60%, treat as 50% in terms of mW               // DeltaPwr -= 3;
1121         {
1122                 DeltaPwr -= 3;
1123         }
1124         else if (pAd->CommonCfg.TxPowerPercentage > 15)  // 16 ~ 30%, treat as 25% in terms of mW               // DeltaPwr -= 6;
1125         {
1126                 BbpR1 |= 0x01;
1127         }
1128         else if (pAd->CommonCfg.TxPowerPercentage > 9)   // 10 ~ 15%, treat as 12.5% in terms of mW             // DeltaPwr -= 9;
1129         {
1130                 BbpR1 |= 0x01;
1131                 DeltaPwr -= 3;
1132         }
1133         else                                           // 0 ~ 9 %, treat as MIN(~3%) in terms of mW             // DeltaPwr -= 12;
1134         {
1135                 BbpR1 |= 0x02;
1136         }
1137
1138         RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R1, BbpR1);
1139
1140         /* reset different new tx power for different TX rate */
1141         for(i=0; i<5; i++)
1142         {
1143                 if (TxPwr[i] != 0xffffffff)
1144                 {
1145                         for (j=0; j<8; j++)
1146                         {
1147                                 Value = (CHAR)((TxPwr[i] >> j*4) & 0x0F); /* 0 ~ 15 */
1148
1149                                 if ((Value + DeltaPwr) < 0)
1150                                 {
1151                                         Value = 0; /* min */
1152                                 }
1153                                 else if ((Value + DeltaPwr) > 0xF)
1154                                 {
1155                                         Value = 0xF; /* max */
1156                                 }
1157                                 else
1158                                 {
1159                                         Value += DeltaPwr; /* temperature compensation */
1160                                 }
1161
1162                                 /* fill new value to CSR offset */
1163                                 TxPwr[i] = (TxPwr[i] & ~(0x0000000F << j*4)) | (Value << j*4);
1164                         }
1165
1166                         /* write tx power value to CSR */
1167                         /* TX_PWR_CFG_0 (8 tx rate) for TX power for OFDM 12M/18M
1168                                                                                         TX power for OFDM 6M/9M
1169                                                                                         TX power for CCK5.5M/11M
1170                                                                                         TX power for CCK1M/2M */
1171                         /* TX_PWR_CFG_1 ~ TX_PWR_CFG_4 */
1172                         RTMP_IO_WRITE32(pAd, TX_PWR_CFG_0 + i*4, TxPwr[i]);
1173                 }
1174         }
1175
1176
1177 }
1178
1179
1180 /*
1181         ==========================================================================
1182         Description:
1183                 put PHY to sleep here, and set next wakeup timer. PHY doesn't not wakeup
1184                 automatically. Instead, MCU will issue a TwakeUpInterrupt to host after
1185                 the wakeup timer timeout. Driver has to issue a separate command to wake
1186                 PHY up.
1187
1188         IRQL = DISPATCH_LEVEL
1189
1190         ==========================================================================
1191  */
1192 VOID AsicSleepThenAutoWakeup(
1193         IN PRTMP_ADAPTER pAd,
1194         IN USHORT TbttNumToNextWakeUp)
1195 {
1196         RTMP_STA_SLEEP_THEN_AUTO_WAKEUP(pAd, TbttNumToNextWakeUp);
1197 }
1198
1199 /*
1200         ==========================================================================
1201         Description:
1202                 AsicForceWakeup() is used whenever manual wakeup is required
1203                 AsicForceSleep() should only be used when not in INFRA BSS. When
1204                 in INFRA BSS, we should use AsicSleepThenAutoWakeup() instead.
1205         ==========================================================================
1206  */
1207 VOID AsicForceSleep(
1208         IN PRTMP_ADAPTER pAd)
1209 {
1210
1211 }
1212
1213 /*
1214         ==========================================================================
1215         Description:
1216                 AsicForceWakeup() is used whenever Twakeup timer (set via AsicSleepThenAutoWakeup)
1217                 expired.
1218
1219         IRQL = PASSIVE_LEVEL
1220         IRQL = DISPATCH_LEVEL
1221         ==========================================================================
1222  */
1223 VOID AsicForceWakeup(
1224         IN PRTMP_ADAPTER pAd,
1225         IN BOOLEAN    bFromTx)
1226 {
1227     DBGPRINT(RT_DEBUG_INFO, ("--> AsicForceWakeup \n"));
1228     RTMP_STA_FORCE_WAKEUP(pAd, bFromTx);
1229 }
1230
1231
1232 /*
1233         ==========================================================================
1234         Description:
1235                 Set My BSSID
1236
1237         IRQL = DISPATCH_LEVEL
1238
1239         ==========================================================================
1240  */
1241 VOID AsicSetBssid(
1242         IN PRTMP_ADAPTER pAd,
1243         IN PUCHAR pBssid)
1244 {
1245         ULONG             Addr4;
1246         DBGPRINT(RT_DEBUG_TRACE, ("==============> AsicSetBssid %x:%x:%x:%x:%x:%x\n",
1247                 pBssid[0],pBssid[1],pBssid[2],pBssid[3], pBssid[4],pBssid[5]));
1248
1249         Addr4 = (ULONG)(pBssid[0])               |
1250                         (ULONG)(pBssid[1] << 8)  |
1251                         (ULONG)(pBssid[2] << 16) |
1252                         (ULONG)(pBssid[3] << 24);
1253         RTMP_IO_WRITE32(pAd, MAC_BSSID_DW0, Addr4);
1254
1255         Addr4 = 0;
1256         // always one BSSID in STA mode
1257         Addr4 = (ULONG)(pBssid[4]) | (ULONG)(pBssid[5] << 8);
1258
1259         RTMP_IO_WRITE32(pAd, MAC_BSSID_DW1, Addr4);
1260 }
1261
1262 VOID AsicSetMcastWC(
1263         IN PRTMP_ADAPTER pAd)
1264 {
1265         MAC_TABLE_ENTRY *pEntry = &pAd->MacTab.Content[MCAST_WCID];
1266         USHORT          offset;
1267
1268         pEntry->Sst        = SST_ASSOC;
1269         pEntry->Aid        = MCAST_WCID;        // Softap supports 1 BSSID and use WCID=0 as multicast Wcid index
1270         pEntry->PsMode     = PWR_ACTIVE;
1271         pEntry->CurrTxRate = pAd->CommonCfg.MlmeRate;
1272         offset = MAC_WCID_BASE + BSS0Mcast_WCID * HW_WCID_ENTRY_SIZE;
1273 }
1274
1275 /*
1276         ==========================================================================
1277         Description:
1278
1279         IRQL = DISPATCH_LEVEL
1280
1281         ==========================================================================
1282  */
1283 VOID AsicDelWcidTab(
1284         IN PRTMP_ADAPTER pAd,
1285         IN UCHAR        Wcid)
1286 {
1287         ULONG             Addr0 = 0x0, Addr1 = 0x0;
1288         ULONG           offset;
1289
1290         DBGPRINT(RT_DEBUG_TRACE, ("AsicDelWcidTab==>Wcid = 0x%x\n",Wcid));
1291         offset = MAC_WCID_BASE + Wcid * HW_WCID_ENTRY_SIZE;
1292         RTMP_IO_WRITE32(pAd, offset, Addr0);
1293         offset += 4;
1294         RTMP_IO_WRITE32(pAd, offset, Addr1);
1295 }
1296
1297 /*
1298         ==========================================================================
1299         Description:
1300
1301         IRQL = DISPATCH_LEVEL
1302
1303         ==========================================================================
1304  */
1305 VOID AsicEnableRDG(
1306         IN PRTMP_ADAPTER pAd)
1307 {
1308         TX_LINK_CFG_STRUC       TxLinkCfg;
1309         UINT32                          Data = 0;
1310
1311         RTMP_IO_READ32(pAd, TX_LINK_CFG, &TxLinkCfg.word);
1312         TxLinkCfg.field.TxRDGEn = 1;
1313         RTMP_IO_WRITE32(pAd, TX_LINK_CFG, TxLinkCfg.word);
1314
1315         RTMP_IO_READ32(pAd, EDCA_AC0_CFG, &Data);
1316         Data  &= 0xFFFFFF00;
1317         Data  |= 0x80;
1318         RTMP_IO_WRITE32(pAd, EDCA_AC0_CFG, Data);
1319
1320         //OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_AGGREGATION_INUSED);
1321 }
1322
1323 /*
1324         ==========================================================================
1325         Description:
1326
1327         IRQL = DISPATCH_LEVEL
1328
1329         ==========================================================================
1330  */
1331 VOID AsicDisableRDG(
1332         IN PRTMP_ADAPTER pAd)
1333 {
1334         TX_LINK_CFG_STRUC       TxLinkCfg;
1335         UINT32                          Data = 0;
1336
1337
1338         RTMP_IO_READ32(pAd, TX_LINK_CFG, &TxLinkCfg.word);
1339         TxLinkCfg.field.TxRDGEn = 0;
1340         RTMP_IO_WRITE32(pAd, TX_LINK_CFG, TxLinkCfg.word);
1341
1342         RTMP_IO_READ32(pAd, EDCA_AC0_CFG, &Data);
1343
1344         Data  &= 0xFFFFFF00;
1345         //Data  |= 0x20;
1346 #ifndef WIFI_TEST
1347         //if ( pAd->CommonCfg.bEnableTxBurst )
1348         //      Data |= 0x60; // for performance issue not set the TXOP to 0
1349 #endif
1350         if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_DYNAMIC_BE_TXOP_ACTIVE)
1351                 && (pAd->MacTab.fAnyStationMIMOPSDynamic == FALSE)
1352         )
1353         {
1354                 // For CWC test, change txop from 0x30 to 0x20 in TxBurst mode
1355                 if (pAd->CommonCfg.bEnableTxBurst)
1356                 Data |= 0x20;
1357         }
1358         RTMP_IO_WRITE32(pAd, EDCA_AC0_CFG, Data);
1359 }
1360
1361 /*
1362         ==========================================================================
1363         Description:
1364
1365         IRQL = PASSIVE_LEVEL
1366         IRQL = DISPATCH_LEVEL
1367
1368         ==========================================================================
1369  */
1370 VOID AsicDisableSync(
1371         IN PRTMP_ADAPTER pAd)
1372 {
1373         BCN_TIME_CFG_STRUC csr;
1374
1375         DBGPRINT(RT_DEBUG_TRACE, ("--->Disable TSF synchronization\n"));
1376
1377         // 2003-12-20 disable TSF and TBTT while NIC in power-saving have side effect
1378         //                        that NIC will never wakes up because TSF stops and no more
1379         //                        TBTT interrupts
1380         pAd->TbttTickCount = 0;
1381         RTMP_IO_READ32(pAd, BCN_TIME_CFG, &csr.word);
1382         csr.field.bBeaconGen = 0;
1383         csr.field.bTBTTEnable = 0;
1384         csr.field.TsfSyncMode = 0;
1385         csr.field.bTsfTicking = 0;
1386         RTMP_IO_WRITE32(pAd, BCN_TIME_CFG, csr.word);
1387
1388 }
1389
1390 /*
1391         ==========================================================================
1392         Description:
1393
1394         IRQL = DISPATCH_LEVEL
1395
1396         ==========================================================================
1397  */
1398 VOID AsicEnableBssSync(
1399         IN PRTMP_ADAPTER pAd)
1400 {
1401         BCN_TIME_CFG_STRUC csr;
1402
1403         DBGPRINT(RT_DEBUG_TRACE, ("--->AsicEnableBssSync(INFRA mode)\n"));
1404
1405         RTMP_IO_READ32(pAd, BCN_TIME_CFG, &csr.word);
1406 //      RTMP_IO_WRITE32(pAd, BCN_TIME_CFG, 0x00000000);
1407         {
1408                 csr.field.BeaconInterval = pAd->CommonCfg.BeaconPeriod << 4; // ASIC register in units of 1/16 TU
1409                 csr.field.bTsfTicking = 1;
1410                 csr.field.TsfSyncMode = 1; // sync TSF in INFRASTRUCTURE mode
1411                 csr.field.bBeaconGen  = 0; // do NOT generate BEACON
1412                 csr.field.bTBTTEnable = 1;
1413         }
1414         RTMP_IO_WRITE32(pAd, BCN_TIME_CFG, csr.word);
1415 }
1416
1417 /*
1418         ==========================================================================
1419         Description:
1420         Note:
1421                 BEACON frame in shared memory should be built ok before this routine
1422                 can be called. Otherwise, a garbage frame maybe transmitted out every
1423                 Beacon period.
1424
1425         IRQL = DISPATCH_LEVEL
1426
1427         ==========================================================================
1428  */
1429 VOID AsicEnableIbssSync(
1430         IN PRTMP_ADAPTER pAd)
1431 {
1432         BCN_TIME_CFG_STRUC csr9;
1433         PUCHAR                  ptr;
1434         UINT i;
1435
1436         DBGPRINT(RT_DEBUG_TRACE, ("--->AsicEnableIbssSync(ADHOC mode. MPDUtotalByteCount = %d)\n", pAd->BeaconTxWI.MPDUtotalByteCount));
1437
1438         RTMP_IO_READ32(pAd, BCN_TIME_CFG, &csr9.word);
1439         csr9.field.bBeaconGen = 0;
1440         csr9.field.bTBTTEnable = 0;
1441         csr9.field.bTsfTicking = 0;
1442         RTMP_IO_WRITE32(pAd, BCN_TIME_CFG, csr9.word);
1443
1444 #ifdef RTMP_MAC_PCI
1445         // move BEACON TXD and frame content to on-chip memory
1446         ptr = (PUCHAR)&pAd->BeaconTxWI;
1447         for (i=0; i<TXWI_SIZE; i+=4)  // 16-byte TXWI field
1448         {
1449                 UINT32 longptr =  *ptr + (*(ptr+1)<<8) + (*(ptr+2)<<16) + (*(ptr+3)<<24);
1450                 RTMP_IO_WRITE32(pAd, HW_BEACON_BASE0 + i, longptr);
1451                 ptr += 4;
1452         }
1453
1454         // start right after the 16-byte TXWI field
1455         ptr = pAd->BeaconBuf;
1456         for (i=0; i< pAd->BeaconTxWI.MPDUtotalByteCount; i+=4)
1457         {
1458                 UINT32 longptr =  *ptr + (*(ptr+1)<<8) + (*(ptr+2)<<16) + (*(ptr+3)<<24);
1459                 RTMP_IO_WRITE32(pAd, HW_BEACON_BASE0 + TXWI_SIZE + i, longptr);
1460                 ptr +=4;
1461         }
1462 #endif // RTMP_MAC_PCI //
1463 #ifdef RTMP_MAC_USB
1464         // move BEACON TXD and frame content to on-chip memory
1465         ptr = (PUCHAR)&pAd->BeaconTxWI;
1466         for (i=0; i<TXWI_SIZE; i+=2)  // 16-byte TXWI field
1467         {
1468                 //UINT32 longptr =  *ptr + (*(ptr+1)<<8) + (*(ptr+2)<<16) + (*(ptr+3)<<24);
1469                 //RTMP_IO_WRITE32(pAd, HW_BEACON_BASE0 + i, longptr);
1470                 RTUSBMultiWrite(pAd, HW_BEACON_BASE0 + i, ptr, 2);
1471                 ptr += 2;
1472         }
1473
1474         // start right after the 16-byte TXWI field
1475         ptr = pAd->BeaconBuf;
1476         for (i=0; i< pAd->BeaconTxWI.MPDUtotalByteCount; i+=2)
1477         {
1478                 //UINT32 longptr =  *ptr + (*(ptr+1)<<8) + (*(ptr+2)<<16) + (*(ptr+3)<<24);
1479                 //RTMP_IO_WRITE32(pAd, HW_BEACON_BASE0 + TXWI_SIZE + i, longptr);
1480                 RTUSBMultiWrite(pAd, HW_BEACON_BASE0 + TXWI_SIZE + i, ptr, 2);
1481                 ptr +=2;
1482         }
1483 #endif // RTMP_MAC_USB //
1484
1485         //
1486         // For Wi-Fi faily generated beacons between participating stations.
1487         // Set TBTT phase adaptive adjustment step to 8us (default 16us)
1488         // don't change settings 2006-5- by Jerry
1489         //RTMP_IO_WRITE32(pAd, TBTT_SYNC_CFG, 0x00001010);
1490
1491         // start sending BEACON
1492         csr9.field.BeaconInterval = pAd->CommonCfg.BeaconPeriod << 4; // ASIC register in units of 1/16 TU
1493         csr9.field.bTsfTicking = 1;
1494         csr9.field.TsfSyncMode = 2; // sync TSF in IBSS mode
1495         csr9.field.bTBTTEnable = 1;
1496         csr9.field.bBeaconGen = 1;
1497         RTMP_IO_WRITE32(pAd, BCN_TIME_CFG, csr9.word);
1498 }
1499
1500 /*
1501         ==========================================================================
1502         Description:
1503
1504         IRQL = PASSIVE_LEVEL
1505         IRQL = DISPATCH_LEVEL
1506
1507         ==========================================================================
1508  */
1509 VOID AsicSetEdcaParm(
1510         IN PRTMP_ADAPTER pAd,
1511         IN PEDCA_PARM    pEdcaParm)
1512 {
1513         EDCA_AC_CFG_STRUC   Ac0Cfg, Ac1Cfg, Ac2Cfg, Ac3Cfg;
1514         AC_TXOP_CSR0_STRUC csr0;
1515         AC_TXOP_CSR1_STRUC csr1;
1516         AIFSN_CSR_STRUC    AifsnCsr;
1517         CWMIN_CSR_STRUC    CwminCsr;
1518         CWMAX_CSR_STRUC    CwmaxCsr;
1519         int i;
1520
1521         Ac0Cfg.word = 0;
1522         Ac1Cfg.word = 0;
1523         Ac2Cfg.word = 0;
1524         Ac3Cfg.word = 0;
1525         if ((pEdcaParm == NULL) || (pEdcaParm->bValid == FALSE))
1526         {
1527                 DBGPRINT(RT_DEBUG_TRACE,("AsicSetEdcaParm\n"));
1528                 OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_WMM_INUSED);
1529                 for (i=0; i<MAX_LEN_OF_MAC_TABLE; i++)
1530                 {
1531                         if (pAd->MacTab.Content[i].ValidAsCLI || pAd->MacTab.Content[i].ValidAsApCli)
1532                                 CLIENT_STATUS_CLEAR_FLAG(&pAd->MacTab.Content[i], fCLIENT_STATUS_WMM_CAPABLE);
1533                 }
1534
1535                 //========================================================
1536                 //      MAC Register has a copy .
1537                 //========================================================
1538 //#ifndef WIFI_TEST
1539                 if( pAd->CommonCfg.bEnableTxBurst )
1540                 {
1541                         // For CWC test, change txop from 0x30 to 0x20 in TxBurst mode
1542                         Ac0Cfg.field.AcTxop = 0x20; // Suggest by John for TxBurst in HT Mode
1543                 }
1544                 else
1545                         Ac0Cfg.field.AcTxop = 0;        // QID_AC_BE
1546 //#else
1547 //              Ac0Cfg.field.AcTxop = 0;        // QID_AC_BE
1548 //#endif
1549                 Ac0Cfg.field.Cwmin = CW_MIN_IN_BITS;
1550                 Ac0Cfg.field.Cwmax = CW_MAX_IN_BITS;
1551                 Ac0Cfg.field.Aifsn = 2;
1552                 RTMP_IO_WRITE32(pAd, EDCA_AC0_CFG, Ac0Cfg.word);
1553
1554                 Ac1Cfg.field.AcTxop = 0;        // QID_AC_BK
1555                 Ac1Cfg.field.Cwmin = CW_MIN_IN_BITS;
1556                 Ac1Cfg.field.Cwmax = CW_MAX_IN_BITS;
1557                 Ac1Cfg.field.Aifsn = 2;
1558                 RTMP_IO_WRITE32(pAd, EDCA_AC1_CFG, Ac1Cfg.word);
1559
1560                 if (pAd->CommonCfg.PhyMode == PHY_11B)
1561                 {
1562                         Ac2Cfg.field.AcTxop = 192;      // AC_VI: 192*32us ~= 6ms
1563                         Ac3Cfg.field.AcTxop = 96;       // AC_VO: 96*32us  ~= 3ms
1564                 }
1565                 else
1566                 {
1567                         Ac2Cfg.field.AcTxop = 96;       // AC_VI: 96*32us ~= 3ms
1568                         Ac3Cfg.field.AcTxop = 48;       // AC_VO: 48*32us ~= 1.5ms
1569                 }
1570                 Ac2Cfg.field.Cwmin = CW_MIN_IN_BITS;
1571                 Ac2Cfg.field.Cwmax = CW_MAX_IN_BITS;
1572                 Ac2Cfg.field.Aifsn = 2;
1573                 RTMP_IO_WRITE32(pAd, EDCA_AC2_CFG, Ac2Cfg.word);
1574                 Ac3Cfg.field.Cwmin = CW_MIN_IN_BITS;
1575                 Ac3Cfg.field.Cwmax = CW_MAX_IN_BITS;
1576                 Ac3Cfg.field.Aifsn = 2;
1577                 RTMP_IO_WRITE32(pAd, EDCA_AC3_CFG, Ac3Cfg.word);
1578
1579                 //========================================================
1580                 //      DMA Register has a copy too.
1581                 //========================================================
1582                 csr0.field.Ac0Txop = 0;         // QID_AC_BE
1583                 csr0.field.Ac1Txop = 0;         // QID_AC_BK
1584                 RTMP_IO_WRITE32(pAd, WMM_TXOP0_CFG, csr0.word);
1585                 if (pAd->CommonCfg.PhyMode == PHY_11B)
1586                 {
1587                         csr1.field.Ac2Txop = 192;               // AC_VI: 192*32us ~= 6ms
1588                         csr1.field.Ac3Txop = 96;                // AC_VO: 96*32us  ~= 3ms
1589                 }
1590                 else
1591                 {
1592                         csr1.field.Ac2Txop = 96;                // AC_VI: 96*32us ~= 3ms
1593                         csr1.field.Ac3Txop = 48;                // AC_VO: 48*32us ~= 1.5ms
1594                 }
1595                 RTMP_IO_WRITE32(pAd, WMM_TXOP1_CFG, csr1.word);
1596
1597                 CwminCsr.word = 0;
1598                 CwminCsr.field.Cwmin0 = CW_MIN_IN_BITS;
1599                 CwminCsr.field.Cwmin1 = CW_MIN_IN_BITS;
1600                 CwminCsr.field.Cwmin2 = CW_MIN_IN_BITS;
1601                 CwminCsr.field.Cwmin3 = CW_MIN_IN_BITS;
1602                 RTMP_IO_WRITE32(pAd, WMM_CWMIN_CFG, CwminCsr.word);
1603
1604                 CwmaxCsr.word = 0;
1605                 CwmaxCsr.field.Cwmax0 = CW_MAX_IN_BITS;
1606                 CwmaxCsr.field.Cwmax1 = CW_MAX_IN_BITS;
1607                 CwmaxCsr.field.Cwmax2 = CW_MAX_IN_BITS;
1608                 CwmaxCsr.field.Cwmax3 = CW_MAX_IN_BITS;
1609                 RTMP_IO_WRITE32(pAd, WMM_CWMAX_CFG, CwmaxCsr.word);
1610
1611                 RTMP_IO_WRITE32(pAd, WMM_AIFSN_CFG, 0x00002222);
1612
1613                 NdisZeroMemory(&pAd->CommonCfg.APEdcaParm, sizeof(EDCA_PARM));
1614         }
1615         else
1616         {
1617                 OPSTATUS_SET_FLAG(pAd, fOP_STATUS_WMM_INUSED);
1618                 //========================================================
1619                 //      MAC Register has a copy.
1620                 //========================================================
1621                 //
1622                 // Modify Cwmin/Cwmax/Txop on queue[QID_AC_VI], Recommend by Jerry 2005/07/27
1623                 // To degrade our VIDO Queue's throughput for WiFi WMM S3T07 Issue.
1624                 //
1625                 //pEdcaParm->Txop[QID_AC_VI] = pEdcaParm->Txop[QID_AC_VI] * 7 / 10; // rt2860c need this
1626
1627                 Ac0Cfg.field.AcTxop =  pEdcaParm->Txop[QID_AC_BE];
1628                 Ac0Cfg.field.Cwmin= pEdcaParm->Cwmin[QID_AC_BE];
1629                 Ac0Cfg.field.Cwmax = pEdcaParm->Cwmax[QID_AC_BE];
1630                 Ac0Cfg.field.Aifsn = pEdcaParm->Aifsn[QID_AC_BE]; //+1;
1631
1632                 Ac1Cfg.field.AcTxop =  pEdcaParm->Txop[QID_AC_BK];
1633                 Ac1Cfg.field.Cwmin = pEdcaParm->Cwmin[QID_AC_BK]; //+2;
1634                 Ac1Cfg.field.Cwmax = pEdcaParm->Cwmax[QID_AC_BK];
1635                 Ac1Cfg.field.Aifsn = pEdcaParm->Aifsn[QID_AC_BK]; //+1;
1636
1637                 Ac2Cfg.field.AcTxop = (pEdcaParm->Txop[QID_AC_VI] * 6) / 10;
1638                 if(pAd->Antenna.field.TxPath == 1)
1639                 {
1640                         Ac2Cfg.field.Cwmin = pEdcaParm->Cwmin[QID_AC_VI] + 1;
1641                         Ac2Cfg.field.Cwmax = pEdcaParm->Cwmax[QID_AC_VI] + 1;
1642                 }
1643                 else
1644                 {
1645                 Ac2Cfg.field.Cwmin = pEdcaParm->Cwmin[QID_AC_VI];
1646                 Ac2Cfg.field.Cwmax = pEdcaParm->Cwmax[QID_AC_VI];
1647                 }
1648                 Ac2Cfg.field.Aifsn = pEdcaParm->Aifsn[QID_AC_VI] + 1;
1649 #ifdef RTMP_MAC_USB
1650                 Ac2Cfg.field.Aifsn = pEdcaParm->Aifsn[QID_AC_VI] + 3;
1651 #endif // RTMP_MAC_USB //
1652
1653                 {
1654                         // Tuning for Wi-Fi WMM S06
1655                         if (pAd->CommonCfg.bWiFiTest &&
1656                                 pEdcaParm->Aifsn[QID_AC_VI] == 10)
1657                                 Ac2Cfg.field.Aifsn -= 1;
1658
1659                         // Tuning for TGn Wi-Fi 5.2.32
1660                         // STA TestBed changes in this item: conexant legacy sta ==> broadcom 11n sta
1661                         if (STA_TGN_WIFI_ON(pAd) &&
1662                                 pEdcaParm->Aifsn[QID_AC_VI] == 10)
1663                         {
1664                                 Ac0Cfg.field.Aifsn = 3;
1665                                 Ac2Cfg.field.AcTxop = 5;
1666                         }
1667 #ifdef RT30xx
1668                         if (pAd->RfIcType == RFIC_3020 || pAd->RfIcType == RFIC_2020)
1669                         {
1670                                 // Tuning for WiFi WMM S3-T07: connexant legacy sta ==> broadcom 11n sta.
1671                                 Ac2Cfg.field.Aifsn = 5;
1672                         }
1673 #endif // RT30xx //
1674                 }
1675
1676                 Ac3Cfg.field.AcTxop = pEdcaParm->Txop[QID_AC_VO];
1677                 Ac3Cfg.field.Cwmin = pEdcaParm->Cwmin[QID_AC_VO];
1678                 Ac3Cfg.field.Cwmax = pEdcaParm->Cwmax[QID_AC_VO];
1679                 Ac3Cfg.field.Aifsn = pEdcaParm->Aifsn[QID_AC_VO];
1680
1681 //#ifdef WIFI_TEST
1682                 if (pAd->CommonCfg.bWiFiTest)
1683                 {
1684                         if (Ac3Cfg.field.AcTxop == 102)
1685                         {
1686                         Ac0Cfg.field.AcTxop = pEdcaParm->Txop[QID_AC_BE] ? pEdcaParm->Txop[QID_AC_BE] : 10;
1687                                 Ac0Cfg.field.Aifsn  = pEdcaParm->Aifsn[QID_AC_BE]-1; /* AIFSN must >= 1 */
1688                         Ac1Cfg.field.AcTxop = pEdcaParm->Txop[QID_AC_BK];
1689                                 Ac1Cfg.field.Aifsn  = pEdcaParm->Aifsn[QID_AC_BK];
1690                         Ac2Cfg.field.AcTxop = pEdcaParm->Txop[QID_AC_VI];
1691                         } /* End of if */
1692                 }
1693 //#endif // WIFI_TEST //
1694
1695                 RTMP_IO_WRITE32(pAd, EDCA_AC0_CFG, Ac0Cfg.word);
1696                 RTMP_IO_WRITE32(pAd, EDCA_AC1_CFG, Ac1Cfg.word);
1697                 RTMP_IO_WRITE32(pAd, EDCA_AC2_CFG, Ac2Cfg.word);
1698                 RTMP_IO_WRITE32(pAd, EDCA_AC3_CFG, Ac3Cfg.word);
1699
1700
1701                 //========================================================
1702                 //      DMA Register has a copy too.
1703                 //========================================================
1704                 csr0.field.Ac0Txop = Ac0Cfg.field.AcTxop;
1705                 csr0.field.Ac1Txop = Ac1Cfg.field.AcTxop;
1706                 RTMP_IO_WRITE32(pAd, WMM_TXOP0_CFG, csr0.word);
1707
1708                 csr1.field.Ac2Txop = Ac2Cfg.field.AcTxop;
1709                 csr1.field.Ac3Txop = Ac3Cfg.field.AcTxop;
1710                 RTMP_IO_WRITE32(pAd, WMM_TXOP1_CFG, csr1.word);
1711
1712                 CwminCsr.word = 0;
1713                 CwminCsr.field.Cwmin0 = pEdcaParm->Cwmin[QID_AC_BE];
1714                 CwminCsr.field.Cwmin1 = pEdcaParm->Cwmin[QID_AC_BK];
1715                 CwminCsr.field.Cwmin2 = pEdcaParm->Cwmin[QID_AC_VI];
1716                         CwminCsr.field.Cwmin3 = pEdcaParm->Cwmin[QID_AC_VO] - 1; //for TGn wifi test
1717                 RTMP_IO_WRITE32(pAd, WMM_CWMIN_CFG, CwminCsr.word);
1718
1719                 CwmaxCsr.word = 0;
1720                 CwmaxCsr.field.Cwmax0 = pEdcaParm->Cwmax[QID_AC_BE];
1721                 CwmaxCsr.field.Cwmax1 = pEdcaParm->Cwmax[QID_AC_BK];
1722                 CwmaxCsr.field.Cwmax2 = pEdcaParm->Cwmax[QID_AC_VI];
1723                 CwmaxCsr.field.Cwmax3 = pEdcaParm->Cwmax[QID_AC_VO];
1724                 RTMP_IO_WRITE32(pAd, WMM_CWMAX_CFG, CwmaxCsr.word);
1725
1726                 AifsnCsr.word = 0;
1727                 AifsnCsr.field.Aifsn0 = Ac0Cfg.field.Aifsn; //pEdcaParm->Aifsn[QID_AC_BE];
1728                 AifsnCsr.field.Aifsn1 = Ac1Cfg.field.Aifsn; //pEdcaParm->Aifsn[QID_AC_BK];
1729                 AifsnCsr.field.Aifsn2 = Ac2Cfg.field.Aifsn; //pEdcaParm->Aifsn[QID_AC_VI];
1730
1731                 {
1732                         // Tuning for Wi-Fi WMM S06
1733                         if (pAd->CommonCfg.bWiFiTest &&
1734                                 pEdcaParm->Aifsn[QID_AC_VI] == 10)
1735                                 AifsnCsr.field.Aifsn2 = Ac2Cfg.field.Aifsn - 4;
1736
1737                         // Tuning for TGn Wi-Fi 5.2.32
1738                         // STA TestBed changes in this item: connexant legacy sta ==> broadcom 11n sta
1739                         if (STA_TGN_WIFI_ON(pAd) &&
1740                                 pEdcaParm->Aifsn[QID_AC_VI] == 10)
1741                         {
1742                                 AifsnCsr.field.Aifsn0 = 3;
1743                                 AifsnCsr.field.Aifsn2 = 7;
1744                         }
1745
1746                         if (INFRA_ON(pAd))
1747                                 CLIENT_STATUS_SET_FLAG(&pAd->MacTab.Content[BSSID_WCID], fCLIENT_STATUS_WMM_CAPABLE);
1748                 }
1749
1750                 {
1751                         AifsnCsr.field.Aifsn3 = Ac3Cfg.field.Aifsn - 1; //pEdcaParm->Aifsn[QID_AC_VO]; //for TGn wifi test
1752 #ifdef RT30xx
1753                         // TODO: Shiang, this modification also suitable for RT3052/RT3050 ???
1754                         if (pAd->RfIcType == RFIC_3020 || pAd->RfIcType == RFIC_2020)
1755                         {
1756                                         AifsnCsr.field.Aifsn2 = 0x2; //pEdcaParm->Aifsn[QID_AC_VI]; //for WiFi WMM S4-T04.
1757                         }
1758 #endif // RT30xx //
1759                 }
1760                 RTMP_IO_WRITE32(pAd, WMM_AIFSN_CFG, AifsnCsr.word);
1761
1762                 NdisMoveMemory(&pAd->CommonCfg.APEdcaParm, pEdcaParm, sizeof(EDCA_PARM));
1763                 if (!ADHOC_ON(pAd))
1764                 {
1765                         DBGPRINT(RT_DEBUG_TRACE,("EDCA [#%d]: AIFSN CWmin CWmax  TXOP(us)  ACM\n", pEdcaParm->EdcaUpdateCount));
1766                         DBGPRINT(RT_DEBUG_TRACE,("     AC_BE      %2d     %2d     %2d      %4d     %d\n",
1767                                                                          pEdcaParm->Aifsn[0],
1768                                                                          pEdcaParm->Cwmin[0],
1769                                                                          pEdcaParm->Cwmax[0],
1770                                                                          pEdcaParm->Txop[0]<<5,
1771                                                                          pEdcaParm->bACM[0]));
1772                         DBGPRINT(RT_DEBUG_TRACE,("     AC_BK      %2d     %2d     %2d      %4d     %d\n",
1773                                                                          pEdcaParm->Aifsn[1],
1774                                                                          pEdcaParm->Cwmin[1],
1775                                                                          pEdcaParm->Cwmax[1],
1776                                                                          pEdcaParm->Txop[1]<<5,
1777                                                                          pEdcaParm->bACM[1]));
1778                         DBGPRINT(RT_DEBUG_TRACE,("     AC_VI      %2d     %2d     %2d      %4d     %d\n",
1779                                                                          pEdcaParm->Aifsn[2],
1780                                                                          pEdcaParm->Cwmin[2],
1781                                                                          pEdcaParm->Cwmax[2],
1782                                                                          pEdcaParm->Txop[2]<<5,
1783                                                                          pEdcaParm->bACM[2]));
1784                         DBGPRINT(RT_DEBUG_TRACE,("     AC_VO      %2d     %2d     %2d      %4d     %d\n",
1785                                                                          pEdcaParm->Aifsn[3],
1786                                                                          pEdcaParm->Cwmin[3],
1787                                                                          pEdcaParm->Cwmax[3],
1788                                                                          pEdcaParm->Txop[3]<<5,
1789                                                                          pEdcaParm->bACM[3]));
1790                 }
1791         }
1792
1793 }
1794
1795 /*
1796         ==========================================================================
1797         Description:
1798
1799         IRQL = PASSIVE_LEVEL
1800         IRQL = DISPATCH_LEVEL
1801
1802         ==========================================================================
1803  */
1804 VOID    AsicSetSlotTime(
1805         IN PRTMP_ADAPTER pAd,
1806         IN BOOLEAN bUseShortSlotTime)
1807 {
1808         ULONG   SlotTime;
1809         UINT32  RegValue = 0;
1810
1811         if (pAd->CommonCfg.Channel > 14)
1812                 bUseShortSlotTime = TRUE;
1813
1814         if (bUseShortSlotTime && OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_SHORT_SLOT_INUSED))
1815                 return;
1816         else if ((!bUseShortSlotTime) && (!OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_SHORT_SLOT_INUSED)))
1817                 return;
1818
1819         if (bUseShortSlotTime)
1820                 OPSTATUS_SET_FLAG(pAd, fOP_STATUS_SHORT_SLOT_INUSED);
1821         else
1822                 OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_SHORT_SLOT_INUSED);
1823
1824         SlotTime = (bUseShortSlotTime)? 9 : 20;
1825
1826         {
1827                 // force using short SLOT time for FAE to demo performance when TxBurst is ON
1828                 if (((pAd->StaActive.SupportedPhyInfo.bHtEnable == FALSE) && (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_WMM_INUSED)))
1829                         || ((pAd->StaActive.SupportedPhyInfo.bHtEnable == TRUE) && (pAd->CommonCfg.BACapability.field.Policy == BA_NOTUSE))
1830                         )
1831                 {
1832                         // In this case, we will think it is doing Wi-Fi test
1833                         // And we will not set to short slot when bEnableTxBurst is TRUE.
1834                 }
1835                 else if (pAd->CommonCfg.bEnableTxBurst)
1836                 {
1837                         OPSTATUS_SET_FLAG(pAd, fOP_STATUS_SHORT_SLOT_INUSED);
1838                         SlotTime = 9;
1839                 }
1840         }
1841
1842         //
1843         // For some reasons, always set it to short slot time.
1844         //
1845         // ToDo: Should consider capability with 11B
1846         //
1847         {
1848                 if (pAd->StaCfg.BssType == BSS_ADHOC)
1849                 {
1850                         OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_SHORT_SLOT_INUSED);
1851                         SlotTime = 20;
1852                 }
1853         }
1854
1855         RTMP_IO_READ32(pAd, BKOFF_SLOT_CFG, &RegValue);
1856         RegValue = RegValue & 0xFFFFFF00;
1857
1858         RegValue |= SlotTime;
1859
1860         RTMP_IO_WRITE32(pAd, BKOFF_SLOT_CFG, RegValue);
1861 }
1862
1863 /*
1864         ========================================================================
1865         Description:
1866                 Add Shared key information into ASIC.
1867                 Update shared key, TxMic and RxMic to Asic Shared key table
1868                 Update its cipherAlg to Asic Shared key Mode.
1869
1870     Return:
1871         ========================================================================
1872 */
1873 VOID AsicAddSharedKeyEntry(
1874         IN PRTMP_ADAPTER pAd,
1875         IN UCHAR                 BssIndex,
1876         IN UCHAR                 KeyIdx,
1877         IN UCHAR                 CipherAlg,
1878         IN PUCHAR                pKey,
1879         IN PUCHAR                pTxMic,
1880         IN PUCHAR                pRxMic)
1881 {
1882         ULONG offset; //, csr0;
1883         SHAREDKEY_MODE_STRUC csr1;
1884 #ifdef RTMP_MAC_PCI
1885         INT   i;
1886 #endif // RTMP_MAC_PCI //
1887
1888         DBGPRINT(RT_DEBUG_TRACE, ("AsicAddSharedKeyEntry BssIndex=%d, KeyIdx=%d\n", BssIndex,KeyIdx));
1889 //============================================================================================
1890
1891         DBGPRINT(RT_DEBUG_TRACE,("AsicAddSharedKeyEntry: %s key #%d\n", CipherName[CipherAlg], BssIndex*4 + KeyIdx));
1892         DBGPRINT_RAW(RT_DEBUG_TRACE, ("         Key = %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
1893                 pKey[0],pKey[1],pKey[2],pKey[3],pKey[4],pKey[5],pKey[6],pKey[7],pKey[8],pKey[9],pKey[10],pKey[11],pKey[12],pKey[13],pKey[14],pKey[15]));
1894         if (pRxMic)
1895         {
1896                 DBGPRINT_RAW(RT_DEBUG_TRACE, ("         Rx MIC Key = %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
1897                         pRxMic[0],pRxMic[1],pRxMic[2],pRxMic[3],pRxMic[4],pRxMic[5],pRxMic[6],pRxMic[7]));
1898         }
1899         if (pTxMic)
1900         {
1901                 DBGPRINT_RAW(RT_DEBUG_TRACE, ("         Tx MIC Key = %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
1902                         pTxMic[0],pTxMic[1],pTxMic[2],pTxMic[3],pTxMic[4],pTxMic[5],pTxMic[6],pTxMic[7]));
1903         }
1904 //============================================================================================
1905         //
1906         // fill key material - key + TX MIC + RX MIC
1907         //
1908 #ifdef RTMP_MAC_PCI
1909         offset = SHARED_KEY_TABLE_BASE + (4*BssIndex + KeyIdx)*HW_KEY_ENTRY_SIZE;
1910         for (i=0; i<MAX_LEN_OF_SHARE_KEY; i++)
1911         {
1912                 RTMP_IO_WRITE8(pAd, offset + i, pKey[i]);
1913         }
1914
1915         offset += MAX_LEN_OF_SHARE_KEY;
1916         if (pTxMic)
1917         {
1918                 for (i=0; i<8; i++)
1919                 {
1920                         RTMP_IO_WRITE8(pAd, offset + i, pTxMic[i]);
1921                 }
1922         }
1923
1924         offset += 8;
1925         if (pRxMic)
1926         {
1927                 for (i=0; i<8; i++)
1928                 {
1929                         RTMP_IO_WRITE8(pAd, offset + i, pRxMic[i]);
1930                 }
1931         }
1932 #endif // RTMP_MAC_PCI //
1933 #ifdef RTMP_MAC_USB
1934 {
1935         offset = SHARED_KEY_TABLE_BASE + (4*BssIndex + KeyIdx)*HW_KEY_ENTRY_SIZE;
1936         RTUSBMultiWrite(pAd, offset, pKey, MAX_LEN_OF_SHARE_KEY);
1937
1938         offset += MAX_LEN_OF_SHARE_KEY;
1939         if (pTxMic)
1940         {
1941                 RTUSBMultiWrite(pAd, offset, pTxMic, 8);
1942         }
1943
1944         offset += 8;
1945         if (pRxMic)
1946         {
1947                 RTUSBMultiWrite(pAd, offset, pRxMic, 8);
1948         }
1949 }
1950 #endif // RTMP_MAC_USB //
1951
1952         //
1953         // Update cipher algorithm. WSTA always use BSS0
1954         //
1955         RTMP_IO_READ32(pAd, SHARED_KEY_MODE_BASE+4*(BssIndex/2), &csr1.word);
1956         DBGPRINT(RT_DEBUG_TRACE,("Read: SHARED_KEY_MODE_BASE at this Bss[%d] KeyIdx[%d]= 0x%x \n", BssIndex,KeyIdx, csr1.word));
1957         if ((BssIndex%2) == 0)
1958         {
1959                 if (KeyIdx == 0)
1960                         csr1.field.Bss0Key0CipherAlg = CipherAlg;
1961                 else if (KeyIdx == 1)
1962                         csr1.field.Bss0Key1CipherAlg = CipherAlg;
1963                 else if (KeyIdx == 2)
1964                         csr1.field.Bss0Key2CipherAlg = CipherAlg;
1965                 else
1966                         csr1.field.Bss0Key3CipherAlg = CipherAlg;
1967         }
1968         else
1969         {
1970                 if (KeyIdx == 0)
1971                         csr1.field.Bss1Key0CipherAlg = CipherAlg;
1972                 else if (KeyIdx == 1)
1973                         csr1.field.Bss1Key1CipherAlg = CipherAlg;
1974                 else if (KeyIdx == 2)
1975                         csr1.field.Bss1Key2CipherAlg = CipherAlg;
1976                 else
1977                         csr1.field.Bss1Key3CipherAlg = CipherAlg;
1978         }
1979         DBGPRINT(RT_DEBUG_TRACE,("Write: SHARED_KEY_MODE_BASE at this Bss[%d] = 0x%x \n", BssIndex, csr1.word));
1980         RTMP_IO_WRITE32(pAd, SHARED_KEY_MODE_BASE+4*(BssIndex/2), csr1.word);
1981
1982 }
1983
1984 //      IRQL = DISPATCH_LEVEL
1985 VOID AsicRemoveSharedKeyEntry(
1986         IN PRTMP_ADAPTER pAd,
1987         IN UCHAR                 BssIndex,
1988         IN UCHAR                 KeyIdx)
1989 {
1990         //ULONG SecCsr0;
1991         SHAREDKEY_MODE_STRUC csr1;
1992
1993         DBGPRINT(RT_DEBUG_TRACE,("AsicRemoveSharedKeyEntry: #%d \n", BssIndex*4 + KeyIdx));
1994
1995         RTMP_IO_READ32(pAd, SHARED_KEY_MODE_BASE+4*(BssIndex/2), &csr1.word);
1996         if ((BssIndex%2) == 0)
1997         {
1998                 if (KeyIdx == 0)
1999                         csr1.field.Bss0Key0CipherAlg = 0;
2000                 else if (KeyIdx == 1)
2001                         csr1.field.Bss0Key1CipherAlg = 0;
2002                 else if (KeyIdx == 2)
2003                         csr1.field.Bss0Key2CipherAlg = 0;
2004                 else
2005                         csr1.field.Bss0Key3CipherAlg = 0;
2006         }
2007         else
2008         {
2009                 if (KeyIdx == 0)
2010                         csr1.field.Bss1Key0CipherAlg = 0;
2011                 else if (KeyIdx == 1)
2012                         csr1.field.Bss1Key1CipherAlg = 0;
2013                 else if (KeyIdx == 2)
2014                         csr1.field.Bss1Key2CipherAlg = 0;
2015                 else
2016                         csr1.field.Bss1Key3CipherAlg = 0;
2017         }
2018         DBGPRINT(RT_DEBUG_TRACE,("Write: SHARED_KEY_MODE_BASE at this Bss[%d] = 0x%x \n", BssIndex, csr1.word));
2019         RTMP_IO_WRITE32(pAd, SHARED_KEY_MODE_BASE+4*(BssIndex/2), csr1.word);
2020         ASSERT(BssIndex < 4);
2021         ASSERT(KeyIdx < 4);
2022
2023 }
2024
2025
2026 VOID AsicUpdateWCIDAttribute(
2027         IN PRTMP_ADAPTER pAd,
2028         IN USHORT               WCID,
2029         IN UCHAR                BssIndex,
2030         IN UCHAR        CipherAlg,
2031         IN BOOLEAN              bUsePairewiseKeyTable)
2032 {
2033         ULONG   WCIDAttri = 0, offset;
2034
2035         //
2036         // Update WCID attribute.
2037         // Only TxKey could update WCID attribute.
2038         //
2039         offset = MAC_WCID_ATTRIBUTE_BASE + (WCID * HW_WCID_ATTRI_SIZE);
2040         WCIDAttri = (BssIndex << 4) | (CipherAlg << 1) | (bUsePairewiseKeyTable);
2041         RTMP_IO_WRITE32(pAd, offset, WCIDAttri);
2042 }
2043
2044 VOID AsicUpdateWCIDIVEIV(
2045         IN PRTMP_ADAPTER pAd,
2046         IN USHORT               WCID,
2047         IN ULONG        uIV,
2048         IN ULONG        uEIV)
2049 {
2050         ULONG   offset;
2051
2052         offset = MAC_IVEIV_TABLE_BASE + (WCID * HW_IVEIV_ENTRY_SIZE);
2053
2054         RTMP_IO_WRITE32(pAd, offset, uIV);
2055         RTMP_IO_WRITE32(pAd, offset + 4, uEIV);
2056 }
2057
2058 VOID AsicUpdateRxWCIDTable(
2059         IN PRTMP_ADAPTER pAd,
2060         IN USHORT               WCID,
2061         IN PUCHAR        pAddr)
2062 {
2063         ULONG offset;
2064         ULONG Addr;
2065
2066         offset = MAC_WCID_BASE + (WCID * HW_WCID_ENTRY_SIZE);
2067         Addr = pAddr[0] + (pAddr[1] << 8) +(pAddr[2] << 16) +(pAddr[3] << 24);
2068         RTMP_IO_WRITE32(pAd, offset, Addr);
2069         Addr = pAddr[4] + (pAddr[5] << 8);
2070         RTMP_IO_WRITE32(pAd, offset + 4, Addr);
2071 }
2072
2073
2074 /*
2075     ========================================================================
2076
2077     Routine Description:
2078         Set Cipher Key, Cipher algorithm, IV/EIV to Asic
2079
2080     Arguments:
2081         pAd                     Pointer to our adapter
2082         WCID                    WCID Entry number.
2083         BssIndex                BSSID index, station or none multiple BSSID support
2084                                 this value should be 0.
2085         KeyIdx                  This KeyIdx will set to IV's KeyID if bTxKey enabled
2086         pCipherKey              Pointer to Cipher Key.
2087         bUsePairewiseKeyTable   TRUE means saved the key in SharedKey table,
2088                                 otherwise PairewiseKey table
2089         bTxKey                  This is the transmit key if enabled.
2090
2091     Return Value:
2092         None
2093
2094     Note:
2095         This routine will set the relative key stuff to Asic including WCID attribute,
2096         Cipher Key, Cipher algorithm and IV/EIV.
2097
2098         IV/EIV will be update if this CipherKey is the transmission key because
2099         ASIC will base on IV's KeyID value to select Cipher Key.
2100
2101         If bTxKey sets to FALSE, this is not the TX key, but it could be
2102         RX key
2103
2104         For AP mode bTxKey must be always set to TRUE.
2105     ========================================================================
2106 */
2107 VOID AsicAddKeyEntry(
2108         IN PRTMP_ADAPTER pAd,
2109         IN USHORT               WCID,
2110         IN UCHAR                BssIndex,
2111         IN UCHAR                KeyIdx,
2112         IN PCIPHER_KEY  pCipherKey,
2113         IN BOOLEAN              bUsePairewiseKeyTable,
2114         IN BOOLEAN              bTxKey)
2115 {
2116         ULONG   offset;
2117 //      ULONG   WCIDAttri = 0;
2118         UCHAR   IV4 = 0;
2119         PUCHAR          pKey = pCipherKey->Key;
2120 //      ULONG           KeyLen = pCipherKey->KeyLen;
2121         PUCHAR          pTxMic = pCipherKey->TxMic;
2122         PUCHAR          pRxMic = pCipherKey->RxMic;
2123         PUCHAR          pTxtsc = pCipherKey->TxTsc;
2124         UCHAR           CipherAlg = pCipherKey->CipherAlg;
2125         SHAREDKEY_MODE_STRUC csr1;
2126 #ifdef RTMP_MAC_PCI
2127         UCHAR           i;
2128 #endif // RTMP_MAC_PCI //
2129
2130 //      ASSERT(KeyLen <= MAX_LEN_OF_PEER_KEY);
2131
2132         DBGPRINT(RT_DEBUG_TRACE, ("==> AsicAddKeyEntry\n"));
2133         //
2134         // 1.) decide key table offset
2135         //
2136         if (bUsePairewiseKeyTable)
2137                 offset = PAIRWISE_KEY_TABLE_BASE + (WCID * HW_KEY_ENTRY_SIZE);
2138         else
2139                 offset = SHARED_KEY_TABLE_BASE + (4 * BssIndex + KeyIdx) * HW_KEY_ENTRY_SIZE;
2140
2141         //
2142         // 2.) Set Key to Asic
2143         //
2144         //for (i = 0; i < KeyLen; i++)
2145 #ifdef RTMP_MAC_PCI
2146         for (i = 0; i < MAX_LEN_OF_PEER_KEY; i++)
2147         {
2148                 RTMP_IO_WRITE8(pAd, offset + i, pKey[i]);
2149         }
2150         offset += MAX_LEN_OF_PEER_KEY;
2151
2152         //
2153         // 3.) Set MIC key if available
2154         //
2155         if (pTxMic)
2156         {
2157                 for (i = 0; i < 8; i++)
2158                 {
2159                         RTMP_IO_WRITE8(pAd, offset + i, pTxMic[i]);
2160                 }
2161         }
2162         offset += LEN_TKIP_TXMICK;
2163
2164         if (pRxMic)
2165         {
2166                 for (i = 0; i < 8; i++)
2167                 {
2168                         RTMP_IO_WRITE8(pAd, offset + i, pRxMic[i]);
2169                 }
2170         }
2171 #endif // RTMP_MAC_PCI //
2172 #ifdef RTMP_MAC_USB
2173         RTUSBMultiWrite(pAd, offset, pKey, MAX_LEN_OF_PEER_KEY);
2174         offset += MAX_LEN_OF_PEER_KEY;
2175
2176         //
2177         // 3.) Set MIC key if available
2178         //
2179         if (pTxMic)
2180         {
2181                 RTUSBMultiWrite(pAd, offset, pTxMic, 8);
2182         }
2183         offset += LEN_TKIP_TXMICK;
2184
2185         if (pRxMic)
2186         {
2187                 RTUSBMultiWrite(pAd, offset, pRxMic, 8);
2188         }
2189 #endif // RTMP_MAC_USB //
2190
2191         //
2192         // 4.) Modify IV/EIV if needs
2193         //     This will force Asic to use this key ID by setting IV.
2194         //
2195         if (bTxKey)
2196         {
2197 #ifdef RTMP_MAC_PCI
2198                 offset = MAC_IVEIV_TABLE_BASE + (WCID * HW_IVEIV_ENTRY_SIZE);
2199                 //
2200                 // Write IV
2201                 //
2202                 RTMP_IO_WRITE8(pAd, offset, pTxtsc[1]);
2203                 RTMP_IO_WRITE8(pAd, offset + 1, ((pTxtsc[1] | 0x20) & 0x7f));
2204                 RTMP_IO_WRITE8(pAd, offset + 2, pTxtsc[0]);
2205
2206                 IV4 = (KeyIdx << 6);
2207                 if ((CipherAlg == CIPHER_TKIP) || (CipherAlg == CIPHER_TKIP_NO_MIC) ||(CipherAlg == CIPHER_AES))
2208                         IV4 |= 0x20;  // turn on extension bit means EIV existence
2209
2210                 RTMP_IO_WRITE8(pAd, offset + 3, IV4);
2211
2212                 //
2213                 // Write EIV
2214                 //
2215                 offset += 4;
2216                 for (i = 0; i < 4; i++)
2217                 {
2218                         RTMP_IO_WRITE8(pAd, offset + i, pTxtsc[i + 2]);
2219                 }
2220 #endif // RTMP_MAC_PCI //
2221 #ifdef RTMP_MAC_USB
2222                 UINT32 tmpVal;
2223
2224                 //
2225                 // Write IV
2226                 //
2227                 IV4 = (KeyIdx << 6);
2228                 if ((CipherAlg == CIPHER_TKIP) || (CipherAlg == CIPHER_TKIP_NO_MIC) ||(CipherAlg == CIPHER_AES))
2229                         IV4 |= 0x20;  // turn on extension bit means EIV existence
2230
2231                 tmpVal = pTxtsc[1] + (((pTxtsc[1] | 0x20) & 0x7f) << 8) + (pTxtsc[0] << 16) + (IV4 << 24);
2232                 RTMP_IO_WRITE32(pAd, offset, tmpVal);
2233
2234                 //
2235                 // Write EIV
2236                 //
2237                 offset += 4;
2238                 RTMP_IO_WRITE32(pAd, offset, *(PUINT32)&pCipherKey->TxTsc[2]);
2239 #endif // RTMP_MAC_USB //
2240
2241                 AsicUpdateWCIDAttribute(pAd, WCID, BssIndex, CipherAlg, bUsePairewiseKeyTable);
2242         }
2243
2244         if (!bUsePairewiseKeyTable)
2245         {
2246                 //
2247                 // Only update the shared key security mode
2248                 //
2249                 RTMP_IO_READ32(pAd, SHARED_KEY_MODE_BASE + 4 * (BssIndex / 2), &csr1.word);
2250                 if ((BssIndex % 2) == 0)
2251                 {
2252                         if (KeyIdx == 0)
2253                                 csr1.field.Bss0Key0CipherAlg = CipherAlg;
2254                         else if (KeyIdx == 1)
2255                                 csr1.field.Bss0Key1CipherAlg = CipherAlg;
2256                         else if (KeyIdx == 2)
2257                                 csr1.field.Bss0Key2CipherAlg = CipherAlg;
2258                         else
2259                                 csr1.field.Bss0Key3CipherAlg = CipherAlg;
2260                 }
2261                 else
2262                 {
2263                         if (KeyIdx == 0)
2264                                 csr1.field.Bss1Key0CipherAlg = CipherAlg;
2265                         else if (KeyIdx == 1)
2266                                 csr1.field.Bss1Key1CipherAlg = CipherAlg;
2267                         else if (KeyIdx == 2)
2268                                 csr1.field.Bss1Key2CipherAlg = CipherAlg;
2269                         else
2270                                 csr1.field.Bss1Key3CipherAlg = CipherAlg;
2271                 }
2272                 RTMP_IO_WRITE32(pAd, SHARED_KEY_MODE_BASE + 4 * (BssIndex / 2), csr1.word);
2273         }
2274
2275         DBGPRINT(RT_DEBUG_TRACE, ("<== AsicAddKeyEntry\n"));
2276 }
2277
2278
2279 /*
2280         ========================================================================
2281         Description:
2282                 Add Pair-wise key material into ASIC.
2283                 Update pairwise key, TxMic and RxMic to Asic Pair-wise key table
2284
2285     Return:
2286         ========================================================================
2287 */
2288 VOID AsicAddPairwiseKeyEntry(
2289         IN PRTMP_ADAPTER pAd,
2290         IN PUCHAR        pAddr,
2291         IN UCHAR                WCID,
2292         IN CIPHER_KEY            *pCipherKey)
2293 {
2294         INT i;
2295         ULONG           offset;
2296         PUCHAR           pKey = pCipherKey->Key;
2297         PUCHAR           pTxMic = pCipherKey->TxMic;
2298         PUCHAR           pRxMic = pCipherKey->RxMic;
2299 #ifdef DBG
2300         UCHAR           CipherAlg = pCipherKey->CipherAlg;
2301 #endif // DBG //
2302
2303         // EKEY
2304         offset = PAIRWISE_KEY_TABLE_BASE + (WCID * HW_KEY_ENTRY_SIZE);
2305 #ifdef RTMP_MAC_PCI
2306         for (i=0; i<MAX_LEN_OF_PEER_KEY; i++)
2307         {
2308                 RTMP_IO_WRITE8(pAd, offset + i, pKey[i]);
2309         }
2310 #endif // RTMP_MAC_PCI //
2311 #ifdef RTMP_MAC_USB
2312         RTUSBMultiWrite(pAd, offset, &pCipherKey->Key[0], MAX_LEN_OF_PEER_KEY);
2313 #endif // RTMP_MAC_USB //
2314         for (i=0; i<MAX_LEN_OF_PEER_KEY; i+=4)
2315         {
2316                 UINT32 Value;
2317                 RTMP_IO_READ32(pAd, offset + i, &Value);
2318         }
2319
2320         offset += MAX_LEN_OF_PEER_KEY;
2321
2322         //  MIC KEY
2323         if (pTxMic)
2324         {
2325 #ifdef RTMP_MAC_PCI
2326                 for (i=0; i<8; i++)
2327                 {
2328                         RTMP_IO_WRITE8(pAd, offset+i, pTxMic[i]);
2329                 }
2330 #endif // RTMP_MAC_PCI //
2331 #ifdef RTMP_MAC_USB
2332                 RTUSBMultiWrite(pAd, offset, &pCipherKey->TxMic[0], 8);
2333 #endif // RTMP_MAC_USB //
2334         }
2335         offset += 8;
2336         if (pRxMic)
2337         {
2338 #ifdef RTMP_MAC_PCI
2339                 for (i=0; i<8; i++)
2340                 {
2341                         RTMP_IO_WRITE8(pAd, offset+i, pRxMic[i]);
2342                 }
2343 #endif // RTMP_MAC_PCI //
2344 #ifdef RTMP_MAC_USB
2345                 RTUSBMultiWrite(pAd, offset, &pCipherKey->RxMic[0], 8);
2346 #endif // RTMP_MAC_USB //
2347         }
2348
2349         DBGPRINT(RT_DEBUG_TRACE,("AsicAddPairwiseKeyEntry: WCID #%d Alg=%s\n",WCID, CipherName[CipherAlg]));
2350         DBGPRINT(RT_DEBUG_TRACE,("      Key = %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
2351                 pKey[0],pKey[1],pKey[2],pKey[3],pKey[4],pKey[5],pKey[6],pKey[7],pKey[8],pKey[9],pKey[10],pKey[11],pKey[12],pKey[13],pKey[14],pKey[15]));
2352         if (pRxMic)
2353         {
2354                 DBGPRINT(RT_DEBUG_TRACE, ("     Rx MIC Key = %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
2355                         pRxMic[0],pRxMic[1],pRxMic[2],pRxMic[3],pRxMic[4],pRxMic[5],pRxMic[6],pRxMic[7]));
2356         }
2357         if (pTxMic)
2358         {
2359                 DBGPRINT(RT_DEBUG_TRACE, ("     Tx MIC Key = %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
2360                         pTxMic[0],pTxMic[1],pTxMic[2],pTxMic[3],pTxMic[4],pTxMic[5],pTxMic[6],pTxMic[7]));
2361         }
2362 }
2363 /*
2364         ========================================================================
2365         Description:
2366                 Remove Pair-wise key material from ASIC.
2367
2368     Return:
2369         ========================================================================
2370 */
2371 VOID AsicRemovePairwiseKeyEntry(
2372         IN PRTMP_ADAPTER pAd,
2373         IN UCHAR                 BssIdx,
2374         IN UCHAR                 Wcid)
2375 {
2376         ULONG           WCIDAttri;
2377         USHORT          offset;
2378
2379         // re-set the entry's WCID attribute as OPEN-NONE.
2380         offset = MAC_WCID_ATTRIBUTE_BASE + (Wcid * HW_WCID_ATTRI_SIZE);
2381         WCIDAttri = (BssIdx<<4) | PAIRWISEKEYTABLE;
2382         RTMP_IO_WRITE32(pAd, offset, WCIDAttri);
2383 }
2384
2385 BOOLEAN AsicSendCommandToMcu(
2386         IN PRTMP_ADAPTER pAd,
2387         IN UCHAR                 Command,
2388         IN UCHAR                 Token,
2389         IN UCHAR                 Arg0,
2390         IN UCHAR                 Arg1)
2391 {
2392
2393         if (pAd->chipOps.sendCommandToMcu)
2394                 pAd->chipOps.sendCommandToMcu(pAd, Command, Token, Arg0, Arg1);
2395
2396         return TRUE;
2397 }
2398
2399
2400 VOID AsicSetRxAnt(
2401         IN PRTMP_ADAPTER        pAd,
2402         IN UCHAR                        Ant)
2403 {
2404 #ifdef RT30xx
2405         /* RT3572 ATE need not to do this. */
2406         RT30xxSetRxAnt(pAd, Ant);
2407 #endif // RT30xx //
2408 }
2409
2410
2411 VOID AsicTurnOffRFClk(
2412         IN PRTMP_ADAPTER pAd,
2413         IN      UCHAR           Channel)
2414 {
2415         if (pAd->chipOps.AsicRfTurnOff)
2416         {
2417                 pAd->chipOps.AsicRfTurnOff(pAd);
2418         }
2419         else
2420         {
2421                 // RF R2 bit 18 = 0
2422                 UINT32                  R1 = 0, R2 = 0, R3 = 0;
2423                 UCHAR                   index;
2424                 RTMP_RF_REGS    *RFRegTable;
2425
2426                 RFRegTable = RF2850RegTable;
2427
2428                 switch (pAd->RfIcType)
2429                 {
2430                         case RFIC_2820:
2431                         case RFIC_2850:
2432                         case RFIC_2720:
2433                         case RFIC_2750:
2434
2435                                 for (index = 0; index < NUM_OF_2850_CHNL; index++)
2436                                 {
2437                                         if (Channel == RFRegTable[index].Channel)
2438                                         {
2439                                                 R1 = RFRegTable[index].R1 & 0xffffdfff;
2440                                                 R2 = RFRegTable[index].R2 & 0xfffbffff;
2441                                                 R3 = RFRegTable[index].R3 & 0xfff3ffff;
2442
2443                                                 RTMP_RF_IO_WRITE32(pAd, R1);
2444                                                 RTMP_RF_IO_WRITE32(pAd, R2);
2445
2446                                                 // Program R1b13 to 1, R3/b18,19 to 0, R2b18 to 0.
2447                                                 // Set RF R2 bit18=0, R3 bit[18:19]=0
2448                                                 //if (pAd->StaCfg.bRadio == FALSE)
2449                                                 if (1)
2450                                                 {
2451                                                         RTMP_RF_IO_WRITE32(pAd, R3);
2452
2453                                                         DBGPRINT(RT_DEBUG_TRACE, ("AsicTurnOffRFClk#%d(RF=%d, ) , R2=0x%08x,  R3 = 0x%08x \n",
2454                                                                 Channel, pAd->RfIcType, R2, R3));
2455                                                 }
2456                                                 else
2457                                                         DBGPRINT(RT_DEBUG_TRACE, ("AsicTurnOffRFClk#%d(RF=%d, ) , R2=0x%08x \n",
2458                                                                 Channel, pAd->RfIcType, R2));
2459                                                 break;
2460                                         }
2461                                 }
2462                                 break;
2463
2464                         default:
2465                                 break;
2466                 }
2467         }
2468 }
2469
2470
2471 VOID AsicTurnOnRFClk(
2472         IN PRTMP_ADAPTER pAd,
2473         IN      UCHAR                   Channel)
2474 {
2475         // RF R2 bit 18 = 0
2476         UINT32                  R1 = 0, R2 = 0, R3 = 0;
2477         UCHAR                   index;
2478         RTMP_RF_REGS    *RFRegTable;
2479
2480
2481         RFRegTable = RF2850RegTable;
2482
2483         switch (pAd->RfIcType)
2484         {
2485                 case RFIC_2820:
2486                 case RFIC_2850:
2487                 case RFIC_2720:
2488                 case RFIC_2750:
2489
2490                         for (index = 0; index < NUM_OF_2850_CHNL; index++)
2491                         {
2492                                 if (Channel == RFRegTable[index].Channel)
2493                                 {
2494                                         R3 = pAd->LatchRfRegs.R3;
2495                                         R3 &= 0xfff3ffff;
2496                                         R3 |= 0x00080000;
2497                                         RTMP_RF_IO_WRITE32(pAd, R3);
2498
2499                                         R1 = RFRegTable[index].R1;
2500                                         RTMP_RF_IO_WRITE32(pAd, R1);
2501
2502                                         R2 = RFRegTable[index].R2;
2503                                         if (pAd->Antenna.field.TxPath == 1)
2504                                         {
2505                                                 R2 |= 0x4000;   // If TXpath is 1, bit 14 = 1;
2506                                         }
2507
2508                                         if (pAd->Antenna.field.RxPath == 2)
2509                                         {
2510                                                 R2 |= 0x40;     // write 1 to off Rxpath.
2511                                         }
2512                                         else if (pAd->Antenna.field.RxPath == 1)
2513                                         {
2514                                                 R2 |= 0x20040;  // write 1 to off RxPath
2515                                         }
2516                                         RTMP_RF_IO_WRITE32(pAd, R2);
2517
2518                                         break;
2519                                 }
2520                         }
2521                         break;
2522
2523                 default:
2524                         break;
2525         }
2526
2527         DBGPRINT(RT_DEBUG_TRACE, ("AsicTurnOnRFClk#%d(RF=%d, ) , R2=0x%08x\n",
2528                 Channel,
2529                 pAd->RfIcType,
2530                 R2));
2531 }