drivers/staging/rtl8187se/r8180_rtl8225z2.c

   1 /*
   2  * This is part of the rtl8180-sa2400 driver
   3  * released under the GPL (See file COPYING for details).
   4  * Copyright (c) 2005 Andrea Merello <andreamrl@tiscali.it>
   5  *
   6  * This files contains programming code for the rtl8225
   7  * radio frontend.
   8  *
   9  * *Many* thanks to Realtek Corp. for their great support!
  10  */
  11
  12 #include "r8180_hw.h"
  13 #include "r8180_rtl8225.h"
  14 #include "r8180_93cx6.h"
  15
  16 #include "ieee80211/dot11d.h"
  17
  18
  19 static void write_rtl8225(struct net_device *dev, u8 adr, u16 data)
  20 {
  21         int i;
  22         u16 out, select;
  23         u8 bit;
  24         u32 bangdata = (data << 4) | (adr & 0xf);
  25
  26         out = read_nic_word(dev, RFPinsOutput) & 0xfff3;
  27
  28         write_nic_word(dev, RFPinsEnable,
  29                 (read_nic_word(dev, RFPinsEnable) | 0x7));
  30
  31         select = read_nic_word(dev, RFPinsSelect);
  32
  33         write_nic_word(dev, RFPinsSelect, select | 0x7 |
  34                        SW_CONTROL_GPIO);
  35
  36         force_pci_posting(dev);
  37         udelay(10);
  38
  39         write_nic_word(dev, RFPinsOutput, out | BB_HOST_BANG_EN);
  40
  41         force_pci_posting(dev);
  42         udelay(2);
  43
  44         write_nic_word(dev, RFPinsOutput, out);
  45
  46         force_pci_posting(dev);
  47         udelay(10);
  48
  49         for (i = 15; i >= 0; i--) {
  50                 bit = (bangdata & (1 << i)) >> i;
  51
  52                 write_nic_word(dev, RFPinsOutput, bit | out);
  53
  54                 write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
  55                 write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
  56
  57                 i--;
  58                 bit = (bangdata & (1 << i)) >> i;
  59
  60                 write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
  61                 write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
  62
  63                 write_nic_word(dev, RFPinsOutput, bit | out);
  64
  65         }
  66
  67         write_nic_word(dev, RFPinsOutput, out | BB_HOST_BANG_EN);
  68
  69         force_pci_posting(dev);
  70         udelay(10);
  71
  72         write_nic_word(dev, RFPinsOutput, out | BB_HOST_BANG_EN);
  73
  74         write_nic_word(dev, RFPinsSelect, select | SW_CONTROL_GPIO);
  75
  76         rtl8185_rf_pins_enable(dev);
  77 }
  78
  79 static const u16 rtl8225bcd_rxgain[] = {
  80         0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409,
  81         0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541,
  82         0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583,
  83         0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644,
  84         0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688,
  85         0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745,
  86         0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789,
  87         0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793,
  88         0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d,
  89         0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9,
  90         0x07aa, 0x07ab, 0x07ac, 0x07ad, 0x07b0, 0x07b1, 0x07b2, 0x07b3,
  91         0x07b4, 0x07b5, 0x07b8, 0x07b9, 0x07ba, 0x07bb, 0x07bb
  92
  93 };
  94
  95 static const u8 rtl8225_agc[] = {
  96         0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e,
  97         0x9d, 0x9c, 0x9b, 0x9a, 0x99, 0x98, 0x97, 0x96,
  98         0x95, 0x94, 0x93, 0x92, 0x91, 0x90, 0x8f, 0x8e,
  99         0x8d, 0x8c, 0x8b, 0x8a, 0x89, 0x88, 0x87, 0x86,
 100         0x85, 0x84, 0x83, 0x82, 0x81, 0x80, 0x3f, 0x3e,
 101         0x3d, 0x3c, 0x3b, 0x3a, 0x39, 0x38, 0x37, 0x36,
 102         0x35, 0x34, 0x33, 0x32, 0x31, 0x30, 0x2f, 0x2e,
 103         0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28, 0x27, 0x26,
 104         0x25, 0x24, 0x23, 0x22, 0x21, 0x20, 0x1f, 0x1e,
 105         0x1d, 0x1c, 0x1b, 0x1a, 0x19, 0x18, 0x17, 0x16,
 106         0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e,
 107         0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06,
 108         0x05, 0x04, 0x03, 0x02, 0x01, 0x01, 0x01, 0x01,
 109         0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
 110         0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
 111         0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
 112 };
 113
 114 static const u32 rtl8225_chan[] = {
 115         0,
 116         0x0080, 0x0100, 0x0180, 0x0200, 0x0280, 0x0300, 0x0380,
 117         0x0400, 0x0480, 0x0500, 0x0580, 0x0600, 0x0680, 0x074A,
 118 };
 119
 120 static const u8 rtl8225z2_threshold[] = {
 121         0x8d, 0x8d, 0x8d, 0x8d, 0x9d, 0xad, 0xbd,
 122 };
 123
 124 static const u8 rtl8225z2_gain_bg[] = {
 125         0x23, 0x15, 0xa5, /* -82-1dBm */
 126         0x23, 0x15, 0xb5, /* -82-2dBm */
 127         0x23, 0x15, 0xc5, /* -82-3dBm */
 128         0x33, 0x15, 0xc5, /* -78dBm */
 129         0x43, 0x15, 0xc5, /* -74dBm */
 130         0x53, 0x15, 0xc5, /* -70dBm */
 131         0x63, 0x15, 0xc5, /* -66dBm */
 132 };
 133
 134 static const u8 rtl8225z2_gain_a[] = {
 135         0x13, 0x27, 0x5a, /* -82dBm */
 136         0x23, 0x23, 0x58, /* -82dBm */
 137         0x33, 0x1f, 0x56, /* -82dBm */
 138         0x43, 0x1b, 0x54, /* -78dBm */
 139         0x53, 0x17, 0x51, /* -74dBm */
 140         0x63, 0x24, 0x4f, /* -70dBm */
 141         0x73, 0x0f, 0x4c, /* -66dBm */
 142 };
 143
 144 static const u16 rtl8225z2_rxgain[] = {
 145         0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409,
 146         0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541,
 147         0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583,
 148         0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644,
 149         0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688,
 150         0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745,
 151         0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789,
 152         0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793,
 153         0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d,
 154         0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9,
 155         0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3,
 156         0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb
 157
 158 };
 159
 160 static const u8 rtl8225z2_tx_power_ofdm[] = {
 161         0x42, 0x00, 0x40, 0x00, 0x40
 162 };
 163
 164 static const u8 rtl8225z2_tx_power_cck_ch14[] = {
 165         0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00
 166 };
 167
 168 static const u8 rtl8225z2_tx_power_cck[] = {
 169         0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04
 170 };
 171
 172 void rtl8225z2_set_gain(struct net_device *dev, short gain)
 173 {
 174         const u8 *rtl8225_gain;
 175         struct r8180_priv *priv = ieee80211_priv(dev);
 176         u8 mode = priv->ieee80211->mode;
 177
 178         if (mode == IEEE_B || mode == IEEE_G)
 179                 rtl8225_gain = rtl8225z2_gain_bg;
 180         else
 181                 rtl8225_gain = rtl8225z2_gain_a;
 182
 183         write_phy_ofdm(dev, 0x0b, rtl8225_gain[gain * 3]);
 184         write_phy_ofdm(dev, 0x1b, rtl8225_gain[gain * 3 + 1]);
 185         write_phy_ofdm(dev, 0x1d, rtl8225_gain[gain * 3 + 2]);
 186         write_phy_ofdm(dev, 0x21, 0x37);
 187 }
 188
 189 static u32 read_rtl8225(struct net_device *dev, u8 adr)
 190 {
 191         u32 data2Write = ((u32)(adr & 0x1f)) << 27;
 192         u32 dataRead;
 193         u32 mask;
 194         u16 oval, oval2, oval3, tmp;
 195         int i;
 196         short bit, rw;
 197         u8 wLength = 6;
 198         u8 rLength = 12;
 199         u8 low2high = 0;
 200
 201         oval = read_nic_word(dev, RFPinsOutput);
 202         oval2 = read_nic_word(dev, RFPinsEnable);
 203         oval3 = read_nic_word(dev, RFPinsSelect);
 204
 205         write_nic_word(dev, RFPinsEnable, (oval2|0xf));
 206         write_nic_word(dev, RFPinsSelect, (oval3|0xf));
 207
 208         dataRead = 0;
 209
 210         oval &= ~0xf;
 211
 212         write_nic_word(dev, RFPinsOutput, oval | BB_HOST_BANG_EN);
 213         udelay(4);
 214
 215         write_nic_word(dev, RFPinsOutput, oval);
 216         udelay(5);
 217
 218         rw = 0;
 219
 220         mask = (low2high) ? 0x01 : (((u32)0x01)<<(32-1));
 221
 222         for (i = 0; i < wLength/2; i++) {
 223                 bit = ((data2Write&mask) != 0) ? 1 : 0;
 224                 write_nic_word(dev, RFPinsOutput, bit | oval | rw);
 225                 udelay(1);
 226
 227                 write_nic_word(dev, RFPinsOutput,
 228                                 bit | oval | BB_HOST_BANG_CLK | rw);
 229                 udelay(2);
 230                 write_nic_word(dev, RFPinsOutput,
 231                                 bit | oval | BB_HOST_BANG_CLK | rw);
 232                 udelay(2);
 233
 234                 mask = (low2high) ? (mask<<1) : (mask>>1);
 235
 236                 if (i == 2) {
 237                         rw = BB_HOST_BANG_RW;
 238                         write_nic_word(dev, RFPinsOutput,
 239                                         bit | oval | BB_HOST_BANG_CLK | rw);
 240                         udelay(2);
 241                         write_nic_word(dev, RFPinsOutput, bit | oval | rw);
 242                         udelay(2);
 243                         break;
 244                 }
 245
 246                 bit = ((data2Write&mask) != 0) ? 1 : 0;
 247
 248                 write_nic_word(dev, RFPinsOutput,
 249                                 oval | bit | rw | BB_HOST_BANG_CLK);
 250                 udelay(2);
 251                 write_nic_word(dev, RFPinsOutput,
 252                                 oval | bit | rw | BB_HOST_BANG_CLK);
 253                 udelay(2);
 254
 255                 write_nic_word(dev, RFPinsOutput, oval | bit | rw);
 256                 udelay(1);
 257
 258                 mask = (low2high) ? (mask<<1) : (mask>>1);
 259         }
 260
 261         write_nic_word(dev, RFPinsOutput, rw|oval);
 262         udelay(2);
 263         mask = (low2high) ? 0x01 : (((u32)0x01) << (12-1));
 264
 265         /*
 266          * We must set data pin to HW controlled, otherwise RF can't driver it
 267          * and value RF register won't be able to read back properly.
 268          */
 269         write_nic_word(dev, RFPinsEnable, (oval2 & (~0x01)));
 270
 271         for (i = 0; i < rLength; i++) {
 272                 write_nic_word(dev, RFPinsOutput, rw|oval); udelay(1);
 273
 274                 write_nic_word(dev, RFPinsOutput, rw|oval|BB_HOST_BANG_CLK);
 275                 udelay(2);
 276                 write_nic_word(dev, RFPinsOutput, rw|oval|BB_HOST_BANG_CLK);
 277                 udelay(2);
 278                 write_nic_word(dev, RFPinsOutput, rw|oval|BB_HOST_BANG_CLK);
 279                 udelay(2);
 280                 tmp = read_nic_word(dev, RFPinsInput);
 281
 282                 dataRead |= (tmp & BB_HOST_BANG_CLK ? mask : 0);
 283
 284                 write_nic_word(dev, RFPinsOutput, (rw|oval)); udelay(2);
 285
 286                 mask = (low2high) ? (mask<<1) : (mask>>1);
 287         }
 288
 289         write_nic_word(dev, RFPinsOutput,
 290                         BB_HOST_BANG_EN | BB_HOST_BANG_RW | oval);
 291         udelay(2);
 292
 293         write_nic_word(dev, RFPinsEnable, oval2);
 294         write_nic_word(dev, RFPinsSelect, oval3); /* Set To SW Switch */
 295         write_nic_word(dev, RFPinsOutput, 0x3a0);
 296
 297         return dataRead;
 298 }
 299
 300 void rtl8225z2_rf_close(struct net_device *dev)
 301 {
 302         RF_WriteReg(dev, 0x4, 0x1f);
 303
 304         force_pci_posting(dev);
 305         mdelay(1);
 306
 307         rtl8180_set_anaparam(dev, RTL8225z2_ANAPARAM_OFF);
 308         rtl8185_set_anaparam2(dev, RTL8225z2_ANAPARAM2_OFF);
 309 }
 310
 311 /*
 312  * Map dBm into Tx power index according to current HW model, for example,
 313  * RF and PA, and current wireless mode.
 314  */
 315 s8 DbmToTxPwrIdx(struct r8180_priv *priv, WIRELESS_MODE WirelessMode,
 316                  s32 PowerInDbm)
 317 {
 318         bool bUseDefault = true;
 319         s8 TxPwrIdx = 0;
 320
 321         /*
 322          * OFDM Power in dBm = Index * 0.5 + 0
 323          * CCK Power in dBm = Index * 0.25 + 13
 324          */
 325         s32 tmp = 0;
 326
 327         if (WirelessMode == WIRELESS_MODE_G) {
 328                 bUseDefault = false;
 329                 tmp = (2 * PowerInDbm);
 330
 331                 if (tmp < 0)
 332                         TxPwrIdx = 0;
 333                 else if (tmp > 40) /* 40 means 20 dBm. */
 334                         TxPwrIdx = 40;
 335                 else
 336                         TxPwrIdx = (s8)tmp;
 337         } else if (WirelessMode == WIRELESS_MODE_B) {
 338                 bUseDefault = false;
 339                 tmp = (4 * PowerInDbm) - 52;
 340
 341                 if (tmp < 0)
 342                         TxPwrIdx = 0;
 343                 else if (tmp > 28) /* 28 means 20 dBm. */
 344                         TxPwrIdx = 28;
 345                 else
 346                         TxPwrIdx = (s8)tmp;
 347         }
 348
 349         /*
 350          * TRUE if we want to use a default implementation.
 351          * We shall set it to FALSE when we have exact translation formula
 352          * for target IC. 070622, by rcnjko.
 353          */
 354         if (bUseDefault) {
 355                 if (PowerInDbm < 0)
 356                         TxPwrIdx = 0;
 357                 else if (PowerInDbm > 35)
 358                         TxPwrIdx = 35;
 359                 else
 360                         TxPwrIdx = (u8)PowerInDbm;
 361         }
 362
 363         return TxPwrIdx;
 364 }
 365
 366 void rtl8225z2_SetTXPowerLevel(struct net_device *dev, short ch)
 367 {
 368         struct r8180_priv *priv = ieee80211_priv(dev);
 369         u8 max_cck_power_level;
 370         u8 max_ofdm_power_level;
 371         u8 min_ofdm_power_level;
 372         char cck_power_level = (char)(0xff & priv->chtxpwr[ch]);
 373         char ofdm_power_level = (char)(0xff & priv->chtxpwr_ofdm[ch]);
 374
 375         if (IS_DOT11D_ENABLE(priv->ieee80211) &&
 376             IS_DOT11D_STATE_DONE(priv->ieee80211)) {
 377                 u8 MaxTxPwrInDbm = DOT11D_GetMaxTxPwrInDbm(priv->ieee80211, ch);
 378                 u8 CckMaxPwrIdx = DbmToTxPwrIdx(priv, WIRELESS_MODE_B,
 379                                                         MaxTxPwrInDbm);
 380                 u8 OfdmMaxPwrIdx = DbmToTxPwrIdx(priv, WIRELESS_MODE_G,
 381                                                         MaxTxPwrInDbm);
 382
 383                 if (cck_power_level > CckMaxPwrIdx)
 384                         cck_power_level = CckMaxPwrIdx;
 385                 if (ofdm_power_level > OfdmMaxPwrIdx)
 386                         ofdm_power_level = OfdmMaxPwrIdx;
 387         }
 388
 389         max_cck_power_level = 15;
 390         max_ofdm_power_level = 25;
 391         min_ofdm_power_level = 10;
 392
 393         if (cck_power_level > 35)
 394                 cck_power_level = 35;
 395
 396         write_nic_byte(dev, CCK_TXAGC, cck_power_level);
 397         force_pci_posting(dev);
 398         mdelay(1);
 399
 400         if (ofdm_power_level > 35)
 401                 ofdm_power_level = 35;
 402
 403         if (priv->up == 0) {
 404                 write_phy_ofdm(dev, 2, 0x42);
 405                 write_phy_ofdm(dev, 5, 0x00);
 406                 write_phy_ofdm(dev, 6, 0x40);
 407                 write_phy_ofdm(dev, 7, 0x00);
 408                 write_phy_ofdm(dev, 8, 0x40);
 409         }
 410
 411         write_nic_byte(dev, OFDM_TXAGC, ofdm_power_level);
 412
 413         if (ofdm_power_level <= 11) {
 414                 write_phy_ofdm(dev, 0x07, 0x5c);
 415                 write_phy_ofdm(dev, 0x09, 0x5c);
 416         }
 417
 418         if (ofdm_power_level <= 17) {
 419                 write_phy_ofdm(dev, 0x07, 0x54);
 420                 write_phy_ofdm(dev, 0x09, 0x54);
 421         } else {
 422                 write_phy_ofdm(dev, 0x07, 0x50);
 423                 write_phy_ofdm(dev, 0x09, 0x50);
 424         }
 425
 426         force_pci_posting(dev);
 427         mdelay(1);
 428 }
 429
 430 void rtl8225z2_rf_set_chan(struct net_device *dev, short ch)
 431 {
 432         rtl8225z2_SetTXPowerLevel(dev, ch);
 433
 434         RF_WriteReg(dev, 0x7, rtl8225_chan[ch]);
 435
 436         if ((RF_ReadReg(dev, 0x7) & 0x0F80) != rtl8225_chan[ch])
 437                 RF_WriteReg(dev, 0x7, rtl8225_chan[ch]);
 438
 439         mdelay(1);
 440
 441         force_pci_posting(dev);
 442         mdelay(10);
 443 }
 444
 445 static void rtl8225_host_pci_init(struct net_device *dev)
 446 {
 447         write_nic_word(dev, RFPinsOutput, 0x480);
 448
 449         rtl8185_rf_pins_enable(dev);
 450
 451         write_nic_word(dev, RFPinsSelect, 0x88 | SW_CONTROL_GPIO);
 452
 453         write_nic_byte(dev, GP_ENABLE, 0);
 454
 455         force_pci_posting(dev);
 456         mdelay(200);
 457
 458         /* bit 6 is for RF on/off detection */
 459         write_nic_word(dev, GP_ENABLE, 0xff & (~(1 << 6)));
 460 }
 461
 462 void rtl8225z2_rf_init(struct net_device *dev)
 463 {
 464         struct r8180_priv *priv = ieee80211_priv(dev);
 465         int i;
 466         short channel = 1;
 467         u16     brsr;
 468         u32     data, addr;
 469
 470         priv->chan = channel;
 471
 472         rtl8225_host_pci_init(dev);
 473
 474         write_nic_dword(dev, RF_TIMING, 0x000a8008);
 475
 476         brsr = read_nic_word(dev, BRSR);
 477
 478         write_nic_word(dev, BRSR, 0xffff);
 479
 480         write_nic_dword(dev, RF_PARA, 0x100044);
 481
 482         rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
 483         write_nic_byte(dev, CONFIG3, 0x44);
 484         rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
 485
 486         rtl8185_rf_pins_enable(dev);
 487
 488         write_rtl8225(dev, 0x0, 0x2bf); mdelay(1);
 489         write_rtl8225(dev, 0x1, 0xee0); mdelay(1);
 490         write_rtl8225(dev, 0x2, 0x44d); mdelay(1);
 491         write_rtl8225(dev, 0x3, 0x441); mdelay(1);
 492         write_rtl8225(dev, 0x4, 0x8c3); mdelay(1);
 493         write_rtl8225(dev, 0x5, 0xc72); mdelay(1);
 494         write_rtl8225(dev, 0x6, 0xe6);  mdelay(1);
 495         write_rtl8225(dev, 0x7, rtl8225_chan[channel]);  mdelay(1);
 496         write_rtl8225(dev, 0x8, 0x3f);  mdelay(1);
 497         write_rtl8225(dev, 0x9, 0x335); mdelay(1);
 498         write_rtl8225(dev, 0xa, 0x9d4); mdelay(1);
 499         write_rtl8225(dev, 0xb, 0x7bb); mdelay(1);
 500         write_rtl8225(dev, 0xc, 0x850); mdelay(1);
 501         write_rtl8225(dev, 0xd, 0xcdf); mdelay(1);
 502         write_rtl8225(dev, 0xe, 0x2b);  mdelay(1);
 503         write_rtl8225(dev, 0xf, 0x114);
 504
 505         mdelay(100);
 506
 507         write_rtl8225(dev, 0x0, 0x1b7);
 508
 509         for (i = 0; i < 95; i++) {
 510                 write_rtl8225(dev, 0x1, (u8)(i + 1));
 511                 write_rtl8225(dev, 0x2, rtl8225z2_rxgain[i]);
 512         }
 513
 514         write_rtl8225(dev, 0x3, 0x80);
 515         write_rtl8225(dev, 0x5, 0x4);
 516
 517         write_rtl8225(dev, 0x0, 0xb7);
 518
 519         write_rtl8225(dev, 0x2, 0xc4d);
 520
 521         /* FIXME!! rtl8187 we have to check if calibrarion
 522          * is successful and eventually cal. again (repeat
 523          * the two write on reg 2)
 524          */
 525         data = read_rtl8225(dev, 6);
 526         if (!(data & 0x00000080)) {
 527                 write_rtl8225(dev, 0x02, 0x0c4d);
 528                 force_pci_posting(dev); mdelay(200);
 529                 write_rtl8225(dev, 0x02, 0x044d);
 530                 force_pci_posting(dev); mdelay(100);
 531                 data = read_rtl8225(dev, 6);
 532                 if (!(data & 0x00000080))
 533                         DMESGW("RF Calibration Failed!!!!\n");
 534         }
 535
 536         mdelay(200);
 537
 538         write_rtl8225(dev, 0x0, 0x2bf);
 539
 540         for (i = 0; i < 128; i++) {
 541                 data = rtl8225_agc[i];
 542
 543                 addr = i + 0x80; /* enable writing AGC table */
 544                 write_phy_ofdm(dev, 0xb, data);
 545                 mdelay(1);
 546
 547                 write_phy_ofdm(dev, 0xa, addr);
 548                 mdelay(1);
 549         }
 550
 551         force_pci_posting(dev);
 552         mdelay(1);
 553
 554         write_phy_ofdm(dev, 0x00, 0x01); mdelay(1);
 555         write_phy_ofdm(dev, 0x01, 0x02); mdelay(1);
 556         write_phy_ofdm(dev, 0x02, 0x62); mdelay(1);
 557         write_phy_ofdm(dev, 0x03, 0x00); mdelay(1);
 558         write_phy_ofdm(dev, 0x04, 0x00); mdelay(1);
 559         write_phy_ofdm(dev, 0x05, 0x00); mdelay(1);
 560         write_phy_ofdm(dev, 0x06, 0x40); mdelay(1);
 561         write_phy_ofdm(dev, 0x07, 0x00); mdelay(1);
 562         write_phy_ofdm(dev, 0x08, 0x40); mdelay(1);
 563         write_phy_ofdm(dev, 0x09, 0xfe); mdelay(1);
 564         write_phy_ofdm(dev, 0x0a, 0x08); mdelay(1);
 565         write_phy_ofdm(dev, 0x0b, 0x80); mdelay(1);
 566         write_phy_ofdm(dev, 0x0c, 0x01); mdelay(1);
 567         write_phy_ofdm(dev, 0x0d, 0x43);
 568         write_phy_ofdm(dev, 0x0e, 0xd3); mdelay(1);
 569         write_phy_ofdm(dev, 0x0f, 0x38); mdelay(1);
 570         write_phy_ofdm(dev, 0x10, 0x84); mdelay(1);
 571         write_phy_ofdm(dev, 0x11, 0x07); mdelay(1);
 572         write_phy_ofdm(dev, 0x12, 0x20); mdelay(1);
 573         write_phy_ofdm(dev, 0x13, 0x20); mdelay(1);
 574         write_phy_ofdm(dev, 0x14, 0x00); mdelay(1);
 575         write_phy_ofdm(dev, 0x15, 0x40); mdelay(1);
 576         write_phy_ofdm(dev, 0x16, 0x00); mdelay(1);
 577         write_phy_ofdm(dev, 0x17, 0x40); mdelay(1);
 578         write_phy_ofdm(dev, 0x18, 0xef); mdelay(1);
 579         write_phy_ofdm(dev, 0x19, 0x19); mdelay(1);
 580         write_phy_ofdm(dev, 0x1a, 0x20); mdelay(1);
 581         write_phy_ofdm(dev, 0x1b, 0x15); mdelay(1);
 582         write_phy_ofdm(dev, 0x1c, 0x04); mdelay(1);
 583         write_phy_ofdm(dev, 0x1d, 0xc5); mdelay(1);
 584         write_phy_ofdm(dev, 0x1e, 0x95); mdelay(1);
 585         write_phy_ofdm(dev, 0x1f, 0x75); mdelay(1);
 586         write_phy_ofdm(dev, 0x20, 0x1f); mdelay(1);
 587         write_phy_ofdm(dev, 0x21, 0x17); mdelay(1);
 588         write_phy_ofdm(dev, 0x22, 0x16); mdelay(1);
 589         write_phy_ofdm(dev, 0x23, 0x80); mdelay(1); /* FIXME maybe not needed */
 590         write_phy_ofdm(dev, 0x24, 0x46); mdelay(1);
 591         write_phy_ofdm(dev, 0x25, 0x00); mdelay(1);
 592         write_phy_ofdm(dev, 0x26, 0x90); mdelay(1);
 593         write_phy_ofdm(dev, 0x27, 0x88); mdelay(1);
 594
 595         rtl8225z2_set_gain(dev, 4);
 596
 597         write_phy_cck(dev, 0x0, 0x98); mdelay(1);
 598         write_phy_cck(dev, 0x3, 0x20); mdelay(1);
 599         write_phy_cck(dev, 0x4, 0x7e); mdelay(1);
 600         write_phy_cck(dev, 0x5, 0x12); mdelay(1);
 601         write_phy_cck(dev, 0x6, 0xfc); mdelay(1);
 602         write_phy_cck(dev, 0x7, 0x78); mdelay(1);
 603         write_phy_cck(dev, 0x8, 0x2e); mdelay(1);
 604         write_phy_cck(dev, 0x10, 0x93); mdelay(1);
 605         write_phy_cck(dev, 0x11, 0x88); mdelay(1);
 606         write_phy_cck(dev, 0x12, 0x47); mdelay(1);
 607         write_phy_cck(dev, 0x13, 0xd0);
 608         write_phy_cck(dev, 0x19, 0x00);
 609         write_phy_cck(dev, 0x1a, 0xa0);
 610         write_phy_cck(dev, 0x1b, 0x08);
 611         write_phy_cck(dev, 0x40, 0x86); /* CCK Carrier Sense Threshold */
 612         write_phy_cck(dev, 0x41, 0x8d); mdelay(1);
 613         write_phy_cck(dev, 0x42, 0x15); mdelay(1);
 614         write_phy_cck(dev, 0x43, 0x18); mdelay(1);
 615         write_phy_cck(dev, 0x44, 0x36); mdelay(1);
 616         write_phy_cck(dev, 0x45, 0x35); mdelay(1);
 617         write_phy_cck(dev, 0x46, 0x2e); mdelay(1);
 618         write_phy_cck(dev, 0x47, 0x25); mdelay(1);
 619         write_phy_cck(dev, 0x48, 0x1c); mdelay(1);
 620         write_phy_cck(dev, 0x49, 0x12); mdelay(1);
 621         write_phy_cck(dev, 0x4a, 0x09); mdelay(1);
 622         write_phy_cck(dev, 0x4b, 0x04); mdelay(1);
 623         write_phy_cck(dev, 0x4c, 0x05); mdelay(1);
 624
 625         write_nic_byte(dev, 0x5b, 0x0d); mdelay(1);
 626
 627         rtl8225z2_SetTXPowerLevel(dev, channel);
 628
 629         /* RX antenna default to A */
 630         write_phy_cck(dev, 0x11, 0x9b); mdelay(1);              /* B: 0xDB */
 631         write_phy_ofdm(dev, 0x26, 0x90); mdelay(1);             /* B: 0x10 */
 632
 633         rtl8185_tx_antenna(dev, 0x03);                          /* B: 0x00 */
 634
 635         /* switch to high-speed 3-wire
 636          * last digit. 2 for both cck and ofdm
 637          */
 638         write_nic_dword(dev, 0x94, 0x15c00002);
 639         rtl8185_rf_pins_enable(dev);
 640
 641         rtl8225z2_rf_set_chan(dev, priv->chan);
 642 }
 643
 644 void rtl8225z2_rf_set_mode(struct net_device *dev)
 645 {
 646         struct r8180_priv *priv = ieee80211_priv(dev);
 647
 648         if (priv->ieee80211->mode == IEEE_A) {
 649                 write_rtl8225(dev, 0x5, 0x1865);
 650                 write_nic_dword(dev, RF_PARA, 0x10084);
 651                 write_nic_dword(dev, RF_TIMING, 0xa8008);
 652                 write_phy_ofdm(dev, 0x0, 0x0);
 653                 write_phy_ofdm(dev, 0xa, 0x6);
 654                 write_phy_ofdm(dev, 0xb, 0x99);
 655                 write_phy_ofdm(dev, 0xf, 0x20);
 656                 write_phy_ofdm(dev, 0x11, 0x7);
 657
 658                 rtl8225z2_set_gain(dev, 4);
 659
 660                 write_phy_ofdm(dev, 0x15, 0x40);
 661                 write_phy_ofdm(dev, 0x17, 0x40);
 662
 663                 write_nic_dword(dev, 0x94, 0x10000000);
 664         } else {
 665                 write_rtl8225(dev, 0x5, 0x1864);
 666                 write_nic_dword(dev, RF_PARA, 0x10044);
 667                 write_nic_dword(dev, RF_TIMING, 0xa8008);
 668                 write_phy_ofdm(dev, 0x0, 0x1);
 669                 write_phy_ofdm(dev, 0xa, 0x6);
 670                 write_phy_ofdm(dev, 0xb, 0x99);
 671                 write_phy_ofdm(dev, 0xf, 0x20);
 672                 write_phy_ofdm(dev, 0x11, 0x7);
 673
 674                 rtl8225z2_set_gain(dev, 4);
 675
 676                 write_phy_ofdm(dev, 0x15, 0x40);
 677                 write_phy_ofdm(dev, 0x17, 0x40);
 678
 679                 write_nic_dword(dev, 0x94, 0x04000002);
 680         }
 681 }
 682
 683 #define MAX_DOZE_WAITING_TIMES_85B              20
 684 #define MAX_POLLING_24F_TIMES_87SE              10
 685 #define LPS_MAX_SLEEP_WAITING_TIMES_87SE        5
 686
 687 bool SetZebraRFPowerState8185(struct net_device *dev,
 688                               RT_RF_POWER_STATE eRFPowerState)
 689 {
 690         struct r8180_priv *priv = ieee80211_priv(dev);
 691         u8                      btCR9346, btConfig3;
 692         bool bActionAllowed = true, bTurnOffBB = true;
 693         u8                      u1bTmp;
 694         int                     i;
 695         bool            bResult = true;
 696         u8                      QueueID;
 697
 698         if (priv->SetRFPowerStateInProgress == true)
 699                 return false;
 700
 701         priv->SetRFPowerStateInProgress = true;
 702
 703         btCR9346 = read_nic_byte(dev, CR9346);
 704         write_nic_byte(dev, CR9346, (btCR9346 | 0xC0));
 705
 706         btConfig3 = read_nic_byte(dev, CONFIG3);
 707         write_nic_byte(dev, CONFIG3, (btConfig3 | CONFIG3_PARM_En));
 708
 709         switch (eRFPowerState) {
 710         case eRfOn:
 711                 write_nic_word(dev, 0x37C, 0x00EC);
 712
 713                 /* turn on AFE */
 714                 write_nic_byte(dev, 0x54, 0x00);
 715                 write_nic_byte(dev, 0x62, 0x00);
 716
 717                 /* turn on RF */
 718                 RF_WriteReg(dev, 0x0, 0x009f); udelay(500);
 719                 RF_WriteReg(dev, 0x4, 0x0972); udelay(500);
 720
 721                 /* turn on RF again */
 722                 RF_WriteReg(dev, 0x0, 0x009f); udelay(500);
 723                 RF_WriteReg(dev, 0x4, 0x0972); udelay(500);
 724
 725                 /* turn on BB */
 726                 write_phy_ofdm(dev, 0x10, 0x40);
 727                 write_phy_ofdm(dev, 0x12, 0x40);
 728
 729                 /* Avoid power down at init time. */
 730                 write_nic_byte(dev, CONFIG4, priv->RFProgType);
 731
 732                 u1bTmp = read_nic_byte(dev, 0x24E);
 733                 write_nic_byte(dev, 0x24E, (u1bTmp & (~(BIT5 | BIT6))));
 734                 break;
 735         case eRfSleep:
 736                 for (QueueID = 0, i = 0; QueueID < 6;) {
 737                         if (get_curr_tx_free_desc(dev, QueueID) ==
 738                                                         priv->txringcount) {
 739                                 QueueID++;
 740                                 continue;
 741                         } else {
 742                                 priv->TxPollingTimes++;
 743                                 if (priv->TxPollingTimes >=
 744                                         LPS_MAX_SLEEP_WAITING_TIMES_87SE) {
 745                                         bActionAllowed = false;
 746                                         break;
 747                                 } else
 748                                         udelay(10);
 749                         }
 750                 }
 751
 752                 if (bActionAllowed) {
 753                         /* turn off BB RXIQ matrix to cut off rx signal */
 754                         write_phy_ofdm(dev, 0x10, 0x00);
 755                         write_phy_ofdm(dev, 0x12, 0x00);
 756
 757                         /* turn off RF */
 758                         RF_WriteReg(dev, 0x4, 0x0000);
 759                         RF_WriteReg(dev, 0x0, 0x0000);
 760
 761                         /* turn off AFE except PLL */
 762                         write_nic_byte(dev, 0x62, 0xff);
 763                         write_nic_byte(dev, 0x54, 0xec);
 764
 765                         mdelay(1);
 766
 767                         {
 768                                 int i = 0;
 769                                 while (true) {
 770                                         u8 tmp24F = read_nic_byte(dev, 0x24f);
 771
 772                                         if ((tmp24F == 0x01) ||
 773                                                         (tmp24F == 0x09)) {
 774                                                 bTurnOffBB = true;
 775                                                 break;
 776                                         } else {
 777                                                 udelay(10);
 778                                                 i++;
 779                                                 priv->TxPollingTimes++;
 780
 781                                                 if (priv->TxPollingTimes >= LPS_MAX_SLEEP_WAITING_TIMES_87SE) {
 782                                                         bTurnOffBB = false;
 783                                                         break;
 784                                                 } else
 785                                                         udelay(10);
 786                                         }
 787                                 }
 788                         }
 789
 790                         if (bTurnOffBB) {
 791                                 /* turn off BB */
 792                                 u1bTmp = read_nic_byte(dev, 0x24E);
 793                                 write_nic_byte(dev, 0x24E,
 794                                                 (u1bTmp | BIT5 | BIT6));
 795
 796                                 /* turn off AFE PLL */
 797                                 write_nic_byte(dev, 0x54, 0xFC);
 798                                 write_nic_word(dev, 0x37C, 0x00FC);
 799                         }
 800                 }
 801                 break;
 802         case eRfOff:
 803                 for (QueueID = 0, i = 0; QueueID < 6;) {
 804                         if (get_curr_tx_free_desc(dev, QueueID) ==
 805                                         priv->txringcount) {
 806                                 QueueID++;
 807                                 continue;
 808                         } else {
 809                                 udelay(10);
 810                                 i++;
 811                         }
 812
 813                         if (i >= MAX_DOZE_WAITING_TIMES_85B)
 814                                 break;
 815                 }
 816
 817                 /* turn off BB RXIQ matrix to cut off rx signal */
 818                 write_phy_ofdm(dev, 0x10, 0x00);
 819                 write_phy_ofdm(dev, 0x12, 0x00);
 820
 821                 /* turn off RF */
 822                 RF_WriteReg(dev, 0x4, 0x0000);
 823                 RF_WriteReg(dev, 0x0, 0x0000);
 824
 825                 /* turn off AFE except PLL */
 826                 write_nic_byte(dev, 0x62, 0xff);
 827                 write_nic_byte(dev, 0x54, 0xec);
 828
 829                 mdelay(1);
 830
 831                 {
 832                         int i = 0;
 833
 834                         while (true) {
 835                                 u8 tmp24F = read_nic_byte(dev, 0x24f);
 836
 837                                 if ((tmp24F == 0x01) || (tmp24F == 0x09)) {
 838                                         bTurnOffBB = true;
 839                                         break;
 840                                 } else {
 841                                         bTurnOffBB = false;
 842                                         udelay(10);
 843                                         i++;
 844                                 }
 845
 846                                 if (i > MAX_POLLING_24F_TIMES_87SE)
 847                                         break;
 848                         }
 849                 }
 850
 851                 if (bTurnOffBB) {
 852                         /* turn off BB */
 853                         u1bTmp = read_nic_byte(dev, 0x24E);
 854                         write_nic_byte(dev, 0x24E, (u1bTmp | BIT5 | BIT6));
 855
 856                         /* turn off AFE PLL (80M) */
 857                         write_nic_byte(dev, 0x54, 0xFC);
 858                         write_nic_word(dev, 0x37C, 0x00FC);
 859                 }
 860                 break;
 861         }
 862
 863         btConfig3 &= ~(CONFIG3_PARM_En);
 864         write_nic_byte(dev, CONFIG3, btConfig3);
 865
 866         btCR9346 &= ~(0xC0);
 867         write_nic_byte(dev, CR9346, btCR9346);
 868
 869         if (bResult && bActionAllowed)
 870                 priv->eRFPowerState = eRFPowerState;
 871
 872         priv->SetRFPowerStateInProgress = false;
 873
 874         return bResult && bActionAllowed;
 875 }
 876
 877 void rtl8225z4_rf_sleep(struct net_device *dev)
 878 {
 879         MgntActSet_RF_State(dev, eRfSleep, RF_CHANGE_BY_PS);
 880 }
 881
 882 void rtl8225z4_rf_wakeup(struct net_device *dev)
 883 {
 884         MgntActSet_RF_State(dev, eRfOn, RF_CHANGE_BY_PS);
 885 }