2 * Copyright (c) Realtek Semiconductor Corp. All rights reserved.
8 * Hardware Initialization and Hardware IO for RTL8185B
10 * Major Change History:
12 * ---------- --------------- -------------------------------
13 * 2006-11-15 Xiong Created
16 * This file is ported from RTL8185B Windows driver.
21 /*--------------------------Include File------------------------------------*/
22 #include <linux/spinlock.h>
25 #include "r8180_rtl8225.h" /* RTL8225 Radio frontend */
26 #include "r8180_93cx6.h" /* Card EEPROM */
28 #include "ieee80211/dot11d.h"
29 /* #define CONFIG_RTL8180_IO_MAP */
30 #define TC_3W_POLL_MAX_TRY_CNT 5
32 static u8 MAC_REG_TABLE[][2] = {
34 /* 0x34(BRSR), 0xBE(RATE_FALLBACK_CTL), 0x1E0(ARFR) would set in HwConfigureRTL8185() */
35 /* 0x272(RFSW_CTRL), 0x1CE(AESMSK_QC) set in InitializeAdapter8185(). */
36 /* 0x1F0~0x1F8 set in MacConfig_85BASIC() */
37 {0x08, 0xae}, {0x0a, 0x72}, {0x5b, 0x42},
38 {0x84, 0x88}, {0x85, 0x24}, {0x88, 0x54}, {0x8b, 0xb8}, {0x8c, 0x03},
39 {0x8d, 0x40}, {0x8e, 0x00}, {0x8f, 0x00}, {0x5b, 0x18}, {0x91, 0x03},
40 {0x94, 0x0F}, {0x95, 0x32},
41 {0x96, 0x00}, {0x97, 0x07}, {0xb4, 0x22}, {0xdb, 0x00},
42 {0xf0, 0x32}, {0xf1, 0x32}, {0xf2, 0x00}, {0xf3, 0x00}, {0xf4, 0x32},
43 {0xf5, 0x43}, {0xf6, 0x00}, {0xf7, 0x00}, {0xf8, 0x46}, {0xf9, 0xa4},
44 {0xfa, 0x00}, {0xfb, 0x00}, {0xfc, 0x96}, {0xfd, 0xa4}, {0xfe, 0x00},
48 /* For Flextronics system Logo PCIHCT failure: */
49 /* 0x1C4~0x1CD set no-zero value to avoid PCI configuration space 0x45[7]=1 */
51 {0x58, 0x00}, {0x59, 0x00}, {0x5a, 0x04}, {0x5b, 0x00}, {0x60, 0x24},
52 {0x61, 0x97}, {0x62, 0xF0}, {0x63, 0x09}, {0x80, 0x0F}, {0x81, 0xFF},
53 {0x82, 0xFF}, {0x83, 0x03},
54 {0xC4, 0x22}, {0xC5, 0x22}, {0xC6, 0x22}, {0xC7, 0x22}, {0xC8, 0x22}, /* lzm add 080826 */
55 {0xC9, 0x22}, {0xCA, 0x22}, {0xCB, 0x22}, {0xCC, 0x22}, {0xCD, 0x22}, /* lzm add 080826 */
61 {0x0c, 0x04}, {0x4c, 0x30}, {0x4d, 0x08}, {0x50, 0x05}, {0x51, 0xf5},
62 {0x52, 0x04}, {0x53, 0xa0}, {0x54, 0xff}, {0x55, 0xff}, {0x56, 0xff},
63 {0x57, 0xff}, {0x58, 0x08}, {0x59, 0x08}, {0x5a, 0x08}, {0x5b, 0x08},
64 {0x60, 0x08}, {0x61, 0x08}, {0x62, 0x08}, {0x63, 0x08}, {0x64, 0x2f},
65 {0x8c, 0x3f}, {0x8d, 0x3f}, {0x8e, 0x3f},
66 {0x8f, 0x3f}, {0xc4, 0xff}, {0xc5, 0xff}, {0xc6, 0xff}, {0xc7, 0xff},
67 {0xc8, 0x00}, {0xc9, 0x00}, {0xca, 0x80}, {0xcb, 0x00},
70 {0x5e, 0x00}, {0x9f, 0x03}
74 static u8 ZEBRA_AGC[] = {
76 0x7E, 0x7E, 0x7E, 0x7E, 0x7D, 0x7C, 0x7B, 0x7A, 0x79, 0x78, 0x77, 0x76, 0x75, 0x74, 0x73, 0x72,
77 0x71, 0x70, 0x6F, 0x6E, 0x6D, 0x6C, 0x6B, 0x6A, 0x69, 0x68, 0x67, 0x66, 0x65, 0x64, 0x63, 0x62,
78 0x48, 0x47, 0x46, 0x45, 0x44, 0x29, 0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21, 0x08, 0x07,
79 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
80 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x10, 0x11, 0x12, 0x13, 0x15, 0x16,
81 0x17, 0x17, 0x18, 0x18, 0x19, 0x1a, 0x1a, 0x1b, 0x1b, 0x1c, 0x1c, 0x1d, 0x1d, 0x1d, 0x1e, 0x1e,
82 0x1f, 0x1f, 0x1f, 0x20, 0x20, 0x20, 0x20, 0x21, 0x21, 0x21, 0x22, 0x22, 0x22, 0x23, 0x23, 0x24,
83 0x24, 0x25, 0x25, 0x25, 0x26, 0x26, 0x27, 0x27, 0x2F, 0x2F, 0x2F, 0x2F, 0x2F, 0x2F, 0x2F, 0x2F
86 static u32 ZEBRA_RF_RX_GAIN_TABLE[] = {
87 0x0096, 0x0076, 0x0056, 0x0036, 0x0016, 0x01f6, 0x01d6, 0x01b6,
88 0x0196, 0x0176, 0x00F7, 0x00D7, 0x00B7, 0x0097, 0x0077, 0x0057,
89 0x0037, 0x00FB, 0x00DB, 0x00BB, 0x00FF, 0x00E3, 0x00C3, 0x00A3,
90 0x0083, 0x0063, 0x0043, 0x0023, 0x0003, 0x01E3, 0x01C3, 0x01A3,
91 0x0183, 0x0163, 0x0143, 0x0123, 0x0103
94 static u8 OFDM_CONFIG[] = {
95 /* OFDM reg0x06[7:0]=0xFF: Enable power saving mode in RX */
96 /* OFDM reg0x3C[4]=1'b1: Enable RX power saving mode */
97 /* ofdm 0x3a = 0x7b ,(original : 0xfb) For ECS shielding room TP test */
99 0x10, 0x0F, 0x0A, 0x0C, 0x14, 0xFA, 0xFF, 0x50,
100 0x00, 0x50, 0x00, 0x00, 0x00, 0x5C, 0x00, 0x00,
102 0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0xA8, 0x26,
103 0x32, 0x33, 0x06, 0xA5, 0x6F, 0x55, 0xC8, 0xBB,
105 0x0A, 0xE1, 0x2C, 0x4A, 0x86, 0x83, 0x34, 0x00,
106 0x4F, 0x24, 0x6F, 0xC2, 0x03, 0x40, 0x80, 0x00,
108 0xC0, 0xC1, 0x58, 0xF1, 0x00, 0xC4, 0x90, 0x3e,
109 0xD8, 0x3C, 0x7B, 0x10, 0x10
112 /*---------------------------------------------------------------
114 * the code is ported from Windows source code
115 *---------------------------------------------------------------
118 static u8 PlatformIORead1Byte(struct net_device *dev, u32 offset)
120 return read_nic_byte(dev, offset);
123 static void PlatformIOWrite1Byte(struct net_device *dev, u32 offset, u8 data)
125 write_nic_byte(dev, offset, data);
126 read_nic_byte(dev, offset); /* To make sure write operation is completed, 2005.11.09, by rcnjko. */
129 static void PlatformIOWrite2Byte(struct net_device *dev, u32 offset, u16 data)
131 write_nic_word(dev, offset, data);
132 read_nic_word(dev, offset); /* To make sure write operation is completed, 2005.11.09, by rcnjko. */
135 static void PlatformIOWrite4Byte(struct net_device *dev, u32 offset, u32 data)
137 if (offset == PhyAddr) {
138 /* For Base Band configuration. */
139 unsigned char cmdByte;
140 unsigned long dataBytes;
144 cmdByte = (u8)(data & 0x000000ff);
149 * The critical section is only BB read/write race condition.
151 * 1. We assume NO one will access BB at DIRQL, otherwise, system will crash for
152 * acquiring the spinlock in such context.
153 * 2. PlatformIOWrite4Byte() MUST NOT be recursive.
155 /* NdisAcquireSpinLock( &(pDevice->IoSpinLock) ); */
157 for (idx = 0; idx < 30; idx++) {
158 /* Make sure command bit is clear before access it. */
159 u1bTmp = PlatformIORead1Byte(dev, PhyAddr);
160 if ((u1bTmp & BIT7) == 0)
166 for (idx = 0; idx < 3; idx++)
167 PlatformIOWrite1Byte(dev, offset+1+idx, ((u8 *)&dataBytes)[idx]);
169 write_nic_byte(dev, offset, cmdByte);
171 /* NdisReleaseSpinLock( &(pDevice->IoSpinLock) ); */
173 write_nic_dword(dev, offset, data);
174 read_nic_dword(dev, offset); /* To make sure write operation is completed, 2005.11.09, by rcnjko. */
178 static void SetOutputEnableOfRfPins(struct net_device *dev)
180 write_nic_word(dev, RFPinsEnable, 0x1bff);
183 static bool HwHSSIThreeWire(struct net_device *dev,
190 /* Check if WE and RE are cleared. */
191 for (TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++) {
192 u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
193 if ((u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0)
198 if (TryCnt == TC_3W_POLL_MAX_TRY_CNT) {
200 "HwThreeWire(): CmdReg: %#X RE|WE bits are not clear!!\n",
205 /* RTL8187S HSSI Read/Write Function */
206 u1bTmp = read_nic_byte(dev, RF_SW_CONFIG);
207 u1bTmp |= RF_SW_CFG_SI; /* reg08[1]=1 Serial Interface(SI) */
208 write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
210 /* jong: HW SI read must set reg84[3]=0. */
211 u1bTmp = read_nic_byte(dev, RFPinsSelect);
213 write_nic_byte(dev, RFPinsSelect, u1bTmp);
214 /* Fill up data buffer for write operation. */
216 /* SI - reg274[3:0] : RF register's Address */
218 write_nic_word(dev, SW_3W_DB0, *((u16 *)pDataBuf));
220 write_nic_word(dev, SW_3W_DB0, *((u16 *)pDataBuf));
222 /* Set up command: WE or RE. */
224 write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_WE);
226 write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_RE);
229 /* Check if DONE is set. */
230 for (TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++) {
231 u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
232 if (u1bTmp & SW_3W_CMD1_DONE)
238 write_nic_byte(dev, SW_3W_CMD1, 0);
240 /* Read back data for read operation. */
242 /* Serial Interface : reg363_362[11:0] */
243 *((u16 *)pDataBuf) = read_nic_word(dev, SI_DATA_READ);
244 *((u16 *)pDataBuf) &= 0x0FFF;
250 void RF_WriteReg(struct net_device *dev, u8 offset, u16 data)
252 u16 reg = (data << 4) | (offset & 0x0f);
253 HwHSSIThreeWire(dev, (u8 *)®, true);
256 u16 RF_ReadReg(struct net_device *dev, u8 offset)
258 u16 reg = offset & 0x0f;
259 HwHSSIThreeWire(dev, (u8 *)®, false);
263 static u8 ReadBBPortUchar(struct net_device *dev, u32 addr)
265 PlatformIOWrite4Byte(dev, PhyAddr, addr & 0xffffff7f);
266 return PlatformIORead1Byte(dev, PhyDataR);
269 /* by Owen on 04/07/14 for writing BB register successfully */
270 static void WriteBBPortUchar(struct net_device *dev, u32 Data)
272 PlatformIOWrite4Byte(dev, PhyAddr, Data);
273 ReadBBPortUchar(dev, Data);
278 * Perform Antenna settings with antenna diversity on 87SE.
279 * Created by Roger, 2008.01.25.
281 bool SetAntennaConfig87SE(struct net_device *dev,
282 u8 DefaultAnt, /* 0: Main, 1: Aux. */
283 bool bAntDiversity) /* 1:Enable, 0: Disable. */
285 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
286 bool bAntennaSwitched = true;
287 u8 ant_diversity_offset = 0x00; /* 0x00 = disabled, 0x80 = enabled */
289 /* printk("SetAntennaConfig87SE(): DefaultAnt(%d), bAntDiversity(%d)\n", DefaultAnt, bAntDiversity); */
291 /* Threshold for antenna diversity. */
292 write_phy_cck(dev, 0x0c, 0x09); /* Reg0c : 09 */
294 if (bAntDiversity) /* Enable Antenna Diversity. */
295 ant_diversity_offset = 0x80;
297 if (DefaultAnt == 1) { /* aux Antenna */
298 /* Mac register, aux antenna */
299 write_nic_byte(dev, ANTSEL, 0x00);
301 /* Config CCK RX antenna. */
302 write_phy_cck(dev, 0x11, 0xbb); /* Reg11 : bb */
303 write_phy_cck(dev, 0x01, 0x47|ant_diversity_offset); /* Reg01 : 47 | ant_diversity_offset */
305 /* Config OFDM RX antenna. */
306 write_phy_ofdm(dev, 0x0D, 0x54); /* Reg0d : 54 */
307 write_phy_ofdm(dev, 0x18, 0x32|ant_diversity_offset); /* Reg18 : 32 */
308 } else { /* main Antenna */
309 /* Mac register, main antenna */
310 write_nic_byte(dev, ANTSEL, 0x03);
312 /* Config CCK RX antenna. */
313 write_phy_cck(dev, 0x11, 0x9b); /* Reg11 : 9b */
314 write_phy_cck(dev, 0x01, 0x47|ant_diversity_offset); /* Reg01 : 47 */
316 /* Config OFDM RX antenna. */
317 write_phy_ofdm(dev, 0x0D, 0x5c); /* Reg0d : 5c */
318 write_phy_ofdm(dev, 0x18, 0x32|ant_diversity_offset); /*Reg18 : 32 */
320 priv->CurrAntennaIndex = DefaultAnt; /* Update default settings. */
321 return bAntennaSwitched;
324 *--------------------------------------------------------------
325 * Hardware Initialization.
326 * the code is ported from Windows source code
327 *--------------------------------------------------------------
330 static void ZEBRA_Config_85BASIC_HardCode(struct net_device *dev)
333 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
336 u32 u4bRegOffset, u4bRegValue;
337 u16 u4bRF23, u4bRF24;
343 *===========================================================================
344 * 87S_PCIE :: RADIOCFG.TXT
345 *===========================================================================
349 /* Page1 : reg16-reg30 */
350 RF_WriteReg(dev, 0x00, 0x013f); mdelay(1); /* switch to page1 */
351 u4bRF23 = RF_ReadReg(dev, 0x08); mdelay(1);
352 u4bRF24 = RF_ReadReg(dev, 0x09); mdelay(1);
354 if (u4bRF23 == 0x818 && u4bRF24 == 0x70C) {
356 netdev_info(dev, "card type changed from C- to D-cut\n");
359 /* Page0 : reg0-reg15 */
361 RF_WriteReg(dev, 0x00, 0x009f); mdelay(1);/* 1 */
362 RF_WriteReg(dev, 0x01, 0x06e0); mdelay(1);
363 RF_WriteReg(dev, 0x02, 0x004d); mdelay(1);/* 2 */
364 RF_WriteReg(dev, 0x03, 0x07f1); mdelay(1);/* 3 */
365 RF_WriteReg(dev, 0x04, 0x0975); mdelay(1);
366 RF_WriteReg(dev, 0x05, 0x0c72); mdelay(1);
367 RF_WriteReg(dev, 0x06, 0x0ae6); mdelay(1);
368 RF_WriteReg(dev, 0x07, 0x00ca); mdelay(1);
369 RF_WriteReg(dev, 0x08, 0x0e1c); mdelay(1);
370 RF_WriteReg(dev, 0x09, 0x02f0); mdelay(1);
371 RF_WriteReg(dev, 0x0a, 0x09d0); mdelay(1);
372 RF_WriteReg(dev, 0x0b, 0x01ba); mdelay(1);
373 RF_WriteReg(dev, 0x0c, 0x0640); mdelay(1);
374 RF_WriteReg(dev, 0x0d, 0x08df); mdelay(1);
375 RF_WriteReg(dev, 0x0e, 0x0020); mdelay(1);
376 RF_WriteReg(dev, 0x0f, 0x0990); mdelay(1);
378 /* Page1 : reg16-reg30 */
379 RF_WriteReg(dev, 0x00, 0x013f); mdelay(1);
380 RF_WriteReg(dev, 0x03, 0x0806); mdelay(1);
381 RF_WriteReg(dev, 0x04, 0x03a7); mdelay(1);
382 RF_WriteReg(dev, 0x05, 0x059b); mdelay(1);
383 RF_WriteReg(dev, 0x06, 0x0081); mdelay(1);
384 RF_WriteReg(dev, 0x07, 0x01A0); mdelay(1);
385 /* Don't write RF23/RF24 to make a difference between 87S C cut and D cut. asked by SD3 stevenl. */
386 RF_WriteReg(dev, 0x0a, 0x0001); mdelay(1);
387 RF_WriteReg(dev, 0x0b, 0x0418); mdelay(1);
390 RF_WriteReg(dev, 0x0c, 0x0fbe); mdelay(1);
391 RF_WriteReg(dev, 0x0d, 0x0008); mdelay(1);
392 RF_WriteReg(dev, 0x0e, 0x0807); mdelay(1); /* RX LO buffer */
394 RF_WriteReg(dev, 0x0c, 0x0fbe); mdelay(1);
395 RF_WriteReg(dev, 0x0d, 0x0008); mdelay(1);
396 RF_WriteReg(dev, 0x0e, 0x0806); mdelay(1); /* RX LO buffer */
399 RF_WriteReg(dev, 0x0f, 0x0acc); mdelay(1);
400 RF_WriteReg(dev, 0x00, 0x01d7); mdelay(1); /* 6 */
401 RF_WriteReg(dev, 0x03, 0x0e00); mdelay(1);
402 RF_WriteReg(dev, 0x04, 0x0e50); mdelay(1);
404 for (i = 0; i <= 36; i++) {
405 RF_WriteReg(dev, 0x01, i); mdelay(1);
406 RF_WriteReg(dev, 0x02, ZEBRA_RF_RX_GAIN_TABLE[i]); mdelay(1);
409 RF_WriteReg(dev, 0x05, 0x0203); mdelay(1); /* 203, 343 */
410 RF_WriteReg(dev, 0x06, 0x0200); mdelay(1); /* 400 */
411 RF_WriteReg(dev, 0x00, 0x0137); mdelay(1); /* switch to reg16-reg30, and HSSI disable 137 */
412 mdelay(10); /* Deay 10 ms. */ /* 0xfd */
414 RF_WriteReg(dev, 0x0d, 0x0008); mdelay(1); /* Z4 synthesizer loop filter setting, 392 */
415 mdelay(10); /* Deay 10 ms. */ /* 0xfd */
417 RF_WriteReg(dev, 0x00, 0x0037); mdelay(1); /* switch to reg0-reg15, and HSSI disable */
418 mdelay(10); /* Deay 10 ms. */ /* 0xfd */
420 RF_WriteReg(dev, 0x04, 0x0160); mdelay(1); /* CBC on, Tx Rx disable, High gain */
421 mdelay(10); /* Deay 10 ms. */ /* 0xfd */
423 RF_WriteReg(dev, 0x07, 0x0080); mdelay(1); /* Z4 setted channel 1 */
424 mdelay(10); /* Deay 10 ms. */ /* 0xfd */
426 RF_WriteReg(dev, 0x02, 0x088D); mdelay(1); /* LC calibration */
427 mdelay(200); /* Deay 200 ms. */ /* 0xfd */
428 mdelay(10); /* Deay 10 ms. */ /* 0xfd */
429 mdelay(10); /* Deay 10 ms. */ /* 0xfd */
431 RF_WriteReg(dev, 0x00, 0x0137); mdelay(1); /* switch to reg16-reg30 137, and HSSI disable 137 */
432 mdelay(10); /* Deay 10 ms. */ /* 0xfd */
434 RF_WriteReg(dev, 0x07, 0x0000); mdelay(1);
435 RF_WriteReg(dev, 0x07, 0x0180); mdelay(1);
436 RF_WriteReg(dev, 0x07, 0x0220); mdelay(1);
437 RF_WriteReg(dev, 0x07, 0x03E0); mdelay(1);
439 /* DAC calibration off 20070702 */
440 RF_WriteReg(dev, 0x06, 0x00c1); mdelay(1);
441 RF_WriteReg(dev, 0x0a, 0x0001); mdelay(1);
442 /* For crystal calibration, added by Roger, 2007.12.11. */
443 if (priv->bXtalCalibration) { /* reg 30. */
445 * enable crystal calibration.
446 * RF Reg[30], (1)Xin:[12:9], Xout:[8:5], addr[4:0].
447 * (2)PA Pwr delay timer[15:14], default: 2.4us, set BIT15=0
448 * (3)RF signal on/off when calibration[13], default: on, set BIT13=0.
449 * So we should minus 4 BITs offset.
451 RF_WriteReg(dev, 0x0f, (priv->XtalCal_Xin<<5) | (priv->XtalCal_Xout<<1) | BIT11 | BIT9); mdelay(1);
452 printk("ZEBRA_Config_85BASIC_HardCode(): (%02x)\n",
453 (priv->XtalCal_Xin<<5) | (priv->XtalCal_Xout<<1) | BIT11 | BIT9);
455 /* using default value. Xin=6, Xout=6. */
456 RF_WriteReg(dev, 0x0f, 0x0acc); mdelay(1);
459 RF_WriteReg(dev, 0x00, 0x00bf); mdelay(1); /* switch to reg0-reg15, and HSSI enable */
460 RF_WriteReg(dev, 0x0d, 0x08df); mdelay(1); /* Rx BB start calibration, 00c//+edward */
461 RF_WriteReg(dev, 0x02, 0x004d); mdelay(1); /* temperature meter off */
462 RF_WriteReg(dev, 0x04, 0x0975); mdelay(1); /* Rx mode */
463 mdelay(10); /* Deay 10 ms.*/ /* 0xfe */
464 mdelay(10); /* Deay 10 ms.*/ /* 0xfe */
465 mdelay(10); /* Deay 10 ms.*/ /* 0xfe */
466 RF_WriteReg(dev, 0x00, 0x0197); mdelay(1); /* Rx mode*/ /*+edward */
467 RF_WriteReg(dev, 0x05, 0x05ab); mdelay(1); /* Rx mode*/ /*+edward */
468 RF_WriteReg(dev, 0x00, 0x009f); mdelay(1); /* Rx mode*/ /*+edward */
469 RF_WriteReg(dev, 0x01, 0x0000); mdelay(1); /* Rx mode*/ /*+edward */
470 RF_WriteReg(dev, 0x02, 0x0000); mdelay(1); /* Rx mode*/ /*+edward */
471 /* power save parameters. */
472 u1b24E = read_nic_byte(dev, 0x24E);
473 write_nic_byte(dev, 0x24E, (u1b24E & (~(BIT5|BIT6))));
475 /*=============================================================================
477 *===========================================================================
479 *===========================================================================
481 * [POWER SAVE] Power Saving Parameters by jong. 2007-11-27
482 * CCK reg0x00[7]=1'b1 :power saving for TX (default)
483 * CCK reg0x00[6]=1'b1: power saving for RX (default)
484 * CCK reg0x06[4]=1'b1: turn off channel estimation related circuits if not doing channel estimation.
485 * CCK reg0x06[3]=1'b1: turn off unused circuits before cca = 1
486 * CCK reg0x06[2]=1'b1: turn off cck's circuit if macrst =0
489 write_phy_cck(dev, 0x00, 0xc8);
490 write_phy_cck(dev, 0x06, 0x1c);
491 write_phy_cck(dev, 0x10, 0x78);
492 write_phy_cck(dev, 0x2e, 0xd0);
493 write_phy_cck(dev, 0x2f, 0x06);
494 write_phy_cck(dev, 0x01, 0x46);
497 write_nic_byte(dev, CCK_TXAGC, 0x10);
498 write_nic_byte(dev, OFDM_TXAGC, 0x1B);
499 write_nic_byte(dev, ANTSEL, 0x03);
504 *===========================================================================
506 *===========================================================================
509 write_phy_ofdm(dev, 0x00, 0x12);
511 for (i = 0; i < 128; i++) {
513 data = ZEBRA_AGC[i+1];
515 data = data | 0x0000008F;
517 addr = i + 0x80; /* enable writing AGC table */
519 addr = addr | 0x0000008E;
521 WriteBBPortUchar(dev, data);
522 WriteBBPortUchar(dev, addr);
523 WriteBBPortUchar(dev, 0x0000008E);
526 PlatformIOWrite4Byte(dev, PhyAddr, 0x00001080); /* Annie, 2006-05-05 */
529 *===========================================================================
531 *===========================================================================
533 *===========================================================================
536 for (i = 0; i < 60; i++) {
538 u4bRegValue = OFDM_CONFIG[i];
540 WriteBBPortUchar(dev,
542 (u4bRegOffset & 0x7f) |
543 ((u4bRegValue & 0xff) << 8)));
547 *===========================================================================
549 *===========================================================================
551 /* Config Sw/Hw Combinational Antenna Diversity. Added by Roger, 2008.02.26. */
552 SetAntennaConfig87SE(dev, priv->bDefaultAntenna1, priv->bSwAntennaDiverity);
556 void UpdateInitialGain(struct net_device *dev)
558 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
561 if (priv->eRFPowerState != eRfOn) {
562 /* Don't access BB/RF under disable PLL situation.
563 * RT_TRACE(COMP_DIG, DBG_LOUD, ("UpdateInitialGain - pHalData->eRFPowerState!=eRfOn\n"));
564 * Back to the original state
566 priv->InitialGain = priv->InitialGainBackUp;
570 switch (priv->InitialGain) {
571 case 1: /* m861dBm */
572 write_phy_ofdm(dev, 0x17, 0x26); mdelay(1);
573 write_phy_ofdm(dev, 0x24, 0x86); mdelay(1);
574 write_phy_ofdm(dev, 0x05, 0xfa); mdelay(1);
577 case 2: /* m862dBm */
578 write_phy_ofdm(dev, 0x17, 0x36); mdelay(1);
579 write_phy_ofdm(dev, 0x24, 0x86); mdelay(1);
580 write_phy_ofdm(dev, 0x05, 0xfa); mdelay(1);
583 case 3: /* m863dBm */
584 write_phy_ofdm(dev, 0x17, 0x36); mdelay(1);
585 write_phy_ofdm(dev, 0x24, 0x86); mdelay(1);
586 write_phy_ofdm(dev, 0x05, 0xfb); mdelay(1);
589 case 4: /* m864dBm */
590 write_phy_ofdm(dev, 0x17, 0x46); mdelay(1);
591 write_phy_ofdm(dev, 0x24, 0x86); mdelay(1);
592 write_phy_ofdm(dev, 0x05, 0xfb); mdelay(1);
596 write_phy_ofdm(dev, 0x17, 0x46); mdelay(1);
597 write_phy_ofdm(dev, 0x24, 0x96); mdelay(1);
598 write_phy_ofdm(dev, 0x05, 0xfb); mdelay(1);
602 write_phy_ofdm(dev, 0x17, 0x56); mdelay(1);
603 write_phy_ofdm(dev, 0x24, 0x96); mdelay(1);
604 write_phy_ofdm(dev, 0x05, 0xfc); mdelay(1);
608 write_phy_ofdm(dev, 0x17, 0x56); mdelay(1);
609 write_phy_ofdm(dev, 0x24, 0xa6); mdelay(1);
610 write_phy_ofdm(dev, 0x05, 0xfc); mdelay(1);
614 write_phy_ofdm(dev, 0x17, 0x66); mdelay(1);
615 write_phy_ofdm(dev, 0x24, 0xb6); mdelay(1);
616 write_phy_ofdm(dev, 0x05, 0xfc); mdelay(1);
620 write_phy_ofdm(dev, 0x17, 0x26); mdelay(1);
621 write_phy_ofdm(dev, 0x24, 0x86); mdelay(1);
622 write_phy_ofdm(dev, 0x05, 0xfa); mdelay(1);
628 * Tx Power tracking mechanism routine on 87SE.
629 * Created by Roger, 2007.12.11.
631 static void InitTxPwrTracking87SE(struct net_device *dev)
635 u4bRfReg = RF_ReadReg(dev, 0x02);
637 /* Enable Thermal meter indication. */
638 RF_WriteReg(dev, 0x02, u4bRfReg|PWR_METER_EN); mdelay(1);
641 static void PhyConfig8185(struct net_device *dev)
643 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
644 write_nic_dword(dev, RCR, priv->ReceiveConfig);
645 priv->RFProgType = read_nic_byte(dev, CONFIG4) & 0x03;
647 ZEBRA_Config_85BASIC_HardCode(dev);
648 /* Set default initial gain state to 4, approved by SD3 DZ, by Bruce, 2007-06-06. */
649 if (priv->bDigMechanism) {
650 if (priv->InitialGain == 0)
651 priv->InitialGain = 4;
655 * Enable thermal meter indication to implement TxPower tracking on 87SE.
656 * We initialize thermal meter here to avoid unsuccessful configuration.
657 * Added by Roger, 2007.12.11.
659 if (priv->bTxPowerTrack)
660 InitTxPwrTracking87SE(dev);
662 priv->InitialGainBackUp = priv->InitialGain;
663 UpdateInitialGain(dev);
668 static void HwConfigureRTL8185(struct net_device *dev)
670 /* RTL8185_TODO: Determine Retrylimit, TxAGC, AutoRateFallback control. */
671 u8 bUNIVERSAL_CONTROL_RL = 0;
672 u8 bUNIVERSAL_CONTROL_AGC = 1;
673 u8 bUNIVERSAL_CONTROL_ANT = 1;
674 u8 bAUTO_RATE_FALLBACK_CTL = 1;
676 write_nic_word(dev, BRSR, 0x0fff);
678 val8 = read_nic_byte(dev, CW_CONF);
680 if (bUNIVERSAL_CONTROL_RL)
685 write_nic_byte(dev, CW_CONF, val8);
688 val8 = read_nic_byte(dev, TXAGC_CTL);
689 if (bUNIVERSAL_CONTROL_AGC) {
690 write_nic_byte(dev, CCK_TXAGC, 128);
691 write_nic_byte(dev, OFDM_TXAGC, 128);
698 write_nic_byte(dev, TXAGC_CTL, val8);
700 /* Tx Antenna including Feedback control */
701 val8 = read_nic_byte(dev, TXAGC_CTL);
703 if (bUNIVERSAL_CONTROL_ANT) {
704 write_nic_byte(dev, ANTSEL, 0x00);
707 val8 = val8 & (val8|0x02); /* xiong-2006-11-15 */
710 write_nic_byte(dev, TXAGC_CTL, val8);
712 /* Auto Rate fallback control */
713 val8 = read_nic_byte(dev, RATE_FALLBACK);
715 if (bAUTO_RATE_FALLBACK_CTL) {
716 val8 |= RATE_FALLBACK_CTL_ENABLE | RATE_FALLBACK_CTL_AUTO_STEP1;
718 /* <RJ_TODO_8185B> We shall set up the ARFR according to user's setting. */
719 PlatformIOWrite2Byte(dev, ARFR, 0x0fff); /* set 1M ~ 54Mbps. */
721 write_nic_byte(dev, RATE_FALLBACK, val8);
724 static void MacConfig_85BASIC_HardCode(struct net_device *dev)
727 *==========================================================================
729 *==========================================================================
732 u32 u4bRegOffset, u4bRegValue, u4bPageIndex = 0;
735 nLinesRead = sizeof(MAC_REG_TABLE)/2;
737 for (i = 0; i < nLinesRead; i++) { /* nLinesRead=101 */
738 u4bRegOffset = MAC_REG_TABLE[i][0];
739 u4bRegValue = MAC_REG_TABLE[i][1];
741 if (u4bRegOffset == 0x5e)
742 u4bPageIndex = u4bRegValue;
744 u4bRegOffset |= (u4bPageIndex << 8);
746 write_nic_byte(dev, u4bRegOffset, (u8)u4bRegValue);
748 /* ============================================================================ */
751 static void MacConfig_85BASIC(struct net_device *dev)
755 MacConfig_85BASIC_HardCode(dev);
757 /* ============================================================================ */
759 /* Follow TID_AC_MAP of WMac. */
760 write_nic_word(dev, TID_AC_MAP, 0xfa50);
762 /* Interrupt Migration, Jong suggested we use set 0x0000 first, 2005.12.14, by rcnjko. */
763 write_nic_word(dev, IntMig, 0x0000);
765 /* Prevent TPC to cause CRC error. Added by Annie, 2006-06-10. */
766 PlatformIOWrite4Byte(dev, 0x1F0, 0x00000000);
767 PlatformIOWrite4Byte(dev, 0x1F4, 0x00000000);
768 PlatformIOWrite1Byte(dev, 0x1F8, 0x00);
770 /* Asked for by SD3 CM Lin, 2006.06.27, by rcnjko. */
771 /* power save parameter based on "87SE power save parameters 20071127.doc", as follow. */
773 /* Enable DA10 TX power saving */
774 u1DA = read_nic_byte(dev, PHYPR);
775 write_nic_byte(dev, PHYPR, (u1DA | BIT2));
778 write_nic_word(dev, 0x360, 0x1000);
779 write_nic_word(dev, 0x362, 0x1000);
782 write_nic_word(dev, 0x370, 0x0560);
783 write_nic_word(dev, 0x372, 0x0560);
784 write_nic_word(dev, 0x374, 0x0DA4);
785 write_nic_word(dev, 0x376, 0x0DA4);
786 write_nic_word(dev, 0x378, 0x0560);
787 write_nic_word(dev, 0x37A, 0x0560);
788 write_nic_word(dev, 0x37C, 0x00EC);
789 write_nic_word(dev, 0x37E, 0x00EC); /* +edward */
790 write_nic_byte(dev, 0x24E, 0x01);
793 static u8 GetSupportedWirelessMode8185(struct net_device *dev)
795 return WIRELESS_MODE_B | WIRELESS_MODE_G;
798 static void ActUpdateChannelAccessSetting(struct net_device *dev,
799 WIRELESS_MODE WirelessMode,
800 PCHANNEL_ACCESS_SETTING ChnlAccessSetting)
806 * TODO: We still don't know how to set up these registers, just follow WMAC to
810 * Jong said CWmin/CWmax register are not functional in 8185B,
811 * so we shall fill channel access realted register into AC parameter registers,
814 ChnlAccessSetting->SIFS_Timer = 0x22; /* Suggested by Jong, 2005.12.08. */
815 ChnlAccessSetting->DIFS_Timer = 0x1C; /* 2006.06.02, by rcnjko. */
816 ChnlAccessSetting->SlotTimeTimer = 9; /* 2006.06.02, by rcnjko. */
817 ChnlAccessSetting->EIFS_Timer = 0x5B; /* Suggested by wcchu, it is the default value of EIFS register, 2005.12.08. */
818 ChnlAccessSetting->CWminIndex = 3; /* 2006.06.02, by rcnjko. */
819 ChnlAccessSetting->CWmaxIndex = 7; /* 2006.06.02, by rcnjko. */
821 write_nic_byte(dev, SIFS, ChnlAccessSetting->SIFS_Timer);
822 write_nic_byte(dev, SLOT, ChnlAccessSetting->SlotTimeTimer); /* Rewrited from directly use PlatformEFIOWrite1Byte(), by Annie, 2006-03-29. */
824 write_nic_byte(dev, EIFS, ChnlAccessSetting->EIFS_Timer);
826 write_nic_byte(dev, AckTimeOutReg, 0x5B); /* <RJ_EXPR_QOS> Suggested by wcchu, it is the default value of EIFS register, 2005.12.08. */
828 for (eACI = 0; eACI < AC_MAX; eACI++) {
829 write_nic_byte(dev, ACM_CONTROL, 0);
833 static void ActSetWirelessMode8185(struct net_device *dev, u8 btWirelessMode)
835 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
836 struct ieee80211_device *ieee = priv->ieee80211;
837 u8 btSupportedWirelessMode = GetSupportedWirelessMode8185(dev);
839 if ((btWirelessMode & btSupportedWirelessMode) == 0) {
840 /* Don't switch to unsupported wireless mode, 2006.02.15, by rcnjko. */
841 DMESGW("ActSetWirelessMode8185(): WirelessMode(%d) is not supported (%d)!\n",
842 btWirelessMode, btSupportedWirelessMode);
846 /* 1. Assign wireless mode to switch if necessary. */
847 if (btWirelessMode == WIRELESS_MODE_AUTO) {
848 if ((btSupportedWirelessMode & WIRELESS_MODE_A)) {
849 btWirelessMode = WIRELESS_MODE_A;
850 } else if (btSupportedWirelessMode & WIRELESS_MODE_G) {
851 btWirelessMode = WIRELESS_MODE_G;
853 } else if ((btSupportedWirelessMode & WIRELESS_MODE_B)) {
854 btWirelessMode = WIRELESS_MODE_B;
856 DMESGW("ActSetWirelessMode8185(): No valid wireless mode supported, btSupportedWirelessMode(%x)!!!\n",
857 btSupportedWirelessMode);
858 btWirelessMode = WIRELESS_MODE_B;
863 * 2. Swtich band: RF or BB specific actions,
864 * for example, refresh tables in omc8255, or change initial gain if necessary.
865 * Nothing to do for Zebra to switch band.
866 * Update current wireless mode if we switch to specified band successfully.
869 ieee->mode = (WIRELESS_MODE)btWirelessMode;
871 /* 3. Change related setting. */
872 if (ieee->mode == WIRELESS_MODE_A)
873 DMESG("WIRELESS_MODE_A\n");
874 else if (ieee->mode == WIRELESS_MODE_B)
875 DMESG("WIRELESS_MODE_B\n");
876 else if (ieee->mode == WIRELESS_MODE_G)
877 DMESG("WIRELESS_MODE_G\n");
879 ActUpdateChannelAccessSetting( dev, ieee->mode, &priv->ChannelAccessSetting);
882 void rtl8185b_irq_enable(struct net_device *dev)
884 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
886 priv->irq_enabled = 1;
887 write_nic_dword(dev, IMR, priv->IntrMask);
890 static void MgntDisconnectIBSS(struct net_device *dev)
892 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
895 for (i = 0; i < 6 ; i++)
896 priv->ieee80211->current_network.bssid[i] = 0x55;
900 priv->ieee80211->state = IEEE80211_NOLINK;
904 * Vista add a Adhoc profile, HW radio off until OID_DOT11_RESET_REQUEST
905 * Driver would set MSR=NO_LINK, then HW Radio ON, MgntQueue Stuck.
906 * Because Bcn DMA isn't complete, mgnt queue would stuck until Bcn packet send.
908 * Disable Beacon Queue Own bit, suggested by jong
910 ieee80211_stop_send_beacons(priv->ieee80211);
912 priv->ieee80211->link_change(dev);
913 notify_wx_assoc_event(priv->ieee80211);
916 static void MlmeDisassociateRequest(struct net_device *dev, u8 *asSta, u8 asRsn)
918 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
921 SendDisassociation(priv->ieee80211, asSta, asRsn);
923 if (memcmp(priv->ieee80211->current_network.bssid, asSta, 6) == 0) {
924 /* ShuChen TODO: change media status. */
926 for (i = 0; i < 6; i++)
927 priv->ieee80211->current_network.bssid[i] = 0x22;
929 ieee80211_disassociate(priv->ieee80211);
933 static void MgntDisconnectAP(struct net_device *dev, u8 asRsn)
935 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
938 * Commented out by rcnjko, 2005.01.27:
939 * I move SecClearAllKeys() to MgntActSet_802_11_DISASSOCIATE().
941 * 2004/09/15, kcwu, the key should be cleared, or the new handshaking will not success
943 * In WPA WPA2 need to Clear all key ... because new key will set after new handshaking.
944 * 2004.10.11, by rcnjko.
946 MlmeDisassociateRequest(dev, priv->ieee80211->current_network.bssid, asRsn);
948 priv->ieee80211->state = IEEE80211_NOLINK;
951 static bool MgntDisconnect(struct net_device *dev, u8 asRsn)
953 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
955 * Schedule an workitem to wake up for ps mode, 070109, by rcnjko.
958 if (IS_DOT11D_ENABLE(priv->ieee80211))
959 Dot11d_Reset(priv->ieee80211);
960 /* In adhoc mode, update beacon frame. */
961 if (priv->ieee80211->state == IEEE80211_LINKED) {
962 if (priv->ieee80211->iw_mode == IW_MODE_ADHOC)
963 MgntDisconnectIBSS(dev);
965 if (priv->ieee80211->iw_mode == IW_MODE_INFRA) {
967 * We clear key here instead of MgntDisconnectAP() because that
968 * MgntActSet_802_11_DISASSOCIATE() is an interface called by OS,
969 * e.g. OID_802_11_DISASSOCIATE in Windows while as MgntDisconnectAP() is
970 * used to handle disassociation related things to AP, e.g. send Disassoc
971 * frame to AP. 2005.01.27, by rcnjko.
973 MgntDisconnectAP(dev, asRsn);
975 /* Indicate Disconnect, 2005.02.23, by rcnjko. */
981 * Chang RF Power State.
982 * Note that, only MgntActSet_RF_State() is allowed to set HW_VAR_RF_STATE.
987 static bool SetRFPowerState(struct net_device *dev, RT_RF_POWER_STATE eRFPowerState)
989 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
990 bool bResult = false;
992 if (eRFPowerState == priv->eRFPowerState)
995 bResult = SetZebraRFPowerState8185(dev, eRFPowerState);
1000 bool MgntActSet_RF_State(struct net_device *dev, RT_RF_POWER_STATE StateToSet, u32 ChangeSource)
1002 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1003 bool bActionAllowed = false;
1004 bool bConnectBySSID = false;
1005 RT_RF_POWER_STATE rtState;
1006 u16 RFWaitCounter = 0;
1009 * Prevent the race condition of RF state change. By Bruce, 2007-11-28.
1010 * Only one thread can change the RF state at one time, and others should wait to be executed.
1013 spin_lock_irqsave(&priv->rf_ps_lock, flag);
1014 if (priv->RFChangeInProgress) {
1015 spin_unlock_irqrestore(&priv->rf_ps_lock, flag);
1016 /* Set RF after the previous action is done. */
1017 while (priv->RFChangeInProgress) {
1019 udelay(1000); /* 1 ms */
1021 /* Wait too long, return FALSE to avoid to be stuck here. */
1022 if (RFWaitCounter > 1000) { /* 1sec */
1023 printk("MgntActSet_RF_State(): Wait too long to set RF\n");
1024 /* TODO: Reset RF state? */
1029 priv->RFChangeInProgress = true;
1030 spin_unlock_irqrestore(&priv->rf_ps_lock, flag);
1034 rtState = priv->eRFPowerState;
1036 switch (StateToSet) {
1039 * Turn On RF no matter the IPS setting because we need to update the RF state to Ndis under Vista, or
1040 * the Windows does not allow the driver to perform site survey any more. By Bruce, 2007-10-02.
1042 priv->RfOffReason &= (~ChangeSource);
1044 if (!priv->RfOffReason) {
1045 priv->RfOffReason = 0;
1046 bActionAllowed = true;
1048 if (rtState == eRfOff && ChangeSource >= RF_CHANGE_BY_HW)
1049 bConnectBySSID = true;
1054 /* 070125, rcnjko: we always keep connected in AP mode. */
1056 if (priv->RfOffReason > RF_CHANGE_BY_IPS) {
1059 * Disconnect to current BSS when radio off. Asked by QuanTa.
1061 * Calling MgntDisconnect() instead of MgntActSet_802_11_DISASSOCIATE(),
1062 * because we do NOT need to set ssid to dummy ones.
1064 MgntDisconnect(dev, disas_lv_ss);
1065 /* Clear content of bssDesc[] and bssDesc4Query[] to avoid reporting old bss to UI. */
1068 priv->RfOffReason |= ChangeSource;
1069 bActionAllowed = true;
1072 priv->RfOffReason |= ChangeSource;
1073 bActionAllowed = true;
1079 if (bActionAllowed) {
1080 /* Config HW to the specified mode. */
1081 SetRFPowerState(dev, StateToSet);
1084 /* Release RF spinlock */
1085 spin_lock_irqsave(&priv->rf_ps_lock, flag);
1086 priv->RFChangeInProgress = false;
1087 spin_unlock_irqrestore(&priv->rf_ps_lock, flag);
1088 return bActionAllowed;
1091 static void InactivePowerSave(struct net_device *dev)
1093 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1095 * This flag "bSwRfProcessing", indicates the status of IPS procedure, should be set if the IPS workitem
1096 * is really scheduled.
1097 * The old code, sets this flag before scheduling the IPS workitem and however, at the same time the
1098 * previous IPS workitem did not end yet, fails to schedule the current workitem. Thus, bSwRfProcessing
1099 * blocks the IPS procedure of switching RF.
1101 priv->bSwRfProcessing = true;
1103 MgntActSet_RF_State(dev, priv->eInactivePowerState, RF_CHANGE_BY_IPS);
1106 * To solve CAM values miss in RF OFF, rewrite CAM values after RF ON. By Bruce, 2007-09-20.
1109 priv->bSwRfProcessing = false;
1114 * Enter the inactive power save mode. RF will be off
1116 void IPSEnter(struct net_device *dev)
1118 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1119 RT_RF_POWER_STATE rtState;
1120 if (priv->bInactivePs) {
1121 rtState = priv->eRFPowerState;
1124 * Do not enter IPS in the following conditions:
1125 * (1) RF is already OFF or Sleep
1126 * (2) bSwRfProcessing (indicates the IPS is still under going)
1127 * (3) Connected (only disconnected can trigger IPS)
1128 * (4) IBSS (send Beacon)
1129 * (5) AP mode (send Beacon)
1131 if (rtState == eRfOn && !priv->bSwRfProcessing
1132 && (priv->ieee80211->state != IEEE80211_LINKED)) {
1133 priv->eInactivePowerState = eRfOff;
1134 InactivePowerSave(dev);
1138 void IPSLeave(struct net_device *dev)
1140 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1141 RT_RF_POWER_STATE rtState;
1142 if (priv->bInactivePs) {
1143 rtState = priv->eRFPowerState;
1144 if ((rtState == eRfOff || rtState == eRfSleep) && (!priv->bSwRfProcessing) && priv->RfOffReason <= RF_CHANGE_BY_IPS) {
1145 priv->eInactivePowerState = eRfOn;
1146 InactivePowerSave(dev);
1151 void rtl8185b_adapter_start(struct net_device *dev)
1153 struct r8180_priv *priv = ieee80211_priv(dev);
1154 struct ieee80211_device *ieee = priv->ieee80211;
1156 u8 SupportedWirelessMode;
1157 u8 InitWirelessMode;
1158 u8 bInvalidWirelessMode = 0;
1164 write_nic_byte(dev, 0x24e, (BIT5|BIT6|BIT0));
1167 priv->dma_poll_mask = 0;
1168 priv->dma_poll_stop_mask = 0;
1170 HwConfigureRTL8185(dev);
1171 write_nic_dword(dev, MAC0, ((u32 *)dev->dev_addr)[0]);
1172 write_nic_word(dev, MAC4, ((u32 *)dev->dev_addr)[1] & 0xffff);
1173 write_nic_byte(dev, MSR, read_nic_byte(dev, MSR) & 0xf3); /* default network type to 'No Link' */
1174 write_nic_word(dev, BcnItv, 100);
1175 write_nic_word(dev, AtimWnd, 2);
1176 PlatformIOWrite2Byte(dev, FEMR, 0xFFFF);
1177 write_nic_byte(dev, WPA_CONFIG, 0);
1178 MacConfig_85BASIC(dev);
1179 /* Override the RFSW_CTRL (MAC offset 0x272-0x273), 2006.06.07, by rcnjko. */
1180 /* BT_DEMO_BOARD type */
1181 PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x569a);
1184 *---------------------------------------------------------------------------
1185 * Set up PHY related.
1186 *---------------------------------------------------------------------------
1188 /* Enable Config3.PARAM_En to revise AnaaParm. */
1189 write_nic_byte(dev, CR9346, 0xc0); /* enable config register write */
1190 tmpu8 = read_nic_byte(dev, CONFIG3);
1191 write_nic_byte(dev, CONFIG3, (tmpu8 | CONFIG3_PARM_En));
1192 /* Turn on Analog power. */
1193 /* Asked for by William, otherwise, MAC 3-wire can't work, 2006.06.27, by rcnjko. */
1194 write_nic_dword(dev, ANAPARAM2, ANAPARM2_ASIC_ON);
1195 write_nic_dword(dev, ANAPARAM, ANAPARM_ASIC_ON);
1196 write_nic_word(dev, ANAPARAM3, 0x0010);
1198 write_nic_byte(dev, CONFIG3, tmpu8);
1199 write_nic_byte(dev, CR9346, 0x00);
1200 /* enable EEM0 and EEM1 in 9346CR */
1201 btCR9346 = read_nic_byte(dev, CR9346);
1202 write_nic_byte(dev, CR9346, (btCR9346 | 0xC0));
1204 /* B cut use LED1 to control HW RF on/off */
1205 TmpU1b = read_nic_byte(dev, CONFIG5);
1206 TmpU1b = TmpU1b & ~BIT3;
1207 write_nic_byte(dev, CONFIG5, TmpU1b);
1209 /* disable EEM0 and EEM1 in 9346CR */
1210 btCR9346 &= ~(0xC0);
1211 write_nic_byte(dev, CR9346, btCR9346);
1213 /* Enable Led (suggested by Jong) */
1214 /* B-cut RF Radio on/off 5e[3]=0 */
1215 btPSR = read_nic_byte(dev, PSR);
1216 write_nic_byte(dev, PSR, (btPSR | BIT3));
1217 /* setup initial timing for RFE. */
1218 write_nic_word(dev, RFPinsOutput, 0x0480);
1219 SetOutputEnableOfRfPins(dev);
1220 write_nic_word(dev, RFPinsSelect, 0x2488);
1226 * We assume RegWirelessMode has already been initialized before,
1227 * however, we has to validate the wireless mode here and provide a
1228 * reasonable initialized value if necessary. 2005.01.13, by rcnjko.
1230 SupportedWirelessMode = GetSupportedWirelessMode8185(dev);
1231 if ((ieee->mode != WIRELESS_MODE_B) &&
1232 (ieee->mode != WIRELESS_MODE_G) &&
1233 (ieee->mode != WIRELESS_MODE_A) &&
1234 (ieee->mode != WIRELESS_MODE_AUTO)) {
1235 /* It should be one of B, G, A, or AUTO. */
1236 bInvalidWirelessMode = 1;
1238 /* One of B, G, A, or AUTO. */
1239 /* Check if the wireless mode is supported by RF. */
1240 if ((ieee->mode != WIRELESS_MODE_AUTO) &&
1241 (ieee->mode & SupportedWirelessMode) == 0) {
1242 bInvalidWirelessMode = 1;
1246 if (bInvalidWirelessMode || ieee->mode == WIRELESS_MODE_AUTO) {
1247 /* Auto or other invalid value. */
1248 /* Assigne a wireless mode to initialize. */
1249 if ((SupportedWirelessMode & WIRELESS_MODE_A)) {
1250 InitWirelessMode = WIRELESS_MODE_A;
1251 } else if ((SupportedWirelessMode & WIRELESS_MODE_G)) {
1252 InitWirelessMode = WIRELESS_MODE_G;
1253 } else if ((SupportedWirelessMode & WIRELESS_MODE_B)) {
1254 InitWirelessMode = WIRELESS_MODE_B;
1256 DMESGW("InitializeAdapter8185(): No valid wireless mode supported, SupportedWirelessMode(%x)!!!\n",
1257 SupportedWirelessMode);
1258 InitWirelessMode = WIRELESS_MODE_B;
1261 /* Initialize RegWirelessMode if it is not a valid one. */
1262 if (bInvalidWirelessMode)
1263 ieee->mode = (WIRELESS_MODE)InitWirelessMode;
1266 /* One of B, G, A. */
1267 InitWirelessMode = ieee->mode;
1269 priv->eRFPowerState = eRfOff;
1270 priv->RfOffReason = 0;
1272 MgntActSet_RF_State(dev, eRfOn, 0);
1275 * If inactive power mode is enabled, disable rf while in disconnected state.
1277 if (priv->bInactivePs)
1278 MgntActSet_RF_State(dev , eRfOff, RF_CHANGE_BY_IPS);
1280 ActSetWirelessMode8185(dev, (u8)(InitWirelessMode));
1282 /* ----------------------------------------------------------------------------- */
1284 rtl8185b_irq_enable(dev);
1286 netif_start_queue(dev);
1289 void rtl8185b_rx_enable(struct net_device *dev)
1292 /* for now we accept data, management & ctl frame*/
1293 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1296 if (dev->flags & IFF_PROMISC)
1297 DMESG("NIC in promisc mode");
1299 if (priv->ieee80211->iw_mode == IW_MODE_MONITOR || \
1300 dev->flags & IFF_PROMISC) {
1301 priv->ReceiveConfig = priv->ReceiveConfig & (~RCR_APM);
1302 priv->ReceiveConfig = priv->ReceiveConfig | RCR_AAP;
1305 if (priv->ieee80211->iw_mode == IW_MODE_MONITOR)
1306 priv->ReceiveConfig = priv->ReceiveConfig | RCR_ACF | RCR_APWRMGT | RCR_AICV;
1309 if (priv->crcmon == 1 && priv->ieee80211->iw_mode == IW_MODE_MONITOR)
1310 priv->ReceiveConfig = priv->ReceiveConfig | RCR_ACRC32;
1312 write_nic_dword(dev, RCR, priv->ReceiveConfig);
1316 cmd = read_nic_byte(dev, CMD);
1317 write_nic_byte(dev, CMD, cmd | (1<<CMD_RX_ENABLE_SHIFT));
1321 void rtl8185b_tx_enable(struct net_device *dev)
1325 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1327 write_nic_dword(dev, TCR, priv->TransmitConfig);
1328 byte = read_nic_byte(dev, MSR);
1329 byte |= MSR_LINK_ENEDCA;
1330 write_nic_byte(dev, MSR, byte);
1334 cmd = read_nic_byte(dev, CMD);
1335 write_nic_byte(dev, CMD, cmd | (1<<CMD_TX_ENABLE_SHIFT));