1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 ******************************************************************************/
21 #include "odm_precomp.h"
25 #define read_next_pair(array, v1, v2, i) \
32 static bool CheckCondition(const u32 condition, const u32 hex)
34 u32 _board = (hex & 0x000000FF);
35 u32 _interface = (hex & 0x0000FF00) >> 8;
36 u32 _platform = (hex & 0x00FF0000) >> 16;
39 if (condition == 0xCDCDCDCD)
42 cond = condition & 0x000000FF;
43 if ((_board == cond) && cond != 0x00)
46 cond = condition & 0x0000FF00;
48 if ((_interface & cond) == 0 && cond != 0x07)
51 cond = condition & 0x00FF0000;
53 if ((_platform & cond) == 0 && cond != 0x0F)
59 /******************************************************************************
61 ******************************************************************************/
63 static u32 array_agc_tab_1t_8188e[] = {
194 enum HAL_STATUS ODM_ReadAndConfig_AGC_TAB_1T_8188E(struct odm_dm_struct *dm_odm)
198 u8 platform = dm_odm->SupportPlatform;
199 u8 interfaceValue = dm_odm->SupportInterface;
200 u8 board = dm_odm->BoardType;
201 u32 arraylen = sizeof(array_agc_tab_1t_8188e)/sizeof(u32);
202 u32 *array = array_agc_tab_1t_8188e;
204 struct adapter *adapter = dm_odm->Adapter;
205 struct xmit_frame *pxmit_frame = NULL;
207 enum HAL_STATUS rst = HAL_STATUS_SUCCESS;
210 hex += interfaceValue << 8;
211 hex += platform << 16;
213 biol = rtw_IOL_applied(adapter);
216 pxmit_frame = rtw_IOL_accquire_xmit_frame(adapter);
217 if (pxmit_frame == NULL) {
218 pr_info("rtw_IOL_accquire_xmit_frame failed\n");
219 return HAL_STATUS_FAILURE;
223 for (i = 0; i < arraylen; i += 2) {
227 /* This (offset, data) pair meets the condition. */
228 if (v1 < 0xCDCDCDCD) {
230 if (rtw_IOL_cmd_boundary_handle(pxmit_frame))
232 rtw_IOL_append_WD_cmd(pxmit_frame, (u16)v1, v2, bMaskDWord);
234 odm_ConfigBB_AGC_8188E(dm_odm, v1, bMaskDWord, v2);
238 /* This line is the start line of branch. */
239 if (!CheckCondition(array[i], hex)) {
240 /* Discard the following (offset, data) pairs. */
241 read_next_pair(array, v1, v2, i);
242 while (v2 != 0xDEAD &&
244 v2 != 0xCDCD && i < arraylen - 2)
245 read_next_pair(array, v1, v2, i);
246 i -= 2; /* prevent from for-loop += 2 */
247 } else { /* Configure matched pairs and skip to end of if-else. */
248 read_next_pair(array, v1, v2, i);
249 while (v2 != 0xDEAD &&
251 v2 != 0xCDCD && i < arraylen - 2) {
253 if (rtw_IOL_cmd_boundary_handle(pxmit_frame))
255 rtw_IOL_append_WD_cmd(pxmit_frame, (u16)v1, v2, bMaskDWord);
257 odm_ConfigBB_AGC_8188E(dm_odm, v1, bMaskDWord, v2);
259 read_next_pair(array, v1, v2, i);
262 while (v2 != 0xDEAD && i < arraylen - 2)
263 read_next_pair(array, v1, v2, i);
268 if (!rtw_IOL_exec_cmds_sync(dm_odm->Adapter, pxmit_frame, 1000, bndy_cnt)) {
269 printk("~~~ %s IOL_exec_cmds Failed !!!\n", __func__);
270 rst = HAL_STATUS_FAILURE;
276 /******************************************************************************
278 ******************************************************************************/
280 static u32 array_phy_reg_1t_8188e[] = {
474 enum HAL_STATUS ODM_ReadAndConfig_PHY_REG_1T_8188E(struct odm_dm_struct *dm_odm)
478 u8 platform = dm_odm->SupportPlatform;
479 u8 interfaceValue = dm_odm->SupportInterface;
480 u8 board = dm_odm->BoardType;
481 u32 arraylen = sizeof(array_phy_reg_1t_8188e)/sizeof(u32);
482 u32 *array = array_phy_reg_1t_8188e;
484 struct adapter *adapter = dm_odm->Adapter;
485 struct xmit_frame *pxmit_frame = NULL;
487 enum HAL_STATUS rst = HAL_STATUS_SUCCESS;
489 hex += interfaceValue << 8;
490 hex += platform << 16;
492 biol = rtw_IOL_applied(adapter);
495 pxmit_frame = rtw_IOL_accquire_xmit_frame(adapter);
496 if (pxmit_frame == NULL) {
497 pr_info("rtw_IOL_accquire_xmit_frame failed\n");
498 return HAL_STATUS_FAILURE;
502 for (i = 0; i < arraylen; i += 2) {
506 /* This (offset, data) pair meets the condition. */
507 if (v1 < 0xCDCDCDCD) {
509 if (rtw_IOL_cmd_boundary_handle(pxmit_frame))
512 rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 50);
513 } else if (v1 == 0xfd) {
514 rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 5);
515 } else if (v1 == 0xfc) {
516 rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 1);
517 } else if (v1 == 0xfb) {
518 rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 50);
519 } else if (v1 == 0xfa) {
520 rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 5);
521 } else if (v1 == 0xf9) {
522 rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 1);
525 dm_odm->RFCalibrateInfo.RegA24 = v2;
526 rtw_IOL_append_WD_cmd(pxmit_frame, (u16)v1, v2, bMaskDWord);
529 odm_ConfigBB_PHY_8188E(dm_odm, v1, bMaskDWord, v2);
532 } else { /* This line is the start line of branch. */
533 if (!CheckCondition(array[i], hex)) {
534 /* Discard the following (offset, data) pairs. */
535 read_next_pair(array, v1, v2, i);
536 while (v2 != 0xDEAD &&
538 v2 != 0xCDCD && i < arraylen - 2)
539 read_next_pair(array, v1, v2, i);
540 i -= 2; /* prevent from for-loop += 2 */
541 } else { /* Configure matched pairs and skip to end of if-else. */
542 read_next_pair(array, v1, v2, i);
543 while (v2 != 0xDEAD &&
545 v2 != 0xCDCD && i < arraylen - 2) {
547 if (rtw_IOL_cmd_boundary_handle(pxmit_frame))
550 rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 50);
551 } else if (v1 == 0xfd) {
552 rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 5);
553 } else if (v1 == 0xfc) {
554 rtw_IOL_append_DELAY_MS_cmd(pxmit_frame, 1);
555 } else if (v1 == 0xfb) {
556 rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 50);
557 } else if (v1 == 0xfa) {
558 rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 5);
559 } else if (v1 == 0xf9) {
560 rtw_IOL_append_DELAY_US_cmd(pxmit_frame, 1);
563 dm_odm->RFCalibrateInfo.RegA24 = v2;
565 rtw_IOL_append_WD_cmd(pxmit_frame, (u16)v1, v2, bMaskDWord);
568 odm_ConfigBB_PHY_8188E(dm_odm, v1, bMaskDWord, v2);
570 read_next_pair(array, v1, v2, i);
573 while (v2 != 0xDEAD && i < arraylen - 2)
574 read_next_pair(array, v1, v2, i);
579 if (!rtw_IOL_exec_cmds_sync(dm_odm->Adapter, pxmit_frame, 1000, bndy_cnt)) {
580 rst = HAL_STATUS_FAILURE;
581 pr_info("~~~ IOL Config %s Failed !!!\n", __func__);
587 /******************************************************************************
589 ******************************************************************************/
591 static u32 array_phy_reg_pg_8188e[] = {
592 0xE00, 0xFFFFFFFF, 0x06070809,
593 0xE04, 0xFFFFFFFF, 0x02020405,
594 0xE08, 0x0000FF00, 0x00000006,
595 0x86C, 0xFFFFFF00, 0x00020400,
596 0xE10, 0xFFFFFFFF, 0x08090A0B,
597 0xE14, 0xFFFFFFFF, 0x01030607,
598 0xE18, 0xFFFFFFFF, 0x08090A0B,
599 0xE1C, 0xFFFFFFFF, 0x01030607,
600 0xE00, 0xFFFFFFFF, 0x00000000,
601 0xE04, 0xFFFFFFFF, 0x00000000,
602 0xE08, 0x0000FF00, 0x00000000,
603 0x86C, 0xFFFFFF00, 0x00000000,
604 0xE10, 0xFFFFFFFF, 0x00000000,
605 0xE14, 0xFFFFFFFF, 0x00000000,
606 0xE18, 0xFFFFFFFF, 0x00000000,
607 0xE1C, 0xFFFFFFFF, 0x00000000,
608 0xE00, 0xFFFFFFFF, 0x02020202,
609 0xE04, 0xFFFFFFFF, 0x00020202,
610 0xE08, 0x0000FF00, 0x00000000,
611 0x86C, 0xFFFFFF00, 0x00000000,
612 0xE10, 0xFFFFFFFF, 0x04040404,
613 0xE14, 0xFFFFFFFF, 0x00020404,
614 0xE18, 0xFFFFFFFF, 0x00000000,
615 0xE1C, 0xFFFFFFFF, 0x00000000,
616 0xE00, 0xFFFFFFFF, 0x02020202,
617 0xE04, 0xFFFFFFFF, 0x00020202,
618 0xE08, 0x0000FF00, 0x00000000,
619 0x86C, 0xFFFFFF00, 0x00000000,
620 0xE10, 0xFFFFFFFF, 0x04040404,
621 0xE14, 0xFFFFFFFF, 0x00020404,
622 0xE18, 0xFFFFFFFF, 0x00000000,
623 0xE1C, 0xFFFFFFFF, 0x00000000,
624 0xE00, 0xFFFFFFFF, 0x00000000,
625 0xE04, 0xFFFFFFFF, 0x00000000,
626 0xE08, 0x0000FF00, 0x00000000,
627 0x86C, 0xFFFFFF00, 0x00000000,
628 0xE10, 0xFFFFFFFF, 0x00000000,
629 0xE14, 0xFFFFFFFF, 0x00000000,
630 0xE18, 0xFFFFFFFF, 0x00000000,
631 0xE1C, 0xFFFFFFFF, 0x00000000,
632 0xE00, 0xFFFFFFFF, 0x02020202,
633 0xE04, 0xFFFFFFFF, 0x00020202,
634 0xE08, 0x0000FF00, 0x00000000,
635 0x86C, 0xFFFFFF00, 0x00000000,
636 0xE10, 0xFFFFFFFF, 0x04040404,
637 0xE14, 0xFFFFFFFF, 0x00020404,
638 0xE18, 0xFFFFFFFF, 0x00000000,
639 0xE1C, 0xFFFFFFFF, 0x00000000,
640 0xE00, 0xFFFFFFFF, 0x00000000,
641 0xE04, 0xFFFFFFFF, 0x00000000,
642 0xE08, 0x0000FF00, 0x00000000,
643 0x86C, 0xFFFFFF00, 0x00000000,
644 0xE10, 0xFFFFFFFF, 0x00000000,
645 0xE14, 0xFFFFFFFF, 0x00000000,
646 0xE18, 0xFFFFFFFF, 0x00000000,
647 0xE1C, 0xFFFFFFFF, 0x00000000,
648 0xE00, 0xFFFFFFFF, 0x00000000,
649 0xE04, 0xFFFFFFFF, 0x00000000,
650 0xE08, 0x0000FF00, 0x00000000,
651 0x86C, 0xFFFFFF00, 0x00000000,
652 0xE10, 0xFFFFFFFF, 0x00000000,
653 0xE14, 0xFFFFFFFF, 0x00000000,
654 0xE18, 0xFFFFFFFF, 0x00000000,
655 0xE1C, 0xFFFFFFFF, 0x00000000,
656 0xE00, 0xFFFFFFFF, 0x00000000,
657 0xE04, 0xFFFFFFFF, 0x00000000,
658 0xE08, 0x0000FF00, 0x00000000,
659 0x86C, 0xFFFFFF00, 0x00000000,
660 0xE10, 0xFFFFFFFF, 0x00000000,
661 0xE14, 0xFFFFFFFF, 0x00000000,
662 0xE18, 0xFFFFFFFF, 0x00000000,
663 0xE1C, 0xFFFFFFFF, 0x00000000,
664 0xE00, 0xFFFFFFFF, 0x00000000,
665 0xE04, 0xFFFFFFFF, 0x00000000,
666 0xE08, 0x0000FF00, 0x00000000,
667 0x86C, 0xFFFFFF00, 0x00000000,
668 0xE10, 0xFFFFFFFF, 0x00000000,
669 0xE14, 0xFFFFFFFF, 0x00000000,
670 0xE18, 0xFFFFFFFF, 0x00000000,
671 0xE1C, 0xFFFFFFFF, 0x00000000,
672 0xE00, 0xFFFFFFFF, 0x00000000,
673 0xE04, 0xFFFFFFFF, 0x00000000,
674 0xE08, 0x0000FF00, 0x00000000,
675 0x86C, 0xFFFFFF00, 0x00000000,
676 0xE10, 0xFFFFFFFF, 0x00000000,
677 0xE14, 0xFFFFFFFF, 0x00000000,
678 0xE18, 0xFFFFFFFF, 0x00000000,
679 0xE1C, 0xFFFFFFFF, 0x00000000,
683 void ODM_ReadAndConfig_PHY_REG_PG_8188E(struct odm_dm_struct *dm_odm)
687 u8 platform = dm_odm->SupportPlatform;
688 u8 interfaceValue = dm_odm->SupportInterface;
689 u8 board = dm_odm->BoardType;
690 u32 arraylen = sizeof(array_phy_reg_pg_8188e) / sizeof(u32);
691 u32 *array = array_phy_reg_pg_8188e;
693 hex = board + (interfaceValue << 8);
694 hex += (platform << 16) + 0xFF000000;
696 for (i = 0; i < arraylen; i += 3) {
701 /* this line is a line of pure_body */
702 if (v1 < 0xCDCDCDCD) {
703 odm_ConfigBB_PHY_REG_PG_8188E(dm_odm, v1, v2, v3);
705 } else { /* this line is the start of branch */
706 if (!CheckCondition(array[i], hex)) {
707 /* don't need the hw_body */
708 i += 2; /* skip the pair of expression */
712 while (v2 != 0xDEAD) {