1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 ******************************************************************************/
22 #ifndef __HALDMOUTSRC_H__
23 #define __HALDMOUTSRC_H__
26 /* Define all team support ability. */
28 /* Define for all teams. Please Define the constant in your precomp header. */
30 /* define DM_ODM_SUPPORT_AP 0 */
31 /* define DM_ODM_SUPPORT_ADSL 0 */
32 /* define DM_ODM_SUPPORT_CE 0 */
33 /* define DM_ODM_SUPPORT_MP 1 */
35 /* Define ODM SW team support flag. */
37 /* Antenna Switch Relative Definition. */
39 /* Add new function SwAntDivCheck8192C(). */
40 /* This is the main function of Antenna diversity function before link. */
41 /* Mainly, it just retains last scan result and scan again. */
42 /* After that, it compares the scan result to see which one gets better
43 * RSSI. It selects antenna with better receiving power and returns better
49 #define TRAFFIC_HIGH 1
51 /* 3 Tx Power Tracking */
52 /* 3============================================================ */
53 #define DPK_DELTA_MAPPING_NUM 13
54 #define index_mapping_HP_NUM 15
59 /* 3============================================================ */
61 #define AFH_PSD 1 /* 0:normal PSD scan, 1: only do 20 pts PSD */
62 #define MODE_40M 0 /* 0:20M, 1:40M */
64 #define PSD_CHM 20 /* Minimum channel number for BT AFH */
65 #define SIR_STEP_SIZE 3
66 #define Smooth_Size_1 5
68 #define Smooth_Size_2 10
70 #define Smooth_Size_3 20
72 #define Smooth_Step_Size 5
73 #define Adaptive_SIR 1
75 #define PSD_SCAN_INTERVAL 700 /* ms */
77 /* 8723A High Power IGI Setting */
78 #define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22
79 #define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28
80 #define DM_DIG_HIGH_PWR_THRESHOLD 0x3a
83 #define DM_DIG_FA_TH0_LPS 4 /* 4 in lps */
84 #define DM_DIG_FA_TH1_LPS 15 /* 15 lps */
85 #define DM_DIG_FA_TH2_LPS 30 /* 30 lps */
86 #define RSSI_OFFSET_DIG 0x05;
89 #define ANTTESTALL 0x00 /* Ant A or B will be Testing */
90 #define ANTTESTA 0x01 /* Ant A will be Testing */
91 #define ANTTESTB 0x02 /* Ant B will be testing */
93 /* structure and define */
95 /* Add for AP/ADSLpseudo DM structuer requirement. */
96 /* We need to remove to other position??? */
97 struct rtl8192cd_priv {
103 u8 Dig_Ext_Port_Stage;
111 u8 CurSTAConnectState;
112 u8 PreSTAConnectState;
113 u8 CurMultiSTAConnectState;
120 s8 BackoffVal_range_max;
121 s8 BackoffVal_range_min;
122 u8 rx_gain_range_max;
123 u8 rx_gain_range_min;
135 u8 DIG_Dynamic_MIN_0;
136 u8 DIG_Dynamic_MIN_1;
137 bool bMediaConnect_0;
138 bool bMediaConnect_1;
154 u32 Reg874,RegC70,Reg85C,RegA74;
158 struct false_alarm_stats {
160 u32 Cnt_Rate_Illegal;
167 u32 Cnt_SB_Search_fail;
171 u32 Cnt_BW_USC; /* Gary */
172 u32 Cnt_BW_LSC; /* Gary */
175 struct dyn_primary_cca {
186 u8 PSD_bitmap_RXHP[80];
191 bool First_time_enter;
194 struct timer_list PSDTimer;
197 #define ASSOCIATE_ENTRY_NUM 32 /* Max size of AsocEntry[]. */
198 #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM
200 /* This indicates two different steps. */
201 /* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to
202 * the signal on the air. */
203 /* In SWAW_STEP_DETERMINE, driver just compares the signal captured in
204 * SWAW_STEP_PEAK with original RSSI to determine if it is necessary to
207 #define SWAW_STEP_PEAK 0
208 #define SWAW_STEP_DETERMINE 1
212 #define TRAFFIC_LOW 0
213 #define TRAFFIC_HIGH 1
215 struct sw_ant_switch {
222 u8 bTriggerAntennaSwitch;
226 /* Before link Antenna Switch check */
227 u8 SWAS_NoLink_State;
228 u32 SWAS_NoLink_BK_Reg860;
229 bool ANTA_ON; /* To indicate Ant A is or not */
230 bool ANTB_ON; /* To indicate Ant B is on or not */
243 struct timer_list SwAntennaSwitchTimer;
244 /* Hybrid Antenna Diversity */
245 u32 CCK_Ant1_Cnt[ASSOCIATE_ENTRY_NUM];
246 u32 CCK_Ant2_Cnt[ASSOCIATE_ENTRY_NUM];
247 u32 OFDM_Ant1_Cnt[ASSOCIATE_ENTRY_NUM];
248 u32 OFDM_Ant2_Cnt[ASSOCIATE_ENTRY_NUM];
249 u32 RSSI_Ant1_Sum[ASSOCIATE_ENTRY_NUM];
250 u32 RSSI_Ant2_Sum[ASSOCIATE_ENTRY_NUM];
251 u8 TxAnt[ASSOCIATE_ENTRY_NUM];
258 bool bCurrentTurboEDCA;
260 u32 prv_traffic_idx; /* edca turbo */
263 struct odm_rate_adapt {
264 u8 Type; /* DM_Type_ByFW/DM_Type_ByDriver */
265 u8 HighRSSIThresh; /* if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH */
266 u8 LowRSSIThresh; /* if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW */
267 u8 RATRState; /* Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */
268 u32 LastRATR; /* RATR Register Content */
271 #define IQK_MAC_REG_NUM 4
272 #define IQK_ADDA_REG_NUM 16
273 #define IQK_BB_REG_NUM_MAX 10
274 #define IQK_BB_REG_NUM 9
275 #define HP_THERMAL_NUM 8
277 #define AVG_THERMAL_NUM 8
278 #define IQK_Matrix_REG_NUM 8
279 #define IQK_Matrix_Settings_NUM 1+24+21
281 #define DM_Type_ByFWi 0
282 #define DM_Type_ByDriver 1
284 /* Declare for common info */
286 struct odm_phy_status_info {
288 u8 SignalQuality; /* in 0-100 index. */
289 u8 RxMIMOSignalQuality[MAX_PATH_NUM_92CS]; /* EVM */
290 u8 RxMIMOSignalStrength[MAX_PATH_NUM_92CS];/* in 0~100 index */
291 s8 RxPower; /* in dBm Translate from PWdB */
292 s8 RecvSignalPower;/* Real power in dBm for this packet, no
293 * beautification and aggregation. Keep this raw
294 * info to be used for the other procedures. */
295 u8 BTRxRSSIPercentage;
296 u8 SignalStrength; /* in 0-100 index. */
297 u8 RxPwr[MAX_PATH_NUM_92CS];/* per-path's pwdb */
298 u8 RxSNR[MAX_PATH_NUM_92CS];/* per-path's SNR */
301 struct odm_phy_dbg_info {
302 /* ODM Write,debug info */
303 s8 RxSNRdB[MAX_PATH_NUM_92CS];
305 u64 NumQryPhyStatusCCK;
306 u64 NumQryPhyStatusOFDM;
308 s32 RxEVM[MAX_PATH_NUM_92CS];
311 struct odm_per_pkt_info {
314 bool bPacketMatchBSSID;
319 struct odm_mac_status_info {
325 ODM_DIG = 0x00000001,
326 ODM_HIGH_POWER = 0x00000002,
327 ODM_CCK_CCA_TH = 0x00000004,
328 ODM_FA_STATISTICS = 0x00000008,
329 ODM_RAMASK = 0x00000010,
330 ODM_RSSI_MONITOR = 0x00000020,
331 ODM_SW_ANTDIV = 0x00000040,
332 ODM_HW_ANTDIV = 0x00000080,
333 ODM_BB_PWRSV = 0x00000100,
334 ODM_2TPATHDIV = 0x00000200,
335 ODM_1TPATHDIV = 0x00000400,
336 ODM_PSD2AFH = 0x00000800
339 /* 2011/20/20 MH For MP driver RT_WLAN_STA = struct sta_info */
340 /* Please declare below ODM relative info in your STA info structure. */
342 struct odm_sta_info {
344 bool bUsed; /* record the sta status link or not? */
345 u8 IOTPeer; /* Enum value. HT_IOT_PEER_E */
348 /* 1 PHY_STATUS_INFO */
349 u8 RSSI_Path[4]; /* */
355 /* 2011/10/20 MH Define Common info enum for all team. */
357 enum odm_common_info_def {
360 /* HOOK BEFORE REG INIT----------- */
361 ODM_CMNINFO_PLATFORM = 0,
362 ODM_CMNINFO_ABILITY, /* ODM_ABILITY_E */
363 ODM_CMNINFO_INTERFACE, /* ODM_INTERFACE_E */
364 ODM_CMNINFO_MP_TEST_CHIP,
365 ODM_CMNINFO_IC_TYPE, /* ODM_IC_TYPE_E */
366 ODM_CMNINFO_CUT_VER, /* ODM_CUT_VERSION_E */
367 ODM_CMNINFO_FAB_VER, /* ODM_FAB_E */
368 ODM_CMNINFO_RF_TYPE, /* ODM_RF_PATH_E or ODM_RF_TYPE_E? */
369 ODM_CMNINFO_BOARD_TYPE, /* ODM_BOARD_TYPE_E */
370 ODM_CMNINFO_EXT_LNA, /* true */
372 ODM_CMNINFO_EXT_TRSW,
373 ODM_CMNINFO_PATCH_ID, /* CUSTOMER ID */
374 ODM_CMNINFO_BINHCT_TEST,
375 ODM_CMNINFO_BWIFI_TEST,
376 ODM_CMNINFO_SMART_CONCURRENT,
377 /* HOOK BEFORE REG INIT----------- */
380 /* POINTER REFERENCE----------- */
381 ODM_CMNINFO_MAC_PHY_MODE, /* ODM_MAC_PHY_MODE_E */
384 ODM_CMNINFO_WM_MODE, /* ODM_WIRELESS_MODE_E */
385 ODM_CMNINFO_BAND, /* ODM_BAND_TYPE_E */
386 ODM_CMNINFO_SEC_CHNL_OFFSET, /* ODM_SEC_CHNL_OFFSET_E */
387 ODM_CMNINFO_SEC_MODE, /* ODM_SECURITY_E */
388 ODM_CMNINFO_BW, /* ODM_BW_E */
391 ODM_CMNINFO_DMSP_GET_VALUE,
392 ODM_CMNINFO_BUDDY_ADAPTOR,
393 ODM_CMNINFO_DMSP_IS_MASTER,
395 ODM_CMNINFO_POWER_SAVING,
396 ODM_CMNINFO_ONE_PATH_CCA, /* ODM_CCA_PATH_E */
397 ODM_CMNINFO_DRV_STOP,
400 ODM_CMNINFO_ANT_TEST,
401 ODM_CMNINFO_NET_CLOSED,
403 /* POINTER REFERENCE----------- */
405 /* CALL BY VALUE------------- */
406 ODM_CMNINFO_WIFI_DIRECT,
407 ODM_CMNINFO_WIFI_DISPLAY,
409 ODM_CMNINFO_RSSI_MIN,
410 ODM_CMNINFO_DBG_COMP, /* u64 */
411 ODM_CMNINFO_DBG_LEVEL, /* u32 */
412 ODM_CMNINFO_RA_THRESHOLD_HIGH, /* u8 */
413 ODM_CMNINFO_RA_THRESHOLD_LOW, /* u8 */
414 ODM_CMNINFO_RF_ANTENNA_TYPE, /* u8 */
415 ODM_CMNINFO_BT_DISABLED,
416 ODM_CMNINFO_BT_OPERATION,
418 ODM_CMNINFO_BT_BUSY, /* Check Bt is using or not */
419 ODM_CMNINFO_BT_DISABLE_EDCA,
420 /* CALL BY VALUE-------------*/
422 /* Dynamic ptr array hook itms. */
423 ODM_CMNINFO_STA_STATUS,
424 ODM_CMNINFO_PHY_STATUS,
425 ODM_CMNINFO_MAC_STATUS,
429 /* 2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY */
431 enum odm_ability_def {
432 /* BB ODM section BIT 0-15 */
434 ODM_BB_RA_MASK = BIT1,
435 ODM_BB_DYNAMIC_TXPWR = BIT2,
436 ODM_BB_FA_CNT = BIT3,
437 ODM_BB_RSSI_MONITOR = BIT4,
438 ODM_BB_CCK_PD = BIT5,
439 ODM_BB_ANT_DIV = BIT6,
440 ODM_BB_PWR_SAVE = BIT7,
441 ODM_BB_PWR_TRA = BIT8,
442 ODM_BB_RATE_ADAPTIVE = BIT9,
443 ODM_BB_PATH_DIV = BIT10,
447 /* MAC DM section BIT 16-23 */
448 ODM_MAC_EDCA_TURBO = BIT16,
449 ODM_MAC_EARLY_MODE = BIT17,
451 /* RF ODM section BIT 24-31 */
452 ODM_RF_TX_PWR_TRACK = BIT24,
453 ODM_RF_RX_GAIN_TRACK = BIT25,
454 ODM_RF_CALIBRATION = BIT26,
457 #define ODM_RTL8188E BIT4
459 /* ODM_CMNINFO_CUT_VER */
460 enum odm_cut_version {
470 /* ODM_CMNINFO_FAB_VER */
471 enum odm_fab_Version {
476 /* ODM_CMNINFO_RF_TYPE */
477 /* For example 1T2R (A+AB = BIT0|BIT4|BIT5) */
500 /* ODM Dynamic common info value definition */
502 enum odm_mac_phy_mode {
508 enum odm_bt_coexist {
515 /* ODM_CMNINFO_OP_MODE */
516 enum odm_operation_mode {
520 ODM_POWERSAVE = BIT3,
522 ODM_CLIENT_MODE = BIT5,
524 ODM_WIFI_DIRECT = BIT7,
525 ODM_WIFI_DISPLAY = BIT8,
528 /* ODM_CMNINFO_WM_MODE */
529 enum odm_wireless_mode {
540 /* ODM_CMNINFO_BAND */
542 ODM_BAND_2_4G = BIT0,
546 /* ODM_CMNINFO_SEC_CHNL_OFFSET */
547 enum odm_sec_chnl_offset {
553 /* ODM_CMNINFO_SEC_MODE */
561 ODM_WEP_WPA_MIXED = 6, /* WEP + WPA */
574 /* ODM_CMNINFO_BOARD_TYPE */
575 enum odm_board_type {
576 ODM_BOARD_NORMAL = 0,
577 ODM_BOARD_HIGHPWR = 1,
578 ODM_BOARD_MINICARD = 2,
583 /* ODM_CMNINFO_ONE_PATH_CCA */
611 u8 PTActive; /* on or off */
612 u8 PTTryState; /* 0 trying state, 1 for decision state */
613 u8 PTStage; /* 0~6 */
614 u8 PTStopCount; /* Stop PT counter */
615 u8 PTPreRate; /* if rate change do PT */
616 u8 PTPreRssi; /* if RSSI change 5% do PT */
617 u8 PTModeSS; /* decide whitch rate should do PT */
618 u8 RAstage; /* StageRA, decide how many times RA will be done
623 struct ijk_matrix_regs_set {
625 s32 Value[1][IQK_Matrix_REG_NUM];
629 /* for tx power tracking */
630 u32 RegA24; /* for TempCCK */
637 bool bTXPowerTrackingInit;
638 bool bTXPowerTracking;
639 u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking
642 u8 InternalPA5G[2]; /* pathA / pathB */
644 u8 ThermalMeter[2]; /* ThermalMeter, index 0 for RFIC0,
650 u8 ThermalValue_AVG[AVG_THERMAL_NUM];
651 u8 ThermalValue_AVG_index;
652 u8 ThermalValue_RxGain;
653 u8 ThermalValue_Crystal;
654 u8 ThermalValue_DPKstore;
655 u8 ThermalValue_DPKtrack;
656 bool TxPowerTrackingInProgress;
659 bool bReloadtxpowerindex;
661 u32 TXPowerTrackingCallbackCnt; /* cosa add for debug */
668 u8 ThermalValue_HP[HP_THERMAL_NUM];
669 u8 ThermalValue_HP_index;
670 struct ijk_matrix_regs_set IQKMatrixRegSetting[IQK_Matrix_Settings_NUM];
685 bool bIQKInitialized;
687 bool bAntennaDetected;
688 u32 ADDA_backup[IQK_ADDA_REG_NUM];
689 u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
690 u32 IQK_BB_backup_recover[9];
691 u32 IQK_BB_backup[IQK_BB_REG_NUM];
694 u32 APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */
696 u8 bAPKThermalMeterIgnore;
702 /* ODM Dynamic common info value definition */
704 struct fast_ant_train {
714 u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
715 u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
716 u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
717 u32 MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
718 u32 AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
719 u32 MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
720 u32 AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
726 FAT_NORMAL_STATE = 0,
727 FAT_TRAINING_STATE = 1,
732 CG_TRX_HW_ANTDIV = 0x01,
733 CGCS_RX_HW_ANTDIV = 0x02,
734 FIXED_HW_ANTDIV = 0x03,
735 CG_TRX_SMART_ANTDIV = 0x04,
736 CGCS_RX_SW_ANTDIV = 0x05,
739 /* Copy from SD4 defined structure. We use to support PHY DM integration. */
740 struct odm_dm_struct {
741 /* Add for different team use temporarily */
742 struct adapter *Adapter; /* For CE/NIC team */
743 struct rtl8192cd_priv *priv; /* For AP/ADSL team */
744 /* WHen you use above pointers, they must be initialized. */
747 struct rtl8192cd_priv *fake_priv;
751 /* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */
753 u8 RFPathRxEnable; /* ODM_CMNINFO_RFPATH_ENABLE */
755 /* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */
757 /* 1 COMMON INFORMATION */
759 /* HOOK BEFORE REG INIT----------- */
760 /* ODM Platform info AP/ADSL/CE/MP = 1/2/3/4 */
762 /* ODM Support Ability DIG/RATR/TX_PWR_TRACK/ ¡K¡K = 1/2/3/¡K */
764 /* ODM PCIE/USB/SDIO/GSPI = 0/1/2/3 */
766 /* ODM composite or independent. Bit oriented/ 92C+92D+ .... or any
767 * other type = 1/2/3/... */
769 /* Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... */
771 /* Fab Version TSMC/UMC = 0/1 */
773 /* RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/... */
775 /* Board Type Normal/HighPower/MiniCard/SLIM/Combo/. = 0/1/2/3/4/. */
777 /* with external LNA NO/Yes = 0/1 */
779 /* with external PA NO/Yes = 0/1 */
781 /* with external TRSW NO/Yes = 0/1 */
783 u8 PatchID; /* Customer ID */
787 bool bDualMacSmartConcurrent;
788 u32 BK_SupportAbility;
790 /* HOOK BEFORE REG INIT----------- */
793 /* POINTER REFERENCE----------- */
797 struct adapter *adapter_temp;
799 /* MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 */
801 /* TX Unicast byte count */
802 u64 *pNumTxBytesUnicast;
803 /* RX Unicast byte count */
804 u64 *pNumRxBytesUnicast;
805 /* Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 */
806 u8 *pWirelessMode; /* ODM_WIRELESS_MODE_E */
807 /* Frequence band 2.4G/5G = 0/1 */
809 /* Secondary channel offset don't_care/below/above = 0/1/2 */
811 /* Security mode Open/WEP/AES/TKIP = 0/1/2/3 */
813 /* BW info 20M/40M/80M = 0/1/2 */
815 /* Central channel location Ch1/Ch2/.... */
816 u8 *pChannel; /* central channel number */
817 /* Common info for 92D DMSP */
819 bool *pbGetValueFromOtherMac;
820 struct adapter **pBuddyAdapter;
821 bool *pbMasterOfDMSP; /* MAC0: master, MAC1: slave */
822 /* Common info for Status */
823 bool *pbScanInProcess;
825 /* CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E. */
827 /* pMgntInfo->AntennaTest */
830 /* POINTER REFERENCE----------- */
832 /* CALL BY VALUE------------- */
837 u8 InterfaceIndex; /* Add for 92D dual MAC: 0--Mac0 1--Mac1 */
840 /* Common info for BTDM */
841 bool bBtDisabled; /* BT is disabled */
842 bool bBtHsOperation; /* BT HS mode is under progress */
843 u8 btHsDigVal; /* use BT rssi to decide the DIG value */
844 bool bBtDisableEdcaTurbo;/* Under some condition, don't enable the
846 bool bBtBusy; /* BT is busy. */
847 /* CALL BY VALUE------------- */
849 /* 2 Define STA info. */
851 /* For MP, we need to reduce one array pointer for default port.?? */
852 struct sta_info *pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM];
855 struct odm_ra_info RAInfo[ODM_ASSOCIATE_ENTRY_NUM]; /* Use MacID as
856 * array index. STA MacID=0,
857 * VWiFi Client MacID={1, ODM_ASSOCIATE_ENTRY_NUM-1} */
859 /* 2012/02/14 MH Add to share 88E ra with other SW team. */
860 /* We need to colelct all support abilit to a proper area. */
864 /* Define ........... */
866 /* Latest packet phy info (ODM write) */
867 struct odm_phy_dbg_info PhyDbgInfo;
869 /* Latest packet phy info (ODM write) */
870 struct odm_mac_status_info *pMacInfo;
872 /* Different Team independt structure?? */
875 struct fast_ant_train DM_FatTable;
876 struct rtw_dig DM_DigTable;
877 struct rtl_ps DM_PSTable;
878 struct dyn_primary_cca DM_PriCCA;
879 struct rx_hpc DM_RXHP_Table;
880 struct false_alarm_stats FalseAlmCnt;
881 struct false_alarm_stats FlaseAlmCntBuddyAdapter;
882 struct sw_ant_switch DM_SWAT_Table;
885 struct edca_turbo DM_EDCA_Table;
887 /* Copy from SD4 structure */
889 /* ================================================== */
892 bool *pbDriverStopped;
893 bool *pbDriverIsGoingToPnpSetPowerSleep;
894 bool *pinit_adpt_in_progress;
897 bool bUserAssignLevel;
898 struct timer_list PSDTimer;
899 u8 RSSI_BT; /* come from BT */
901 bool bDMInitialGainEnable;
903 /* for rate adaptive, in fact, 88c/92c fw will handle this */
906 struct odm_rate_adapt RateAdaptive;
908 struct odm_rf_cal RFCalibrateInfo;
910 /* TX power tracking */
912 u8 BbSwingIdxOfdmCurrent;
913 u8 BbSwingIdxOfdmBase;
914 bool BbSwingFlagOfdm;
916 u8 BbSwingIdxCckCurrent;
917 u8 BbSwingIdxCckBase;
920 /* ODM system resource. */
922 /* ODM relative time. */
923 struct timer_list PathDivSwitchTimer;
924 /* 2011.09.27 add for Path Diversity */
925 struct timer_list CCKPathDiversityTimer;
926 struct timer_list FastAntTrainingTimer;
927 }; /* DM_Dynamic_Mechanism_Structure */
929 #define ODM_RF_PATH_MAX 3
931 enum ODM_RF_RADIO_PATH {
932 ODM_RF_PATH_A = 0, /* Radio Path A */
933 ODM_RF_PATH_B = 1, /* Radio Path B */
934 ODM_RF_PATH_C = 2, /* Radio Path C */
935 ODM_RF_PATH_D = 3, /* Radio Path D */
938 enum ODM_RF_CONTENT {
939 odm_radioa_txt = 0x1000,
940 odm_radiob_txt = 0x1001,
941 odm_radioc_txt = 0x1002,
942 odm_radiod_txt = 0x1003
945 enum odm_bb_config_type {
948 CONFIG_BB_AGC_TAB_2G,
949 CONFIG_BB_AGC_TAB_5G,
950 CONFIG_BB_PHY_REG_PG,
959 RT_STATUS_INVALID_CONTEXT,
960 RT_STATUS_INVALID_PARAMETER,
961 RT_STATUS_NOT_SUPPORT,
962 RT_STATUS_OS_API_FAILED,
965 /* 3=========================================================== */
967 /* 3=========================================================== */
970 RT_TYPE_THRESH_HIGH = 0,
971 RT_TYPE_THRESH_LOW = 1,
973 RT_TYPE_RX_GAIN_MIN = 3,
974 RT_TYPE_RX_GAIN_MAX = 4,
980 #define DM_DIG_THRESH_HIGH 40
981 #define DM_DIG_THRESH_LOW 35
983 #define DM_SCAN_RSSI_TH 0x14 /* scan return issue for LC */
986 #define DM_false_ALARM_THRESH_LOW 400
987 #define DM_false_ALARM_THRESH_HIGH 1000
989 #define DM_DIG_MAX_NIC 0x4e
990 #define DM_DIG_MIN_NIC 0x1e /* 0x22/0x1c */
992 #define DM_DIG_MAX_AP 0x32
993 #define DM_DIG_MIN_AP 0x20
995 #define DM_DIG_MAX_NIC_HP 0x46
996 #define DM_DIG_MIN_NIC_HP 0x2e
998 #define DM_DIG_MAX_AP_HP 0x42
999 #define DM_DIG_MIN_AP_HP 0x30
1001 /* vivi 92c&92d has different definition, 20110504 */
1002 /* this is for 92c */
1003 #define DM_DIG_FA_TH0 0x200/* 0x20 */
1004 #define DM_DIG_FA_TH1 0x300/* 0x100 */
1005 #define DM_DIG_FA_TH2 0x400/* 0x200 */
1006 /* this is for 92d */
1007 #define DM_DIG_FA_TH0_92D 0x100
1008 #define DM_DIG_FA_TH1_92D 0x400
1009 #define DM_DIG_FA_TH2_92D 0x600
1011 #define DM_DIG_BACKOFF_MAX 12
1012 #define DM_DIG_BACKOFF_MIN -4
1013 #define DM_DIG_BACKOFF_DEFAULT 10
1015 /* 3=========================================================== */
1016 /* 3 AGC RX High Power Mode */
1017 /* 3=========================================================== */
1018 #define LNA_Low_Gain_1 0x64
1019 #define LNA_Low_Gain_2 0x5A
1020 #define LNA_Low_Gain_3 0x58
1022 #define FA_RXHP_TH1 5000
1023 #define FA_RXHP_TH2 1500
1024 #define FA_RXHP_TH3 800
1025 #define FA_RXHP_TH4 600
1026 #define FA_RXHP_TH5 500
1028 /* 3=========================================================== */
1030 /* 3=========================================================== */
1032 /* 3=========================================================== */
1033 /* 3 Dynamic Tx Power */
1034 /* 3=========================================================== */
1035 /* Dynamic Tx Power Control Threshold */
1036 #define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
1037 #define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
1038 #define TX_POWER_NEAR_FIELD_THRESH_AP 0x3F
1040 #define TxHighPwrLevel_Normal 0
1041 #define TxHighPwrLevel_Level1 1
1042 #define TxHighPwrLevel_Level2 2
1043 #define TxHighPwrLevel_BT1 3
1044 #define TxHighPwrLevel_BT2 4
1045 #define TxHighPwrLevel_15 5
1046 #define TxHighPwrLevel_35 6
1047 #define TxHighPwrLevel_50 7
1048 #define TxHighPwrLevel_70 8
1049 #define TxHighPwrLevel_100 9
1051 /* 3=========================================================== */
1052 /* 3 Rate Adaptive */
1053 /* 3=========================================================== */
1054 #define DM_RATR_STA_INIT 0
1055 #define DM_RATR_STA_HIGH 1
1056 #define DM_RATR_STA_MIDDLE 2
1057 #define DM_RATR_STA_LOW 3
1059 /* 3=========================================================== */
1060 /* 3 BB Power Save */
1061 /* 3=========================================================== */
1076 /* 3=========================================================== */
1077 /* 3 Antenna Diversity */
1078 /* 3=========================================================== */
1085 /* Maximal number of antenna detection mechanism needs to perform. */
1086 #define MAX_ANTENNA_DETECTION_CNT 10
1088 /* Extern Global Variables. */
1089 #define OFDM_TABLE_SIZE_92C 37
1090 #define OFDM_TABLE_SIZE_92D 43
1091 #define CCK_TABLE_SIZE 33
1093 extern u32 OFDMSwingTable[OFDM_TABLE_SIZE_92D];
1094 extern u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8];
1095 extern u8 CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8];
1097 /* check Sta pointer valid or not */
1098 #define IS_STA_VALID(pSta) (pSta)
1099 /* 20100514 Joseph: Add definition for antenna switching test after link. */
1100 /* This indicates two different the steps. */
1101 /* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the
1102 * signal on the air. */
1103 /* In SWAW_STEP_DETERMINE, driver just compares the signal captured in
1105 /* with original RSSI to determine if it is necessary to switch antenna. */
1106 #define SWAW_STEP_PEAK 0
1107 #define SWAW_STEP_DETERMINE 1
1109 #define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck
1110 #define dm_RF_Saving ODM_RF_Saving
1112 void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal);
1113 void ODM_TXPowerTrackingCheck(struct odm_dm_struct *pDM_Odm);
1114 void odm_DIGbyRSSI_LPS(struct odm_dm_struct *pDM_Odm);
1115 void ODM_Write_CCK_CCA_Thres(struct odm_dm_struct *pDM_Odm, u8 CurCCK_CCAThres);
1116 bool ODM_RAStateCheck(struct odm_dm_struct *pDM_Odm, s32 RSSI,
1117 bool bForceUpdate, u8 *pRATRState);
1118 u32 ConvertTo_dB(u32 Value);
1119 u32 ODM_Get_Rate_Bitmap(struct odm_dm_struct *pDM_Odm, u32 macid,
1120 u32 ra_mask, u8 rssi_level);
1121 void ODM_CmnInfoInit(struct odm_dm_struct *pDM_Odm,
1122 enum odm_common_info_def CmnInfo, u32 Value);
1123 void ODM_CmnInfoUpdate(struct odm_dm_struct *pDM_Odm, u32 CmnInfo, u64 Value);
1124 void ODM_CmnInfoHook(struct odm_dm_struct *pDM_Odm,
1125 enum odm_common_info_def CmnInfo, void *pValue);
1126 void ODM_CmnInfoPtrArrayHook(struct odm_dm_struct *pDM_Odm,
1127 enum odm_common_info_def CmnInfo,
1128 u16 Index, void *pValue);
1129 void ODM_DMInit(struct odm_dm_struct *pDM_Odm);
1130 void ODM_DMWatchdog(struct odm_dm_struct *pDM_Odm);
1131 void ODM_Write_DIG(struct odm_dm_struct *pDM_Odm, u8 CurrentIGI);