2 /******************************************************************************
4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 ******************************************************************************/
22 #ifndef __HAL8188EPWRSEQ_H__
23 #define __HAL8188EPWRSEQ_H__
25 #include "pwrseqcmd.h"
28 Check document WM-20110607-Paul-RTL8188E_Power_Architecture-R02.vsd
29 There are 6 HW Power States:
32 2: CARDEMU--Card Emulation
34 4: LPS--Low Power State
37 The transision from different states are defined below
48 PWR SEQ Version: rtl8188E_PwrSeq_V09.h
50 #define RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS 10
51 #define RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS 10
52 #define RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS 10
53 #define RTL8188E_TRANS_SUS_TO_CARDEMU_STEPS 10
54 #define RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS 10
55 #define RTL8188E_TRANS_PDN_TO_CARDEMU_STEPS 10
56 #define RTL8188E_TRANS_ACT_TO_LPS_STEPS 15
57 #define RTL8188E_TRANS_LPS_TO_ACT_STEPS 15
58 #define RTL8188E_TRANS_END_STEPS 1
61 #define RTL8188E_TRANS_CARDEMU_TO_ACT \
63 * { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value
67 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
68 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1}, \
69 /* wait till 0x04[17] = 1 power ready*/ \
70 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
71 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0|BIT1, 0}, \
72 /* 0x02[1:0] = 0 reset BB*/ \
73 {0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
74 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7}, \
75 /*0x24[23] = 2b'01 schmit trigger */ \
76 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
77 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0}, \
78 /* 0x04[15] = 0 disable HWPDN (control by DRV)*/ \
79 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
80 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, 0}, \
81 /*0x04[12:11] = 2b'00 disable WL suspend*/ \
82 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
83 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, \
84 /*0x04[8] = 1 polling until return 0*/ \
85 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
86 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0}, \
87 /*wait till 0x04[8] = 0*/ \
88 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
89 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, \
91 {0x0074, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
92 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, \
95 #define RTL8188E_TRANS_ACT_TO_CARDEMU \
97 * { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value
101 {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
102 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, \
103 /*0x1F[7:0] = 0 turn off RF*/ \
104 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
105 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, \
107 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
108 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, \
109 /*0x04[9] = 1 turn off MAC by HW state machine*/ \
110 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
111 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, \
112 /*wait till 0x04[9] = 0 polling until return 0 to disable*/
114 #define RTL8188E_TRANS_CARDEMU_TO_SUS \
116 * { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk,
120 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
121 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \
122 PWR_CMD_WRITE, BIT3|BIT4, BIT3}, \
123 /* 0x04[12:11] = 2b'01enable WL suspend */ \
124 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
125 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, \
126 /* 0x04[12:11] = 2b'11enable WL suspend for PCIe */ \
127 {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
128 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \
129 PWR_CMD_WRITE, 0xFF, BIT7}, \
130 /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */\
131 {0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
132 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \
133 PWR_CMD_WRITE, BIT4, 0}, \
134 /*Clear SIC_EN register 0x40[12] = 1'b0 */ \
135 {0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
136 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \
137 PWR_CMD_WRITE, BIT4, BIT4}, \
138 /*Set USB suspend enable local register 0xfe10[4]=1 */ \
139 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
140 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, \
141 /*Set SDIO suspend local register*/ \
142 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
143 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, \
144 /*wait power state to suspend*/
146 #define RTL8188E_TRANS_SUS_TO_CARDEMU \
148 * { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk,
152 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
153 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, \
154 /*Set SDIO suspend local register*/ \
155 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
156 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, \
157 /*wait power state to suspend*/ \
158 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
159 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0}, \
160 /*0x04[12:11] = 2b'01enable WL suspend*/
162 #define RTL8188E_TRANS_CARDEMU_TO_CARDDIS \
164 * { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk,
168 {0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
169 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7}, \
170 /*0x24[23] = 2b'01 schmit trigger */ \
171 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
172 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \
173 PWR_CMD_WRITE, BIT3|BIT4, BIT3}, \
174 /*0x04[12:11] = 2b'01 enable WL suspend*/ \
175 {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
176 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \
177 PWR_CMD_WRITE, 0xFF, 0}, \
178 /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */\
179 {0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
180 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \
181 PWR_CMD_WRITE, BIT4, 0}, \
182 /*Clear SIC_EN register 0x40[12] = 1'b0 */ \
183 {0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, \
184 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, \
185 /*Set USB suspend enable local register 0xfe10[4]=1 */ \
186 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
187 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, \
188 /*Set SDIO suspend local register*/ \
189 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
190 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, \
191 /*wait power state to suspend*/
193 #define RTL8188E_TRANS_CARDDIS_TO_CARDEMU \
195 * { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk,
199 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
200 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, \
201 /*Set SDIO suspend local register*/ \
202 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
203 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, \
204 /*wait power state to suspend*/ \
205 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
206 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0}, \
207 /*0x04[12:11] = 2b'01enable WL suspend*/
209 #define RTL8188E_TRANS_CARDEMU_TO_PDN \
211 * { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk,
215 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
216 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, \
218 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
219 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7}, \
222 #define RTL8188E_TRANS_PDN_TO_CARDEMU \
224 * { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk,
228 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
229 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0}, \
232 /* This is used by driver for LPSRadioOff Procedure, not for FW LPS Step */
233 #define RTL8188E_TRANS_ACT_TO_LPS \
235 * { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk,
239 {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
240 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \
241 {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
242 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
243 /*Should be zero if no packet is transmitting*/ \
244 {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
245 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
246 /*Should be zero if no packet is transmitting*/ \
247 {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
248 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
249 /*Should be zero if no packet is transmitting*/ \
250 {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
251 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
252 /*Should be zero if no packet is transmitting*/ \
253 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
254 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, \
255 /*CCK and OFDM are disabled,and clock are gated*/ \
256 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
257 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, \
258 PWRSEQ_DELAY_US},/*Delay 1us*/ \
259 {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
260 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/ \
261 {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
262 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/\
263 {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
264 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, \
265 /*Respond TxOK to scheduler*/
268 #define RTL8188E_TRANS_LPS_TO_ACT \
270 * { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk,
274 {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
275 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/ \
276 {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, \
277 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/ \
278 {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
279 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/ \
280 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
281 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/ \
282 {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
283 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, \
284 /* 0x08[4] = 0 switch TSF to 40M */ \
285 {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
286 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, \
287 /* Polling 0x109[7]=0 TSF in 40M */ \
288 {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
289 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0}, \
290 /* 0x29[7:6] = 2b'00 enable BB clock */ \
291 {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
292 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, \
294 {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
295 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, \
296 /* 0x100[7:0] = 0xFF enable WMAC TRX */ \
297 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
298 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, \
299 /* 0x02[1:0] = 2b'11 enable BB macro */ \
300 {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
301 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
303 #define RTL8188E_TRANS_END \
305 * { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk,
309 {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, \
313 extern struct wl_pwr_cfg rtl8188E_power_on_flow
314 [RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS + RTL8188E_TRANS_END_STEPS];
315 extern struct wl_pwr_cfg rtl8188E_radio_off_flow
316 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_END_STEPS];
317 extern struct wl_pwr_cfg rtl8188E_card_disable_flow
318 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
319 RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS +
320 RTL8188E_TRANS_END_STEPS];
321 extern struct wl_pwr_cfg rtl8188E_card_enable_flow
322 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
323 RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS +
324 RTL8188E_TRANS_END_STEPS];
325 extern struct wl_pwr_cfg rtl8188E_suspend_flow[
326 RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
327 RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS +
328 RTL8188E_TRANS_END_STEPS];
329 extern struct wl_pwr_cfg rtl8188E_resume_flow
330 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
331 RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS +
332 RTL8188E_TRANS_END_STEPS];
333 extern struct wl_pwr_cfg rtl8188E_hwpdn_flow
334 [RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
335 RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188E_TRANS_END_STEPS];
336 extern struct wl_pwr_cfg rtl8188E_enter_lps_flow
337 [RTL8188E_TRANS_ACT_TO_LPS_STEPS + RTL8188E_TRANS_END_STEPS];
338 extern struct wl_pwr_cfg rtl8188E_leave_lps_flow
339 [RTL8188E_TRANS_LPS_TO_ACT_STEPS + RTL8188E_TRANS_END_STEPS];
341 #endif /* __HAL8188EPWRSEQ_H__ */