1 /*****************************************************************************
2 * Copyright(c) 2007, RealTEK Technology Inc. All Right Reserved.
4 * Module: Hal819xUsbDM.h (RTL8192 Header H File)
7 * Note: For dynamic control definition constant structure.
16 * 10/04/2007 MHC Create initial version.
18 *****************************************************************************/
19 /* Check to see if the file has been included already. */
20 #ifndef __R8192UDM_H__
21 #define __R8192UDM_H__
24 /*--------------------------Define Parameters-------------------------------*/
25 #define OFDM_Table_Length 19
26 #define CCK_Table_length 12
28 #define DM_DIG_THRESH_HIGH 40
29 #define DM_DIG_THRESH_LOW 35
31 #define DM_DIG_HIGH_PWR_THRESH_HIGH 75
32 #define DM_DIG_HIGH_PWR_THRESH_LOW 70
34 #define BW_AUTO_SWITCH_HIGH_LOW 25
35 #define BW_AUTO_SWITCH_LOW_HIGH 30
37 #define DM_check_fsync_time_interval 500
40 #define DM_DIG_BACKOFF 12
41 #define DM_DIG_MAX 0x36
42 #define DM_DIG_MIN 0x1c
43 #define DM_DIG_MIN_Netcore 0x12
45 #define RxPathSelection_SS_TH_low 30
46 #define RxPathSelection_diff_TH 18
48 #define RateAdaptiveTH_High 50
49 #define RateAdaptiveTH_Low_20M 30
50 #define RateAdaptiveTH_Low_40M 10
51 #define VeryLowRSSI 15
52 #define CTSToSelfTHVal 35
54 //defined by vivi, for tx power track
55 #define E_FOR_TX_POWER_TRACK 300
56 //Dynamic Tx Power Control Threshold
57 #define TX_POWER_NEAR_FIELD_THRESH_HIGH 68
58 #define TX_POWER_NEAR_FIELD_THRESH_LOW 62
59 //added by amy for atheros AP
60 #define TX_POWER_ATHEROAP_THRESH_HIGH 78
61 #define TX_POWER_ATHEROAP_THRESH_LOW 72
63 //defined by vivi, for showing on UI. Newer firmware has changed to 0x1e0
64 #define Current_Tx_Rate_Reg 0x1e0//0x1b8
65 #define Initial_Tx_Rate_Reg 0x1e1 //0x1b9
66 #define Tx_Retry_Count_Reg 0x1ac
69 //----------------------------------------------------------------------------
70 // 8190 Rate Adaptive Table Register (offset 0x320, 4 byte)
71 //----------------------------------------------------------------------------
74 #define RATR_1M 0x00000001
75 #define RATR_2M 0x00000002
76 #define RATR_55M 0x00000004
77 #define RATR_11M 0x00000008
79 #define RATR_6M 0x00000010
80 #define RATR_9M 0x00000020
81 #define RATR_12M 0x00000040
82 #define RATR_18M 0x00000080
83 #define RATR_24M 0x00000100
84 #define RATR_36M 0x00000200
85 #define RATR_48M 0x00000400
86 #define RATR_54M 0x00000800
87 //MCS 1 Spatial Stream
88 #define RATR_MCS0 0x00001000
89 #define RATR_MCS1 0x00002000
90 #define RATR_MCS2 0x00004000
91 #define RATR_MCS3 0x00008000
92 #define RATR_MCS4 0x00010000
93 #define RATR_MCS5 0x00020000
94 #define RATR_MCS6 0x00040000
95 #define RATR_MCS7 0x00080000
96 //MCS 2 Spatial Stream
97 #define RATR_MCS8 0x00100000
98 #define RATR_MCS9 0x00200000
99 #define RATR_MCS10 0x00400000
100 #define RATR_MCS11 0x00800000
101 #define RATR_MCS12 0x01000000
102 #define RATR_MCS13 0x02000000
103 #define RATR_MCS14 0x04000000
104 #define RATR_MCS15 0x08000000
106 #define RATE_ALL_CCK RATR_1M|RATR_2M|RATR_55M|RATR_11M
107 #define RATE_ALL_OFDM_AG RATR_6M|RATR_9M|RATR_12M|RATR_18M|RATR_24M\
108 |RATR_36M|RATR_48M|RATR_54M
109 #define RATE_ALL_OFDM_2SS RATR_MCS8|RATR_MCS9 |RATR_MCS10|RATR_MCS11| \
110 RATR_MCS12|RATR_MCS13|RATR_MCS14|RATR_MCS15
112 /*--------------------------Define Parameters-------------------------------*/
115 /*------------------------------Define structure----------------------------*/
116 /* 2007/10/04 MH Define upper and lower threshold of DIG enable or disable. */
117 typedef struct _dynamic_initial_gain_threshold_
122 u8 dig_algorithm_switch;
124 long rssi_low_thresh;
125 long rssi_high_thresh;
127 long rssi_high_power_lowthresh;
128 long rssi_high_power_highthresh;
131 u8 dig_highpwr_state;
132 u8 cur_connect_state;
133 u8 pre_connect_state;
137 u8 curcs_ratio_state;
138 u8 precs_ratio_state;
144 u8 rx_gain_range_max;
145 u8 rx_gain_range_min;
146 bool initialgain_lowerbound_state;
151 typedef enum tag_dynamic_init_gain_state_definition
159 /* 2007/10/08 MH Define RATR state. */
160 typedef enum tag_dynamic_ratr_state_definition
162 DM_RATR_STA_HIGH = 0,
163 DM_RATR_STA_MIDDLE = 1,
168 /* 2007/10/11 MH Define DIG operation type. */
169 typedef enum tag_dynamic_init_gain_operation_type_definition
171 DIG_TYPE_THRESH_HIGH = 0,
172 DIG_TYPE_THRESH_LOW = 1,
173 DIG_TYPE_THRESH_HIGHPWR_HIGH = 2,
174 DIG_TYPE_THRESH_HIGHPWR_LOW = 3,
175 DIG_TYPE_DBG_MODE = 4,
177 DIG_TYPE_ALGORITHM = 6,
178 DIG_TYPE_BACKOFF = 7,
179 DIG_TYPE_PWDB_FACTOR = 8,
180 DIG_TYPE_RX_GAIN_MIN = 9,
181 DIG_TYPE_RX_GAIN_MAX = 10,
182 DIG_TYPE_ENABLE = 20,
183 DIG_TYPE_DISABLE = 30,
187 typedef enum tag_dig_algorithm_definition
189 DIG_ALGO_BY_FALSE_ALARM = 0,
190 DIG_ALGO_BY_RSSI = 1,
194 typedef enum tag_dig_dbgmode_definition
201 typedef enum tag_dig_connect_definition
208 typedef enum tag_dig_packetdetection_threshold_definition
210 DIG_PD_AT_LOW_POWER = 0,
211 DIG_PD_AT_NORMAL_POWER = 1,
212 DIG_PD_AT_HIGH_POWER = 2,
216 typedef enum tag_dig_cck_cs_ratio_state_definition
218 DIG_CS_RATIO_LOWER = 0,
219 DIG_CS_RATIO_HIGHER = 1,
222 typedef struct _Dynamic_Rx_Path_Selection_
235 u8 rf_enable_rssi_th[4];
236 long cck_pwdb_sta[4];
239 typedef enum tag_CCK_Rx_Path_Method_Definition
241 CCK_Rx_Version_1 = 0,
244 }DM_CCK_Rx_Path_Method;
246 typedef enum tag_DM_DbgMode_Definition
253 typedef struct tag_Tx_Config_Cmd_Format
255 u32 Op; /* Command packet type. */
256 u32 Length; /* Command packet length. */
258 }DCMD_TXCMD_T, *PDCMD_TXCMD_T;
259 /*------------------------------Define structure----------------------------*/
262 /*------------------------Export global variable----------------------------*/
263 extern dig_t dm_digtable;
264 extern DRxPathSel DM_RxPathSelTable;
265 /*------------------------Export global variable----------------------------*/
268 /*------------------------Export Marco Definition---------------------------*/
270 /*------------------------Export Marco Definition---------------------------*/
273 /*--------------------------Exported Function prototype---------------------*/
274 /*--------------------------Exported Function prototype---------------------*/
275 extern void init_hal_dm(struct net_device *dev);
276 extern void deinit_hal_dm(struct net_device *dev);
278 extern void hal_dm_watchdog(struct net_device *dev);
281 extern void init_rate_adaptive(struct net_device *dev);
282 extern void dm_txpower_trackingcallback(struct work_struct *work);
284 extern void dm_cck_txpower_adjust(struct net_device *dev,bool binch14);
285 extern void dm_restore_dynamic_mechanism_state(struct net_device *dev);
286 extern void dm_backup_dynamic_mechanism_state(struct net_device *dev);
287 extern void dm_change_dynamic_initgain_thresh(struct net_device *dev,
290 extern void DM_ChangeFsyncSetting(struct net_device *dev,
293 extern void dm_force_tx_fw_info(struct net_device *dev,
296 extern void dm_init_edca_turbo(struct net_device *dev);
297 extern void dm_rf_operation_test_callback(unsigned long data);
298 extern void dm_rf_pathcheck_workitemcallback(struct work_struct *work);
299 extern void dm_fsync_timer_callback(unsigned long data);
301 extern bool dm_check_lbus_status(struct net_device *dev);
303 extern void dm_check_fsync(struct net_device *dev);
304 extern void dm_initialize_txpower_tracking(struct net_device *dev);
307 #endif /*__R8192UDM_H__ */
310 /* End of r8192U_dm.h */