drivers/staging/rtl8192e/rtl8192e/r8190P_def.h

   1 /******************************************************************************
   2  * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
   3  *
   4  * This program is distributed in the hope that it will be useful, but WITHOUT
   5  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   6  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   7  * more details.
   8  *
   9  * You should have received a copy of the GNU General Public License along with
  10  * this program; if not, write to the Free Software Foundation, Inc.,
  11  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  12  *
  13  * The full GNU General Public License is included in this distribution in the
  14  * file called LICENSE.
  15  *
  16  * Contact Information:
  17  * wlanfae <wlanfae@realtek.com>
  18 ******************************************************************************/
  19
  20
  21 #ifndef R8190P_DEF_H
  22 #define R8190P_DEF_H
  23
  24 #include <linux/types.h>
  25
  26 #define         MAX_SILENT_RESET_RX_SLOT_NUM    10
  27
  28 #define RX_MPDU_QUEUE                           0
  29
  30 enum rtl819x_loopback {
  31         RTL819X_NO_LOOPBACK = 0,
  32         RTL819X_MAC_LOOPBACK = 1,
  33         RTL819X_DMA_LOOPBACK = 2,
  34         RTL819X_CCK_LOOPBACK = 3,
  35 };
  36
  37 #define DESC90_RATE1M                           0x00
  38 #define DESC90_RATE2M                           0x01
  39 #define DESC90_RATE5_5M                         0x02
  40 #define DESC90_RATE11M                          0x03
  41 #define DESC90_RATE6M                           0x04
  42 #define DESC90_RATE9M                           0x05
  43 #define DESC90_RATE12M                          0x06
  44 #define DESC90_RATE18M                          0x07
  45 #define DESC90_RATE24M                          0x08
  46 #define DESC90_RATE36M                          0x09
  47 #define DESC90_RATE48M                          0x0a
  48 #define DESC90_RATE54M                          0x0b
  49 #define DESC90_RATEMCS0                         0x00
  50 #define DESC90_RATEMCS1                         0x01
  51 #define DESC90_RATEMCS2                         0x02
  52 #define DESC90_RATEMCS3                         0x03
  53 #define DESC90_RATEMCS4                         0x04
  54 #define DESC90_RATEMCS5                         0x05
  55 #define DESC90_RATEMCS6                         0x06
  56 #define DESC90_RATEMCS7                         0x07
  57 #define DESC90_RATEMCS8                         0x08
  58 #define DESC90_RATEMCS9                         0x09
  59 #define DESC90_RATEMCS10                        0x0a
  60 #define DESC90_RATEMCS11                        0x0b
  61 #define DESC90_RATEMCS12                        0x0c
  62 #define DESC90_RATEMCS13                        0x0d
  63 #define DESC90_RATEMCS14                        0x0e
  64 #define DESC90_RATEMCS15                        0x0f
  65 #define DESC90_RATEMCS32                        0x20
  66
  67 #define SHORT_SLOT_TIME                         9
  68 #define NON_SHORT_SLOT_TIME             20
  69
  70 #define RX_SMOOTH                               20
  71
  72 #define QSLT_BK                                 0x1
  73 #define QSLT_BE                                 0x0
  74 #define QSLT_VI                                 0x4
  75 #define QSLT_VO                                 0x6
  76 #define QSLT_BEACON                     0x10
  77 #define QSLT_HIGH                               0x11
  78 #define QSLT_MGNT                               0x12
  79 #define QSLT_CMD                                0x13
  80
  81 #define NUM_OF_PAGE_IN_FW_QUEUE_BK              0x007
  82 #define NUM_OF_PAGE_IN_FW_QUEUE_BE              0x0aa
  83 #define NUM_OF_PAGE_IN_FW_QUEUE_VI              0x024
  84 #define NUM_OF_PAGE_IN_FW_QUEUE_VO              0x007
  85 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT            0x10
  86 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN             0x4
  87 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB             0xd
  88
  89 #define APPLIED_RESERVED_QUEUE_IN_FW            0x80000000
  90 #define RSVD_FW_QUEUE_PAGE_BK_SHIFT             0x00
  91 #define RSVD_FW_QUEUE_PAGE_BE_SHIFT             0x08
  92 #define RSVD_FW_QUEUE_PAGE_VI_SHIFT             0x10
  93 #define RSVD_FW_QUEUE_PAGE_VO_SHIFT             0x18
  94 #define RSVD_FW_QUEUE_PAGE_MGNT_SHIFT   0x10
  95 #define RSVD_FW_QUEUE_PAGE_BCN_SHIFT            0x00
  96 #define RSVD_FW_QUEUE_PAGE_PUB_SHIFT            0x08
  97
  98 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
  99 #define HAL_PRIME_CHNL_OFFSET_LOWER             1
 100 #define HAL_PRIME_CHNL_OFFSET_UPPER             2
 101
 102
 103 enum version_8190_loopback {
 104         VERSION_8190_BD = 0x3,
 105         VERSION_8190_BE
 106 };
 107
 108 #define IC_VersionCut_C 0x2
 109 #define IC_VersionCut_D 0x3
 110 #define IC_VersionCut_E 0x4
 111
 112 enum rf_optype {
 113         RF_OP_By_SW_3wire = 0,
 114         RF_OP_By_FW,
 115         RF_OP_MAX
 116 };
 117
 118 struct bb_reg_definition {
 119         u32 rfintfs;
 120         u32 rfintfi;
 121         u32 rfintfo;
 122         u32 rfintfe;
 123         u32 rf3wireOffset;
 124         u32 rfLSSI_Select;
 125         u32 rfTxGainStage;
 126         u32 rfHSSIPara1;
 127         u32 rfHSSIPara2;
 128         u32 rfSwitchControl;
 129         u32 rfAGCControl1;
 130         u32 rfAGCControl2;
 131         u32 rfRxIQImbalance;
 132         u32 rfRxAFE;
 133         u32 rfTxIQImbalance;
 134         u32 rfTxAFE;
 135         u32 rfLSSIReadBack;
 136         u32 rfLSSIReadBackPi;
 137 };
 138
 139 struct tx_fwinfo_8190pci {
 140         u8                      TxRate:7;
 141         u8                      CtsEnable:1;
 142         u8                      RtsRate:7;
 143         u8                      RtsEnable:1;
 144         u8                      TxHT:1;
 145         u8                      Short:1;
 146         u8                      TxBandwidth:1;
 147         u8                      TxSubCarrier:2;
 148         u8                      STBC:2;
 149         u8                      AllowAggregation:1;
 150         u8                      RtsHT:1;
 151         u8                      RtsShort:1;
 152         u8                      RtsBandwidth:1;
 153         u8                      RtsSubcarrier:2;
 154         u8                      RtsSTBC:2;
 155         u8                      EnableCPUDur:1;
 156
 157         u32                     RxMF:2;
 158         u32                     RxAMD:3;
 159         u32                     TxPerPktInfoFeedback:1;
 160         u32                     Reserved1:2;
 161         u32                     TxAGCOffset:4;
 162         u32                     TxAGCSign:1;
 163         u32                     RAW_TXD:1;
 164         u32                     Retry_Limit:4;
 165         u32                     Reserved2:1;
 166         u32                     PacketID:13;
 167
 168
 169 };
 170
 171 struct log_int_8190 {
 172         u32     nIMR_COMDOK;
 173         u32     nIMR_MGNTDOK;
 174         u32     nIMR_HIGH;
 175         u32     nIMR_VODOK;
 176         u32     nIMR_VIDOK;
 177         u32     nIMR_BEDOK;
 178         u32     nIMR_BKDOK;
 179         u32     nIMR_ROK;
 180         u32     nIMR_RCOK;
 181         u32     nIMR_TBDOK;
 182         u32     nIMR_BDOK;
 183         u32     nIMR_RXFOVW;
 184 };
 185
 186 struct phy_ofdm_rx_status_rxsc_sgien_exintfflag {
 187         u8                      reserved:4;
 188         u8                      rxsc:2;
 189         u8                      sgi_en:1;
 190         u8                      ex_intf_flag:1;
 191 };
 192
 193 struct phy_sts_ofdm_819xpci {
 194         u8      trsw_gain_X[4];
 195         u8      pwdb_all;
 196         u8      cfosho_X[4];
 197         u8      cfotail_X[4];
 198         u8      rxevm_X[2];
 199         u8      rxsnr_X[4];
 200         u8      pdsnr_X[2];
 201         u8      csi_current_X[2];
 202         u8      csi_target_X[2];
 203         u8      sigevm;
 204         u8      max_ex_pwr;
 205         u8      sgi_en;
 206         u8      rxsc_sgien_exflg;
 207 };
 208
 209 struct phy_sts_cck_819xpci {
 210         u8      adc_pwdb_X[4];
 211         u8      sq_rpt;
 212         u8      cck_agc_rpt;
 213 };
 214
 215
 216 #define         PHY_RSSI_SLID_WIN_MAX                           100
 217 #define         PHY_Beacon_RSSI_SLID_WIN_MAX            10
 218
 219 struct tx_desc {
 220         u16     PktSize;
 221         u8      Offset;
 222         u8      Reserved1:3;
 223         u8      CmdInit:1;
 224         u8      LastSeg:1;
 225         u8      FirstSeg:1;
 226         u8      LINIP:1;
 227         u8      OWN:1;
 228
 229         u8      TxFWInfoSize;
 230         u8      RATid:3;
 231         u8      DISFB:1;
 232         u8      USERATE:1;
 233         u8      MOREFRAG:1;
 234         u8      NoEnc:1;
 235         u8      PIFS:1;
 236         u8      QueueSelect:5;
 237         u8      NoACM:1;
 238         u8      Resv:2;
 239         u8      SecCAMID:5;
 240         u8      SecDescAssign:1;
 241         u8      SecType:2;
 242
 243         u16     TxBufferSize;
 244         u8      PktId:7;
 245         u8      Resv1:1;
 246         u8      Reserved2;
 247
 248         u32     TxBuffAddr;
 249
 250         u32     NextDescAddress;
 251
 252         u32     Reserved5;
 253         u32     Reserved6;
 254         u32     Reserved7;
 255 };
 256
 257
 258 struct tx_desc_cmd {
 259         u16     PktSize;
 260         u8      Reserved1;
 261         u8      CmdType:3;
 262         u8      CmdInit:1;
 263         u8      LastSeg:1;
 264         u8      FirstSeg:1;
 265         u8      LINIP:1;
 266         u8      OWN:1;
 267
 268         u16     ElementReport;
 269         u16     Reserved2;
 270
 271         u16     TxBufferSize;
 272         u16     Reserved3;
 273
 274         u32     TxBuffAddr;
 275         u32     NextDescAddress;
 276         u32     Reserved4;
 277         u32     Reserved5;
 278         u32     Reserved6;
 279 };
 280
 281 struct rx_desc {
 282         u16                     Length:14;
 283         u16                     CRC32:1;
 284         u16                     ICV:1;
 285         u8                      RxDrvInfoSize;
 286         u8                      Shift:2;
 287         u8                      PHYStatus:1;
 288         u8                      SWDec:1;
 289         u8                      LastSeg:1;
 290         u8                      FirstSeg:1;
 291         u8                      EOR:1;
 292         u8                      OWN:1;
 293
 294         u32                     Reserved2;
 295
 296         u32                     Reserved3;
 297
 298         u32     BufferAddress;
 299
 300 };
 301
 302
 303 struct rx_fwinfo {
 304         u16                     Reserved1:12;
 305         u16                     PartAggr:1;
 306         u16                     FirstAGGR:1;
 307         u16                     Reserved2:2;
 308
 309         u8                      RxRate:7;
 310         u8                      RxHT:1;
 311
 312         u8                      BW:1;
 313         u8                      SPLCP:1;
 314         u8                      Reserved3:2;
 315         u8                      PAM:1;
 316         u8                      Mcast:1;
 317         u8                      Bcast:1;
 318         u8                      Reserved4:1;
 319
 320         u32                     TSFL;
 321
 322 };
 323
 324 #endif