drivers/staging/rtl8192e/rtl8192e/r8190P_rtl8256.c

   1 /******************************************************************************
   2  * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
   3  *
   4  * This program is distributed in the hope that it will be useful, but WITHOUT
   5  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   6  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   7  * more details.
   8  *
   9  * You should have received a copy of the GNU General Public License along with
  10  * this program; if not, write to the Free Software Foundation, Inc.,
  11  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  12  *
  13  * The full GNU General Public License is included in this distribution in the
  14  * file called LICENSE.
  15  *
  16  * Contact Information:
  17  * wlanfae <wlanfae@realtek.com>
  18 ******************************************************************************/
  19
  20 #include "rtl_core.h"
  21 #include "r8192E_phyreg.h"
  22 #include "r8192E_phy.h"
  23 #include "r8190P_rtl8256.h"
  24
  25 void rtl92e_set_bandwidth(struct net_device *dev,
  26                           enum ht_channel_width Bandwidth)
  27 {
  28         u8      eRFPath;
  29         struct r8192_priv *priv = rtllib_priv(dev);
  30
  31         if (priv->card_8192_version != VERSION_8190_BD &&
  32             priv->card_8192_version != VERSION_8190_BE) {
  33                 netdev_warn(dev, "%s(): Unknown HW version.\n", __func__);
  34                 return;
  35         }
  36
  37         for (eRFPath = 0; eRFPath < priv->NumTotalRFPath; eRFPath++) {
  38                 if (!rtl92e_is_legal_rf_path(dev, eRFPath))
  39                                 continue;
  40
  41                 switch (Bandwidth) {
  42                 case HT_CHANNEL_WIDTH_20:
  43                         rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath,
  44                                           0x0b, bMask12Bits, 0x100);
  45                         rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath,
  46                                           0x2c, bMask12Bits, 0x3d7);
  47                         rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath,
  48                                           0x0e, bMask12Bits, 0x021);
  49                         break;
  50                 case HT_CHANNEL_WIDTH_20_40:
  51                         rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath,
  52                                           0x0b, bMask12Bits, 0x300);
  53                         rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath,
  54                                           0x2c, bMask12Bits, 0x3ff);
  55                         rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath,
  56                                           0x0e, bMask12Bits, 0x0e1);
  57                         break;
  58                 default:
  59                         netdev_err(dev, "%s(): Unknown bandwidth: %#X\n",
  60                                    __func__, Bandwidth);
  61                         break;
  62
  63                 }
  64         }
  65 }
  66
  67 bool rtl92e_config_rf(struct net_device *dev)
  68 {
  69         u32     u4RegValue = 0;
  70         u8      eRFPath;
  71         bool rtStatus = true;
  72         struct bb_reg_definition *pPhyReg;
  73         struct r8192_priv *priv = rtllib_priv(dev);
  74         u32     RegOffSetToBeCheck = 0x3;
  75         u32     RegValueToBeCheck = 0x7f1;
  76         u32     RF3_Final_Value = 0;
  77         u8      ConstRetryTimes = 5, RetryTimes = 5;
  78         u8 ret = 0;
  79
  80         priv->NumTotalRFPath = RTL819X_TOTAL_RF_PATH;
  81
  82         for (eRFPath = (enum rf90_radio_path)RF90_PATH_A;
  83              eRFPath < priv->NumTotalRFPath; eRFPath++) {
  84                 if (!rtl92e_is_legal_rf_path(dev, eRFPath))
  85                                 continue;
  86
  87                 pPhyReg = &priv->PHYRegDef[eRFPath];
  88
  89
  90                 switch (eRFPath) {
  91                 case RF90_PATH_A:
  92                 case RF90_PATH_C:
  93                         u4RegValue = rtl92e_get_bb_reg(dev, pPhyReg->rfintfs,
  94                                                        bRFSI_RFENV);
  95                         break;
  96                 case RF90_PATH_B:
  97                 case RF90_PATH_D:
  98                         u4RegValue = rtl92e_get_bb_reg(dev, pPhyReg->rfintfs,
  99                                                        bRFSI_RFENV<<16);
 100                         break;
 101                 }
 102
 103                 rtl92e_set_bb_reg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
 104
 105                 rtl92e_set_bb_reg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
 106
 107                 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2,
 108                                   b3WireAddressLength, 0x0);
 109                 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2,
 110                                   b3WireDataLength, 0x0);
 111
 112                 rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath, 0x0,
 113                                   bMask12Bits, 0xbf);
 114
 115                 rtStatus = rtl92e_check_bb_and_rf(dev, HW90_BLOCK_RF,
 116                                                   (enum rf90_radio_path)eRFPath);
 117                 if (!rtStatus) {
 118                         netdev_err(dev, "%s(): Failed to check RF Path %d.\n",
 119                                    __func__, eRFPath);
 120                         goto fail;
 121                 }
 122
 123                 RetryTimes = ConstRetryTimes;
 124                 RF3_Final_Value = 0;
 125                 while (RF3_Final_Value != RegValueToBeCheck &&
 126                        RetryTimes != 0) {
 127                         ret = rtl92e_config_rf_path(dev,
 128                                                 (enum rf90_radio_path)eRFPath);
 129                         RF3_Final_Value = rtl92e_get_rf_reg(dev,
 130                                                 (enum rf90_radio_path)eRFPath,
 131                                                 RegOffSetToBeCheck,
 132                                                 bMask12Bits);
 133                         RT_TRACE(COMP_RF,
 134                                  "RF %d %d register final value: %x\n",
 135                                  eRFPath, RegOffSetToBeCheck,
 136                                  RF3_Final_Value);
 137                         RetryTimes--;
 138                 }
 139
 140                 switch (eRFPath) {
 141                 case RF90_PATH_A:
 142                 case RF90_PATH_C:
 143                         rtl92e_set_bb_reg(dev, pPhyReg->rfintfs, bRFSI_RFENV,
 144                                           u4RegValue);
 145                         break;
 146                 case RF90_PATH_B:
 147                 case RF90_PATH_D:
 148                         rtl92e_set_bb_reg(dev, pPhyReg->rfintfs,
 149                                           bRFSI_RFENV<<16, u4RegValue);
 150                         break;
 151                 }
 152
 153                 if (ret) {
 154                         netdev_err(dev,
 155                                    "%s(): Failed to initialize RF Path %d.\n",
 156                                    __func__, eRFPath);
 157                         goto fail;
 158                 }
 159
 160         }
 161
 162         RT_TRACE(COMP_PHY, "PHY Initialization Success\n");
 163         return true;
 164
 165 fail:
 166         return false;
 167 }
 168
 169 void rtl92e_set_cck_tx_power(struct net_device *dev, u8 powerlevel)
 170 {
 171         u32     TxAGC = 0;
 172         struct r8192_priv *priv = rtllib_priv(dev);
 173
 174         TxAGC = powerlevel;
 175         if (priv->bDynamicTxLowPower) {
 176                 if (priv->CustomerID == RT_CID_819x_Netcore)
 177                         TxAGC = 0x22;
 178                 else
 179                         TxAGC += priv->CckPwEnl;
 180         }
 181         if (TxAGC > 0x24)
 182                 TxAGC = 0x24;
 183         rtl92e_set_bb_reg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC);
 184 }
 185
 186
 187 void rtl92e_set_ofdm_tx_power(struct net_device *dev, u8 powerlevel)
 188 {
 189         struct r8192_priv *priv = rtllib_priv(dev);
 190         u32 writeVal, powerBase0, powerBase1, writeVal_tmp;
 191         u8 index = 0;
 192         u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c};
 193         u8 byte0, byte1, byte2, byte3;
 194
 195         powerBase0 = powerlevel + priv->LegacyHTTxPowerDiff;
 196         powerBase0 = (powerBase0 << 24) | (powerBase0 << 16) |
 197                      (powerBase0 << 8) | powerBase0;
 198         powerBase1 = powerlevel;
 199         powerBase1 = (powerBase1 << 24) | (powerBase1 << 16) |
 200                      (powerBase1 << 8) | powerBase1;
 201
 202         for (index = 0; index < 6; index++) {
 203                 writeVal = (u32)(priv->MCSTxPowerLevelOriginalOffset[index] +
 204                            ((index < 2) ? powerBase0 : powerBase1));
 205                 byte0 = (u8)(writeVal & 0x7f);
 206                 byte1 = (u8)((writeVal & 0x7f00)>>8);
 207                 byte2 = (u8)((writeVal & 0x7f0000)>>16);
 208                 byte3 = (u8)((writeVal & 0x7f000000)>>24);
 209                 if (byte0 > 0x24)
 210                         byte0 = 0x24;
 211                 if (byte1 > 0x24)
 212                         byte1 = 0x24;
 213                 if (byte2 > 0x24)
 214                         byte2 = 0x24;
 215                 if (byte3 > 0x24)
 216                         byte3 = 0x24;
 217
 218                 if (index == 3) {
 219                         writeVal_tmp = (byte3 << 24) | (byte2 << 16) |
 220                                        (byte1 << 8) | byte0;
 221                         priv->Pwr_Track = writeVal_tmp;
 222                 }
 223
 224                 if (priv->bDynamicTxHighPower)
 225                         writeVal = 0x03030303;
 226                 else
 227                         writeVal = (byte3 << 24) | (byte2 << 16) |
 228                                    (byte1 << 8) | byte0;
 229                 rtl92e_set_bb_reg(dev, RegOffset[index], 0x7f7f7f7f, writeVal);
 230         }
 231
 232 }