1 /******************************************************************************
2 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
4 * This program is distributed in the hope that it will be useful, but WITHOUT
5 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
6 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
9 * The full GNU General Public License is included in this distribution in the
10 * file called LICENSE.
12 * Contact Information:
13 * wlanfae <wlanfae@realtek.com>
14 ******************************************************************************/
20 enum baseband_config {
21 BaseBand_Config_PHY_REG = 0,
22 BaseBand_Config_AGC_TAB = 1,
25 #define RTL8187_REQT_READ 0xc0
26 #define RTL8187_REQT_WRITE 0x40
27 #define RTL8187_REQ_GET_REGS 0x05
28 #define RTL8187_REQ_SET_REGS 0x05
32 #define RX_URB_SIZE 9100
34 #define BB_ANTATTEN_CHAN14 0x0c
35 #define BB_ANTENNA_B 0x40
37 #define BB_HOST_BANG (1<<30)
38 #define BB_HOST_BANG_EN (1<<2)
39 #define BB_HOST_BANG_CLK (1<<1)
40 #define BB_HOST_BANG_RW (1<<3)
41 #define BB_HOST_BANG_DATA 1
43 #define RTL8190_EEPROM_ID 0x8129
44 #define EEPROM_VID 0x02
45 #define EEPROM_DID 0x04
46 #define EEPROM_NODE_ADDRESS_BYTE_0 0x0C
48 #define EEPROM_TxPowerDiff 0x1F
51 #define EEPROM_PwDiff 0x21
52 #define EEPROM_CrystalCap 0x22
56 #define EEPROM_TxPwIndex_CCK_V1 0x29
57 #define EEPROM_TxPwIndex_OFDM_24G_V1 0x2C
58 #define EEPROM_TxPwIndex_Ver 0x27
60 #define EEPROM_Default_TxPowerDiff 0x0
61 #define EEPROM_Default_ThermalMeter 0x77
62 #define EEPROM_Default_AntTxPowerDiff 0x0
63 #define EEPROM_Default_TxPwDiff_CrystalCap 0x5
64 #define EEPROM_Default_PwDiff 0x4
65 #define EEPROM_Default_CrystalCap 0x5
66 #define EEPROM_Default_TxPower 0x1010
67 #define EEPROM_ICVersion_ChannelPlan 0x7C
68 #define EEPROM_Customer_ID 0x7B
69 #define EEPROM_RFInd_PowerDiff 0x28
70 #define EEPROM_ThermalMeter 0x29
71 #define EEPROM_TxPwDiff_CrystalCap 0x2A
72 #define EEPROM_TxPwIndex_CCK 0x2C
73 #define EEPROM_TxPwIndex_OFDM_24G 0x3A
74 #define EEPROM_Default_TxPowerLevel 0x10
75 #define EEPROM_IC_VER 0x7d
76 #define EEPROM_CRC 0x7e
78 #define EEPROM_CID_DEFAULT 0x0
79 #define EEPROM_CID_CAMEO 0x1
80 #define EEPROM_CID_RUNTOP 0x2
81 #define EEPROM_CID_Senao 0x3
82 #define EEPROM_CID_TOSHIBA 0x4
83 #define EEPROM_CID_NetCore 0x5
84 #define EEPROM_CID_Nettronix 0x6
85 #define EEPROM_CID_Pronet 0x7
86 #define EEPROM_CID_DLINK 0x8
87 #define EEPROM_CID_WHQL 0xFE
96 #define MXDMA2_16bytes 0x000
97 #define MXDMA2_32bytes 0x001
98 #define MXDMA2_64bytes 0x010
99 #define MXDMA2_128bytes 0x011
100 #define MXDMA2_256bytes 0x100
101 #define MXDMA2_512bytes 0x101
102 #define MXDMA2_1024bytes 0x110
103 #define MXDMA2_NoLimit 0x7
105 #define MULRW_SHIFT 3
106 #define MXDMA2_RX_SHIFT 4
107 #define MXDMA2_TX_SHIFT 0
110 #define EPROM_CMD_RESERVED_MASK BIT5
111 #define EPROM_CMD_9356SEL BIT4
112 #define EPROM_CMD_OPERATING_MODE_SHIFT 6
113 #define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6))
114 #define EPROM_CMD_CONFIG 0x3
115 #define EPROM_CMD_NORMAL 0
116 #define EPROM_CMD_LOAD 1
117 #define EPROM_CMD_PROGRAM 2
118 #define EPROM_CS_BIT 3
119 #define EPROM_CK_BIT 2
120 #define EPROM_W_BIT 1
121 #define EPROM_R_BIT 0
124 #define AFR_CardBEn (1<<0)
125 #define AFR_CLKRUN_SEL (1<<1)
126 #define AFR_FuncRegEn (1<<2)
129 #define BB_GLOBAL_RESET_BIT 0x1
130 BB_GLOBAL_RESET = 0x020,
136 #define CR_MulRW 0x01
140 #define RCR_FILTER_MASK (BIT0 | BIT1 | BIT2 | BIT3 | BIT5 | BIT12 | \
141 BIT18 | BIT19 | BIT20 | BIT21 | BIT22 | BIT23)
142 #define RCR_ONLYERLPKT BIT31
143 #define RCR_ENCS2 BIT30
144 #define RCR_ENCS1 BIT29
145 #define RCR_ENMBID BIT27
146 #define RCR_ACKTXBW (BIT24|BIT25)
147 #define RCR_CBSSID BIT23
148 #define RCR_APWRMGT BIT22
149 #define RCR_ADD3 BIT21
150 #define RCR_AMF BIT20
151 #define RCR_ACF BIT19
152 #define RCR_ADF BIT18
153 #define RCR_RXFTH BIT13
154 #define RCR_AICV BIT12
155 #define RCR_ACRC32 BIT5
160 #define RCR_MXDMA_OFFSET 8
161 #define RCR_FIFO_OFFSET 13
170 #define AC_PARAM_TXOP_LIMIT_OFFSET 16
171 #define AC_PARAM_ECW_MAX_OFFSET 12
172 #define AC_PARAM_ECW_MIN_OFFSET 8
173 #define AC_PARAM_AIFS_OFFSET 0
177 #define BCN_TCFG_CW_SHIFT 8
178 #define BCN_TCFG_IFS 0
179 BCN_INTERVAL = 0x070,
181 BCN_DRV_EARLY_INT = 0x074,
182 #define BCN_DRV_EARLY_INT_SWBCN_SHIFT 8
183 #define BCN_DRV_EARLY_INT_TIME_SHIFT 0
185 BCN_ERR_THRESH = 0x078,
187 #define CAM_CM_SecCAMPolling BIT31
188 #define CAM_CM_SecCAMClr BIT30
189 #define CAM_CM_SecCAMWE BIT16
190 #define CAM_VALID BIT15
191 #define CAM_NOTVALID 0x0000
192 #define CAM_USEDK BIT5
195 #define CAM_WEP40 0x01
196 #define CAM_TKIP 0x02
198 #define CAM_WEP104 0x05
200 #define TOTAL_CAM_ENTRY 32
202 #define CAM_CONFIG_USEDK true
203 #define CAM_CONFIG_NO_USEDK false
204 #define CAM_WRITE BIT16
205 #define CAM_READ 0x00000000
206 #define CAM_POLLINIG BIT31
207 #define SCR_UseDK 0x01
211 #define SCR_TxUseDK BIT0
212 #define SCR_RxUseDK BIT1
213 #define SCR_TxEncEnable BIT2
214 #define SCR_RxDecEnable BIT3
215 #define SCR_SKByA2 BIT4
216 #define SCR_NoSKMC BIT5
219 #define IMR8190_DISABLED 0x0
220 #define IMR_ATIMEND BIT28
221 #define IMR_TBDOK BIT27
222 #define IMR_TBDER BIT26
223 #define IMR_TXFOVW BIT15
224 #define IMR_TIMEOUT0 BIT14
225 #define IMR_BcnInt BIT13
226 #define IMR_RXFOVW BIT12
227 #define IMR_RDU BIT11
228 #define IMR_RXCMDOK BIT10
229 #define IMR_BDOK BIT9
230 #define IMR_HIGHDOK BIT8
231 #define IMR_COMDOK BIT7
232 #define IMR_MGNTDOK BIT6
233 #define IMR_HCCADOK BIT5
234 #define IMR_BKDOK BIT4
235 #define IMR_BEDOK BIT3
236 #define IMR_VIDOK BIT2
237 #define IMR_VODOK BIT1
241 #define TPPoll_BKQ BIT0
242 #define TPPoll_BEQ BIT1
243 #define TPPoll_VIQ BIT2
244 #define TPPoll_VOQ BIT3
245 #define TPPoll_BQ BIT4
246 #define TPPoll_CQ BIT5
247 #define TPPoll_MQ BIT6
248 #define TPPoll_HQ BIT7
249 #define TPPoll_HCCAQ BIT8
250 #define TPPoll_StopBK BIT9
251 #define TPPoll_StopBE BIT10
252 #define TPPoll_StopVI BIT11
253 #define TPPoll_StopVO BIT12
254 #define TPPoll_StopMgt BIT13
255 #define TPPoll_StopHigh BIT14
256 #define TPPoll_StopHCCA BIT15
257 #define TPPoll_SHIFT 8
264 #define CPU_CCK_LOOPBACK 0x00030000
265 #define CPU_GEN_SYSTEM_RESET 0x00000001
266 #define CPU_GEN_FIRMWARE_RESET 0x00000008
267 #define CPU_GEN_BOOT_RDY 0x00000010
268 #define CPU_GEN_FIRM_RDY 0x00000020
269 #define CPU_GEN_PUT_CODE_OK 0x00000080
270 #define CPU_GEN_BB_RST 0x00000100
271 #define CPU_GEN_PWR_STB_CPU 0x00000004
272 #define CPU_GEN_NO_LOOPBACK_MSK 0xFFF8FFFF
273 #define CPU_GEN_NO_LOOPBACK_SET 0x00080000
274 #define CPU_GEN_GPIO_UART 0x00007000
281 #define AcmHw_HwEn BIT0
282 #define AcmHw_BeqEn BIT1
283 #define AcmHw_ViqEn BIT2
284 #define AcmHw_VoqEn BIT3
285 #define AcmHw_BeqStatus BIT4
286 #define AcmHw_ViqStatus BIT5
287 #define AcmHw_VoqStatus BIT6
289 #define AcmFw_BeqStatus BIT0
290 #define AcmFw_ViqStatus BIT1
291 #define AcmFw_VoqStatus BIT2
319 NHM_THRESHOLD0 = 0x253,
320 NHM_THRESHOLD1 = 0x254,
321 NHM_THRESHOLD2 = 0x255,
322 NHM_THRESHOLD3 = 0x256,
323 NHM_THRESHOLD4 = 0x257,
324 NHM_THRESHOLD5 = 0x258,
325 NHM_THRESHOLD6 = 0x259,
329 NHM_RPI_COUNTER0 = 0x264,
330 NHM_RPI_COUNTER1 = 0x265,
331 NHM_RPI_COUNTER2 = 0x266,
332 NHM_RPI_COUNTER3 = 0x267,
333 NHM_RPI_COUNTER4 = 0x268,
334 NHM_RPI_COUNTER5 = 0x269,
335 NHM_RPI_COUNTER6 = 0x26A,
336 NHM_RPI_COUNTER7 = 0x26B,
342 #define BW_OPMODE_11J BIT0
343 #define BW_OPMODE_5G BIT1
344 #define BW_OPMODE_20MHZ BIT2
347 #define MSR_LINK_MASK ((1<<0)|(1<<1))
348 #define MSR_LINK_MANAGED 2
349 #define MSR_LINK_NONE 0
350 #define MSR_LINK_SHIFT 0
351 #define MSR_LINK_ADHOC 1
352 #define MSR_LINK_MASTER 3
353 #define MSR_LINK_ENEDCA (1<<4)
355 #define MSR_NOLINK 0x00
356 #define MSR_ADHOC 0x01
357 #define MSR_INFRA 0x02
361 #define RETRY_LIMIT_SHORT_SHIFT 8
362 #define RETRY_LIMIT_LONG_SHIFT 0
365 #define RRSR_RSC_OFFSET 21
366 #define RRSR_SHORT_OFFSET 23
367 #define RRSR_RSC_DUPLICATE 0x600000
368 #define RRSR_RSC_UPSUBCHNL 0x400000
369 #define RRSR_RSC_LOWSUBCHNL 0x200000
370 #define RRSR_SHORT 0x800000
373 #define RRSR_5_5M BIT2
374 #define RRSR_11M BIT3
377 #define RRSR_12M BIT6
378 #define RRSR_18M BIT7
379 #define RRSR_24M BIT8
380 #define RRSR_36M BIT9
381 #define RRSR_48M BIT10
382 #define RRSR_54M BIT11
383 #define RRSR_MCS0 BIT12
384 #define RRSR_MCS1 BIT13
385 #define RRSR_MCS2 BIT14
386 #define RRSR_MCS3 BIT15
387 #define RRSR_MCS4 BIT16
388 #define RRSR_MCS5 BIT17
389 #define RRSR_MCS6 BIT18
390 #define RRSR_MCS7 BIT19
391 #define BRSR_AckShortPmb BIT23
394 #define RATR_1M 0x00000001
395 #define RATR_2M 0x00000002
396 #define RATR_55M 0x00000004
397 #define RATR_11M 0x00000008
398 #define RATR_6M 0x00000010
399 #define RATR_9M 0x00000020
400 #define RATR_12M 0x00000040
401 #define RATR_18M 0x00000080
402 #define RATR_24M 0x00000100
403 #define RATR_36M 0x00000200
404 #define RATR_48M 0x00000400
405 #define RATR_54M 0x00000800
406 #define RATR_MCS0 0x00001000
407 #define RATR_MCS1 0x00002000
408 #define RATR_MCS2 0x00004000
409 #define RATR_MCS3 0x00008000
410 #define RATR_MCS4 0x00010000
411 #define RATR_MCS5 0x00020000
412 #define RATR_MCS6 0x00040000
413 #define RATR_MCS7 0x00080000
414 #define RATR_MCS8 0x00100000
415 #define RATR_MCS9 0x00200000
416 #define RATR_MCS10 0x00400000
417 #define RATR_MCS11 0x00800000
418 #define RATR_MCS12 0x01000000
419 #define RATR_MCS13 0x02000000
420 #define RATR_MCS14 0x04000000
421 #define RATR_MCS15 0x08000000
422 #define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | RATR_11M)
423 #define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | RATR_12M | RATR_18M | \
424 RATR_24M | RATR_36M | RATR_48M | RATR_54M)
425 #define RATE_ALL_OFDM_1SS (RATR_MCS0 | RATR_MCS1 | RATR_MCS2 | \
426 RATR_MCS3 | RATR_MCS4 | RATR_MCS5 | \
427 RATR_MCS6 | RATR_MCS7)
428 #define RATE_ALL_OFDM_2SS (RATR_MCS8 | RATR_MCS9 | RATR_MCS10 | \
429 RATR_MCS11 | RATR_MCS12 | RATR_MCS13 | \
430 RATR_MCS14|RATR_MCS15)
445 #define HWSET_MAX_SIZE_92S 128
447 #define ANAPAR_FOR_8192PciE 0x17