drivers/staging/rtl8192e/rtl8192e/rtl_dm.h

   1 /******************************************************************************
   2  * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
   3  *
   4  * This program is distributed in the hope that it will be useful, but WITHOUT
   5  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   6  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   7  * more details.
   8  *
   9  * You should have received a copy of the GNU General Public License along with
  10  * this program; if not, write to the Free Software Foundation, Inc.,
  11  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  12  *
  13  * The full GNU General Public License is included in this distribution in the
  14  * file called LICENSE.
  15  *
  16  * Contact Information:
  17  * wlanfae <wlanfae@realtek.com>
  18 ******************************************************************************/
  19 #ifndef __R8192UDM_H__
  20 #define __R8192UDM_H__
  21
  22
  23 /*--------------------------Define Parameters-------------------------------*/
  24 #define                 OFDM_Table_Length       19
  25 #define         CCK_Table_length        12
  26
  27 #define         DM_DIG_THRESH_HIGH                                      40
  28 #define         DM_DIG_THRESH_LOW                                       35
  29
  30 #define         DM_DIG_HIGH_PWR_THRESH_HIGH             75
  31 #define         DM_DIG_HIGH_PWR_THRESH_LOW              70
  32
  33 #define         BW_AUTO_SWITCH_HIGH_LOW                 25
  34 #define         BW_AUTO_SWITCH_LOW_HIGH                 30
  35
  36 #define         DM_DIG_BACKOFF                          12
  37 #define         DM_DIG_MAX                                      0x36
  38 #define         DM_DIG_MIN                                      0x1c
  39 #define         DM_DIG_MIN_Netcore                      0x12
  40
  41 #define         RxPathSelection_SS_TH_low               30
  42 #define         RxPathSelection_diff_TH                 18
  43
  44 #define         RateAdaptiveTH_High                     50
  45 #define         RateAdaptiveTH_Low_20M          30
  46 #define         RateAdaptiveTH_Low_40M          10
  47 #define         VeryLowRSSI                                     15
  48
  49 #define         WAIotTHVal                                              25
  50
  51 #define         E_FOR_TX_POWER_TRACK           300
  52 #define         TX_POWER_NEAR_FIELD_THRESH_HIGH         68
  53 #define         TX_POWER_NEAR_FIELD_THRESH_LOW          62
  54 #define  TX_POWER_ATHEROAP_THRESH_HIGH     78
  55 #define         TX_POWER_ATHEROAP_THRESH_LOW            72
  56
  57 #define                 Current_Tx_Rate_Reg      0x1e0
  58 #define                 Initial_Tx_Rate_Reg      0x1e1
  59 #define                 Tx_Retry_Count_Reg       0x1ac
  60 #define         RegC38_TH                                20
  61
  62 #define         DM_Type_ByDriver                1
  63
  64 /*--------------------------Define Parameters-------------------------------*/
  65
  66
  67 /*------------------------------Define structure----------------------------*/
  68 struct dig_t {
  69         u8              dig_enable_flag;
  70         u8              dig_algorithm;
  71         u8              dig_algorithm_switch;
  72
  73         long            rssi_low_thresh;
  74         long            rssi_high_thresh;
  75
  76         long            rssi_high_power_lowthresh;
  77         long            rssi_high_power_highthresh;
  78
  79         u8              dig_state;
  80         u8              dig_highpwr_state;
  81         u8              CurSTAConnectState;
  82         u8              PreSTAConnectState;
  83
  84         u8              curpd_thstate;
  85         u8              prepd_thstate;
  86         u8              curcs_ratio_state;
  87         u8              precs_ratio_state;
  88
  89         u32             pre_ig_value;
  90         u32             cur_ig_value;
  91
  92         u8              backoff_val;
  93         u8              rx_gain_range_max;
  94         u8              rx_gain_range_min;
  95
  96         long            rssi_val;
  97 };
  98
  99 enum dm_dig_sta {
 100         DM_STA_DIG_OFF = 0,
 101         DM_STA_DIG_ON,
 102         DM_STA_DIG_MAX
 103 };
 104
 105
 106 enum dm_ratr_sta {
 107         DM_RATR_STA_HIGH = 0,
 108         DM_RATR_STA_MIDDLE = 1,
 109         DM_RATR_STA_LOW = 2,
 110         DM_RATR_STA_MAX
 111 };
 112
 113 enum dm_dig_alg {
 114         DIG_ALGO_BY_FALSE_ALARM = 0,
 115         DIG_ALGO_BY_RSSI        = 1,
 116         DIG_ALGO_BEFORE_CONNECT_BY_RSSI_AND_ALARM = 2,
 117         DIG_ALGO_BY_TOW_PORT = 3,
 118         DIG_ALGO_MAX
 119 };
 120
 121 enum dm_dig_connect {
 122         DIG_STA_DISCONNECT = 0,
 123         DIG_STA_CONNECT = 1,
 124         DIG_STA_BEFORE_CONNECT = 2,
 125         DIG_AP_DISCONNECT = 3,
 126         DIG_AP_CONNECT = 4,
 127         DIG_AP_ADD_STATION = 5,
 128         DIG_CONNECT_MAX
 129 };
 130
 131 enum dm_dig_pd_th {
 132         DIG_PD_AT_LOW_POWER = 0,
 133         DIG_PD_AT_NORMAL_POWER = 1,
 134         DIG_PD_AT_HIGH_POWER = 2,
 135         DIG_PD_MAX
 136 };
 137
 138 enum dm_dig_cs_ratio {
 139         DIG_CS_RATIO_LOWER = 0,
 140         DIG_CS_RATIO_HIGHER = 1,
 141         DIG_CS_MAX
 142 };
 143
 144 struct drx_path_sel {
 145         u8              Enable;
 146         u8              cck_method;
 147         u8              cck_Rx_path;
 148
 149         u8              SS_TH_low;
 150         u8              diff_TH;
 151         u8              disabledRF;
 152         u8              reserved;
 153
 154         u8              rf_rssi[4];
 155         u8              rf_enable_rssi_th[4];
 156         long            cck_pwdb_sta[4];
 157 };
 158
 159 enum dm_cck_rx_path_method {
 160         CCK_Rx_Version_1 = 0,
 161         CCK_Rx_Version_2 = 1,
 162         CCK_Rx_Version_MAX
 163 };
 164
 165
 166 struct dcmd_txcmd {
 167         u32     Op;
 168         u32     Length;
 169         u32     Value;
 170 };
 171 /*------------------------------Define structure----------------------------*/
 172
 173
 174 /*------------------------Export global variable----------------------------*/
 175 extern  struct dig_t dm_digtable;
 176 extern struct drx_path_sel DM_RxPathSelTable;
 177
 178 /* Pre-calculated gain tables */
 179 extern const u32 dm_tx_bb_gain[TxBBGainTableLength];
 180 extern const u8 dm_cck_tx_bb_gain[CCKTxBBGainTableLength][8];
 181 extern const u8 dm_cck_tx_bb_gain_ch14[CCKTxBBGainTableLength][8];
 182 /* Maps table index to iq amplify gain (dB, 12 to -24dB) */
 183 #define dm_tx_bb_gain_idx_to_amplify(idx) (-idx + 12)
 184
 185 /*------------------------Export global variable----------------------------*/
 186
 187
 188 /*--------------------------Exported Function prototype---------------------*/
 189 /*--------------------------Exported Function prototype---------------------*/
 190
 191 void rtl92e_dm_init(struct net_device *dev);
 192 void rtl92e_dm_deinit(struct net_device *dev);
 193
 194 void rtl92e_dm_watchdog(struct net_device *dev);
 195
 196
 197 void    rtl92e_init_adaptive_rate(struct net_device *dev);
 198 void    rtl92e_dm_txpower_tracking_wq(void *data);
 199
 200 void rtl92e_dm_cck_txpower_adjust(struct net_device *dev, bool binch14);
 201
 202 void    rtl92e_dm_restore_state(struct net_device *dev);
 203 void    rtl92e_dm_backup_state(struct net_device *dev);
 204 void    rtl92e_dm_init_edca_turbo(struct net_device *dev);
 205 void    rtl92e_dm_rf_pathcheck_wq(void *data);
 206 void rtl92e_dm_init_txpower_tracking(struct net_device *dev);
 207 #endif  /*__R8192UDM_H__ */