drivers/staging/rtl8192u/r8190_rtl8256.c

   1 /*
   2   This is part of the rtl8192 driver
   3   released under the GPL (See file COPYING for details).
   4
   5   This files contains programming code for the rtl8256
   6   radio frontend.
   7
   8   *Many* thanks to Realtek Corp. for their great support!
   9
  10 */
  11
  12 #include "r8192U.h"
  13 #include "r8192U_hw.h"
  14 #include "r819xU_phyreg.h"
  15 #include "r819xU_phy.h"
  16 #include "r8190_rtl8256.h"
  17
  18 /*--------------------------------------------------------------------------
  19  * Overview:    set RF band width (20M or 40M)
  20  * Input:       struct net_device*      dev
  21  *              WIRELESS_BANDWIDTH_E    Bandwidth       //20M or 40M
  22  * Output:      NONE
  23  * Return:      NONE
  24  * Note:        8226 support both 20M  and 40 MHz
  25  *---------------------------------------------------------------------------*/
  26 void PHY_SetRF8256Bandwidth(struct net_device *dev , HT_CHANNEL_WIDTH Bandwidth)
  27 {
  28         u8      eRFPath;
  29         struct r8192_priv *priv = ieee80211_priv(dev);
  30
  31         /* for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath;
  32          *  eRFPath++)
  33          */
  34         for (eRFPath = 0; eRFPath < RF90_PATH_MAX; eRFPath++) {
  35                 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
  36                         continue;
  37
  38                 switch (Bandwidth) {
  39                 case HT_CHANNEL_WIDTH_20:
  40                                 if (priv->card_8192_version == VERSION_819xU_A
  41                                         || priv->card_8192_version
  42                                         == VERSION_819xU_B) { /* 8256 D-cut, E-cut, xiong: consider it later! */
  43                                         rtl8192_phy_SetRFReg(dev,
  44                                                 (RF90_RADIO_PATH_E)eRFPath,
  45                                                 0x0b, bMask12Bits, 0x100); /* phy para:1ba */
  46                                         rtl8192_phy_SetRFReg(dev,
  47                                                 (RF90_RADIO_PATH_E)eRFPath,
  48                                                 0x2c, bMask12Bits, 0x3d7);
  49                                         rtl8192_phy_SetRFReg(dev,
  50                                                 (RF90_RADIO_PATH_E)eRFPath,
  51                                                 0x0e, bMask12Bits, 0x021);
  52
  53                                         /* cosa add for sd3's request 01/23/2008
  54                                          */
  55                                         rtl8192_phy_SetRFReg(dev,
  56                                                 (RF90_RADIO_PATH_E)eRFPath,
  57                                                 0x14, bMask12Bits, 0x5ab);
  58                                 } else {
  59                                         RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown hardware version\n");
  60                                         }
  61                                 break;
  62                 case HT_CHANNEL_WIDTH_20_40:
  63                                 if (priv->card_8192_version == VERSION_819xU_A || priv->card_8192_version == VERSION_819xU_B) { /* 8256 D-cut, E-cut, xiong: consider it later! */
  64                                         rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0b, bMask12Bits, 0x300); //phy para:3ba
  65                                         rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3df);
  66                                         rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0e, bMask12Bits, 0x0a1);
  67
  68                                         //cosa add for sd3's request 01/23/2008
  69                                         if (priv->chan == 3 || priv->chan == 9)
  70                                                 //I need to set priv->chan whenever current channel changes
  71                                                 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x14, bMask12Bits, 0x59b);
  72                                         else
  73                                                 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x14, bMask12Bits, 0x5ab);
  74                                 } else {
  75                                         RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown hardware version\n");
  76                                         }
  77                                 break;
  78                 default:
  79                                 RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown Bandwidth: %#X\n", Bandwidth);
  80                                 break;
  81
  82                 }
  83         }
  84 }
  85 /*--------------------------------------------------------------------------
  86  * Overview:    Interface to config 8256
  87  * Input:       struct net_device*      dev
  88  * Output:      NONE
  89  * Return:      NONE
  90  *---------------------------------------------------------------------------*/
  91 void PHY_RF8256_Config(struct net_device *dev)
  92 {
  93         struct r8192_priv *priv = ieee80211_priv(dev);
  94         // Initialize general global value
  95         //
  96         // TODO: Extend RF_PATH_C and RF_PATH_D in the future
  97         priv->NumTotalRFPath = RTL819X_TOTAL_RF_PATH;
  98         // Config BB and RF
  99         phy_RF8256_Config_ParaFile(dev);
 100 }
 101 /*--------------------------------------------------------------------------
 102  * Overview:    Interface to config 8256
 103  * Input:       struct net_device*      dev
 104  * Output:      NONE
 105  * Return:      NONE
 106  *---------------------------------------------------------------------------*/
 107 void phy_RF8256_Config_ParaFile(struct net_device *dev)
 108 {
 109         u32     u4RegValue = 0;
 110         //static s1Byte                         szRadioAFile[] = RTL819X_PHY_RADIO_A;
 111         //static s1Byte                         szRadioBFile[] = RTL819X_PHY_RADIO_B;
 112         //static s1Byte                         szRadioCFile[] = RTL819X_PHY_RADIO_C;
 113         //static s1Byte                         szRadioDFile[] = RTL819X_PHY_RADIO_D;
 114         u8      eRFPath;
 115         BB_REGISTER_DEFINITION_T        *pPhyReg;
 116         struct r8192_priv *priv = ieee80211_priv(dev);
 117         u32     RegOffSetToBeCheck = 0x3;
 118         u32     RegValueToBeCheck = 0x7f1;
 119         u32     RF3_Final_Value = 0;
 120         u8      ConstRetryTimes = 5, RetryTimes = 5;
 121         u8 ret = 0;
 122         //3//-----------------------------------------------------------------
 123         //3// <2> Initialize RF
 124         //3//-----------------------------------------------------------------
 125         for (eRFPath = (RF90_RADIO_PATH_E)RF90_PATH_A; eRFPath < priv->NumTotalRFPath; eRFPath++) {
 126                 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
 127                         continue;
 128
 129                 pPhyReg = &priv->PHYRegDef[eRFPath];
 130
 131                 // Joseph test for shorten RF config
 132         //      pHalData->RfReg0Value[eRFPath] =  rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, rGlobalCtrl, bMaskDWord);
 133
 134                 /*----Store original RFENV control type----*/
 135                 switch (eRFPath) {
 136                 case RF90_PATH_A:
 137                 case RF90_PATH_C:
 138                         u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV);
 139                         break;
 140                 case RF90_PATH_B:
 141                 case RF90_PATH_D:
 142                         u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16);
 143                         break;
 144                 }
 145
 146                 /*----Set RF_ENV enable----*/
 147                 rtl8192_setBBreg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
 148
 149                 /*----Set RF_ENV output high----*/
 150                 rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
 151
 152                 /* Set bit number of Address and Data for RF register */
 153                 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0);  // Set 0 to 4 bits for Z-serial and set 1 to 6 bits for 8258
 154                 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0);     // Set 0 to 12 bits for Z-serial and 8258, and set 1 to 14 bits for ???
 155
 156                 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E) eRFPath, 0x0, bMask12Bits, 0xbf);
 157
 158                 /*----Check RF block (for FPGA platform only)----*/
 159                 // TODO: this function should be removed on ASIC , Emily 2007.2.2
 160                 if (rtl8192_phy_checkBBAndRF(dev, HW90_BLOCK_RF, (RF90_RADIO_PATH_E)eRFPath)) {
 161                         RT_TRACE(COMP_ERR, "PHY_RF8256_Config():Check Radio[%d] Fail!!\n", eRFPath);
 162                         goto phy_RF8256_Config_ParaFile_Fail;
 163                 }
 164
 165                 RetryTimes = ConstRetryTimes;
 166                 RF3_Final_Value = 0;
 167                 /*----Initialize RF fom connfiguration file----*/
 168                 switch (eRFPath) {
 169                 case RF90_PATH_A:
 170                         while (RF3_Final_Value != RegValueToBeCheck && RetryTimes != 0) {
 171                                 ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, (RF90_RADIO_PATH_E)eRFPath);
 172                                 RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
 173                                 RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
 174                                 RetryTimes--;
 175                         }
 176                         break;
 177                 case RF90_PATH_B:
 178                         while (RF3_Final_Value != RegValueToBeCheck && RetryTimes != 0) {
 179                                 ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, (RF90_RADIO_PATH_E)eRFPath);
 180                                 RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
 181                                 RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
 182                                 RetryTimes--;
 183                         }
 184                         break;
 185                 case RF90_PATH_C:
 186                         while (RF3_Final_Value != RegValueToBeCheck && RetryTimes != 0) {
 187                                 ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, (RF90_RADIO_PATH_E)eRFPath);
 188                                 RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
 189                                 RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
 190                                 RetryTimes--;
 191                         }
 192                         break;
 193                 case RF90_PATH_D:
 194                         while (RF3_Final_Value != RegValueToBeCheck && RetryTimes != 0) {
 195                                 ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, (RF90_RADIO_PATH_E)eRFPath);
 196                                 RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
 197                                 RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
 198                                 RetryTimes--;
 199                         }
 200                         break;
 201                 }
 202
 203                 /*----Restore RFENV control type----*/;
 204                 switch (eRFPath) {
 205                 case RF90_PATH_A:
 206                 case RF90_PATH_C:
 207                         rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
 208                         break;
 209                 case RF90_PATH_B:
 210                 case RF90_PATH_D:
 211                         rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);
 212                         break;
 213                 }
 214
 215                 if (ret) {
 216                         RT_TRACE(COMP_ERR, "phy_RF8256_Config_ParaFile():Radio[%d] Fail!!", eRFPath);
 217                         goto phy_RF8256_Config_ParaFile_Fail;
 218                 }
 219
 220         }
 221
 222         RT_TRACE(COMP_PHY, "PHY Initialization Success\n");
 223         return;
 224
 225 phy_RF8256_Config_ParaFile_Fail:
 226         RT_TRACE(COMP_ERR, "PHY Initialization failed\n");
 227 }
 228
 229
 230 void PHY_SetRF8256CCKTxPower(struct net_device *dev, u8 powerlevel)
 231 {
 232         u32     TxAGC = 0;
 233         struct r8192_priv *priv = ieee80211_priv(dev);
 234         //modified by vivi, 20080109
 235         TxAGC = powerlevel;
 236
 237         if (priv->bDynamicTxLowPower == TRUE) {
 238                 //cosa 05/22/2008 for scan
 239                 if (priv->CustomerID == RT_CID_819x_Netcore)
 240                         TxAGC = 0x22;
 241                 else
 242                         TxAGC += priv->CckPwEnl;
 243         }
 244
 245         if (TxAGC > 0x24)
 246                 TxAGC = 0x24;
 247         rtl8192_setBBreg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC);
 248 }
 249
 250
 251 void PHY_SetRF8256OFDMTxPower(struct net_device *dev, u8 powerlevel)
 252 {
 253         struct r8192_priv *priv = ieee80211_priv(dev);
 254         //Joseph TxPower for 8192 testing
 255         u32 writeVal, powerBase0, powerBase1, writeVal_tmp;
 256         u8 index = 0;
 257         u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c};
 258         u8 byte0, byte1, byte2, byte3;
 259
 260         powerBase0 = powerlevel + priv->TxPowerDiff;    //OFDM rates
 261         powerBase0 = (powerBase0<<24) | (powerBase0<<16) | (powerBase0<<8) | powerBase0;
 262         powerBase1 = powerlevel;                                                        //MCS rates
 263         powerBase1 = (powerBase1<<24) | (powerBase1<<16) | (powerBase1<<8) | powerBase1;
 264
 265         for (index = 0; index < 6; index++) {
 266                 writeVal = priv->MCSTxPowerLevelOriginalOffset[index] + ((index < 2)?powerBase0:powerBase1);
 267                 byte0 = (u8)(writeVal & 0x7f);
 268                 byte1 = (u8)((writeVal & 0x7f00)>>8);
 269                 byte2 = (u8)((writeVal & 0x7f0000)>>16);
 270                 byte3 = (u8)((writeVal & 0x7f000000)>>24);
 271
 272                 if (byte0 > 0x24)
 273                         /* Max power index = 0x24 */
 274                         byte0 = 0x24;
 275                 if (byte1 > 0x24)
 276                         byte1 = 0x24;
 277                 if (byte2 > 0x24)
 278                         byte2 = 0x24;
 279                 if (byte3 > 0x24)
 280                         byte3 = 0x24;
 281
 282                 //for tx power track
 283                 if (index == 3) {
 284                         writeVal_tmp = (byte3<<24) | (byte2<<16) | (byte1<<8) | byte0;
 285                         priv->Pwr_Track = writeVal_tmp;
 286                 }
 287
 288                 if (priv->bDynamicTxHighPower == TRUE) {
 289                         /*Add by Jacken 2008/03/06
 290                          *Emily, 20080613. Set low tx power for both MCS and legacy OFDM
 291                          */
 292                         writeVal = 0x03030303;
 293                 } else {
 294                         writeVal = (byte3<<24) | (byte2<<16) | (byte1<<8) | byte0;
 295                         }
 296                         rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal);
 297         }
 298         return;
 299
 300 }