2 This is part of the rtl8192 driver
3 released under the GPL (See file COPYING for details).
5 This files contains programming code for the rtl8256
8 *Many* thanks to Realtek Corp. for their great support!
13 #include "r8192U_hw.h"
14 #include "r819xU_phyreg.h"
15 #include "r819xU_phy.h"
16 #include "r8190_rtl8256.h"
18 /*--------------------------------------------------------------------------
19 * Overview: set RF band width (20M or 40M)
20 * Input: struct net_device* dev
21 * WIRELESS_BANDWIDTH_E Bandwidth //20M or 40M
24 * Note: 8226 support both 20M and 40 MHz
25 *---------------------------------------------------------------------------*/
26 void PHY_SetRF8256Bandwidth(struct net_device *dev , HT_CHANNEL_WIDTH Bandwidth)
29 struct r8192_priv *priv = ieee80211_priv(dev);
31 /* for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath;
34 for (eRFPath = 0; eRFPath < RF90_PATH_MAX; eRFPath++) {
35 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
39 case HT_CHANNEL_WIDTH_20:
40 if (priv->card_8192_version == VERSION_819xU_A
41 || priv->card_8192_version
42 == VERSION_819xU_B) { /* 8256 D-cut, E-cut, xiong: consider it later! */
43 rtl8192_phy_SetRFReg(dev,
44 (RF90_RADIO_PATH_E)eRFPath,
45 0x0b, bMask12Bits, 0x100); /* phy para:1ba */
46 rtl8192_phy_SetRFReg(dev,
47 (RF90_RADIO_PATH_E)eRFPath,
48 0x2c, bMask12Bits, 0x3d7);
49 rtl8192_phy_SetRFReg(dev,
50 (RF90_RADIO_PATH_E)eRFPath,
51 0x0e, bMask12Bits, 0x021);
52 rtl8192_phy_SetRFReg(dev,
53 (RF90_RADIO_PATH_E)eRFPath,
54 0x14, bMask12Bits, 0x5ab);
56 RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown hardware version\n");
59 case HT_CHANNEL_WIDTH_20_40:
60 if (priv->card_8192_version == VERSION_819xU_A || priv->card_8192_version == VERSION_819xU_B) { /* 8256 D-cut, E-cut, xiong: consider it later! */
61 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0b, bMask12Bits, 0x300); /* phy para:3ba */
62 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3df);
63 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0e, bMask12Bits, 0x0a1);
65 if (priv->chan == 3 || priv->chan == 9)
66 /* I need to set priv->chan whenever current channel changes */
67 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x14, bMask12Bits, 0x59b);
69 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x14, bMask12Bits, 0x5ab);
71 RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown hardware version\n");
75 RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown Bandwidth: %#X\n", Bandwidth);
81 /*--------------------------------------------------------------------------
82 * Overview: Interface to config 8256
83 * Input: struct net_device* dev
86 *---------------------------------------------------------------------------*/
87 void PHY_RF8256_Config(struct net_device *dev)
89 struct r8192_priv *priv = ieee80211_priv(dev);
90 /* Initialize general global value
92 * TODO: Extend RF_PATH_C and RF_PATH_D in the future
94 priv->NumTotalRFPath = RTL819X_TOTAL_RF_PATH;
95 /* Config BB and RF */
96 phy_RF8256_Config_ParaFile(dev);
98 /*--------------------------------------------------------------------------
99 * Overview: Interface to config 8256
100 * Input: struct net_device* dev
103 *---------------------------------------------------------------------------*/
104 void phy_RF8256_Config_ParaFile(struct net_device *dev)
108 BB_REGISTER_DEFINITION_T *pPhyReg;
109 struct r8192_priv *priv = ieee80211_priv(dev);
110 u32 RegOffSetToBeCheck = 0x3;
111 u32 RegValueToBeCheck = 0x7f1;
112 u32 RF3_Final_Value = 0;
113 u8 ConstRetryTimes = 5, RetryTimes = 5;
116 for (eRFPath = (RF90_RADIO_PATH_E)RF90_PATH_A; eRFPath < priv->NumTotalRFPath; eRFPath++) {
117 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
120 pPhyReg = &priv->PHYRegDef[eRFPath];
122 /* Joseph test for shorten RF config
123 * pHalData->RfReg0Value[eRFPath] = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, rGlobalCtrl, bMaskDWord);
124 * ----Store original RFENV control type
129 u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV);
133 u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16);
137 /*----Set RF_ENV enable----*/
138 rtl8192_setBBreg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
140 /*----Set RF_ENV output high----*/
141 rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
143 /* Set bit number of Address and Data for RF register */
144 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); /* Set 0 to 4 bits for Z-serial and set 1 to 6 bits for 8258 */
145 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); /* Set 0 to 12 bits for Z-serial and 8258, and set 1 to 14 bits for ??? */
147 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E) eRFPath, 0x0, bMask12Bits, 0xbf);
149 /* Check RF block (for FPGA platform only)----
150 * TODO: this function should be removed on ASIC , Emily 2007.2.2
152 if (rtl8192_phy_checkBBAndRF(dev, HW90_BLOCK_RF, (RF90_RADIO_PATH_E)eRFPath)) {
153 RT_TRACE(COMP_ERR, "PHY_RF8256_Config():Check Radio[%d] Fail!!\n", eRFPath);
154 goto phy_RF8256_Config_ParaFile_Fail;
157 RetryTimes = ConstRetryTimes;
159 /*----Initialize RF fom connfiguration file----*/
162 while (RF3_Final_Value != RegValueToBeCheck && RetryTimes != 0) {
163 ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, (RF90_RADIO_PATH_E)eRFPath);
164 RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
165 RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
170 while (RF3_Final_Value != RegValueToBeCheck && RetryTimes != 0) {
171 ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, (RF90_RADIO_PATH_E)eRFPath);
172 RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
173 RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
178 while (RF3_Final_Value != RegValueToBeCheck && RetryTimes != 0) {
179 ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, (RF90_RADIO_PATH_E)eRFPath);
180 RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
181 RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
186 while (RF3_Final_Value != RegValueToBeCheck && RetryTimes != 0) {
187 ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, (RF90_RADIO_PATH_E)eRFPath);
188 RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
189 RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
195 /*----Restore RFENV control type----*/;
199 rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
203 rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);
208 RT_TRACE(COMP_ERR, "phy_RF8256_Config_ParaFile():Radio[%d] Fail!!", eRFPath);
209 goto phy_RF8256_Config_ParaFile_Fail;
214 RT_TRACE(COMP_PHY, "PHY Initialization Success\n");
217 phy_RF8256_Config_ParaFile_Fail:
218 RT_TRACE(COMP_ERR, "PHY Initialization failed\n");
222 void PHY_SetRF8256CCKTxPower(struct net_device *dev, u8 powerlevel)
225 struct r8192_priv *priv = ieee80211_priv(dev);
228 if (priv->bDynamicTxLowPower == TRUE) {
229 if (priv->CustomerID == RT_CID_819x_Netcore)
232 TxAGC += priv->CckPwEnl;
237 rtl8192_setBBreg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC);
241 void PHY_SetRF8256OFDMTxPower(struct net_device *dev, u8 powerlevel)
243 struct r8192_priv *priv = ieee80211_priv(dev);
244 /* Joseph TxPower for 8192 testing */
245 u32 writeVal, powerBase0, powerBase1, writeVal_tmp;
247 u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c};
248 u8 byte0, byte1, byte2, byte3;
250 powerBase0 = powerlevel + priv->TxPowerDiff; /* OFDM rates */
251 powerBase0 = (powerBase0<<24) | (powerBase0<<16) | (powerBase0<<8) | powerBase0;
252 powerBase1 = powerlevel; /* MCS rates */
253 powerBase1 = (powerBase1<<24) | (powerBase1<<16) | (powerBase1<<8) | powerBase1;
255 for (index = 0; index < 6; index++) {
256 writeVal = priv->MCSTxPowerLevelOriginalOffset[index] + ((index < 2)?powerBase0:powerBase1);
257 byte0 = (u8)(writeVal & 0x7f);
258 byte1 = (u8)((writeVal & 0x7f00)>>8);
259 byte2 = (u8)((writeVal & 0x7f0000)>>16);
260 byte3 = (u8)((writeVal & 0x7f000000)>>24);
263 /* Max power index = 0x24 */
272 /* for tx power track */
274 writeVal_tmp = (byte3<<24) | (byte2<<16) | (byte1<<8) | byte0;
275 priv->Pwr_Track = writeVal_tmp;
278 if (priv->bDynamicTxHighPower == TRUE) {
279 /*Add by Jacken 2008/03/06
280 *Emily, 20080613. Set low tx power for both MCS and legacy OFDM
282 writeVal = 0x03030303;
284 writeVal = (byte3<<24) | (byte2<<16) | (byte1<<8) | byte0;
286 rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal);