drivers/staging/rtl8192u/r8192U.h

   1 /*
   2    This is part of rtl8187 OpenSource driver.
   3    Copyright (C) Andrea Merello 2004-2005  <andreamrl@tiscali.it>
   4    Released under the terms of GPL (General Public Licence)
   5
   6    Parts of this driver are based on the GPL part of the
   7    official realtek driver
   8
   9    Parts of this driver are based on the rtl8192 driver skeleton
  10    from Patric Schenke & Andres Salomon
  11
  12    Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver
  13
  14    We want to thank the Authors of those projects and the Ndiswrapper
  15    project Authors.
  16 */
  17
  18 #ifndef R819xU_H
  19 #define R819xU_H
  20
  21 #include <linux/module.h>
  22 #include <linux/kernel.h>
  23 #include <linux/init.h>
  24 #include <linux/ioport.h>
  25 #include <linux/sched.h>
  26 #include <linux/types.h>
  27 #include <linux/slab.h>
  28 #include <linux/netdevice.h>
  29 #include <linux/usb.h>
  30 #include <linux/etherdevice.h>
  31 #include <linux/delay.h>
  32 #include <linux/rtnetlink.h>    //for rtnl_lock()
  33 #include <linux/wireless.h>
  34 #include <linux/timer.h>
  35 #include <linux/proc_fs.h>      // Necessary because we use the proc fs
  36 #include <linux/if_arp.h>
  37 #include <linux/random.h>
  38 #include <asm/io.h>
  39 #include "ieee80211/ieee80211.h"
  40
  41 #define RTL8192U
  42 #define RTL819xU_MODULE_NAME "rtl819xU"
  43 //added for HW security, john.0629
  44 #define FALSE 0
  45 #define TRUE 1
  46 #define MAX_KEY_LEN     61
  47 #define KEY_BUF_SIZE    5
  48
  49 #define BIT0            0x00000001
  50 #define BIT1            0x00000002
  51 #define BIT2            0x00000004
  52 #define BIT3            0x00000008
  53 #define BIT4            0x00000010
  54 #define BIT5            0x00000020
  55 #define BIT6            0x00000040
  56 #define BIT7            0x00000080
  57 #define BIT8            0x00000100
  58 #define BIT9            0x00000200
  59 #define BIT10           0x00000400
  60 #define BIT11           0x00000800
  61 #define BIT12           0x00001000
  62 #define BIT13           0x00002000
  63 #define BIT14           0x00004000
  64 #define BIT15           0x00008000
  65 #define BIT16           0x00010000
  66 #define BIT17           0x00020000
  67 #define BIT18           0x00040000
  68 #define BIT19           0x00080000
  69 #define BIT20           0x00100000
  70 #define BIT21           0x00200000
  71 #define BIT22           0x00400000
  72 #define BIT23           0x00800000
  73 #define BIT24           0x01000000
  74 #define BIT25           0x02000000
  75 #define BIT26           0x04000000
  76 #define BIT27           0x08000000
  77 #define BIT28           0x10000000
  78 #define BIT29           0x20000000
  79 #define BIT30           0x40000000
  80 #define BIT31           0x80000000
  81
  82 // Rx smooth factor
  83 #define Rx_Smooth_Factor                20
  84 #define DMESG(x,a...)
  85 #define DMESGW(x,a...)
  86 #define DMESGE(x,a...)
  87 extern u32 rt_global_debug_component;
  88 #define RT_TRACE(component, x, args...) \
  89 do { if (rt_global_debug_component & component) \
  90         printk(KERN_DEBUG RTL819xU_MODULE_NAME ":" x "\n" , \
  91                ##args);\
  92 }while(0);
  93
  94 #define COMP_TRACE                              BIT0            // For function call tracing.
  95 #define COMP_DBG                                BIT1            // Only for temporary debug message.
  96 #define COMP_INIT                               BIT2            // during driver initialization / halt / reset.
  97
  98
  99 #define COMP_RECV                               BIT3            // Receive data path.
 100 #define COMP_SEND                               BIT4            // Send part path.
 101 #define COMP_IO                                 BIT5            // I/O Related. Added by Annie, 2006-03-02.
 102 #define COMP_POWER                              BIT6            // 802.11 Power Save mode or System/Device Power state related.
 103 #define COMP_EPROM                              BIT7            // 802.11 link related: join/start BSS, leave BSS.
 104 #define COMP_SWBW                               BIT8    // For bandwidth switch.
 105 #define COMP_POWER_TRACKING                     BIT9    //FOR 8190 TX POWER TRACKING
 106 #define COMP_TURBO                              BIT10   // For Turbo Mode related. By Annie, 2005-10-21.
 107 #define COMP_QOS                                BIT11   // For QoS.
 108 #define COMP_RATE                               BIT12   // For Rate Adaptive mechanism, 2006.07.02, by rcnjko.
 109 #define COMP_RM                                 BIT13   // For Radio Measurement.
 110 #define COMP_DIG                                BIT14   // For DIG, 2006.09.25, by rcnjko.
 111 #define COMP_PHY                                BIT15
 112 #define COMP_CH                                 BIT16   //channel setting debug
 113 #define COMP_TXAGC                              BIT17   // For Tx power, 060928, by rcnjko.
 114 #define COMP_HIPWR                              BIT18   // For High Power Mechanism, 060928, by rcnjko.
 115 #define COMP_HALDM                              BIT19   // For HW Dynamic Mechanism, 061010, by rcnjko.
 116 #define COMP_SEC                                BIT20   // Event handling
 117 #define COMP_LED                                BIT21   // For LED.
 118 #define COMP_RF                                 BIT22   // For RF.
 119 //1!!!!!!!!!!!!!!!!!!!!!!!!!!!
 120 #define COMP_RXDESC                             BIT23   // Show Rx desc information for SD3 debug. Added by Annie, 2006-07-15.
 121 //1//1Attention Please!!!<11n or 8190 specific code should be put below this line>
 122 //1!!!!!!!!!!!!!!!!!!!!!!!!!!!
 123
 124 #define COMP_FIRMWARE                           BIT24   //for firmware downloading
 125 #define COMP_HT                                 BIT25   // For 802.11n HT related information. by Emily 2006-8-11
 126 #define COMP_AMSDU                              BIT26   // For A-MSDU Debugging
 127
 128 #define COMP_SCAN                               BIT27
 129 #define COMP_DOWN                               BIT29  //for rm driver module
 130 #define COMP_RESET                              BIT30  //for silent reset
 131 #define COMP_ERR                                BIT31 //for error out, always on
 132
 133 #define RTL819x_DEBUG
 134 #ifdef RTL819x_DEBUG
 135 #define assert(expr) \
 136         if (!(expr)) {                                  \
 137                 printk("Assertion failed! %s,%s,%s,line=%d\n", \
 138                 #expr,__FILE__,__FUNCTION__,__LINE__);          \
 139         }
 140 //wb added to debug out data buf
 141 //if you want print DATA buffer related BA, please set ieee80211_debug_level to DATA|BA
 142 #define RT_DEBUG_DATA(level, data, datalen)      \
 143         do{ if ((rt_global_debug_component & (level)) == (level))   \
 144                 {       \
 145                         int i;                                  \
 146                         u8 *pdata = (u8 *) data;                 \
 147                         printk(KERN_DEBUG RTL819xU_MODULE_NAME ": %s()\n", __FUNCTION__);   \
 148                         for(i=0; i<(int)(datalen); i++)                 \
 149                         {                                               \
 150                                 printk("%2x ", pdata[i]);               \
 151                                 if ((i+1)%16 == 0) printk("\n");        \
 152                         }                               \
 153                         printk("\n");                   \
 154                 }                                       \
 155         } while (0)
 156 #else
 157 #define assert(expr) do {} while (0)
 158 #define RT_DEBUG_DATA(level, data, datalen) do {} while(0)
 159 #endif /* RTL8169_DEBUG */
 160
 161
 162 //
 163 // Queue Select Value in TxDesc
 164 //
 165 #define QSLT_BK                                 0x1
 166 #define QSLT_BE                                 0x0
 167 #define QSLT_VI                                 0x4
 168 #define QSLT_VO                                 0x6
 169 #define QSLT_BEACON                             0x10
 170 #define QSLT_HIGH                               0x11
 171 #define QSLT_MGNT                               0x12
 172 #define QSLT_CMD                                0x13
 173
 174 #define DESC90_RATE1M                           0x00
 175 #define DESC90_RATE2M                           0x01
 176 #define DESC90_RATE5_5M                         0x02
 177 #define DESC90_RATE11M                          0x03
 178 #define DESC90_RATE6M                           0x04
 179 #define DESC90_RATE9M                           0x05
 180 #define DESC90_RATE12M                          0x06
 181 #define DESC90_RATE18M                          0x07
 182 #define DESC90_RATE24M                          0x08
 183 #define DESC90_RATE36M                          0x09
 184 #define DESC90_RATE48M                          0x0a
 185 #define DESC90_RATE54M                          0x0b
 186 #define DESC90_RATEMCS0                         0x00
 187 #define DESC90_RATEMCS1                         0x01
 188 #define DESC90_RATEMCS2                         0x02
 189 #define DESC90_RATEMCS3                         0x03
 190 #define DESC90_RATEMCS4                         0x04
 191 #define DESC90_RATEMCS5                         0x05
 192 #define DESC90_RATEMCS6                         0x06
 193 #define DESC90_RATEMCS7                         0x07
 194 #define DESC90_RATEMCS8                         0x08
 195 #define DESC90_RATEMCS9                         0x09
 196 #define DESC90_RATEMCS10                        0x0a
 197 #define DESC90_RATEMCS11                        0x0b
 198 #define DESC90_RATEMCS12                        0x0c
 199 #define DESC90_RATEMCS13                        0x0d
 200 #define DESC90_RATEMCS14                        0x0e
 201 #define DESC90_RATEMCS15                        0x0f
 202 #define DESC90_RATEMCS32                        0x20
 203
 204 #define RTL819X_DEFAULT_RF_TYPE RF_1T2R
 205
 206 #define IEEE80211_WATCH_DOG_TIME    2000
 207 #define         PHY_Beacon_RSSI_SLID_WIN_MAX            10
 208 //for txpowertracking by amy
 209 #define         OFDM_Table_Length       19
 210 #define CCK_Table_length        12
 211
 212 /* for rtl819x */
 213 typedef struct _tx_desc_819x_usb {
 214         //DWORD 0
 215         u16     PktSize;
 216         u8      Offset;
 217         u8      Reserved0:3;
 218         u8      CmdInit:1;
 219         u8      LastSeg:1;
 220         u8      FirstSeg:1;
 221         u8      LINIP:1;
 222         u8      OWN:1;
 223
 224         //DWORD 1
 225         u8      TxFWInfoSize;
 226         u8      RATid:3;
 227         u8      DISFB:1;
 228         u8      USERATE:1;
 229         u8      MOREFRAG:1;
 230         u8      NoEnc:1;
 231         u8      PIFS:1;
 232         u8      QueueSelect:5;
 233         u8      NoACM:1;
 234         u8      Reserved1:2;
 235         u8      SecCAMID:5;
 236         u8      SecDescAssign:1;
 237         u8      SecType:2;
 238
 239         //DWORD 2
 240         u16     TxBufferSize;
 241         u8      ResvForPaddingLen:7;
 242         u8      Reserved3:1;
 243         u8      Reserved4;
 244
 245         //DWORD 3, 4, 5
 246         u32     Reserved5;
 247         u32     Reserved6;
 248         u32     Reserved7;
 249 }tx_desc_819x_usb, *ptx_desc_819x_usb;
 250
 251 #ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
 252 typedef struct _tx_desc_819x_usb_aggr_subframe {
 253         //DWORD 0
 254         u16     PktSize;
 255         u8      Offset;
 256         u8      TxFWInfoSize;
 257
 258         //DWORD 1
 259         u8      RATid:3;
 260         u8      DISFB:1;
 261         u8      USERATE:1;
 262         u8      MOREFRAG:1;
 263         u8      NoEnc:1;
 264         u8      PIFS:1;
 265         u8      QueueSelect:5;
 266         u8      NoACM:1;
 267         u8      Reserved1:2;
 268         u8      SecCAMID:5;
 269         u8      SecDescAssign:1;
 270         u8      SecType:2;
 271         u8      PacketID:7;
 272         u8      OWN:1;
 273 }tx_desc_819x_usb_aggr_subframe, *ptx_desc_819x_usb_aggr_subframe;
 274 #endif
 275
 276
 277
 278 typedef struct _tx_desc_cmd_819x_usb {
 279         //DWORD 0
 280         u16     Reserved0;
 281         u8      Reserved1;
 282         u8      Reserved2:3;
 283         u8      CmdInit:1;
 284         u8      LastSeg:1;
 285         u8      FirstSeg:1;
 286         u8      LINIP:1;
 287         u8      OWN:1;
 288
 289         //DOWRD 1
 290         u8      TxFWInfoSize;
 291         u8      Reserved3;
 292         u8      QueueSelect;
 293         u8      Reserved4;
 294
 295         //DOWRD 2
 296         u16     TxBufferSize;
 297         u16     Reserved5;
 298
 299        //DWORD 3,4,5
 300         u32     Reserved6;
 301         u32     Reserved7;
 302         u32     Reserved8;
 303 }tx_desc_cmd_819x_usb, *ptx_desc_cmd_819x_usb;
 304
 305
 306 typedef struct _tx_fwinfo_819x_usb {
 307         //DOWRD 0
 308         u8              TxRate:7;
 309         u8              CtsEnable:1;
 310         u8              RtsRate:7;
 311         u8              RtsEnable:1;
 312         u8              TxHT:1;
 313         u8              Short:1;                //Short PLCP for CCK, or short GI for 11n MCS
 314         u8              TxBandwidth:1;          // This is used for HT MCS rate only.
 315         u8              TxSubCarrier:2;         // This is used for legacy OFDM rate only.
 316         u8              STBC:2;
 317         u8              AllowAggregation:1;
 318         u8              RtsHT:1;                //Interpret RtsRate field as high throughput data rate
 319         u8              RtsShort:1;             //Short PLCP for CCK, or short GI for 11n MCS
 320         u8              RtsBandwidth:1;         // This is used for HT MCS rate only.
 321         u8              RtsSubcarrier:2;        // This is used for legacy OFDM rate only.
 322         u8              RtsSTBC:2;
 323         u8              EnableCPUDur:1;         //Enable firmware to recalculate and assign packet duration
 324
 325         //DWORD 1
 326         u32             RxMF:2;
 327         u32             RxAMD:3;
 328         u32             TxPerPktInfoFeedback:1;//1 indicate Tx info gathtered by firmware and returned by Rx Cmd
 329         u32             Reserved1:2;
 330         u32             TxAGCOffSet:4;
 331         u32             TxAGCSign:1;
 332         u32             Tx_INFO_RSVD:6;
 333         u32             PacketID:13;
 334 }tx_fwinfo_819x_usb, *ptx_fwinfo_819x_usb;
 335
 336 typedef struct rtl8192_rx_info {
 337         struct urb *urb;
 338         struct net_device *dev;
 339         u8 out_pipe;
 340 }rtl8192_rx_info ;
 341
 342 typedef struct rx_desc_819x_usb{
 343         //DOWRD 0
 344         u16                 Length:14;
 345         u16                 CRC32:1;
 346         u16                 ICV:1;
 347         u8                  RxDrvInfoSize;
 348         u8                  Shift:2;
 349         u8                  PHYStatus:1;
 350         u8                  SWDec:1;
 351         u8                  Reserved1:4;
 352
 353         //DWORD 1
 354         u32                 Reserved2;
 355
 356         //DWORD 2
 357
 358         //DWORD 3
 359
 360 }rx_desc_819x_usb, *prx_desc_819x_usb;
 361
 362 #ifdef USB_RX_AGGREGATION_SUPPORT
 363 typedef struct _rx_desc_819x_usb_aggr_subframe{
 364         //DOWRD 0
 365         u16                     Length:14;
 366         u16                     CRC32:1;
 367         u16                     ICV:1;
 368         u8                      Offset;
 369         u8                      RxDrvInfoSize;
 370         //DOWRD 1
 371         u8                      Shift:2;
 372         u8                      PHYStatus:1;
 373         u8                      SWDec:1;
 374         u8                      Reserved1:4;
 375         u8                      Reserved2;
 376         u16                     Reserved3;
 377         //DWORD 2
 378         //DWORD 3
 379 }rx_desc_819x_usb_aggr_subframe, *prx_desc_819x_usb_aggr_subframe;
 380 #endif
 381
 382 typedef struct rx_drvinfo_819x_usb{
 383         //DWORD 0
 384         u16                 Reserved1:12;
 385         u16                 PartAggr:1;
 386         u16                 FirstAGGR:1;
 387         u16                 Reserved2:2;
 388
 389         u8                  RxRate:7;
 390         u8                  RxHT:1;
 391
 392         u8                  BW:1;
 393         u8                  SPLCP:1;
 394         u8                  Reserved3:2;
 395         u8                  PAM:1;
 396         u8                  Mcast:1;
 397         u8                  Bcast:1;
 398         u8                  Reserved4:1;
 399
 400         //DWORD 1
 401         u32                  TSFL;
 402
 403 }rx_drvinfo_819x_usb, *prx_drvinfo_819x_usb;
 404
 405
 406 #define MAX_DEV_ADDR_SIZE               8  /* support till 64 bit bus width OS */
 407 #define MAX_FIRMWARE_INFORMATION_SIZE   32 /*2006/04/30 by Emily forRTL8190*/
 408 #define MAX_802_11_HEADER_LENGTH        (40 + MAX_FIRMWARE_INFORMATION_SIZE)
 409 #define ENCRYPTION_MAX_OVERHEAD         128
 410 #define USB_HWDESC_HEADER_LEN           sizeof(tx_desc_819x_usb)
 411 #define TX_PACKET_SHIFT_BYTES           (USB_HWDESC_HEADER_LEN + sizeof(tx_fwinfo_819x_usb))
 412 #define MAX_FRAGMENT_COUNT              8
 413 #ifdef RTL8192U
 414 #ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
 415 #define MAX_TRANSMIT_BUFFER_SIZE                        32000
 416 #else
 417 #define MAX_TRANSMIT_BUFFER_SIZE                        8000
 418 #endif
 419 #else
 420 #define MAX_TRANSMIT_BUFFER_SIZE        (1600+(MAX_802_11_HEADER_LENGTH+ENCRYPTION_MAX_OVERHEAD)*MAX_FRAGMENT_COUNT)
 421 #endif
 422 #ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
 423 #define TX_PACKET_DRVAGGR_SUBFRAME_SHIFT_BYTES (sizeof(tx_desc_819x_usb_aggr_subframe) + sizeof(tx_fwinfo_819x_usb))
 424 #endif
 425 #define scrclng                                 4               // octets for crc32 (FCS, ICV)
 426
 427 typedef enum rf_optype
 428 {
 429         RF_OP_By_SW_3wire = 0,
 430         RF_OP_By_FW,
 431         RF_OP_MAX
 432 }rf_op_type;
 433 /* 8190 Loopback Mode definition */
 434 typedef enum _rtl819xUsb_loopback{
 435         RTL819xU_NO_LOOPBACK = 0,
 436         RTL819xU_MAC_LOOPBACK = 1,
 437         RTL819xU_DMA_LOOPBACK = 2,
 438         RTL819xU_CCK_LOOPBACK = 3,
 439 }rtl819xUsb_loopback_e;
 440
 441 /* due to rtl8192 firmware */
 442 typedef enum _desc_packet_type_e{
 443         DESC_PACKET_TYPE_INIT = 0,
 444         DESC_PACKET_TYPE_NORMAL = 1,
 445 }desc_packet_type_e;
 446
 447 typedef enum _firmware_status{
 448         FW_STATUS_0_INIT = 0,
 449         FW_STATUS_1_MOVE_BOOT_CODE = 1,
 450         FW_STATUS_2_MOVE_MAIN_CODE = 2,
 451         FW_STATUS_3_TURNON_CPU = 3,
 452         FW_STATUS_4_MOVE_DATA_CODE = 4,
 453         FW_STATUS_5_READY = 5,
 454 }firmware_status_e;
 455
 456 typedef struct _rt_firmare_seg_container {
 457         u16     seg_size;
 458         u8      *seg_ptr;
 459 }fw_seg_container, *pfw_seg_container;
 460 typedef struct _rt_firmware{
 461         firmware_status_e firmware_status;
 462         u16               cmdpacket_frag_thresold;
 463 #define RTL8190_MAX_FIRMWARE_CODE_SIZE  64000   //64k
 464         u8                firmware_buf[RTL8190_MAX_FIRMWARE_CODE_SIZE];
 465         u16               firmware_buf_size;
 466 }rt_firmware, *prt_firmware;
 467
 468 //+by amy 080507
 469 #define MAX_RECEIVE_BUFFER_SIZE 9100    // Add this to 9100 bytes to receive A-MSDU from RT-AP
 470
 471 typedef struct _rt_firmware_info_819xUsb{
 472         u8              sz_info[16];
 473 }rt_firmware_info_819xUsb, *prt_firmware_info_819xUsb;
 474
 475 /* Firmware Queue Layout */
 476 #define NUM_OF_FIRMWARE_QUEUE           10
 477 #define NUM_OF_PAGES_IN_FW              0x100
 478
 479 #ifdef USE_ONE_PIPE
 480 #define NUM_OF_PAGE_IN_FW_QUEUE_BE      0x000
 481 #define NUM_OF_PAGE_IN_FW_QUEUE_BK      0x000
 482 #define NUM_OF_PAGE_IN_FW_QUEUE_VI      0x0ff
 483 #define NUM_OF_PAGE_IN_FW_QUEUE_VO      0x000
 484 #define NUM_OF_PAGE_IN_FW_QUEUE_HCCA    0
 485 #define NUM_OF_PAGE_IN_FW_QUEUE_CMD     0x0
 486 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT    0x00
 487 #define NUM_OF_PAGE_IN_FW_QUEUE_HIGH    0
 488 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN     0x0
 489 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB     0x00
 490 #else
 491
 492 #define NUM_OF_PAGE_IN_FW_QUEUE_BE      0x020
 493 #define NUM_OF_PAGE_IN_FW_QUEUE_BK      0x020
 494 #define NUM_OF_PAGE_IN_FW_QUEUE_VI      0x040
 495 #define NUM_OF_PAGE_IN_FW_QUEUE_VO      0x040
 496 #define NUM_OF_PAGE_IN_FW_QUEUE_HCCA    0
 497 #define NUM_OF_PAGE_IN_FW_QUEUE_CMD     0x4
 498 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT    0x20
 499 #define NUM_OF_PAGE_IN_FW_QUEUE_HIGH    0
 500 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN     0x4
 501 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB     0x18
 502
 503 #endif
 504
 505 #define APPLIED_RESERVED_QUEUE_IN_FW    0x80000000
 506 #define RSVD_FW_QUEUE_PAGE_BK_SHIFT     0x00
 507 #define RSVD_FW_QUEUE_PAGE_BE_SHIFT     0x08
 508 #define RSVD_FW_QUEUE_PAGE_VI_SHIFT     0x10
 509 #define RSVD_FW_QUEUE_PAGE_VO_SHIFT     0x18
 510 #define RSVD_FW_QUEUE_PAGE_MGNT_SHIFT   0x10
 511 #define RSVD_FW_QUEUE_PAGE_CMD_SHIFT    0x08
 512 #define RSVD_FW_QUEUE_PAGE_BCN_SHIFT    0x00
 513 #define RSVD_FW_QUEUE_PAGE_PUB_SHIFT    0x08
 514 //=================================================================
 515 //=================================================================
 516
 517 #define EPROM_93c46 0
 518 #define EPROM_93c56 1
 519
 520 #define DEFAULT_FRAG_THRESHOLD 2342U
 521 #define MIN_FRAG_THRESHOLD     256U
 522 #define DEFAULT_BEACONINTERVAL 0x64U
 523 #define DEFAULT_BEACON_ESSID "Rtl819xU"
 524
 525 #define DEFAULT_SSID ""
 526 #define DEFAULT_RETRY_RTS 7
 527 #define DEFAULT_RETRY_DATA 7
 528 #define PRISM_HDR_SIZE 64
 529
 530 #define         PHY_RSSI_SLID_WIN_MAX                           100
 531
 532
 533 typedef enum _WIRELESS_MODE {
 534         WIRELESS_MODE_UNKNOWN = 0x00,
 535         WIRELESS_MODE_A = 0x01,
 536         WIRELESS_MODE_B = 0x02,
 537         WIRELESS_MODE_G = 0x04,
 538         WIRELESS_MODE_AUTO = 0x08,
 539         WIRELESS_MODE_N_24G = 0x10,
 540         WIRELESS_MODE_N_5G = 0x20
 541 } WIRELESS_MODE;
 542
 543
 544 #define RTL_IOCTL_WPA_SUPPLICANT                SIOCIWFIRSTPRIV+30
 545
 546 typedef struct buffer {
 547         struct buffer *next;
 548         u32 *buf;
 549
 550 } buffer;
 551
 552 typedef struct rtl_reg_debug{
 553         unsigned int  cmd;
 554         struct {
 555                 unsigned char type;
 556                 unsigned char addr;
 557                 unsigned char page;
 558                 unsigned char length;
 559         } head;
 560         unsigned char buf[0xff];
 561 }rtl_reg_debug;
 562
 563
 564
 565
 566
 567
 568 typedef struct _rt_9x_tx_rate_history {
 569         u32             cck[4];
 570         u32             ofdm[8];
 571         u32             ht_mcs[4][16];
 572 }rt_tx_rahis_t, *prt_tx_rahis_t;
 573 typedef struct _RT_SMOOTH_DATA_4RF {
 574         char    elements[4][100];//array to store values
 575         u32     index;                  //index to current array to store
 576         u32     TotalNum;               //num of valid elements
 577         u32     TotalVal[4];            //sum of valid elements
 578 }RT_SMOOTH_DATA_4RF, *PRT_SMOOTH_DATA_4RF;
 579
 580 #define MAX_8192U_RX_SIZE                       8192    // This maybe changed for D-cut larger aggregation size
 581 //stats seems messed up, clean it ASAP
 582 typedef struct Stats {
 583         unsigned long txrdu;
 584         unsigned long rxok;
 585         unsigned long rxframgment;
 586         unsigned long rxurberr;
 587         unsigned long rxstaterr;
 588         unsigned long received_rate_histogram[4][32];   //0: Total, 1:OK, 2:CRC, 3:ICV, 2007 07 03 cosa
 589         unsigned long received_preamble_GI[2][32];              //0: Long preamble/GI, 1:Short preamble/GI
 590         unsigned long rx_AMPDUsize_histogram[5]; // level: (<4K), (4K~8K), (8K~16K), (16K~32K), (32K~64K)
 591         unsigned long rx_AMPDUnum_histogram[5]; // level: (<5), (5~10), (10~20), (20~40), (>40)
 592         unsigned long numpacket_matchbssid;     // debug use only.
 593         unsigned long numpacket_toself;         // debug use only.
 594         unsigned long num_process_phyinfo;              // debug use only.
 595         unsigned long numqry_phystatus;
 596         unsigned long numqry_phystatusCCK;
 597         unsigned long numqry_phystatusHT;
 598         unsigned long received_bwtype[5];              //0: 20M, 1: funn40M, 2: upper20M, 3: lower20M, 4: duplicate
 599         unsigned long txnperr;
 600         unsigned long txnpdrop;
 601         unsigned long txresumed;
 602         unsigned long txnpokint;
 603         unsigned long txoverflow;
 604         unsigned long txlpokint;
 605         unsigned long txlpdrop;
 606         unsigned long txlperr;
 607         unsigned long txbeokint;
 608         unsigned long txbedrop;
 609         unsigned long txbeerr;
 610         unsigned long txbkokint;
 611         unsigned long txbkdrop;
 612         unsigned long txbkerr;
 613         unsigned long txviokint;
 614         unsigned long txvidrop;
 615         unsigned long txvierr;
 616         unsigned long txvookint;
 617         unsigned long txvodrop;
 618         unsigned long txvoerr;
 619         unsigned long txbeaconokint;
 620         unsigned long txbeacondrop;
 621         unsigned long txbeaconerr;
 622         unsigned long txmanageokint;
 623         unsigned long txmanagedrop;
 624         unsigned long txmanageerr;
 625         unsigned long txdatapkt;
 626         unsigned long txfeedback;
 627         unsigned long txfeedbackok;
 628
 629         unsigned long txoktotal;
 630         unsigned long txokbytestotal;
 631         unsigned long txokinperiod;
 632         unsigned long txmulticast;
 633         unsigned long txbytesmulticast;
 634         unsigned long txbroadcast;
 635         unsigned long txbytesbroadcast;
 636         unsigned long txunicast;
 637         unsigned long txbytesunicast;
 638
 639         unsigned long rxoktotal;
 640         unsigned long rxbytesunicast;
 641         unsigned long txfeedbackfail;
 642         unsigned long txerrtotal;
 643         unsigned long txerrbytestotal;
 644         unsigned long txerrmulticast;
 645         unsigned long txerrbroadcast;
 646         unsigned long txerrunicast;
 647         unsigned long txretrycount;
 648         unsigned long txfeedbackretry;
 649         u8            last_packet_rate;
 650         unsigned long slide_signal_strength[100];
 651         unsigned long slide_evm[100];
 652         unsigned long slide_rssi_total; // For recording sliding window's RSSI value
 653         unsigned long slide_evm_total;  // For recording sliding window's EVM value
 654         long signal_strength; // Transformed, in dbm. Beautified signal strength for UI, not correct.
 655         long signal_quality;
 656         long last_signal_strength_inpercent;
 657         long recv_signal_power; // Correct smoothed ss in Dbm, only used in driver to report real power now.
 658         u8 rx_rssi_percentage[4];
 659         u8 rx_evm_percentage[2];
 660         long rxSNRdB[4];
 661         rt_tx_rahis_t txrate;
 662         u32 Slide_Beacon_pwdb[100];     //cosa add for beacon rssi
 663         u32 Slide_Beacon_Total;         //cosa add for beacon rssi
 664         RT_SMOOTH_DATA_4RF              cck_adc_pwdb;
 665
 666         u32     CurrentShowTxate;
 667 } Stats;
 668
 669
 670 // Bandwidth Offset
 671 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE         0
 672 #define HAL_PRIME_CHNL_OFFSET_LOWER                     1
 673 #define HAL_PRIME_CHNL_OFFSET_UPPER                     2
 674
 675 //+by amy 080507
 676
 677 typedef struct  ChnlAccessSetting {
 678         u16 SIFS_Timer;
 679         u16 DIFS_Timer;
 680         u16 SlotTimeTimer;
 681         u16 EIFS_Timer;
 682         u16 CWminIndex;
 683         u16 CWmaxIndex;
 684 }*PCHANNEL_ACCESS_SETTING,CHANNEL_ACCESS_SETTING;
 685
 686 typedef struct _BB_REGISTER_DEFINITION{
 687         u32 rfintfs;                    // set software control: //             0x870~0x877[8 bytes]
 688         u32 rfintfi;                    // readback data: //            0x8e0~0x8e7[8 bytes]
 689         u32 rfintfo;                    // output data: //              0x860~0x86f [16 bytes]
 690         u32 rfintfe;                    // output enable: //            0x860~0x86f [16 bytes]
 691         u32 rf3wireOffset;              // LSSI data: //                0x840~0x84f [16 bytes]
 692         u32 rfLSSI_Select;              // BB Band Select: //           0x878~0x87f [8 bytes]
 693         u32 rfTxGainStage;              // Tx gain stage: //            0x80c~0x80f [4 bytes]
 694         u32 rfHSSIPara1;                // wire parameter control1 : //         0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
 695         u32 rfHSSIPara2;                // wire parameter control2 : //         0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
 696         u32 rfSwitchControl;    //Tx Rx antenna control : //            0x858~0x85f [16 bytes]
 697         u32 rfAGCControl1;      //AGC parameter control1 : //           0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
 698         u32 rfAGCControl2;      //AGC parameter control2 : //           0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
 699         u32 rfRxIQImbalance;    //OFDM Rx IQ imbalance matrix : //              0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
 700         u32 rfRxAFE;                    //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : //         0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
 701         u32 rfTxIQImbalance;    //OFDM Tx IQ imbalance matrix //                0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
 702         u32 rfTxAFE;                    //Tx IQ DC Offset and Tx DFIR type //           0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
 703         u32 rfLSSIReadBack;     //LSSI RF readback data //              0x8a0~0x8af [16 bytes]
 704 }BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
 705
 706 typedef enum _RT_RF_TYPE_819xU{
 707         RF_TYPE_MIN = 0,
 708         RF_8225,
 709         RF_8256,
 710         RF_8258,
 711         RF_PSEUDO_11N = 4,
 712 }RT_RF_TYPE_819xU, *PRT_RF_TYPE_819xU;
 713
 714 typedef struct _rate_adaptive {
 715         u8                              rate_adaptive_disabled;
 716         u8                              ratr_state;
 717         u16                             reserve;
 718
 719         u32                             high_rssi_thresh_for_ra;
 720         u32                             high2low_rssi_thresh_for_ra;
 721         u8                              low2high_rssi_thresh_for_ra40M;
 722         u32                             low_rssi_thresh_for_ra40M;
 723         u8                              low2high_rssi_thresh_for_ra20M;
 724         u32                             low_rssi_thresh_for_ra20M;
 725         u32                             upper_rssi_threshold_ratr;
 726         u32                             middle_rssi_threshold_ratr;
 727         u32                             low_rssi_threshold_ratr;
 728         u32                             low_rssi_threshold_ratr_40M;
 729         u32                             low_rssi_threshold_ratr_20M;
 730         u8                              ping_rssi_enable;       //cosa add for test
 731         u32                             ping_rssi_ratr; //cosa add for test
 732         u32                             ping_rssi_thresh_for_ra;//cosa add for test
 733         u32                             last_ratr;
 734
 735 } rate_adaptive, *prate_adaptive;
 736
 737 #define TxBBGainTableLength 37
 738 #define CCKTxBBGainTableLength 23
 739
 740 typedef struct _txbbgain_struct {
 741         long    txbb_iq_amplifygain;
 742         u32     txbbgain_value;
 743 } txbbgain_struct, *ptxbbgain_struct;
 744
 745 typedef struct _ccktxbbgain_struct {
 746         //The Value is from a22 to a29 one Byte one time is much Safer
 747         u8      ccktxbb_valuearray[8];
 748 } ccktxbbgain_struct,*pccktxbbgain_struct;
 749
 750
 751 typedef struct _init_gain {
 752         u8                              xaagccore1;
 753         u8                              xbagccore1;
 754         u8                              xcagccore1;
 755         u8                              xdagccore1;
 756         u8                              cca;
 757
 758 } init_gain, *pinit_gain;
 759 //by amy 0606
 760
 761 typedef struct _phy_ofdm_rx_status_report_819xusb {
 762         u8      trsw_gain_X[4];
 763         u8      pwdb_all;
 764         u8      cfosho_X[4];
 765         u8      cfotail_X[4];
 766         u8      rxevm_X[2];
 767         u8      rxsnr_X[4];
 768         u8      pdsnr_X[2];
 769         u8      csi_current_X[2];
 770         u8      csi_target_X[2];
 771         u8      sigevm;
 772         u8      max_ex_pwr;
 773         u8      sgi_en;
 774         u8  rxsc_sgien_exflg;
 775 }phy_sts_ofdm_819xusb_t;
 776
 777 typedef struct _phy_cck_rx_status_report_819xusb {
 778         /* For CCK rate descriptor. This is a unsigned 8:1 variable. LSB bit presend
 779            0.5. And MSB 7 bts presend a signed value. Range from -64~+63.5. */
 780         u8      adc_pwdb_X[4];
 781         u8      sq_rpt;
 782         u8      cck_agc_rpt;
 783 }phy_sts_cck_819xusb_t;
 784
 785
 786 typedef struct _phy_ofdm_rx_status_rxsc_sgien_exintfflag{
 787         u8                      reserved:4;
 788         u8                      rxsc:2;
 789         u8                      sgi_en:1;
 790         u8                      ex_intf_flag:1;
 791 }phy_ofdm_rx_status_rxsc_sgien_exintfflag;
 792
 793 typedef enum _RT_CUSTOMER_ID
 794 {
 795         RT_CID_DEFAULT = 0,
 796         RT_CID_8187_ALPHA0 = 1,
 797         RT_CID_8187_SERCOMM_PS = 2,
 798         RT_CID_8187_HW_LED = 3,
 799         RT_CID_8187_NETGEAR = 4,
 800         RT_CID_WHQL = 5,
 801         RT_CID_819x_CAMEO  = 6,
 802         RT_CID_819x_RUNTOP = 7,
 803         RT_CID_819x_Senao = 8,
 804         RT_CID_TOSHIBA = 9,     // Merge by Jacken, 2008/01/31.
 805         RT_CID_819x_Netcore = 10,
 806         RT_CID_Nettronix = 11,
 807         RT_CID_DLINK = 12,
 808         RT_CID_PRONET = 13,
 809 }RT_CUSTOMER_ID, *PRT_CUSTOMER_ID;
 810
 811 //================================================================================
 812 // LED customization.
 813 //================================================================================
 814
 815 typedef enum _LED_STRATEGY_8190{
 816         SW_LED_MODE0, // SW control 1 LED via GPIO0. It is default option.
 817         SW_LED_MODE1, // SW control for PCI Express
 818         SW_LED_MODE2, // SW control for Cameo.
 819         SW_LED_MODE3, // SW contorl for RunTop.
 820         SW_LED_MODE4, // SW control for Netcore
 821         HW_LED, // HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes)
 822 }LED_STRATEGY_8190, *PLED_STRATEGY_8190;
 823
 824 typedef enum _RESET_TYPE {
 825         RESET_TYPE_NORESET = 0x00,
 826         RESET_TYPE_NORMAL = 0x01,
 827         RESET_TYPE_SILENT = 0x02
 828 } RESET_TYPE;
 829
 830 /* The simple tx command OP code. */
 831 typedef enum _tag_TxCmd_Config_Index{
 832         TXCMD_TXRA_HISTORY_CTRL                         = 0xFF900000,
 833         TXCMD_RESET_TX_PKT_BUFF                         = 0xFF900001,
 834         TXCMD_RESET_RX_PKT_BUFF                         = 0xFF900002,
 835         TXCMD_SET_TX_DURATION                           = 0xFF900003,
 836         TXCMD_SET_RX_RSSI                                               = 0xFF900004,
 837         TXCMD_SET_TX_PWR_TRACKING                       = 0xFF900005,
 838         TXCMD_XXXX_CTRL,
 839 }DCMD_TXCMD_OP;
 840
 841 typedef struct r8192_priv {
 842         struct usb_device *udev;
 843         //added for maintain info from eeprom
 844         short epromtype;
 845         u16 eeprom_vid;
 846         u16 eeprom_pid;
 847         u8  eeprom_CustomerID;
 848         u8  eeprom_ChannelPlan;
 849         RT_CUSTOMER_ID CustomerID;
 850         LED_STRATEGY_8190       LedStrategy;
 851         u8  txqueue_to_outpipemap[9];
 852         int irq;
 853         struct ieee80211_device *ieee80211;
 854
 855         short card_8192; /* O: rtl8192, 1:rtl8185 V B/C, 2:rtl8185 V D */
 856         u8 card_8192_version; /* if TCR reports card V B/C this discriminates */
 857         short enable_gpio0;
 858         enum card_type {PCI,MINIPCI,CARDBUS,USB}card_type;
 859         short hw_plcp_len;
 860         short plcp_preamble_mode;
 861
 862         spinlock_t irq_lock;
 863         spinlock_t tx_lock;
 864         struct mutex mutex;
 865
 866         u16 irq_mask;
 867         short chan;
 868         short sens;
 869         short max_sens;
 870
 871
 872         short up;
 873         short crcmon; //if 1 allow bad crc frame reception in monitor mode
 874
 875         struct semaphore wx_sem;
 876         struct semaphore rf_sem; //used to lock rf write operation added by wb, modified by david
 877
 878         u8 rf_type; //0 means 1T2R, 1 means 2T4R
 879         RT_RF_TYPE_819xU rf_chip;
 880
 881         short (*rf_set_sens)(struct net_device *dev,short sens);
 882         u8 (*rf_set_chan)(struct net_device *dev,u8 ch);
 883         void (*rf_close)(struct net_device *dev);
 884         void (*rf_init)(struct net_device *dev);
 885         short promisc;
 886         /*stats*/
 887         struct Stats stats;
 888         struct iw_statistics wstats;
 889
 890         /*RX stuff*/
 891         struct urb **rx_urb;
 892         struct urb **rx_cmd_urb;
 893 #ifdef THOMAS_BEACON
 894         u32 *oldaddr;
 895 #endif
 896 #ifdef THOMAS_TASKLET
 897         atomic_t irt_counter;//count for irq_rx_tasklet
 898 #endif
 899 #ifdef JACKSON_NEW_RX
 900         struct sk_buff **pp_rxskb;
 901         int     rx_inx;
 902 #endif
 903
 904 /* modified by davad for Rx process */
 905        struct sk_buff_head rx_queue;
 906        struct sk_buff_head skb_queue;
 907        struct work_struct qos_activate;
 908         short  tx_urb_index;
 909         atomic_t tx_pending[0x10];//UART_PRIORITY+1
 910
 911
 912         struct tasklet_struct irq_rx_tasklet;
 913         struct urb *rxurb_task;
 914
 915         //2 Tx Related variables
 916         u16     ShortRetryLimit;
 917         u16     LongRetryLimit;
 918         u32     TransmitConfig;
 919         u8      RegCWinMin;             // For turbo mode CW adaptive. Added by Annie, 2005-10-27.
 920
 921         u32     LastRxDescTSFHigh;
 922         u32     LastRxDescTSFLow;
 923
 924
 925         //2 Rx Related variables
 926         u16     EarlyRxThreshold;
 927         u32     ReceiveConfig;
 928         u8      AcmControl;
 929
 930         u8      RFProgType;
 931
 932         u8 retry_data;
 933         u8 retry_rts;
 934         u16 rts;
 935
 936         struct  ChnlAccessSetting  ChannelAccessSetting;
 937         struct work_struct reset_wq;
 938
 939 /**********************************************************/
 940         //for rtl819xUsb
 941         u16     basic_rate;
 942         u8      short_preamble;
 943         u8      slot_time;
 944         bool    bDcut;
 945         bool bCurrentRxAggrEnable;
 946         u8 Rf_Mode; //add for Firmware RF -R/W switch
 947         prt_firmware            pFirmware;
 948         rtl819xUsb_loopback_e   LoopbackMode;
 949         u16 EEPROMTxPowerDiff;
 950         u8 EEPROMThermalMeter;
 951         u8 EEPROMPwDiff;
 952         u8 EEPROMCrystalCap;
 953         u8 EEPROM_Def_Ver;
 954         u8 EEPROMTxPowerLevelCCK;// CCK channel 1~14
 955         u8 EEPROMTxPowerLevelCCK_V1[3];
 956         u8 EEPROMTxPowerLevelOFDM24G[3]; // OFDM 2.4G channel 1~14
 957         u8 EEPROMTxPowerLevelOFDM5G[24];        // OFDM 5G
 958
 959 /*PHY related*/
 960         BB_REGISTER_DEFINITION_T        PHYRegDef[4];   //Radio A/B/C/D
 961         // Read/write are allow for following hardware information variables
 962         u32     MCSTxPowerLevelOriginalOffset[6];
 963         u32     CCKTxPowerLevelOriginalOffset;
 964         u8      TxPowerLevelCCK[14];                    // CCK channel 1~14
 965         u8      TxPowerLevelOFDM24G[14];                // OFDM 2.4G channel 1~14
 966         u8      TxPowerLevelOFDM5G[14];                 // OFDM 5G
 967         u32     Pwr_Track;
 968         u8      TxPowerDiff;
 969         u8      AntennaTxPwDiff[2];                             // Antenna gain offset, index 0 for B, 1 for C, and 2 for D
 970         u8      CrystalCap;                                             // CrystalCap.
 971         u8      ThermalMeter[2];                                // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
 972
 973         u8      CckPwEnl;
 974         // Use to calculate PWBD.
 975         u8      bCckHighPower;
 976         long    undecorated_smoothed_pwdb;
 977
 978         //for set channel
 979         u8      SwChnlInProgress;
 980         u8      SwChnlStage;
 981         u8      SwChnlStep;
 982         u8      SetBWModeInProgress;
 983         HT_CHANNEL_WIDTH                CurrentChannelBW;
 984         u8      ChannelPlan;
 985         // 8190 40MHz mode
 986         //
 987         u8      nCur40MhzPrimeSC;       // Control channel sub-carrier
 988         // Joseph test for shorten RF configuration time.
 989         // We save RF reg0 in this variable to reduce RF reading.
 990         //
 991         u32                                     RfReg0Value[4];
 992         u8                                      NumTotalRFPath;
 993         bool                            brfpath_rxenable[4];
 994         //RF set related
 995         bool                            SetRFPowerStateInProgress;
 996 //+by amy 080507
 997         struct timer_list watch_dog_timer;
 998
 999 //+by amy 080515 for dynamic mechenism
1000         //Add by amy Tx Power Control for Near/Far Range 2008/05/15
1001         bool    bdynamic_txpower;  //bDynamicTxPower
1002         bool    bDynamicTxHighPower;  // Tx high power state
1003         bool    bDynamicTxLowPower;  // Tx low power state
1004         bool    bLastDTPFlag_High;
1005         bool    bLastDTPFlag_Low;
1006
1007         bool    bstore_last_dtpflag;
1008         bool    bstart_txctrl_bydtp;   //Define to discriminate on High power State or on sitesuvey to change Tx gain index
1009         //Add by amy for Rate Adaptive
1010         rate_adaptive rate_adaptive;
1011         //Add by amy for TX power tracking
1012         //2008/05/15  Mars OPEN/CLOSE TX POWER TRACKING
1013        txbbgain_struct txbbgain_table[TxBBGainTableLength];
1014         u8                         txpower_count;//For 6 sec do tracking again
1015         bool                       btxpower_trackingInit;
1016         u8                         OFDM_index;
1017         u8                         CCK_index;
1018         //2007/09/10 Mars Add CCK TX Power Tracking
1019         ccktxbbgain_struct      cck_txbbgain_table[CCKTxBBGainTableLength];
1020         ccktxbbgain_struct      cck_txbbgain_ch14_table[CCKTxBBGainTableLength];
1021         u8 rfa_txpowertrackingindex;
1022         u8 rfa_txpowertrackingindex_real;
1023         u8 rfa_txpowertracking_default;
1024         u8 rfc_txpowertrackingindex;
1025         u8 rfc_txpowertrackingindex_real;
1026
1027         s8 cck_present_attentuation;
1028         u8 cck_present_attentuation_20Mdefault;
1029         u8 cck_present_attentuation_40Mdefault;
1030         char cck_present_attentuation_difference;
1031         bool btxpower_tracking;
1032         bool bcck_in_ch14;
1033         bool btxpowerdata_readfromEEPORM;
1034         u16     TSSI_13dBm;
1035         //For Backup Initial Gain
1036         init_gain initgain_backup;
1037         u8 DefaultInitialGain[4];
1038         // For EDCA Turbo mode, Added by amy 080515.
1039         bool            bis_any_nonbepkts;
1040         bool            bcurrent_turbo_EDCA;
1041         bool            bis_cur_rdlstate;
1042         struct timer_list fsync_timer;
1043         bool bfsync_processing; // 500ms Fsync timer is active or not
1044         u32     rate_record;
1045         u32     rateCountDiffRecord;
1046         u32     ContinueDiffCount;
1047         bool bswitch_fsync;
1048
1049         u8      framesync;
1050         u32     framesyncC34;
1051         u8      framesyncMonitor;
1052                 //Added by amy 080516  for RX related
1053         u16     nrxAMPDU_size;
1054         u8      nrxAMPDU_aggr_num;
1055
1056         //by amy for gpio
1057          bool bHwRadioOff;
1058
1059         //by amy for reset_count
1060         u32 reset_count;
1061         bool bpbc_pressed;
1062         //by amy for debug
1063         u32 txpower_checkcnt;
1064         u32 txpower_tracking_callback_cnt;
1065         u8 thermal_read_val[40];
1066         u8 thermal_readback_index;
1067         u32 ccktxpower_adjustcnt_not_ch14;
1068         u32 ccktxpower_adjustcnt_ch14;
1069         u8 tx_fwinfo_force_subcarriermode;
1070         u8 tx_fwinfo_force_subcarrierval;
1071         //by amy for silent reset
1072         RESET_TYPE      ResetProgress;
1073         bool            bForcedSilentReset;
1074         bool            bDisableNormalResetCheck;
1075         u16             TxCounter;
1076         u16             RxCounter;
1077         int             IrpPendingCount;
1078         bool            bResetInProgress;
1079         bool            force_reset;
1080         u8              InitialGainOperateType;
1081
1082         u16             SifsTime;
1083
1084         //define work item by amy 080526
1085
1086         struct delayed_work update_beacon_wq;
1087         struct delayed_work watch_dog_wq;
1088         struct delayed_work txpower_tracking_wq;
1089         struct delayed_work rfpath_check_wq;
1090         struct delayed_work gpio_change_rf_wq;
1091         struct delayed_work initialgain_operate_wq;
1092         struct workqueue_struct *priv_wq;
1093 }r8192_priv;
1094
1095 //for rtl8187B
1096 typedef enum{
1097         BULK_PRIORITY = 0x01,
1098         LOW_PRIORITY,
1099         NORM_PRIORITY,
1100         VO_PRIORITY,
1101         VI_PRIORITY, //0x05
1102         BE_PRIORITY,
1103         BK_PRIORITY,
1104         RSVD2,
1105         RSVD3,
1106         BEACON_PRIORITY, //0x0A
1107         HIGH_PRIORITY,
1108         MANAGE_PRIORITY,
1109         RSVD4,
1110         RSVD5,
1111         UART_PRIORITY //0x0F
1112 } priority_t;
1113
1114 typedef enum{
1115         NIC_8192U = 1,
1116         NIC_8190P = 2,
1117         NIC_8192E = 3,
1118         } nic_t;
1119
1120
1121 #ifdef JOHN_HWSEC
1122 struct ssid_thread {
1123         struct net_device *dev;
1124         u8 name[IW_ESSID_MAX_SIZE + 1];
1125 };
1126 #endif
1127
1128 bool init_firmware(struct net_device *dev);
1129 short rtl819xU_tx_cmd(struct net_device *dev, struct sk_buff *skb);
1130 short rtl8192_tx(struct net_device *dev, struct sk_buff *skb);
1131
1132 u32 read_cam(struct net_device *dev, u8 addr);
1133 void write_cam(struct net_device *dev, u8 addr, u32 data);
1134
1135 int read_nic_byte(struct net_device *dev, int x, u8 *data);
1136 int read_nic_byte_E(struct net_device *dev, int x, u8 *data);
1137 int read_nic_dword(struct net_device *dev, int x, u32 *data);
1138 int read_nic_word(struct net_device *dev, int x, u16 *data);
1139 void write_nic_byte(struct net_device *dev, int x,u8 y);
1140 void write_nic_byte_E(struct net_device *dev, int x,u8 y);
1141 void write_nic_word(struct net_device *dev, int x,u16 y);
1142 void write_nic_dword(struct net_device *dev, int x,u32 y);
1143 void force_pci_posting(struct net_device *dev);
1144
1145 void rtl8192_rtx_disable(struct net_device *);
1146 void rtl8192_rx_enable(struct net_device *);
1147 void rtl8192_tx_enable(struct net_device *);
1148
1149 void rtl8192_disassociate(struct net_device *dev);
1150 void rtl8185_set_rf_pins_enable(struct net_device *dev,u32 a);
1151
1152 void rtl8192_set_anaparam(struct net_device *dev,u32 a);
1153 void rtl8185_set_anaparam2(struct net_device *dev,u32 a);
1154 void rtl8192_update_msr(struct net_device *dev);
1155 int rtl8192_down(struct net_device *dev);
1156 int rtl8192_up(struct net_device *dev);
1157 void rtl8192_commit(struct net_device *dev);
1158 void rtl8192_set_chan(struct net_device *dev,short ch);
1159 void write_phy(struct net_device *dev, u8 adr, u8 data);
1160 void write_phy_cck(struct net_device *dev, u8 adr, u32 data);
1161 void write_phy_ofdm(struct net_device *dev, u8 adr, u32 data);
1162 void rtl8185_tx_antenna(struct net_device *dev, u8 ant);
1163 void rtl8192_set_rxconf(struct net_device *dev);
1164 extern void rtl819xusb_beacon_tx(struct net_device *dev,u16  tx_rate);
1165
1166 void EnableHWSecurityConfig8192(struct net_device *dev);
1167 void setKey(struct net_device *dev, u8 EntryNo, u8 KeyIndex, u16 KeyType, u8 *MacAddr, u8 DefaultKey, u32 *KeyContent);
1168
1169
1170 #endif