2 Copyright-c Realtek Semiconductor Corp. All rights reserved.
12 ---------- --------------- -------------------------------
13 2008-05-14 amy create version 0 porting from windows code.
17 #include "r8192U_dm.h"
18 #include "r8192U_hw.h"
19 #include "r819xU_phy.h"
20 #include "r819xU_phyreg.h"
21 #include "r8190_rtl8256.h"
22 #include "r819xU_cmdpkt.h"
23 /*---------------------------Define Local Constant---------------------------*/
25 // Indicate different AP vendor for IOT issue.
27 static u32 edca_setting_DL[HT_IOT_PEER_MAX] =
28 { 0x5e4322, 0x5e4322, 0x5e4322, 0x604322, 0xa44f, 0x5ea44f};
29 static u32 edca_setting_UL[HT_IOT_PEER_MAX] =
30 { 0x5e4322, 0xa44f, 0x5e4322, 0x604322, 0x5ea44f, 0x5ea44f};
33 #define RTK_UL_EDCA 0xa44f
34 #define RTK_DL_EDCA 0x5e4322
35 /*---------------------------Define Local Constant---------------------------*/
38 /*------------------------Define global variable-----------------------------*/
41 // Store current software write register content for MAC PHY.
42 u8 dm_shadow[16][256] = {{0}};
43 // For Dynamic Rx Path Selection by Signal Strength
44 DRxPathSel DM_RxPathSelTable;
45 /*------------------------Define global variable-----------------------------*/
48 /*------------------------Define local variable------------------------------*/
49 /*------------------------Define local variable------------------------------*/
52 /*--------------------Define export function prototype-----------------------*/
53 extern void dm_check_fsync(struct net_device *dev);
55 /*--------------------Define export function prototype-----------------------*/
58 /*---------------------Define local function prototype-----------------------*/
59 // DM --> Rate Adaptive
60 static void dm_check_rate_adaptive(struct net_device *dev);
62 // DM --> Bandwidth switch
63 static void dm_init_bandwidth_autoswitch(struct net_device *dev);
64 static void dm_bandwidth_autoswitch(struct net_device *dev);
66 // DM --> TX power control
67 //static void dm_initialize_txpower_tracking(struct net_device *dev);
69 static void dm_check_txpower_tracking(struct net_device *dev);
73 //static void dm_txpower_reset_recovery(struct net_device *dev);
76 // DM --> Dynamic Init Gain by RSSI
77 static void dm_dig_init(struct net_device *dev);
78 static void dm_ctrl_initgain_byrssi(struct net_device *dev);
79 static void dm_ctrl_initgain_byrssi_highpwr(struct net_device *dev);
80 static void dm_ctrl_initgain_byrssi_by_driverrssi(struct net_device *dev);
81 static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(struct net_device *dev);
82 static void dm_initial_gain(struct net_device *dev);
83 static void dm_pd_th(struct net_device *dev);
84 static void dm_cs_ratio(struct net_device *dev);
86 static void dm_init_ctstoself(struct net_device *dev);
87 // DM --> EDCA turbo mode control
88 static void dm_check_edca_turbo(struct net_device *dev);
90 //static void dm_gpio_change_rf(struct net_device *dev);
92 static void dm_check_pbc_gpio(struct net_device *dev);
95 // DM --> Check current RX RF path state
96 static void dm_check_rx_path_selection(struct net_device *dev);
97 static void dm_init_rxpath_selection(struct net_device *dev);
98 static void dm_rxpath_sel_byrssi(struct net_device *dev);
101 // DM --> Fsync for broadcom ap
102 static void dm_init_fsync(struct net_device *dev);
103 static void dm_deInit_fsync(struct net_device *dev);
105 //Added by vivi, 20080522
106 static void dm_check_txrateandretrycount(struct net_device *dev);
108 /*---------------------Define local function prototype-----------------------*/
110 /*---------------------Define of Tx Power Control For Near/Far Range --------*/ //Add by Jacken 2008/02/18
111 static void dm_init_dynamic_txpower(struct net_device *dev);
112 static void dm_dynamic_txpower(struct net_device *dev);
115 // DM --> For rate adaptive and DIG, we must send RSSI to firmware
116 static void dm_send_rssi_tofw(struct net_device *dev);
117 static void dm_ctstoself(struct net_device *dev);
118 /*---------------------------Define function prototype------------------------*/
119 //================================================================================
120 // HW Dynamic mechanism interface.
121 //================================================================================
125 // Prepare SW resource for HW dynamic mechanism.
128 // This function is only invoked at driver intialization once.
131 void init_hal_dm(struct net_device *dev)
133 struct r8192_priv *priv = ieee80211_priv(dev);
135 // Undecorated Smoothed Signal Strength, it can utilized to dynamic mechanism.
136 priv->undecorated_smoothed_pwdb = -1;
138 //Initial TX Power Control for near/far range , add by amy 2008/05/15, porting from windows code.
139 dm_init_dynamic_txpower(dev);
140 init_rate_adaptive(dev);
141 //dm_initialize_txpower_tracking(dev);
143 dm_init_edca_turbo(dev);
144 dm_init_bandwidth_autoswitch(dev);
146 dm_init_rxpath_selection(dev);
147 dm_init_ctstoself(dev);
151 void deinit_hal_dm(struct net_device *dev)
154 dm_deInit_fsync(dev);
159 #ifdef USB_RX_AGGREGATION_SUPPORT
160 void dm_CheckRxAggregation(struct net_device *dev) {
161 struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev);
162 PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;
163 static unsigned long lastTxOkCnt;
164 static unsigned long lastRxOkCnt;
165 unsigned long curTxOkCnt = 0;
166 unsigned long curRxOkCnt = 0;
169 if (pHalData->bForcedUsbRxAggr) {
170 if (pHalData->ForcedUsbRxAggrInfo == 0) {
171 if (pHalData->bCurrentRxAggrEnable) {
172 Adapter->HalFunc.HalUsbRxAggrHandler(Adapter, FALSE);
175 if (!pHalData->bCurrentRxAggrEnable || (pHalData->ForcedUsbRxAggrInfo != pHalData->LastUsbRxAggrInfoSetting)) {
176 Adapter->HalFunc.HalUsbRxAggrHandler(Adapter, TRUE);
183 curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt;
184 curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt;
186 if ((curTxOkCnt + curRxOkCnt) < 15000000)
189 if(curTxOkCnt > 4*curRxOkCnt) {
190 if (priv->bCurrentRxAggrEnable) {
191 write_nic_dword(dev, 0x1a8, 0);
192 priv->bCurrentRxAggrEnable = false;
195 if (!priv->bCurrentRxAggrEnable && !pHTInfo->bCurrentRT2RTAggregation) {
197 ulValue = (pHTInfo->UsbRxFwAggrEn<<24) | (pHTInfo->UsbRxFwAggrPageNum<<16) |
198 (pHTInfo->UsbRxFwAggrPacketNum<<8) | (pHTInfo->UsbRxFwAggrTimeout);
200 * If usb rx firmware aggregation is enabled,
201 * when anyone of three threshold conditions above is reached,
202 * firmware will send aggregated packet to driver.
204 write_nic_dword(dev, 0x1a8, ulValue);
205 priv->bCurrentRxAggrEnable = true;
209 lastTxOkCnt = priv->stats.txbytesunicast;
210 lastRxOkCnt = priv->stats.rxbytesunicast;
211 } // dm_CheckEdcaTurbo
216 void hal_dm_watchdog(struct net_device *dev)
218 //struct r8192_priv *priv = ieee80211_priv(dev);
220 //static u8 previous_bssid[6] ={0};
222 /*Add by amy 2008/05/15 ,porting from windows code.*/
223 dm_check_rate_adaptive(dev);
224 dm_dynamic_txpower(dev);
225 dm_check_txrateandretrycount(dev);
226 dm_check_txpower_tracking(dev);
227 dm_ctrl_initgain_byrssi(dev);
228 dm_check_edca_turbo(dev);
229 dm_bandwidth_autoswitch(dev);
230 dm_check_rx_path_selection(dev);
233 // Add by amy 2008-05-15 porting from windows code.
234 dm_check_pbc_gpio(dev);
235 dm_send_rssi_tofw(dev);
237 #ifdef USB_RX_AGGREGATION_SUPPORT
238 dm_CheckRxAggregation(dev);
244 * Decide Rate Adaptive Set according to distance (signal strength)
245 * 01/11/2008 MHC Modify input arguments and RATR table level.
246 * 01/16/2008 MHC RF_Type is assigned in ReadAdapterInfo(). We must call
247 * the function after making sure RF_Type.
249 void init_rate_adaptive(struct net_device *dev)
252 struct r8192_priv *priv = ieee80211_priv(dev);
253 prate_adaptive pra = (prate_adaptive)&priv->rate_adaptive;
255 pra->ratr_state = DM_RATR_STA_MAX;
256 pra->high2low_rssi_thresh_for_ra = RateAdaptiveTH_High;
257 pra->low2high_rssi_thresh_for_ra20M = RateAdaptiveTH_Low_20M+5;
258 pra->low2high_rssi_thresh_for_ra40M = RateAdaptiveTH_Low_40M+5;
260 pra->high_rssi_thresh_for_ra = RateAdaptiveTH_High+5;
261 pra->low_rssi_thresh_for_ra20M = RateAdaptiveTH_Low_20M;
262 pra->low_rssi_thresh_for_ra40M = RateAdaptiveTH_Low_40M;
264 if(priv->CustomerID == RT_CID_819x_Netcore)
265 pra->ping_rssi_enable = 1;
267 pra->ping_rssi_enable = 0;
268 pra->ping_rssi_thresh_for_ra = 15;
271 if (priv->rf_type == RF_2T4R)
273 // 07/10/08 MH Modify for RA smooth scheme.
274 /* 2008/01/11 MH Modify 2T RATR table for different RSSI. 080515 porting by amy from windows code.*/
275 pra->upper_rssi_threshold_ratr = 0x8f0f0000;
276 pra->middle_rssi_threshold_ratr = 0x8f0ff000;
277 pra->low_rssi_threshold_ratr = 0x8f0ff001;
278 pra->low_rssi_threshold_ratr_40M = 0x8f0ff005;
279 pra->low_rssi_threshold_ratr_20M = 0x8f0ff001;
280 pra->ping_rssi_ratr = 0x0000000d;//cosa add for test
282 else if (priv->rf_type == RF_1T2R)
284 pra->upper_rssi_threshold_ratr = 0x000f0000;
285 pra->middle_rssi_threshold_ratr = 0x000ff000;
286 pra->low_rssi_threshold_ratr = 0x000ff001;
287 pra->low_rssi_threshold_ratr_40M = 0x000ff005;
288 pra->low_rssi_threshold_ratr_20M = 0x000ff001;
289 pra->ping_rssi_ratr = 0x0000000d;//cosa add for test
292 } // InitRateAdaptive
295 /*-----------------------------------------------------------------------------
296 * Function: dm_check_rate_adaptive()
308 * 05/26/08 amy Create version 0 porting from windows code.
310 *---------------------------------------------------------------------------*/
311 static void dm_check_rate_adaptive(struct net_device *dev)
313 struct r8192_priv *priv = ieee80211_priv(dev);
314 PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;
315 prate_adaptive pra = (prate_adaptive)&priv->rate_adaptive;
316 u32 currentRATR, targetRATR = 0;
317 u32 LowRSSIThreshForRA = 0, HighRSSIThreshForRA = 0;
318 bool bshort_gi_enabled = false;
319 static u8 ping_rssi_state;
324 RT_TRACE(COMP_RATE, "<---- dm_check_rate_adaptive(): driver is going to unload\n");
328 if(pra->rate_adaptive_disabled)//this variable is set by ioctl.
331 // TODO: Only 11n mode is implemented currently,
332 if(!(priv->ieee80211->mode == WIRELESS_MODE_N_24G ||
333 priv->ieee80211->mode == WIRELESS_MODE_N_5G))
336 if(priv->ieee80211->state == IEEE80211_LINKED)
338 // RT_TRACE(COMP_RATE, "dm_CheckRateAdaptive(): \t");
341 // Check whether Short GI is enabled
343 bshort_gi_enabled = (pHTInfo->bCurTxBW40MHz && pHTInfo->bCurShortGI40MHz) ||
344 (!pHTInfo->bCurTxBW40MHz && pHTInfo->bCurShortGI20MHz);
347 pra->upper_rssi_threshold_ratr =
348 (pra->upper_rssi_threshold_ratr & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ;
350 pra->middle_rssi_threshold_ratr =
351 (pra->middle_rssi_threshold_ratr & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ;
353 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
355 pra->low_rssi_threshold_ratr =
356 (pra->low_rssi_threshold_ratr_40M & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ;
360 pra->low_rssi_threshold_ratr =
361 (pra->low_rssi_threshold_ratr_20M & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ;
364 pra->ping_rssi_ratr =
365 (pra->ping_rssi_ratr & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ;
367 /* 2007/10/08 MH We support RA smooth scheme now. When it is the first
368 time to link with AP. We will not change upper/lower threshold. If
369 STA stay in high or low level, we must change two different threshold
370 to prevent jumping frequently. */
371 if (pra->ratr_state == DM_RATR_STA_HIGH)
373 HighRSSIThreshForRA = pra->high2low_rssi_thresh_for_ra;
374 LowRSSIThreshForRA = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)?
375 (pra->low_rssi_thresh_for_ra40M):(pra->low_rssi_thresh_for_ra20M);
377 else if (pra->ratr_state == DM_RATR_STA_LOW)
379 HighRSSIThreshForRA = pra->high_rssi_thresh_for_ra;
380 LowRSSIThreshForRA = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)?
381 (pra->low2high_rssi_thresh_for_ra40M):(pra->low2high_rssi_thresh_for_ra20M);
385 HighRSSIThreshForRA = pra->high_rssi_thresh_for_ra;
386 LowRSSIThreshForRA = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)?
387 (pra->low_rssi_thresh_for_ra40M):(pra->low_rssi_thresh_for_ra20M);
390 //DbgPrint("[DM] THresh H/L=%d/%d\n\r", RATR.HighRSSIThreshForRA, RATR.LowRSSIThreshForRA);
391 if(priv->undecorated_smoothed_pwdb >= (long)HighRSSIThreshForRA)
393 //DbgPrint("[DM] RSSI=%d STA=HIGH\n\r", pHalData->UndecoratedSmoothedPWDB);
394 pra->ratr_state = DM_RATR_STA_HIGH;
395 targetRATR = pra->upper_rssi_threshold_ratr;
396 }else if(priv->undecorated_smoothed_pwdb >= (long)LowRSSIThreshForRA)
398 //DbgPrint("[DM] RSSI=%d STA=Middle\n\r", pHalData->UndecoratedSmoothedPWDB);
399 pra->ratr_state = DM_RATR_STA_MIDDLE;
400 targetRATR = pra->middle_rssi_threshold_ratr;
403 //DbgPrint("[DM] RSSI=%d STA=LOW\n\r", pHalData->UndecoratedSmoothedPWDB);
404 pra->ratr_state = DM_RATR_STA_LOW;
405 targetRATR = pra->low_rssi_threshold_ratr;
409 if(pra->ping_rssi_enable)
411 //pHalData->UndecoratedSmoothedPWDB = 19;
412 if(priv->undecorated_smoothed_pwdb < (long)(pra->ping_rssi_thresh_for_ra+5))
414 if((priv->undecorated_smoothed_pwdb < (long)pra->ping_rssi_thresh_for_ra) ||
417 //DbgPrint("TestRSSI = %d, set RATR to 0x%x \n", pHalData->UndecoratedSmoothedPWDB, pRA->TestRSSIRATR);
418 pra->ratr_state = DM_RATR_STA_LOW;
419 targetRATR = pra->ping_rssi_ratr;
423 // DbgPrint("TestRSSI is between the range. \n");
427 //DbgPrint("TestRSSI Recover to 0x%x \n", targetRATR);
433 // For RTL819X, if pairwisekey = wep/tkip, we support only MCS0~7.
434 if(priv->ieee80211->GetHalfNmodeSupportByAPsHandler(dev))
435 targetRATR &= 0xf00fffff;
438 // Check whether updating of RATR0 is required
440 read_nic_dword(dev, RATR0, ¤tRATR);
441 if(targetRATR != currentRATR)
444 ratr_value = targetRATR;
445 RT_TRACE(COMP_RATE,"currentRATR = %x, targetRATR = %x\n", currentRATR, targetRATR);
446 if(priv->rf_type == RF_1T2R)
448 ratr_value &= ~(RATE_ALL_OFDM_2SS);
450 write_nic_dword(dev, RATR0, ratr_value);
451 write_nic_byte(dev, UFWP, 1);
453 pra->last_ratr = targetRATR;
459 pra->ratr_state = DM_RATR_STA_MAX;
462 } // dm_CheckRateAdaptive
465 static void dm_init_bandwidth_autoswitch(struct net_device *dev)
467 struct r8192_priv *priv = ieee80211_priv(dev);
469 priv->ieee80211->bandwidth_auto_switch.threshold_20Mhzto40Mhz = BW_AUTO_SWITCH_LOW_HIGH;
470 priv->ieee80211->bandwidth_auto_switch.threshold_40Mhzto20Mhz = BW_AUTO_SWITCH_HIGH_LOW;
471 priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz = false;
472 priv->ieee80211->bandwidth_auto_switch.bautoswitch_enable = false;
474 } // dm_init_bandwidth_autoswitch
477 static void dm_bandwidth_autoswitch(struct net_device *dev)
479 struct r8192_priv *priv = ieee80211_priv(dev);
481 if(priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20 ||!priv->ieee80211->bandwidth_auto_switch.bautoswitch_enable){
484 if(priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz == false){//If send packets in 40 Mhz in 20/40
485 if(priv->undecorated_smoothed_pwdb <= priv->ieee80211->bandwidth_auto_switch.threshold_40Mhzto20Mhz)
486 priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz = true;
487 }else{//in force send packets in 20 Mhz in 20/40
488 if(priv->undecorated_smoothed_pwdb >= priv->ieee80211->bandwidth_auto_switch.threshold_20Mhzto40Mhz)
489 priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz = false;
493 } // dm_BandwidthAutoSwitch
495 //OFDM default at 0db, index=6.
496 static u32 OFDMSwingTable[OFDM_Table_Length] = {
497 0x7f8001fe, // 0, +6db
498 0x71c001c7, // 1, +5db
499 0x65400195, // 2, +4db
500 0x5a400169, // 3, +3db
501 0x50800142, // 4, +2db
502 0x47c0011f, // 5, +1db
503 0x40000100, // 6, +0db ===> default, upper for higher temperature, lower for low temperature
504 0x390000e4, // 7, -1db
505 0x32c000cb, // 8, -2db
506 0x2d4000b5, // 9, -3db
507 0x288000a2, // 10, -4db
508 0x24000090, // 11, -5db
509 0x20000080, // 12, -6db
510 0x1c800072, // 13, -7db
511 0x19800066, // 14, -8db
512 0x26c0005b, // 15, -9db
513 0x24400051, // 16, -10db
514 0x12000048, // 17, -11db
515 0x10000040 // 18, -12db
518 static u8 CCKSwingTable_Ch1_Ch13[CCK_Table_length][8] = {
519 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, // 0, +0db ===> CCK40M default
520 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, // 1, -1db
521 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, // 2, -2db
522 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, // 3, -3db
523 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, // 4, -4db
524 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, // 5, -5db
525 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, // 6, -6db ===> CCK20M default
526 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, // 7, -7db
527 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, // 8, -8db
528 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, // 9, -9db
529 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 10, -10db
530 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01} // 11, -11db
533 static u8 CCKSwingTable_Ch14[CCK_Table_length][8] = {
534 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, // 0, +0db ===> CCK40M default
535 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, // 1, -1db
536 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, // 2, -2db
537 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, // 3, -3db
538 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, // 4, -4db
539 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, // 5, -5db
540 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 6, -6db ===> CCK20M default
541 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, // 7, -7db
542 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 8, -8db
543 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 9, -9db
544 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 10, -10db
545 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00} // 11, -11db
548 static void dm_TXPowerTrackingCallback_TSSI(struct net_device *dev)
550 struct r8192_priv *priv = ieee80211_priv(dev);
551 bool bHighpowerstate, viviflag = FALSE;
553 u8 powerlevelOFDM24G;
554 int i =0, j = 0, k = 0;
555 u8 RF_Type, tmp_report[5]={0, 0, 0, 0, 0};
558 u16 Avg_TSSI_Meas, TSSI_13dBm, Avg_TSSI_Meas_from_driver=0;
559 //RT_STATUS rtStatus = RT_STATUS_SUCCESS;
560 bool rtStatus = true;
563 write_nic_byte(dev, 0x1ba, 0);
565 priv->ieee80211->bdynamic_txpower_enable = false;
566 bHighpowerstate = priv->bDynamicTxHighPower;
568 powerlevelOFDM24G = (u8)(priv->Pwr_Track>>24);
569 RF_Type = priv->rf_type;
570 Value = (RF_Type<<8) | powerlevelOFDM24G;
572 RT_TRACE(COMP_POWER_TRACKING, "powerlevelOFDM24G = %x\n", powerlevelOFDM24G);
574 for(j = 0; j<=30; j++)
577 tx_cmd.Op = TXCMD_SET_TX_PWR_TRACKING;
579 tx_cmd.Value = Value;
580 rtStatus = SendTxCommandPacket(dev, &tx_cmd, 12);
581 if (rtStatus == RT_STATUS_FAILURE)
583 RT_TRACE(COMP_POWER_TRACKING, "Set configuration with tx cmd queue fail!\n");
586 //DbgPrint("hi, vivi, strange\n");
587 for(i = 0;i <= 30; i++)
589 read_nic_byte(dev, 0x1ba, &Pwr_Flag);
596 read_nic_word(dev, 0x13c, &Avg_TSSI_Meas);
597 if(Avg_TSSI_Meas == 0)
599 write_nic_byte(dev, 0x1ba, 0);
603 for(k = 0;k < 5; k++)
606 read_nic_byte(dev, 0x134+k, &tmp_report[k]);
608 read_nic_byte(dev, 0x13e, &tmp_report[k]);
609 RT_TRACE(COMP_POWER_TRACKING, "TSSI_report_value = %d\n", tmp_report[k]);
612 //check if the report value is right
613 for(k = 0;k < 5; k++)
615 if(tmp_report[k] <= 20)
623 write_nic_byte(dev, 0x1ba, 0);
625 RT_TRACE(COMP_POWER_TRACKING, "we filtered the data\n");
626 for(k = 0;k < 5; k++)
631 for(k = 0;k < 5; k++)
633 Avg_TSSI_Meas_from_driver += tmp_report[k];
636 Avg_TSSI_Meas_from_driver = Avg_TSSI_Meas_from_driver*100/5;
637 RT_TRACE(COMP_POWER_TRACKING, "Avg_TSSI_Meas_from_driver = %d\n", Avg_TSSI_Meas_from_driver);
638 TSSI_13dBm = priv->TSSI_13dBm;
639 RT_TRACE(COMP_POWER_TRACKING, "TSSI_13dBm = %d\n", TSSI_13dBm);
641 //if(abs(Avg_TSSI_Meas_from_driver - TSSI_13dBm) <= E_FOR_TX_POWER_TRACK)
642 // For MacOS-compatible
643 if(Avg_TSSI_Meas_from_driver > TSSI_13dBm)
644 delta = Avg_TSSI_Meas_from_driver - TSSI_13dBm;
646 delta = TSSI_13dBm - Avg_TSSI_Meas_from_driver;
648 if(delta <= E_FOR_TX_POWER_TRACK)
650 priv->ieee80211->bdynamic_txpower_enable = TRUE;
651 write_nic_byte(dev, 0x1ba, 0);
652 RT_TRACE(COMP_POWER_TRACKING, "tx power track is done\n");
653 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex = %d\n", priv->rfa_txpowertrackingindex);
654 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_real = %d\n", priv->rfa_txpowertrackingindex_real);
655 RT_TRACE(COMP_POWER_TRACKING, "priv->cck_present_attentuation_difference = %d\n", priv->cck_present_attentuation_difference);
656 RT_TRACE(COMP_POWER_TRACKING, "priv->cck_present_attentuation = %d\n", priv->cck_present_attentuation);
661 if(Avg_TSSI_Meas_from_driver < TSSI_13dBm - E_FOR_TX_POWER_TRACK)
663 if (priv->rfa_txpowertrackingindex > 0)
665 priv->rfa_txpowertrackingindex--;
666 if(priv->rfa_txpowertrackingindex_real > 4)
668 priv->rfa_txpowertrackingindex_real--;
669 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex_real].txbbgain_value);
675 if (priv->rfa_txpowertrackingindex < 36)
677 priv->rfa_txpowertrackingindex++;
678 priv->rfa_txpowertrackingindex_real++;
679 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex_real].txbbgain_value);
683 priv->cck_present_attentuation_difference
684 = priv->rfa_txpowertrackingindex - priv->rfa_txpowertracking_default;
686 if(priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
687 priv->cck_present_attentuation
688 = priv->cck_present_attentuation_20Mdefault + priv->cck_present_attentuation_difference;
690 priv->cck_present_attentuation
691 = priv->cck_present_attentuation_40Mdefault + priv->cck_present_attentuation_difference;
693 if(priv->cck_present_attentuation > -1&&priv->cck_present_attentuation <23)
695 if(priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14)
697 priv->bcck_in_ch14 = TRUE;
698 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
700 else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14)
702 priv->bcck_in_ch14 = FALSE;
703 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
706 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
708 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex = %d\n", priv->rfa_txpowertrackingindex);
709 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_real = %d\n", priv->rfa_txpowertrackingindex_real);
710 RT_TRACE(COMP_POWER_TRACKING, "priv->cck_present_attentuation_difference = %d\n", priv->cck_present_attentuation_difference);
711 RT_TRACE(COMP_POWER_TRACKING, "priv->cck_present_attentuation = %d\n", priv->cck_present_attentuation);
713 if (priv->cck_present_attentuation_difference <= -12||priv->cck_present_attentuation_difference >= 24)
715 priv->ieee80211->bdynamic_txpower_enable = TRUE;
716 write_nic_byte(dev, 0x1ba, 0);
717 RT_TRACE(COMP_POWER_TRACKING, "tx power track--->limited\n");
723 write_nic_byte(dev, 0x1ba, 0);
724 Avg_TSSI_Meas_from_driver = 0;
725 for(k = 0;k < 5; k++)
730 priv->ieee80211->bdynamic_txpower_enable = TRUE;
731 write_nic_byte(dev, 0x1ba, 0);
734 static void dm_TXPowerTrackingCallback_ThermalMeter(struct net_device *dev)
736 #define ThermalMeterVal 9
737 struct r8192_priv *priv = ieee80211_priv(dev);
738 u32 tmpRegA, TempCCk;
739 u8 tmpOFDMindex, tmpCCKindex, tmpCCK20Mindex, tmpCCK40Mindex, tmpval;
740 int i =0, CCKSwingNeedUpdate=0;
742 if(!priv->btxpower_trackingInit)
744 //Query OFDM default setting
745 tmpRegA= rtl8192_QueryBBReg(dev, rOFDM0_XATxIQImbalance, bMaskDWord);
746 for(i=0; i<OFDM_Table_Length; i++) //find the index
748 if(tmpRegA == OFDMSwingTable[i])
750 priv->OFDM_index= (u8)i;
751 RT_TRACE(COMP_POWER_TRACKING, "Initial reg0x%x = 0x%x, OFDM_index=0x%x\n",
752 rOFDM0_XATxIQImbalance, tmpRegA, priv->OFDM_index);
756 //Query CCK default setting From 0xa22
757 TempCCk = rtl8192_QueryBBReg(dev, rCCK0_TxFilter1, bMaskByte2);
758 for(i=0 ; i<CCK_Table_length ; i++)
760 if(TempCCk == (u32)CCKSwingTable_Ch1_Ch13[i][0])
762 priv->CCK_index =(u8) i;
763 RT_TRACE(COMP_POWER_TRACKING, "Initial reg0x%x = 0x%x, CCK_index=0x%x\n",
764 rCCK0_TxFilter1, TempCCk, priv->CCK_index);
768 priv->btxpower_trackingInit = TRUE;
769 //pHalData->TXPowercount = 0;
773 //==========================
774 // this is only for test, should be masked
775 //==========================
777 // read and filter out unreasonable value
778 tmpRegA = rtl8192_phy_QueryRFReg(dev, RF90_PATH_A, 0x12, 0x078); // 0x12: RF Reg[10:7]
779 RT_TRACE(COMP_POWER_TRACKING, "Readback ThermalMeterA = %d \n", tmpRegA);
780 if(tmpRegA < 3 || tmpRegA > 13)
782 if(tmpRegA >= 12) // if over 12, TP will be bad when high temperature
784 RT_TRACE(COMP_POWER_TRACKING, "Valid ThermalMeterA = %d \n", tmpRegA);
785 priv->ThermalMeter[0] = ThermalMeterVal; //We use fixed value by Bryant's suggestion
786 priv->ThermalMeter[1] = ThermalMeterVal; //We use fixed value by Bryant's suggestion
788 //Get current RF-A temperature index
789 if(priv->ThermalMeter[0] >= (u8)tmpRegA) //lower temperature
791 tmpOFDMindex = tmpCCK20Mindex = 6+(priv->ThermalMeter[0]-(u8)tmpRegA);
792 tmpCCK40Mindex = tmpCCK20Mindex - 6;
793 if(tmpOFDMindex >= OFDM_Table_Length)
794 tmpOFDMindex = OFDM_Table_Length-1;
795 if(tmpCCK20Mindex >= CCK_Table_length)
796 tmpCCK20Mindex = CCK_Table_length-1;
797 if(tmpCCK40Mindex >= CCK_Table_length)
798 tmpCCK40Mindex = CCK_Table_length-1;
802 tmpval = ((u8)tmpRegA - priv->ThermalMeter[0]);
803 if(tmpval >= 6) // higher temperature
804 tmpOFDMindex = tmpCCK20Mindex = 0; // max to +6dB
806 tmpOFDMindex = tmpCCK20Mindex = 6 - tmpval;
809 //DbgPrint("%ddb, tmpOFDMindex = %d, tmpCCK20Mindex = %d, tmpCCK40Mindex = %d",
810 //((u1Byte)tmpRegA - pHalData->ThermalMeter[0]),
811 //tmpOFDMindex, tmpCCK20Mindex, tmpCCK40Mindex);
812 if(priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) //40M
813 tmpCCKindex = tmpCCK40Mindex;
815 tmpCCKindex = tmpCCK20Mindex;
817 if(priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14)
819 priv->bcck_in_ch14 = TRUE;
820 CCKSwingNeedUpdate = 1;
822 else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14)
824 priv->bcck_in_ch14 = FALSE;
825 CCKSwingNeedUpdate = 1;
828 if(priv->CCK_index != tmpCCKindex)
830 priv->CCK_index = tmpCCKindex;
831 CCKSwingNeedUpdate = 1;
834 if(CCKSwingNeedUpdate)
836 //DbgPrint("Update CCK Swing, CCK_index = %d\n", pHalData->CCK_index);
837 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
839 if(priv->OFDM_index != tmpOFDMindex)
841 priv->OFDM_index = tmpOFDMindex;
842 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable[priv->OFDM_index]);
843 RT_TRACE(COMP_POWER_TRACKING, "Update OFDMSwing[%d] = 0x%x\n",
844 priv->OFDM_index, OFDMSwingTable[priv->OFDM_index]);
846 priv->txpower_count = 0;
849 void dm_txpower_trackingcallback(struct work_struct *work)
851 struct delayed_work *dwork = container_of(work,struct delayed_work,work);
852 struct r8192_priv *priv = container_of(dwork,struct r8192_priv,txpower_tracking_wq);
853 struct net_device *dev = priv->ieee80211->dev;
855 if(priv->bDcut == TRUE)
856 dm_TXPowerTrackingCallback_TSSI(dev);
858 dm_TXPowerTrackingCallback_ThermalMeter(dev);
862 static void dm_InitializeTXPowerTracking_TSSI(struct net_device *dev)
865 struct r8192_priv *priv = ieee80211_priv(dev);
867 //Initial the Tx BB index and mapping value
868 priv->txbbgain_table[0].txbb_iq_amplifygain = 12;
869 priv->txbbgain_table[0].txbbgain_value=0x7f8001fe;
870 priv->txbbgain_table[1].txbb_iq_amplifygain = 11;
871 priv->txbbgain_table[1].txbbgain_value=0x788001e2;
872 priv->txbbgain_table[2].txbb_iq_amplifygain = 10;
873 priv->txbbgain_table[2].txbbgain_value=0x71c001c7;
874 priv->txbbgain_table[3].txbb_iq_amplifygain = 9;
875 priv->txbbgain_table[3].txbbgain_value=0x6b8001ae;
876 priv->txbbgain_table[4].txbb_iq_amplifygain = 8;
877 priv->txbbgain_table[4].txbbgain_value=0x65400195;
878 priv->txbbgain_table[5].txbb_iq_amplifygain = 7;
879 priv->txbbgain_table[5].txbbgain_value=0x5fc0017f;
880 priv->txbbgain_table[6].txbb_iq_amplifygain = 6;
881 priv->txbbgain_table[6].txbbgain_value=0x5a400169;
882 priv->txbbgain_table[7].txbb_iq_amplifygain = 5;
883 priv->txbbgain_table[7].txbbgain_value=0x55400155;
884 priv->txbbgain_table[8].txbb_iq_amplifygain = 4;
885 priv->txbbgain_table[8].txbbgain_value=0x50800142;
886 priv->txbbgain_table[9].txbb_iq_amplifygain = 3;
887 priv->txbbgain_table[9].txbbgain_value=0x4c000130;
888 priv->txbbgain_table[10].txbb_iq_amplifygain = 2;
889 priv->txbbgain_table[10].txbbgain_value=0x47c0011f;
890 priv->txbbgain_table[11].txbb_iq_amplifygain = 1;
891 priv->txbbgain_table[11].txbbgain_value=0x43c0010f;
892 priv->txbbgain_table[12].txbb_iq_amplifygain = 0;
893 priv->txbbgain_table[12].txbbgain_value=0x40000100;
894 priv->txbbgain_table[13].txbb_iq_amplifygain = -1;
895 priv->txbbgain_table[13].txbbgain_value=0x3c8000f2;
896 priv->txbbgain_table[14].txbb_iq_amplifygain = -2;
897 priv->txbbgain_table[14].txbbgain_value=0x390000e4;
898 priv->txbbgain_table[15].txbb_iq_amplifygain = -3;
899 priv->txbbgain_table[15].txbbgain_value=0x35c000d7;
900 priv->txbbgain_table[16].txbb_iq_amplifygain = -4;
901 priv->txbbgain_table[16].txbbgain_value=0x32c000cb;
902 priv->txbbgain_table[17].txbb_iq_amplifygain = -5;
903 priv->txbbgain_table[17].txbbgain_value=0x300000c0;
904 priv->txbbgain_table[18].txbb_iq_amplifygain = -6;
905 priv->txbbgain_table[18].txbbgain_value=0x2d4000b5;
906 priv->txbbgain_table[19].txbb_iq_amplifygain = -7;
907 priv->txbbgain_table[19].txbbgain_value=0x2ac000ab;
908 priv->txbbgain_table[20].txbb_iq_amplifygain = -8;
909 priv->txbbgain_table[20].txbbgain_value=0x288000a2;
910 priv->txbbgain_table[21].txbb_iq_amplifygain = -9;
911 priv->txbbgain_table[21].txbbgain_value=0x26000098;
912 priv->txbbgain_table[22].txbb_iq_amplifygain = -10;
913 priv->txbbgain_table[22].txbbgain_value=0x24000090;
914 priv->txbbgain_table[23].txbb_iq_amplifygain = -11;
915 priv->txbbgain_table[23].txbbgain_value=0x22000088;
916 priv->txbbgain_table[24].txbb_iq_amplifygain = -12;
917 priv->txbbgain_table[24].txbbgain_value=0x20000080;
918 priv->txbbgain_table[25].txbb_iq_amplifygain = -13;
919 priv->txbbgain_table[25].txbbgain_value=0x1a00006c;
920 priv->txbbgain_table[26].txbb_iq_amplifygain = -14;
921 priv->txbbgain_table[26].txbbgain_value=0x1c800072;
922 priv->txbbgain_table[27].txbb_iq_amplifygain = -15;
923 priv->txbbgain_table[27].txbbgain_value=0x18000060;
924 priv->txbbgain_table[28].txbb_iq_amplifygain = -16;
925 priv->txbbgain_table[28].txbbgain_value=0x19800066;
926 priv->txbbgain_table[29].txbb_iq_amplifygain = -17;
927 priv->txbbgain_table[29].txbbgain_value=0x15800056;
928 priv->txbbgain_table[30].txbb_iq_amplifygain = -18;
929 priv->txbbgain_table[30].txbbgain_value=0x26c0005b;
930 priv->txbbgain_table[31].txbb_iq_amplifygain = -19;
931 priv->txbbgain_table[31].txbbgain_value=0x14400051;
932 priv->txbbgain_table[32].txbb_iq_amplifygain = -20;
933 priv->txbbgain_table[32].txbbgain_value=0x24400051;
934 priv->txbbgain_table[33].txbb_iq_amplifygain = -21;
935 priv->txbbgain_table[33].txbbgain_value=0x1300004c;
936 priv->txbbgain_table[34].txbb_iq_amplifygain = -22;
937 priv->txbbgain_table[34].txbbgain_value=0x12000048;
938 priv->txbbgain_table[35].txbb_iq_amplifygain = -23;
939 priv->txbbgain_table[35].txbbgain_value=0x11000044;
940 priv->txbbgain_table[36].txbb_iq_amplifygain = -24;
941 priv->txbbgain_table[36].txbbgain_value=0x10000040;
943 //ccktxbb_valuearray[0] is 0xA22 [1] is 0xA24 ...[7] is 0xA29
944 //This Table is for CH1~CH13
945 priv->cck_txbbgain_table[0].ccktxbb_valuearray[0] = 0x36;
946 priv->cck_txbbgain_table[0].ccktxbb_valuearray[1] = 0x35;
947 priv->cck_txbbgain_table[0].ccktxbb_valuearray[2] = 0x2e;
948 priv->cck_txbbgain_table[0].ccktxbb_valuearray[3] = 0x25;
949 priv->cck_txbbgain_table[0].ccktxbb_valuearray[4] = 0x1c;
950 priv->cck_txbbgain_table[0].ccktxbb_valuearray[5] = 0x12;
951 priv->cck_txbbgain_table[0].ccktxbb_valuearray[6] = 0x09;
952 priv->cck_txbbgain_table[0].ccktxbb_valuearray[7] = 0x04;
954 priv->cck_txbbgain_table[1].ccktxbb_valuearray[0] = 0x33;
955 priv->cck_txbbgain_table[1].ccktxbb_valuearray[1] = 0x32;
956 priv->cck_txbbgain_table[1].ccktxbb_valuearray[2] = 0x2b;
957 priv->cck_txbbgain_table[1].ccktxbb_valuearray[3] = 0x23;
958 priv->cck_txbbgain_table[1].ccktxbb_valuearray[4] = 0x1a;
959 priv->cck_txbbgain_table[1].ccktxbb_valuearray[5] = 0x11;
960 priv->cck_txbbgain_table[1].ccktxbb_valuearray[6] = 0x08;
961 priv->cck_txbbgain_table[1].ccktxbb_valuearray[7] = 0x04;
963 priv->cck_txbbgain_table[2].ccktxbb_valuearray[0] = 0x30;
964 priv->cck_txbbgain_table[2].ccktxbb_valuearray[1] = 0x2f;
965 priv->cck_txbbgain_table[2].ccktxbb_valuearray[2] = 0x29;
966 priv->cck_txbbgain_table[2].ccktxbb_valuearray[3] = 0x21;
967 priv->cck_txbbgain_table[2].ccktxbb_valuearray[4] = 0x19;
968 priv->cck_txbbgain_table[2].ccktxbb_valuearray[5] = 0x10;
969 priv->cck_txbbgain_table[2].ccktxbb_valuearray[6] = 0x08;
970 priv->cck_txbbgain_table[2].ccktxbb_valuearray[7] = 0x03;
972 priv->cck_txbbgain_table[3].ccktxbb_valuearray[0] = 0x2d;
973 priv->cck_txbbgain_table[3].ccktxbb_valuearray[1] = 0x2d;
974 priv->cck_txbbgain_table[3].ccktxbb_valuearray[2] = 0x27;
975 priv->cck_txbbgain_table[3].ccktxbb_valuearray[3] = 0x1f;
976 priv->cck_txbbgain_table[3].ccktxbb_valuearray[4] = 0x18;
977 priv->cck_txbbgain_table[3].ccktxbb_valuearray[5] = 0x0f;
978 priv->cck_txbbgain_table[3].ccktxbb_valuearray[6] = 0x08;
979 priv->cck_txbbgain_table[3].ccktxbb_valuearray[7] = 0x03;
981 priv->cck_txbbgain_table[4].ccktxbb_valuearray[0] = 0x2b;
982 priv->cck_txbbgain_table[4].ccktxbb_valuearray[1] = 0x2a;
983 priv->cck_txbbgain_table[4].ccktxbb_valuearray[2] = 0x25;
984 priv->cck_txbbgain_table[4].ccktxbb_valuearray[3] = 0x1e;
985 priv->cck_txbbgain_table[4].ccktxbb_valuearray[4] = 0x16;
986 priv->cck_txbbgain_table[4].ccktxbb_valuearray[5] = 0x0e;
987 priv->cck_txbbgain_table[4].ccktxbb_valuearray[6] = 0x07;
988 priv->cck_txbbgain_table[4].ccktxbb_valuearray[7] = 0x03;
990 priv->cck_txbbgain_table[5].ccktxbb_valuearray[0] = 0x28;
991 priv->cck_txbbgain_table[5].ccktxbb_valuearray[1] = 0x28;
992 priv->cck_txbbgain_table[5].ccktxbb_valuearray[2] = 0x22;
993 priv->cck_txbbgain_table[5].ccktxbb_valuearray[3] = 0x1c;
994 priv->cck_txbbgain_table[5].ccktxbb_valuearray[4] = 0x15;
995 priv->cck_txbbgain_table[5].ccktxbb_valuearray[5] = 0x0d;
996 priv->cck_txbbgain_table[5].ccktxbb_valuearray[6] = 0x07;
997 priv->cck_txbbgain_table[5].ccktxbb_valuearray[7] = 0x03;
999 priv->cck_txbbgain_table[6].ccktxbb_valuearray[0] = 0x26;
1000 priv->cck_txbbgain_table[6].ccktxbb_valuearray[1] = 0x25;
1001 priv->cck_txbbgain_table[6].ccktxbb_valuearray[2] = 0x21;
1002 priv->cck_txbbgain_table[6].ccktxbb_valuearray[3] = 0x1b;
1003 priv->cck_txbbgain_table[6].ccktxbb_valuearray[4] = 0x14;
1004 priv->cck_txbbgain_table[6].ccktxbb_valuearray[5] = 0x0d;
1005 priv->cck_txbbgain_table[6].ccktxbb_valuearray[6] = 0x06;
1006 priv->cck_txbbgain_table[6].ccktxbb_valuearray[7] = 0x03;
1008 priv->cck_txbbgain_table[7].ccktxbb_valuearray[0] = 0x24;
1009 priv->cck_txbbgain_table[7].ccktxbb_valuearray[1] = 0x23;
1010 priv->cck_txbbgain_table[7].ccktxbb_valuearray[2] = 0x1f;
1011 priv->cck_txbbgain_table[7].ccktxbb_valuearray[3] = 0x19;
1012 priv->cck_txbbgain_table[7].ccktxbb_valuearray[4] = 0x13;
1013 priv->cck_txbbgain_table[7].ccktxbb_valuearray[5] = 0x0c;
1014 priv->cck_txbbgain_table[7].ccktxbb_valuearray[6] = 0x06;
1015 priv->cck_txbbgain_table[7].ccktxbb_valuearray[7] = 0x03;
1017 priv->cck_txbbgain_table[8].ccktxbb_valuearray[0] = 0x22;
1018 priv->cck_txbbgain_table[8].ccktxbb_valuearray[1] = 0x21;
1019 priv->cck_txbbgain_table[8].ccktxbb_valuearray[2] = 0x1d;
1020 priv->cck_txbbgain_table[8].ccktxbb_valuearray[3] = 0x18;
1021 priv->cck_txbbgain_table[8].ccktxbb_valuearray[4] = 0x11;
1022 priv->cck_txbbgain_table[8].ccktxbb_valuearray[5] = 0x0b;
1023 priv->cck_txbbgain_table[8].ccktxbb_valuearray[6] = 0x06;
1024 priv->cck_txbbgain_table[8].ccktxbb_valuearray[7] = 0x02;
1026 priv->cck_txbbgain_table[9].ccktxbb_valuearray[0] = 0x20;
1027 priv->cck_txbbgain_table[9].ccktxbb_valuearray[1] = 0x20;
1028 priv->cck_txbbgain_table[9].ccktxbb_valuearray[2] = 0x1b;
1029 priv->cck_txbbgain_table[9].ccktxbb_valuearray[3] = 0x16;
1030 priv->cck_txbbgain_table[9].ccktxbb_valuearray[4] = 0x11;
1031 priv->cck_txbbgain_table[9].ccktxbb_valuearray[5] = 0x08;
1032 priv->cck_txbbgain_table[9].ccktxbb_valuearray[6] = 0x05;
1033 priv->cck_txbbgain_table[9].ccktxbb_valuearray[7] = 0x02;
1035 priv->cck_txbbgain_table[10].ccktxbb_valuearray[0] = 0x1f;
1036 priv->cck_txbbgain_table[10].ccktxbb_valuearray[1] = 0x1e;
1037 priv->cck_txbbgain_table[10].ccktxbb_valuearray[2] = 0x1a;
1038 priv->cck_txbbgain_table[10].ccktxbb_valuearray[3] = 0x15;
1039 priv->cck_txbbgain_table[10].ccktxbb_valuearray[4] = 0x10;
1040 priv->cck_txbbgain_table[10].ccktxbb_valuearray[5] = 0x0a;
1041 priv->cck_txbbgain_table[10].ccktxbb_valuearray[6] = 0x05;
1042 priv->cck_txbbgain_table[10].ccktxbb_valuearray[7] = 0x02;
1044 priv->cck_txbbgain_table[11].ccktxbb_valuearray[0] = 0x1d;
1045 priv->cck_txbbgain_table[11].ccktxbb_valuearray[1] = 0x1c;
1046 priv->cck_txbbgain_table[11].ccktxbb_valuearray[2] = 0x18;
1047 priv->cck_txbbgain_table[11].ccktxbb_valuearray[3] = 0x14;
1048 priv->cck_txbbgain_table[11].ccktxbb_valuearray[4] = 0x0f;
1049 priv->cck_txbbgain_table[11].ccktxbb_valuearray[5] = 0x0a;
1050 priv->cck_txbbgain_table[11].ccktxbb_valuearray[6] = 0x05;
1051 priv->cck_txbbgain_table[11].ccktxbb_valuearray[7] = 0x02;
1053 priv->cck_txbbgain_table[12].ccktxbb_valuearray[0] = 0x1b;
1054 priv->cck_txbbgain_table[12].ccktxbb_valuearray[1] = 0x1a;
1055 priv->cck_txbbgain_table[12].ccktxbb_valuearray[2] = 0x17;
1056 priv->cck_txbbgain_table[12].ccktxbb_valuearray[3] = 0x13;
1057 priv->cck_txbbgain_table[12].ccktxbb_valuearray[4] = 0x0e;
1058 priv->cck_txbbgain_table[12].ccktxbb_valuearray[5] = 0x09;
1059 priv->cck_txbbgain_table[12].ccktxbb_valuearray[6] = 0x04;
1060 priv->cck_txbbgain_table[12].ccktxbb_valuearray[7] = 0x02;
1062 priv->cck_txbbgain_table[13].ccktxbb_valuearray[0] = 0x1a;
1063 priv->cck_txbbgain_table[13].ccktxbb_valuearray[1] = 0x19;
1064 priv->cck_txbbgain_table[13].ccktxbb_valuearray[2] = 0x16;
1065 priv->cck_txbbgain_table[13].ccktxbb_valuearray[3] = 0x12;
1066 priv->cck_txbbgain_table[13].ccktxbb_valuearray[4] = 0x0d;
1067 priv->cck_txbbgain_table[13].ccktxbb_valuearray[5] = 0x09;
1068 priv->cck_txbbgain_table[13].ccktxbb_valuearray[6] = 0x04;
1069 priv->cck_txbbgain_table[13].ccktxbb_valuearray[7] = 0x02;
1071 priv->cck_txbbgain_table[14].ccktxbb_valuearray[0] = 0x18;
1072 priv->cck_txbbgain_table[14].ccktxbb_valuearray[1] = 0x17;
1073 priv->cck_txbbgain_table[14].ccktxbb_valuearray[2] = 0x15;
1074 priv->cck_txbbgain_table[14].ccktxbb_valuearray[3] = 0x11;
1075 priv->cck_txbbgain_table[14].ccktxbb_valuearray[4] = 0x0c;
1076 priv->cck_txbbgain_table[14].ccktxbb_valuearray[5] = 0x08;
1077 priv->cck_txbbgain_table[14].ccktxbb_valuearray[6] = 0x04;
1078 priv->cck_txbbgain_table[14].ccktxbb_valuearray[7] = 0x02;
1080 priv->cck_txbbgain_table[15].ccktxbb_valuearray[0] = 0x17;
1081 priv->cck_txbbgain_table[15].ccktxbb_valuearray[1] = 0x16;
1082 priv->cck_txbbgain_table[15].ccktxbb_valuearray[2] = 0x13;
1083 priv->cck_txbbgain_table[15].ccktxbb_valuearray[3] = 0x10;
1084 priv->cck_txbbgain_table[15].ccktxbb_valuearray[4] = 0x0c;
1085 priv->cck_txbbgain_table[15].ccktxbb_valuearray[5] = 0x08;
1086 priv->cck_txbbgain_table[15].ccktxbb_valuearray[6] = 0x04;
1087 priv->cck_txbbgain_table[15].ccktxbb_valuearray[7] = 0x02;
1089 priv->cck_txbbgain_table[16].ccktxbb_valuearray[0] = 0x16;
1090 priv->cck_txbbgain_table[16].ccktxbb_valuearray[1] = 0x15;
1091 priv->cck_txbbgain_table[16].ccktxbb_valuearray[2] = 0x12;
1092 priv->cck_txbbgain_table[16].ccktxbb_valuearray[3] = 0x0f;
1093 priv->cck_txbbgain_table[16].ccktxbb_valuearray[4] = 0x0b;
1094 priv->cck_txbbgain_table[16].ccktxbb_valuearray[5] = 0x07;
1095 priv->cck_txbbgain_table[16].ccktxbb_valuearray[6] = 0x04;
1096 priv->cck_txbbgain_table[16].ccktxbb_valuearray[7] = 0x01;
1098 priv->cck_txbbgain_table[17].ccktxbb_valuearray[0] = 0x14;
1099 priv->cck_txbbgain_table[17].ccktxbb_valuearray[1] = 0x14;
1100 priv->cck_txbbgain_table[17].ccktxbb_valuearray[2] = 0x11;
1101 priv->cck_txbbgain_table[17].ccktxbb_valuearray[3] = 0x0e;
1102 priv->cck_txbbgain_table[17].ccktxbb_valuearray[4] = 0x0b;
1103 priv->cck_txbbgain_table[17].ccktxbb_valuearray[5] = 0x07;
1104 priv->cck_txbbgain_table[17].ccktxbb_valuearray[6] = 0x03;
1105 priv->cck_txbbgain_table[17].ccktxbb_valuearray[7] = 0x02;
1107 priv->cck_txbbgain_table[18].ccktxbb_valuearray[0] = 0x13;
1108 priv->cck_txbbgain_table[18].ccktxbb_valuearray[1] = 0x13;
1109 priv->cck_txbbgain_table[18].ccktxbb_valuearray[2] = 0x10;
1110 priv->cck_txbbgain_table[18].ccktxbb_valuearray[3] = 0x0d;
1111 priv->cck_txbbgain_table[18].ccktxbb_valuearray[4] = 0x0a;
1112 priv->cck_txbbgain_table[18].ccktxbb_valuearray[5] = 0x06;
1113 priv->cck_txbbgain_table[18].ccktxbb_valuearray[6] = 0x03;
1114 priv->cck_txbbgain_table[18].ccktxbb_valuearray[7] = 0x01;
1116 priv->cck_txbbgain_table[19].ccktxbb_valuearray[0] = 0x12;
1117 priv->cck_txbbgain_table[19].ccktxbb_valuearray[1] = 0x12;
1118 priv->cck_txbbgain_table[19].ccktxbb_valuearray[2] = 0x0f;
1119 priv->cck_txbbgain_table[19].ccktxbb_valuearray[3] = 0x0c;
1120 priv->cck_txbbgain_table[19].ccktxbb_valuearray[4] = 0x09;
1121 priv->cck_txbbgain_table[19].ccktxbb_valuearray[5] = 0x06;
1122 priv->cck_txbbgain_table[19].ccktxbb_valuearray[6] = 0x03;
1123 priv->cck_txbbgain_table[19].ccktxbb_valuearray[7] = 0x01;
1125 priv->cck_txbbgain_table[20].ccktxbb_valuearray[0] = 0x11;
1126 priv->cck_txbbgain_table[20].ccktxbb_valuearray[1] = 0x11;
1127 priv->cck_txbbgain_table[20].ccktxbb_valuearray[2] = 0x0f;
1128 priv->cck_txbbgain_table[20].ccktxbb_valuearray[3] = 0x0c;
1129 priv->cck_txbbgain_table[20].ccktxbb_valuearray[4] = 0x09;
1130 priv->cck_txbbgain_table[20].ccktxbb_valuearray[5] = 0x06;
1131 priv->cck_txbbgain_table[20].ccktxbb_valuearray[6] = 0x03;
1132 priv->cck_txbbgain_table[20].ccktxbb_valuearray[7] = 0x01;
1134 priv->cck_txbbgain_table[21].ccktxbb_valuearray[0] = 0x10;
1135 priv->cck_txbbgain_table[21].ccktxbb_valuearray[1] = 0x10;
1136 priv->cck_txbbgain_table[21].ccktxbb_valuearray[2] = 0x0e;
1137 priv->cck_txbbgain_table[21].ccktxbb_valuearray[3] = 0x0b;
1138 priv->cck_txbbgain_table[21].ccktxbb_valuearray[4] = 0x08;
1139 priv->cck_txbbgain_table[21].ccktxbb_valuearray[5] = 0x05;
1140 priv->cck_txbbgain_table[21].ccktxbb_valuearray[6] = 0x03;
1141 priv->cck_txbbgain_table[21].ccktxbb_valuearray[7] = 0x01;
1143 priv->cck_txbbgain_table[22].ccktxbb_valuearray[0] = 0x0f;
1144 priv->cck_txbbgain_table[22].ccktxbb_valuearray[1] = 0x0f;
1145 priv->cck_txbbgain_table[22].ccktxbb_valuearray[2] = 0x0d;
1146 priv->cck_txbbgain_table[22].ccktxbb_valuearray[3] = 0x0b;
1147 priv->cck_txbbgain_table[22].ccktxbb_valuearray[4] = 0x08;
1148 priv->cck_txbbgain_table[22].ccktxbb_valuearray[5] = 0x05;
1149 priv->cck_txbbgain_table[22].ccktxbb_valuearray[6] = 0x03;
1150 priv->cck_txbbgain_table[22].ccktxbb_valuearray[7] = 0x01;
1152 //ccktxbb_valuearray[0] is 0xA22 [1] is 0xA24 ...[7] is 0xA29
1153 //This Table is for CH14
1154 priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[0] = 0x36;
1155 priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[1] = 0x35;
1156 priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[2] = 0x2e;
1157 priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[3] = 0x1b;
1158 priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[4] = 0x00;
1159 priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[5] = 0x00;
1160 priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[6] = 0x00;
1161 priv->cck_txbbgain_ch14_table[0].ccktxbb_valuearray[7] = 0x00;
1163 priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[0] = 0x33;
1164 priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[1] = 0x32;
1165 priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[2] = 0x2b;
1166 priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[3] = 0x19;
1167 priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[4] = 0x00;
1168 priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[5] = 0x00;
1169 priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[6] = 0x00;
1170 priv->cck_txbbgain_ch14_table[1].ccktxbb_valuearray[7] = 0x00;
1172 priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[0] = 0x30;
1173 priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[1] = 0x2f;
1174 priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[2] = 0x29;
1175 priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[3] = 0x18;
1176 priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[4] = 0x00;
1177 priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[5] = 0x00;
1178 priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[6] = 0x00;
1179 priv->cck_txbbgain_ch14_table[2].ccktxbb_valuearray[7] = 0x00;
1181 priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[0] = 0x2d;
1182 priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[1] = 0x2d;
1183 priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[2] = 0x27;
1184 priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[3] = 0x17;
1185 priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[4] = 0x00;
1186 priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[5] = 0x00;
1187 priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[6] = 0x00;
1188 priv->cck_txbbgain_ch14_table[3].ccktxbb_valuearray[7] = 0x00;
1190 priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[0] = 0x2b;
1191 priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[1] = 0x2a;
1192 priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[2] = 0x25;
1193 priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[3] = 0x15;
1194 priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[4] = 0x00;
1195 priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[5] = 0x00;
1196 priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[6] = 0x00;
1197 priv->cck_txbbgain_ch14_table[4].ccktxbb_valuearray[7] = 0x00;
1199 priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[0] = 0x28;
1200 priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[1] = 0x28;
1201 priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[2] = 0x22;
1202 priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[3] = 0x14;
1203 priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[4] = 0x00;
1204 priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[5] = 0x00;
1205 priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[6] = 0x00;
1206 priv->cck_txbbgain_ch14_table[5].ccktxbb_valuearray[7] = 0x00;
1208 priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[0] = 0x26;
1209 priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[1] = 0x25;
1210 priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[2] = 0x21;
1211 priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[3] = 0x13;
1212 priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[4] = 0x00;
1213 priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[5] = 0x00;
1214 priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[6] = 0x00;
1215 priv->cck_txbbgain_ch14_table[6].ccktxbb_valuearray[7] = 0x00;
1217 priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[0] = 0x24;
1218 priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[1] = 0x23;
1219 priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[2] = 0x1f;
1220 priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[3] = 0x12;
1221 priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[4] = 0x00;
1222 priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[5] = 0x00;
1223 priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[6] = 0x00;
1224 priv->cck_txbbgain_ch14_table[7].ccktxbb_valuearray[7] = 0x00;
1226 priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[0] = 0x22;
1227 priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[1] = 0x21;
1228 priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[2] = 0x1d;
1229 priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[3] = 0x11;
1230 priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[4] = 0x00;
1231 priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[5] = 0x00;
1232 priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[6] = 0x00;
1233 priv->cck_txbbgain_ch14_table[8].ccktxbb_valuearray[7] = 0x00;
1235 priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[0] = 0x20;
1236 priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[1] = 0x20;
1237 priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[2] = 0x1b;
1238 priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[3] = 0x10;
1239 priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[4] = 0x00;
1240 priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[5] = 0x00;
1241 priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[6] = 0x00;
1242 priv->cck_txbbgain_ch14_table[9].ccktxbb_valuearray[7] = 0x00;
1244 priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[0] = 0x1f;
1245 priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[1] = 0x1e;
1246 priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[2] = 0x1a;
1247 priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[3] = 0x0f;
1248 priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[4] = 0x00;
1249 priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[5] = 0x00;
1250 priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[6] = 0x00;
1251 priv->cck_txbbgain_ch14_table[10].ccktxbb_valuearray[7] = 0x00;
1253 priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[0] = 0x1d;
1254 priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[1] = 0x1c;
1255 priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[2] = 0x18;
1256 priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[3] = 0x0e;
1257 priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[4] = 0x00;
1258 priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[5] = 0x00;
1259 priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[6] = 0x00;
1260 priv->cck_txbbgain_ch14_table[11].ccktxbb_valuearray[7] = 0x00;
1262 priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[0] = 0x1b;
1263 priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[1] = 0x1a;
1264 priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[2] = 0x17;
1265 priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[3] = 0x0e;
1266 priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[4] = 0x00;
1267 priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[5] = 0x00;
1268 priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[6] = 0x00;
1269 priv->cck_txbbgain_ch14_table[12].ccktxbb_valuearray[7] = 0x00;
1271 priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[0] = 0x1a;
1272 priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[1] = 0x19;
1273 priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[2] = 0x16;
1274 priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[3] = 0x0d;
1275 priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[4] = 0x00;
1276 priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[5] = 0x00;
1277 priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[6] = 0x00;
1278 priv->cck_txbbgain_ch14_table[13].ccktxbb_valuearray[7] = 0x00;
1280 priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[0] = 0x18;
1281 priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[1] = 0x17;
1282 priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[2] = 0x15;
1283 priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[3] = 0x0c;
1284 priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[4] = 0x00;
1285 priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[5] = 0x00;
1286 priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[6] = 0x00;
1287 priv->cck_txbbgain_ch14_table[14].ccktxbb_valuearray[7] = 0x00;
1289 priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[0] = 0x17;
1290 priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[1] = 0x16;
1291 priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[2] = 0x13;
1292 priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[3] = 0x0b;
1293 priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[4] = 0x00;
1294 priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[5] = 0x00;
1295 priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[6] = 0x00;
1296 priv->cck_txbbgain_ch14_table[15].ccktxbb_valuearray[7] = 0x00;
1298 priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[0] = 0x16;
1299 priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[1] = 0x15;
1300 priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[2] = 0x12;
1301 priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[3] = 0x0b;
1302 priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[4] = 0x00;
1303 priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[5] = 0x00;
1304 priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[6] = 0x00;
1305 priv->cck_txbbgain_ch14_table[16].ccktxbb_valuearray[7] = 0x00;
1307 priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[0] = 0x14;
1308 priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[1] = 0x14;
1309 priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[2] = 0x11;
1310 priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[3] = 0x0a;
1311 priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[4] = 0x00;
1312 priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[5] = 0x00;
1313 priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[6] = 0x00;
1314 priv->cck_txbbgain_ch14_table[17].ccktxbb_valuearray[7] = 0x00;
1316 priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[0] = 0x13;
1317 priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[1] = 0x13;
1318 priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[2] = 0x10;
1319 priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[3] = 0x0a;
1320 priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[4] = 0x00;
1321 priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[5] = 0x00;
1322 priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[6] = 0x00;
1323 priv->cck_txbbgain_ch14_table[18].ccktxbb_valuearray[7] = 0x00;
1325 priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[0] = 0x12;
1326 priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[1] = 0x12;
1327 priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[2] = 0x0f;
1328 priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[3] = 0x09;
1329 priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[4] = 0x00;
1330 priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[5] = 0x00;
1331 priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[6] = 0x00;
1332 priv->cck_txbbgain_ch14_table[19].ccktxbb_valuearray[7] = 0x00;
1334 priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[0] = 0x11;
1335 priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[1] = 0x11;
1336 priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[2] = 0x0f;
1337 priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[3] = 0x09;
1338 priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[4] = 0x00;
1339 priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[5] = 0x00;
1340 priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[6] = 0x00;
1341 priv->cck_txbbgain_ch14_table[20].ccktxbb_valuearray[7] = 0x00;
1343 priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[0] = 0x10;
1344 priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[1] = 0x10;
1345 priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[2] = 0x0e;
1346 priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[3] = 0x08;
1347 priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[4] = 0x00;
1348 priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[5] = 0x00;
1349 priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[6] = 0x00;
1350 priv->cck_txbbgain_ch14_table[21].ccktxbb_valuearray[7] = 0x00;
1352 priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[0] = 0x0f;
1353 priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[1] = 0x0f;
1354 priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[2] = 0x0d;
1355 priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[3] = 0x08;
1356 priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[4] = 0x00;
1357 priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[5] = 0x00;
1358 priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[6] = 0x00;
1359 priv->cck_txbbgain_ch14_table[22].ccktxbb_valuearray[7] = 0x00;
1361 priv->btxpower_tracking = TRUE;
1362 priv->txpower_count = 0;
1363 priv->btxpower_trackingInit = FALSE;
1367 static void dm_InitializeTXPowerTracking_ThermalMeter(struct net_device *dev)
1369 struct r8192_priv *priv = ieee80211_priv(dev);
1371 // Tx Power tracking by Thermal Meter requires Firmware R/W 3-wire. This mechanism
1372 // can be enabled only when Firmware R/W 3-wire is enabled. Otherwise, frequent r/w
1373 // 3-wire by driver causes RF to go into a wrong state.
1374 if(priv->ieee80211->FwRWRF)
1375 priv->btxpower_tracking = TRUE;
1377 priv->btxpower_tracking = FALSE;
1378 priv->txpower_count = 0;
1379 priv->btxpower_trackingInit = FALSE;
1383 void dm_initialize_txpower_tracking(struct net_device *dev)
1385 struct r8192_priv *priv = ieee80211_priv(dev);
1386 if(priv->bDcut == TRUE)
1387 dm_InitializeTXPowerTracking_TSSI(dev);
1389 dm_InitializeTXPowerTracking_ThermalMeter(dev);
1390 }// dm_InitializeTXPowerTracking
1393 static void dm_CheckTXPowerTracking_TSSI(struct net_device *dev)
1395 struct r8192_priv *priv = ieee80211_priv(dev);
1396 static u32 tx_power_track_counter;
1398 if(!priv->btxpower_tracking)
1402 if((tx_power_track_counter % 30 == 0)&&(tx_power_track_counter != 0))
1404 queue_delayed_work(priv->priv_wq,&priv->txpower_tracking_wq,0);
1406 tx_power_track_counter++;
1412 static void dm_CheckTXPowerTracking_ThermalMeter(struct net_device *dev)
1414 struct r8192_priv *priv = ieee80211_priv(dev);
1415 static u8 TM_Trigger;
1416 //DbgPrint("dm_CheckTXPowerTracking() \n");
1417 if(!priv->btxpower_tracking)
1421 if(priv->txpower_count <= 2)
1423 priv->txpower_count++;
1430 //Attention!! You have to write all 12bits of data to RF, or it may cause RF to crash
1431 //actually write reg0x02 bit1=0, then bit1=1.
1432 //DbgPrint("Trigger ThermalMeter, write RF reg0x2 = 0x4d to 0x4f\n");
1433 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4d);
1434 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4f);
1435 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4d);
1436 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4f);
1442 //DbgPrint("Schedule TxPowerTrackingWorkItem\n");
1443 queue_delayed_work(priv->priv_wq,&priv->txpower_tracking_wq,0);
1449 static void dm_check_txpower_tracking(struct net_device *dev)
1451 struct r8192_priv *priv = ieee80211_priv(dev);
1452 //static u32 tx_power_track_counter = 0;
1455 dm_CheckTXPowerTracking_TSSI(dev);
1457 if(priv->bDcut == TRUE)
1458 dm_CheckTXPowerTracking_TSSI(dev);
1460 dm_CheckTXPowerTracking_ThermalMeter(dev);
1463 } // dm_CheckTXPowerTracking
1466 static void dm_CCKTxPowerAdjust_TSSI(struct net_device *dev, bool bInCH14)
1469 struct r8192_priv *priv = ieee80211_priv(dev);
1474 TempVal = priv->cck_txbbgain_table[priv->cck_present_attentuation].ccktxbb_valuearray[0] +
1475 (priv->cck_txbbgain_table[priv->cck_present_attentuation].ccktxbb_valuearray[1]<<8) ;
1477 rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal);
1478 //Write 0xa24 ~ 0xa27
1480 TempVal = priv->cck_txbbgain_table[priv->cck_present_attentuation].ccktxbb_valuearray[2] +
1481 (priv->cck_txbbgain_table[priv->cck_present_attentuation].ccktxbb_valuearray[3]<<8) +
1482 (priv->cck_txbbgain_table[priv->cck_present_attentuation].ccktxbb_valuearray[4]<<16)+
1483 (priv->cck_txbbgain_table[priv->cck_present_attentuation].ccktxbb_valuearray[5]<<24);
1484 rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal);
1487 TempVal = priv->cck_txbbgain_table[priv->cck_present_attentuation].ccktxbb_valuearray[6] +
1488 (priv->cck_txbbgain_table[priv->cck_present_attentuation].ccktxbb_valuearray[7]<<8) ;
1490 rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal);
1494 TempVal = priv->cck_txbbgain_ch14_table[priv->cck_present_attentuation].ccktxbb_valuearray[0] +
1495 (priv->cck_txbbgain_ch14_table[priv->cck_present_attentuation].ccktxbb_valuearray[1]<<8) ;
1497 rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal);
1498 //Write 0xa24 ~ 0xa27
1500 TempVal = priv->cck_txbbgain_ch14_table[priv->cck_present_attentuation].ccktxbb_valuearray[2] +
1501 (priv->cck_txbbgain_ch14_table[priv->cck_present_attentuation].ccktxbb_valuearray[3]<<8) +
1502 (priv->cck_txbbgain_ch14_table[priv->cck_present_attentuation].ccktxbb_valuearray[4]<<16)+
1503 (priv->cck_txbbgain_ch14_table[priv->cck_present_attentuation].ccktxbb_valuearray[5]<<24);
1504 rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal);
1507 TempVal = priv->cck_txbbgain_ch14_table[priv->cck_present_attentuation].ccktxbb_valuearray[6] +
1508 (priv->cck_txbbgain_ch14_table[priv->cck_present_attentuation].ccktxbb_valuearray[7]<<8) ;
1510 rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal);
1516 static void dm_CCKTxPowerAdjust_ThermalMeter(struct net_device *dev, bool bInCH14)
1519 struct r8192_priv *priv = ieee80211_priv(dev);
1525 TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][0] +
1526 (CCKSwingTable_Ch1_Ch13[priv->CCK_index][1]<<8) ;
1527 rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal);
1528 RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n",
1529 rCCK0_TxFilter1, TempVal);
1530 //Write 0xa24 ~ 0xa27
1532 TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][2] +
1533 (CCKSwingTable_Ch1_Ch13[priv->CCK_index][3]<<8) +
1534 (CCKSwingTable_Ch1_Ch13[priv->CCK_index][4]<<16)+
1535 (CCKSwingTable_Ch1_Ch13[priv->CCK_index][5]<<24);
1536 rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal);
1537 RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n",
1538 rCCK0_TxFilter2, TempVal);
1541 TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][6] +
1542 (CCKSwingTable_Ch1_Ch13[priv->CCK_index][7]<<8) ;
1544 rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal);
1545 RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n",
1546 rCCK0_DebugPort, TempVal);
1550 // priv->CCKTxPowerAdjustCntNotCh14++; //cosa add for debug.
1552 TempVal = CCKSwingTable_Ch14[priv->CCK_index][0] +
1553 (CCKSwingTable_Ch14[priv->CCK_index][1]<<8) ;
1555 rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal);
1556 RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n",
1557 rCCK0_TxFilter1, TempVal);
1558 //Write 0xa24 ~ 0xa27
1560 TempVal = CCKSwingTable_Ch14[priv->CCK_index][2] +
1561 (CCKSwingTable_Ch14[priv->CCK_index][3]<<8) +
1562 (CCKSwingTable_Ch14[priv->CCK_index][4]<<16)+
1563 (CCKSwingTable_Ch14[priv->CCK_index][5]<<24);
1564 rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal);
1565 RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n",
1566 rCCK0_TxFilter2, TempVal);
1569 TempVal = CCKSwingTable_Ch14[priv->CCK_index][6] +
1570 (CCKSwingTable_Ch14[priv->CCK_index][7]<<8) ;
1572 rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal);
1573 RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n",
1574 rCCK0_DebugPort, TempVal);
1580 void dm_cck_txpower_adjust(struct net_device *dev, bool binch14)
1581 { // dm_CCKTxPowerAdjust
1583 struct r8192_priv *priv = ieee80211_priv(dev);
1584 if(priv->bDcut == TRUE)
1585 dm_CCKTxPowerAdjust_TSSI(dev, binch14);
1587 dm_CCKTxPowerAdjust_ThermalMeter(dev, binch14);
1592 static void dm_txpower_reset_recovery(
1593 struct net_device *dev
1596 struct r8192_priv *priv = ieee80211_priv(dev);
1598 RT_TRACE(COMP_POWER_TRACKING, "Start Reset Recovery ==>\n");
1599 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbbgain_value);
1600 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in 0xc80 is %08x\n",priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbbgain_value);
1601 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in RFA_txPowerTrackingIndex is %x\n",priv->rfa_txpowertrackingindex);
1602 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery : RF A I/Q Amplify Gain is %ld\n",priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbb_iq_amplifygain);
1603 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: CCK Attenuation is %d dB\n",priv->cck_present_attentuation);
1604 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1606 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbbgain_value);
1607 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in 0xc90 is %08x\n",priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbbgain_value);
1608 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in RFC_txPowerTrackingIndex is %x\n",priv->rfc_txpowertrackingindex);
1609 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery : RF C I/Q Amplify Gain is %ld\n",priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbb_iq_amplifygain);
1611 } // dm_TXPowerResetRecovery
1613 void dm_restore_dynamic_mechanism_state(struct net_device *dev)
1615 struct r8192_priv *priv = ieee80211_priv(dev);
1616 u32 reg_ratr = priv->rate_adaptive.last_ratr;
1620 RT_TRACE(COMP_RATE, "<---- dm_restore_dynamic_mechanism_state(): driver is going to unload\n");
1625 // Restore previous state for rate adaptive
1627 if(priv->rate_adaptive.rate_adaptive_disabled)
1629 // TODO: Only 11n mode is implemented currently,
1630 if(!(priv->ieee80211->mode==WIRELESS_MODE_N_24G ||
1631 priv->ieee80211->mode==WIRELESS_MODE_N_5G))
1634 /* 2007/11/15 MH Copy from 8190PCI. */
1636 ratr_value = reg_ratr;
1637 if(priv->rf_type == RF_1T2R) // 1T2R, Spatial Stream 2 should be disabled
1639 ratr_value &= ~(RATE_ALL_OFDM_2SS);
1640 //DbgPrint("HW_VAR_TATR_0 from 0x%x ==> 0x%x\n", ((pu4Byte)(val))[0], ratr_value);
1642 //DbgPrint("set HW_VAR_TATR_0 = 0x%x\n", ratr_value);
1643 //cosa PlatformEFIOWrite4Byte(Adapter, RATR0, ((pu4Byte)(val))[0]);
1644 write_nic_dword(dev, RATR0, ratr_value);
1645 write_nic_byte(dev, UFWP, 1);
1647 //Restore TX Power Tracking Index
1648 if (priv->btxpower_trackingInit && priv->btxpower_tracking)
1649 dm_txpower_reset_recovery(dev);
1652 //Restore BB Initial Gain
1654 dm_bb_initialgain_restore(dev);
1656 } // DM_RestoreDynamicMechanismState
1658 static void dm_bb_initialgain_restore(struct net_device *dev)
1660 struct r8192_priv *priv = ieee80211_priv(dev);
1661 u32 bit_mask = 0x7f; //Bit0~ Bit6
1663 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI)
1666 //Disable Initial Gain
1667 //PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x800);
1668 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
1669 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bit_mask, (u32)priv->initgain_backup.xaagccore1);
1670 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bit_mask, (u32)priv->initgain_backup.xbagccore1);
1671 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, bit_mask, (u32)priv->initgain_backup.xcagccore1);
1672 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, bit_mask, (u32)priv->initgain_backup.xdagccore1);
1673 bit_mask = bMaskByte2;
1674 rtl8192_setBBreg(dev, rCCK0_CCA, bit_mask, (u32)priv->initgain_backup.cca);
1676 RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
1677 RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
1678 RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
1679 RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
1680 RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca);
1681 //Enable Initial Gain
1682 //PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x100);
1683 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite.
1685 } // dm_BBInitialGainRestore
1688 void dm_backup_dynamic_mechanism_state(struct net_device *dev)
1690 struct r8192_priv *priv = ieee80211_priv(dev);
1692 // Fsync to avoid reset
1693 priv->bswitch_fsync = false;
1694 priv->bfsync_processing = false;
1695 //Backup BB InitialGain
1696 dm_bb_initialgain_backup(dev);
1698 } // DM_BackupDynamicMechanismState
1701 static void dm_bb_initialgain_backup(struct net_device *dev)
1703 struct r8192_priv *priv = ieee80211_priv(dev);
1704 u32 bit_mask = bMaskByte0; //Bit0~ Bit6
1706 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI)
1709 //PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x800);
1710 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
1711 priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bit_mask);
1712 priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bit_mask);
1713 priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bit_mask);
1714 priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bit_mask);
1715 bit_mask = bMaskByte2;
1716 priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, bit_mask);
1718 RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
1719 RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
1720 RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
1721 RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
1722 RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca);
1724 } // dm_BBInitialGainBakcup
1727 /*-----------------------------------------------------------------------------
1728 * Function: dm_change_dynamic_initgain_thresh()
1740 * 05/29/2008 amy Create Version 0 porting from windows code.
1742 *---------------------------------------------------------------------------*/
1744 void dm_change_dynamic_initgain_thresh(struct net_device *dev, u32 dm_type,
1747 if (dm_type == DIG_TYPE_THRESH_HIGH)
1749 dm_digtable.rssi_high_thresh = dm_value;
1751 else if (dm_type == DIG_TYPE_THRESH_LOW)
1753 dm_digtable.rssi_low_thresh = dm_value;
1755 else if (dm_type == DIG_TYPE_THRESH_HIGHPWR_HIGH)
1757 dm_digtable.rssi_high_power_highthresh = dm_value;
1759 else if (dm_type == DIG_TYPE_THRESH_HIGHPWR_HIGH)
1761 dm_digtable.rssi_high_power_highthresh = dm_value;
1763 else if (dm_type == DIG_TYPE_ENABLE)
1765 dm_digtable.dig_state = DM_STA_DIG_MAX;
1766 dm_digtable.dig_enable_flag = true;
1768 else if (dm_type == DIG_TYPE_DISABLE)
1770 dm_digtable.dig_state = DM_STA_DIG_MAX;
1771 dm_digtable.dig_enable_flag = false;
1773 else if (dm_type == DIG_TYPE_DBG_MODE)
1775 if(dm_value >= DM_DBG_MAX)
1776 dm_value = DM_DBG_OFF;
1777 dm_digtable.dbg_mode = (u8)dm_value;
1779 else if (dm_type == DIG_TYPE_RSSI)
1783 dm_digtable.rssi_val = (long)dm_value;
1785 else if (dm_type == DIG_TYPE_ALGORITHM)
1787 if (dm_value >= DIG_ALGO_MAX)
1788 dm_value = DIG_ALGO_BY_FALSE_ALARM;
1789 if(dm_digtable.dig_algorithm != (u8)dm_value)
1790 dm_digtable.dig_algorithm_switch = 1;
1791 dm_digtable.dig_algorithm = (u8)dm_value;
1793 else if (dm_type == DIG_TYPE_BACKOFF)
1797 dm_digtable.backoff_val = (u8)dm_value;
1799 else if(dm_type == DIG_TYPE_RX_GAIN_MIN)
1803 dm_digtable.rx_gain_range_min = (u8)dm_value;
1805 else if(dm_type == DIG_TYPE_RX_GAIN_MAX)
1809 dm_digtable.rx_gain_range_max = (u8)dm_value;
1811 } /* DM_ChangeDynamicInitGainThresh */
1814 dm_change_rxpath_selection_setting(
1815 struct net_device *dev,
1819 struct r8192_priv *priv = ieee80211_priv(dev);
1820 prate_adaptive pRA = (prate_adaptive)&(priv->rate_adaptive);
1827 DM_RxPathSelTable.Enable = (u8)DM_Value;
1829 else if(DM_Type == 1)
1833 DM_RxPathSelTable.DbgMode = (u8)DM_Value;
1835 else if(DM_Type == 2)
1839 DM_RxPathSelTable.SS_TH_low = (u8)DM_Value;
1841 else if(DM_Type == 3)
1845 DM_RxPathSelTable.diff_TH = (u8)DM_Value;
1847 else if(DM_Type == 4)
1849 if(DM_Value >= CCK_Rx_Version_MAX)
1850 DM_Value = CCK_Rx_Version_1;
1851 DM_RxPathSelTable.cck_method= (u8)DM_Value;
1853 else if(DM_Type == 10)
1857 DM_RxPathSelTable.rf_rssi[0] = (u8)DM_Value;
1859 else if(DM_Type == 11)
1863 DM_RxPathSelTable.rf_rssi[1] = (u8)DM_Value;
1865 else if(DM_Type == 12)
1869 DM_RxPathSelTable.rf_rssi[2] = (u8)DM_Value;
1871 else if(DM_Type == 13)
1875 DM_RxPathSelTable.rf_rssi[3] = (u8)DM_Value;
1877 else if(DM_Type == 20)
1881 pRA->ping_rssi_enable = (u8)DM_Value;
1883 else if(DM_Type == 21)
1887 pRA->ping_rssi_thresh_for_ra = DM_Value;
1892 /*-----------------------------------------------------------------------------
1893 * Function: dm_dig_init()
1895 * Overview: Set DIG scheme init value.
1905 * 05/15/2008 amy Create Version 0 porting from windows code.
1907 *---------------------------------------------------------------------------*/
1908 static void dm_dig_init(struct net_device *dev)
1910 struct r8192_priv *priv = ieee80211_priv(dev);
1911 /* 2007/10/05 MH Disable DIG scheme now. Not tested. */
1912 dm_digtable.dig_enable_flag = true;
1913 dm_digtable.dig_algorithm = DIG_ALGO_BY_RSSI;
1914 dm_digtable.dbg_mode = DM_DBG_OFF; //off=by real rssi value, on=by DM_DigTable.Rssi_val for new dig
1915 dm_digtable.dig_algorithm_switch = 0;
1917 /* 2007/10/04 MH Define init gain threshold. */
1918 dm_digtable.dig_state = DM_STA_DIG_MAX;
1919 dm_digtable.dig_highpwr_state = DM_STA_DIG_MAX;
1920 dm_digtable.initialgain_lowerbound_state = false;
1922 dm_digtable.rssi_low_thresh = DM_DIG_THRESH_LOW;
1923 dm_digtable.rssi_high_thresh = DM_DIG_THRESH_HIGH;
1925 dm_digtable.rssi_high_power_lowthresh = DM_DIG_HIGH_PWR_THRESH_LOW;
1926 dm_digtable.rssi_high_power_highthresh = DM_DIG_HIGH_PWR_THRESH_HIGH;
1928 dm_digtable.rssi_val = 50; //for new dig debug rssi value
1929 dm_digtable.backoff_val = DM_DIG_BACKOFF;
1930 dm_digtable.rx_gain_range_max = DM_DIG_MAX;
1931 if(priv->CustomerID == RT_CID_819x_Netcore)
1932 dm_digtable.rx_gain_range_min = DM_DIG_MIN_Netcore;
1934 dm_digtable.rx_gain_range_min = DM_DIG_MIN;
1939 /*-----------------------------------------------------------------------------
1940 * Function: dm_ctrl_initgain_byrssi()
1942 * Overview: Driver must monitor RSSI and notify firmware to change initial
1943 * gain according to different threshold. BB team provide the
1944 * suggested solution.
1946 * Input: struct net_device *dev
1954 * 05/27/2008 amy Create Version 0 porting from windows code.
1955 *---------------------------------------------------------------------------*/
1956 static void dm_ctrl_initgain_byrssi(struct net_device *dev)
1959 if (dm_digtable.dig_enable_flag == false)
1962 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1963 dm_ctrl_initgain_byrssi_by_fwfalse_alarm(dev);
1964 else if(dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI)
1965 dm_ctrl_initgain_byrssi_by_driverrssi(dev);
1972 static void dm_ctrl_initgain_byrssi_by_driverrssi(
1973 struct net_device *dev)
1975 struct r8192_priv *priv = ieee80211_priv(dev);
1979 if (dm_digtable.dig_enable_flag == false)
1982 //DbgPrint("Dig by Sw Rssi \n");
1983 if(dm_digtable.dig_algorithm_switch) // if switched algorithm, we have to disable FW Dig.
1985 if(fw_dig <= 3) // execute several times to make sure the FW Dig is disabled
1988 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
1990 dm_digtable.dig_state = DM_STA_DIG_OFF; //fw dig off.
1993 if(priv->ieee80211->state == IEEE80211_LINKED)
1994 dm_digtable.cur_connect_state = DIG_CONNECT;
1996 dm_digtable.cur_connect_state = DIG_DISCONNECT;
1998 //DbgPrint("DM_DigTable.PreConnectState = %d, DM_DigTable.CurConnectState = %d \n",
1999 //DM_DigTable.PreConnectState, DM_DigTable.CurConnectState);
2001 if(dm_digtable.dbg_mode == DM_DBG_OFF)
2002 dm_digtable.rssi_val = priv->undecorated_smoothed_pwdb;
2003 //DbgPrint("DM_DigTable.Rssi_val = %d \n", DM_DigTable.Rssi_val);
2004 dm_initial_gain(dev);
2007 if(dm_digtable.dig_algorithm_switch)
2008 dm_digtable.dig_algorithm_switch = 0;
2009 dm_digtable.pre_connect_state = dm_digtable.cur_connect_state;
2011 } /* dm_CtrlInitGainByRssi */
2013 static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(
2014 struct net_device *dev)
2016 struct r8192_priv *priv = ieee80211_priv(dev);
2017 static u32 reset_cnt;
2020 if (dm_digtable.dig_enable_flag == false)
2023 if(dm_digtable.dig_algorithm_switch)
2025 dm_digtable.dig_state = DM_STA_DIG_MAX;
2028 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite.
2029 dm_digtable.dig_algorithm_switch = 0;
2032 if (priv->ieee80211->state != IEEE80211_LINKED)
2035 // For smooth, we can not change DIG state.
2036 if ((priv->undecorated_smoothed_pwdb > dm_digtable.rssi_low_thresh) &&
2037 (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_thresh))
2041 //DbgPrint("Dig by Fw False Alarm\n");
2042 //if (DM_DigTable.Dig_State == DM_STA_DIG_OFF)
2043 /*DbgPrint("DIG Check\n\r RSSI=%d LOW=%d HIGH=%d STATE=%d",
2044 pHalData->UndecoratedSmoothedPWDB, DM_DigTable.RssiLowThresh,
2045 DM_DigTable.RssiHighThresh, DM_DigTable.Dig_State);*/
2046 /* 1. When RSSI decrease, We have to judge if it is smaller than a threshold
2047 and then execute the step below. */
2048 if ((priv->undecorated_smoothed_pwdb <= dm_digtable.rssi_low_thresh))
2050 /* 2008/02/05 MH When we execute silent reset, the DIG PHY parameters
2051 will be reset to init value. We must prevent the condition. */
2052 if (dm_digtable.dig_state == DM_STA_DIG_OFF &&
2053 (priv->reset_count == reset_cnt))
2059 reset_cnt = priv->reset_count;
2062 // If DIG is off, DIG high power state must reset.
2063 dm_digtable.dig_highpwr_state = DM_STA_DIG_MAX;
2064 dm_digtable.dig_state = DM_STA_DIG_OFF;
2067 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
2069 // 1.2 Set initial gain.
2070 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x17);
2071 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x17);
2072 write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x17);
2073 write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x17);
2075 // 1.3 Lower PD_TH for OFDM.
2076 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
2078 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
2079 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
2080 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x00);
2081 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2082 write_nic_byte(pAdapter, rOFDM0_RxDetector1, 0x40);
2084 //else if (pAdapter->HardwareType == HARDWARE_TYPE_RTL8192E)
2088 //PlatformEFIOWrite1Byte(pAdapter, rOFDM0_RxDetector1, 0x40);
2091 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2093 // 1.4 Lower CS ratio for CCK.
2094 write_nic_byte(dev, 0xa0a, 0x08);
2096 // 1.5 Higher EDCCA.
2097 //PlatformEFIOWrite4Byte(pAdapter, rOFDM0_ECCAThreshold, 0x325);
2102 /* 2. When RSSI increase, We have to judge if it is larger than a threshold
2103 and then execute the step below. */
2104 if ((priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_thresh))
2108 if (dm_digtable.dig_state == DM_STA_DIG_ON &&
2109 (priv->reset_count == reset_cnt))
2111 dm_ctrl_initgain_byrssi_highpwr(dev);
2116 if (priv->reset_count != reset_cnt)
2119 reset_cnt = priv->reset_count;
2122 dm_digtable.dig_state = DM_STA_DIG_ON;
2123 //DbgPrint("DIG ON\n\r");
2125 // 2.1 Set initial gain.
2126 // 2008/02/26 MH SD3-Jerry suggest to prevent dirty environment.
2127 if (reset_flag == 1)
2129 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x2c);
2130 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x2c);
2131 write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x2c);
2132 write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x2c);
2136 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x20);
2137 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x20);
2138 write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x20);
2139 write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x20);
2142 // 2.2 Higher PD_TH for OFDM.
2143 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
2145 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
2146 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
2147 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20);
2149 else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2150 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2152 //else if (pAdapter->HardwareType == HARDWARE_TYPE_RTL8192E)
2155 //PlatformEFIOWrite1Byte(pAdapter, rOFDM0_RxDetector1, 0x42);
2158 write_nic_byte(dev, rOFDM0_RxDetector1, 0x44);
2160 // 2.3 Higher CS ratio for CCK.
2161 write_nic_byte(dev, 0xa0a, 0xcd);
2164 /* 2008/01/11 MH 90/92 series are the same. */
2165 //PlatformEFIOWrite4Byte(pAdapter, rOFDM0_ECCAThreshold, 0x346);
2168 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite.
2172 dm_ctrl_initgain_byrssi_highpwr(dev);
2174 } /* dm_CtrlInitGainByRssi */
2177 /*-----------------------------------------------------------------------------
2178 * Function: dm_ctrl_initgain_byrssi_highpwr()
2190 * 05/28/2008 amy Create Version 0 porting from windows code.
2192 *---------------------------------------------------------------------------*/
2193 static void dm_ctrl_initgain_byrssi_highpwr(
2194 struct net_device *dev)
2196 struct r8192_priv *priv = ieee80211_priv(dev);
2197 static u32 reset_cnt_highpwr;
2199 // For smooth, we can not change high power DIG state in the range.
2200 if ((priv->undecorated_smoothed_pwdb > dm_digtable.rssi_high_power_lowthresh) &&
2201 (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_power_highthresh))
2206 /* 3. When RSSI >75% or <70%, it is a high power issue. We have to judge if
2207 it is larger than a threshold and then execute the step below. */
2208 // 2008/02/05 MH SD3-Jerry Modify PD_TH for high power issue.
2209 if (priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_power_highthresh)
2211 if (dm_digtable.dig_highpwr_state == DM_STA_DIG_ON &&
2212 (priv->reset_count == reset_cnt_highpwr))
2215 dm_digtable.dig_highpwr_state = DM_STA_DIG_ON;
2217 // 3.1 Higher PD_TH for OFDM for high power state.
2218 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
2220 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x10);
2222 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2223 write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);
2228 write_nic_byte(dev, rOFDM0_RxDetector1, 0x43);
2232 if (dm_digtable.dig_highpwr_state == DM_STA_DIG_OFF&&
2233 (priv->reset_count == reset_cnt_highpwr))
2236 dm_digtable.dig_highpwr_state = DM_STA_DIG_OFF;
2238 if (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_power_lowthresh &&
2239 priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_thresh)
2241 // 3.2 Recover PD_TH for OFDM for normal power region.
2242 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
2244 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20);
2245 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2246 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2251 write_nic_byte(dev, rOFDM0_RxDetector1, 0x44);
2255 reset_cnt_highpwr = priv->reset_count;
2257 } /* dm_CtrlInitGainByRssiHighPwr */
2260 static void dm_initial_gain(
2261 struct net_device *dev)
2263 struct r8192_priv *priv = ieee80211_priv(dev);
2265 static u8 initialized, force_write;
2266 static u32 reset_cnt;
2269 if(dm_digtable.dig_algorithm_switch)
2275 if(dm_digtable.pre_connect_state == dm_digtable.cur_connect_state)
2277 if(dm_digtable.cur_connect_state == DIG_CONNECT)
2279 if((dm_digtable.rssi_val+10-dm_digtable.backoff_val) > dm_digtable.rx_gain_range_max)
2280 dm_digtable.cur_ig_value = dm_digtable.rx_gain_range_max;
2281 else if((dm_digtable.rssi_val+10-dm_digtable.backoff_val) < dm_digtable.rx_gain_range_min)
2282 dm_digtable.cur_ig_value = dm_digtable.rx_gain_range_min;
2284 dm_digtable.cur_ig_value = dm_digtable.rssi_val+10-dm_digtable.backoff_val;
2286 else //current state is disconnected
2288 if(dm_digtable.cur_ig_value == 0)
2289 dm_digtable.cur_ig_value = priv->DefaultInitialGain[0];
2291 dm_digtable.cur_ig_value = dm_digtable.pre_ig_value;
2294 else // disconnected -> connected or connected -> disconnected
2296 dm_digtable.cur_ig_value = priv->DefaultInitialGain[0];
2297 dm_digtable.pre_ig_value = 0;
2299 //DbgPrint("DM_DigTable.CurIGValue = 0x%x, DM_DigTable.PreIGValue = 0x%x\n", DM_DigTable.CurIGValue, DM_DigTable.PreIGValue);
2301 // if silent reset happened, we should rewrite the values back
2302 if(priv->reset_count != reset_cnt)
2305 reset_cnt = priv->reset_count;
2308 read_nic_byte(dev, rOFDM0_XAAGCCore1, &tmp);
2309 if (dm_digtable.pre_ig_value != tmp)
2313 if((dm_digtable.pre_ig_value != dm_digtable.cur_ig_value)
2314 || !initialized || force_write)
2316 initial_gain = (u8)dm_digtable.cur_ig_value;
2317 //DbgPrint("Write initial gain = 0x%x\n", initial_gain);
2318 // Set initial gain.
2319 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
2320 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
2321 write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
2322 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
2323 dm_digtable.pre_ig_value = dm_digtable.cur_ig_value;
2330 static void dm_pd_th(
2331 struct net_device *dev)
2333 struct r8192_priv *priv = ieee80211_priv(dev);
2334 static u8 initialized, force_write;
2335 static u32 reset_cnt;
2337 if(dm_digtable.dig_algorithm_switch)
2343 if(dm_digtable.pre_connect_state == dm_digtable.cur_connect_state)
2345 if(dm_digtable.cur_connect_state == DIG_CONNECT)
2347 if (dm_digtable.rssi_val >= dm_digtable.rssi_high_power_highthresh)
2348 dm_digtable.curpd_thstate = DIG_PD_AT_HIGH_POWER;
2349 else if ((dm_digtable.rssi_val <= dm_digtable.rssi_low_thresh))
2350 dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER;
2351 else if ((dm_digtable.rssi_val >= dm_digtable.rssi_high_thresh) &&
2352 (dm_digtable.rssi_val < dm_digtable.rssi_high_power_lowthresh))
2353 dm_digtable.curpd_thstate = DIG_PD_AT_NORMAL_POWER;
2355 dm_digtable.curpd_thstate = dm_digtable.prepd_thstate;
2359 dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER;
2362 else // disconnected -> connected or connected -> disconnected
2364 dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER;
2367 // if silent reset happened, we should rewrite the values back
2368 if(priv->reset_count != reset_cnt)
2371 reset_cnt = priv->reset_count;
2375 if((dm_digtable.prepd_thstate != dm_digtable.curpd_thstate) ||
2376 (initialized<=3) || force_write)
2378 //DbgPrint("Write PD_TH state = %d\n", DM_DigTable.CurPD_THState);
2379 if(dm_digtable.curpd_thstate == DIG_PD_AT_LOW_POWER)
2381 // Lower PD_TH for OFDM.
2382 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
2384 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
2385 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
2386 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x00);
2387 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2388 write_nic_byte(dev, rOFDM0_RxDetector1, 0x40);
2392 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2394 else if(dm_digtable.curpd_thstate == DIG_PD_AT_NORMAL_POWER)
2396 // Higher PD_TH for OFDM.
2397 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
2399 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
2400 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
2401 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20);
2402 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2403 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
2407 write_nic_byte(dev, rOFDM0_RxDetector1, 0x44);
2409 else if(dm_digtable.curpd_thstate == DIG_PD_AT_HIGH_POWER)
2411 // Higher PD_TH for OFDM for high power state.
2412 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
2414 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x10);
2415 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2416 write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);
2420 write_nic_byte(dev, rOFDM0_RxDetector1, 0x43);
2422 dm_digtable.prepd_thstate = dm_digtable.curpd_thstate;
2423 if(initialized <= 3)
2430 static void dm_cs_ratio(
2431 struct net_device *dev)
2433 struct r8192_priv *priv = ieee80211_priv(dev);
2434 static u8 initialized, force_write;
2435 static u32 reset_cnt;
2437 if(dm_digtable.dig_algorithm_switch)
2443 if(dm_digtable.pre_connect_state == dm_digtable.cur_connect_state)
2445 if(dm_digtable.cur_connect_state == DIG_CONNECT)
2447 if ((dm_digtable.rssi_val <= dm_digtable.rssi_low_thresh))
2448 dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER;
2449 else if ((dm_digtable.rssi_val >= dm_digtable.rssi_high_thresh))
2450 dm_digtable.curcs_ratio_state = DIG_CS_RATIO_HIGHER;
2452 dm_digtable.curcs_ratio_state = dm_digtable.precs_ratio_state;
2456 dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER;
2459 else // disconnected -> connected or connected -> disconnected
2461 dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER;
2464 // if silent reset happened, we should rewrite the values back
2465 if(priv->reset_count != reset_cnt)
2468 reset_cnt = priv->reset_count;
2473 if((dm_digtable.precs_ratio_state != dm_digtable.curcs_ratio_state) ||
2474 !initialized || force_write)
2476 //DbgPrint("Write CS_ratio state = %d\n", DM_DigTable.CurCS_ratioState);
2477 if(dm_digtable.curcs_ratio_state == DIG_CS_RATIO_LOWER)
2479 // Lower CS ratio for CCK.
2480 write_nic_byte(dev, 0xa0a, 0x08);
2482 else if(dm_digtable.curcs_ratio_state == DIG_CS_RATIO_HIGHER)
2484 // Higher CS ratio for CCK.
2485 write_nic_byte(dev, 0xa0a, 0xcd);
2487 dm_digtable.precs_ratio_state = dm_digtable.curcs_ratio_state;
2494 void dm_init_edca_turbo(struct net_device *dev)
2496 struct r8192_priv *priv = ieee80211_priv(dev);
2498 priv->bcurrent_turbo_EDCA = false;
2499 priv->ieee80211->bis_any_nonbepkts = false;
2500 priv->bis_cur_rdlstate = false;
2501 } // dm_init_edca_turbo
2503 static void dm_check_edca_turbo(
2504 struct net_device *dev)
2506 struct r8192_priv *priv = ieee80211_priv(dev);
2507 PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;
2508 //PSTA_QOS pStaQos = pMgntInfo->pStaQos;
2510 // Keep past Tx/Rx packet count for RT-to-RT EDCA turbo.
2511 static unsigned long lastTxOkCnt;
2512 static unsigned long lastRxOkCnt;
2513 unsigned long curTxOkCnt = 0;
2514 unsigned long curRxOkCnt = 0;
2517 // Do not be Turbo if it's under WiFi config and Qos Enabled, because the EDCA parameters
2518 // should follow the settings from QAP. By Bruce, 2007-12-07.
2520 if(priv->ieee80211->state != IEEE80211_LINKED)
2521 goto dm_CheckEdcaTurbo_EXIT;
2522 // We do not turn on EDCA turbo mode for some AP that has IOT issue
2523 if(priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_EDCA_TURBO)
2524 goto dm_CheckEdcaTurbo_EXIT;
2526 // printk("========>%s():bis_any_nonbepkts is %d\n",__func__,priv->bis_any_nonbepkts);
2527 // Check the status for current condition.
2528 if(!priv->ieee80211->bis_any_nonbepkts)
2530 curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt;
2531 curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt;
2532 // For RT-AP, we needs to turn it on when Rx>Tx
2533 if(curRxOkCnt > 4*curTxOkCnt)
2535 //printk("%s():curRxOkCnt > 4*curTxOkCnt\n");
2536 if(!priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA)
2538 write_nic_dword(dev, EDCAPARA_BE, edca_setting_DL[pHTInfo->IOTPeer]);
2539 priv->bis_cur_rdlstate = true;
2545 //printk("%s():curRxOkCnt < 4*curTxOkCnt\n");
2546 if(priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA)
2548 write_nic_dword(dev, EDCAPARA_BE, edca_setting_UL[pHTInfo->IOTPeer]);
2549 priv->bis_cur_rdlstate = false;
2554 priv->bcurrent_turbo_EDCA = true;
2559 // Turn Off EDCA turbo here.
2560 // Restore original EDCA according to the declaration of AP.
2562 if(priv->bcurrent_turbo_EDCA)
2568 struct ieee80211_qos_parameters *qos_parameters = &priv->ieee80211->current_network.qos_data.parameters;
2569 u8 mode = priv->ieee80211->mode;
2571 // For Each time updating EDCA parameter, reset EDCA turbo mode status.
2572 dm_init_edca_turbo(dev);
2573 u1bAIFS = qos_parameters->aifs[0] * ((mode&(IEEE_G|IEEE_N_24G)) ?9:20) + aSifsTime;
2574 u4bAcParam = ((((u32)(qos_parameters->tx_op_limit[0]))<< AC_PARAM_TXOP_LIMIT_OFFSET)|
2575 (((u32)(qos_parameters->cw_max[0]))<< AC_PARAM_ECW_MAX_OFFSET)|
2576 (((u32)(qos_parameters->cw_min[0]))<< AC_PARAM_ECW_MIN_OFFSET)|
2577 ((u32)u1bAIFS << AC_PARAM_AIFS_OFFSET));
2578 //write_nic_dword(dev, WDCAPARA_ADD[i], u4bAcParam);
2579 write_nic_dword(dev, EDCAPARA_BE, u4bAcParam);
2582 // If it is set, immediately set ACM control bit to downgrading AC for passing WMM testplan. Annie, 2005-12-13.
2584 // TODO: Modified this part and try to set acm control in only 1 IO processing!!
2586 PACI_AIFSN pAciAifsn = (PACI_AIFSN)&(qos_parameters->aifs[0]);
2588 read_nic_byte(dev, AcmHwCtrl, &AcmCtrl);
2589 if(pAciAifsn->f.ACM)
2591 AcmCtrl |= AcmHw_BeqEn;
2595 AcmCtrl &= (~AcmHw_BeqEn);
2598 RT_TRACE(COMP_QOS,"SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl) ;
2599 write_nic_byte(dev, AcmHwCtrl, AcmCtrl);
2602 priv->bcurrent_turbo_EDCA = false;
2607 dm_CheckEdcaTurbo_EXIT:
2608 // Set variables for next time.
2609 priv->ieee80211->bis_any_nonbepkts = false;
2610 lastTxOkCnt = priv->stats.txbytesunicast;
2611 lastRxOkCnt = priv->stats.rxbytesunicast;
2612 } // dm_CheckEdcaTurbo
2614 static void dm_init_ctstoself(struct net_device *dev)
2616 struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev);
2618 priv->ieee80211->bCTSToSelfEnable = TRUE;
2619 priv->ieee80211->CTSToSelfTH = CTSToSelfTHVal;
2622 static void dm_ctstoself(struct net_device *dev)
2624 struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev);
2625 PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;
2626 static unsigned long lastTxOkCnt;
2627 static unsigned long lastRxOkCnt;
2628 unsigned long curTxOkCnt = 0;
2629 unsigned long curRxOkCnt = 0;
2631 if(priv->ieee80211->bCTSToSelfEnable != TRUE)
2633 pHTInfo->IOTAction &= ~HT_IOT_ACT_FORCED_CTS2SELF;
2638 2. Linksys350/Linksys300N
2639 3. <50 disable, >55 enable
2642 if(pHTInfo->IOTPeer == HT_IOT_PEER_BROADCOM)
2644 curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt;
2645 curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt;
2646 if(curRxOkCnt > 4*curTxOkCnt) //downlink, disable CTS to self
2648 pHTInfo->IOTAction &= ~HT_IOT_ACT_FORCED_CTS2SELF;
2649 //DbgPrint("dm_CTSToSelf() ==> CTS to self disabled -- downlink\n");
2653 pHTInfo->IOTAction |= HT_IOT_ACT_FORCED_CTS2SELF;
2656 lastTxOkCnt = priv->stats.txbytesunicast;
2657 lastRxOkCnt = priv->stats.rxbytesunicast;
2661 /*-----------------------------------------------------------------------------
2662 * Function: dm_check_pbc_gpio()
2664 * Overview: Check if PBC button is pressed.
2674 * 05/28/2008 amy Create Version 0 porting from windows code.
2676 *---------------------------------------------------------------------------*/
2677 static void dm_check_pbc_gpio(struct net_device *dev)
2679 struct r8192_priv *priv = ieee80211_priv(dev);
2683 read_nic_byte(dev, GPI, &tmp1byte);
2684 if(tmp1byte == 0xff)
2687 if (tmp1byte&BIT6 || tmp1byte&BIT0)
2689 // Here we only set bPbcPressed to TRUE
2690 // After trigger PBC, the variable will be set to FALSE
2691 RT_TRACE(COMP_IO, "CheckPbcGPIO - PBC is pressed\n");
2692 priv->bpbc_pressed = true;
2697 /*-----------------------------------------------------------------------------
2698 * Function: DM_RFPathCheckWorkItemCallBack()
2700 * Overview: Check if Current RF RX path is enabled
2710 * 01/30/2008 MHC Create Version 0.
2712 *---------------------------------------------------------------------------*/
2713 void dm_rf_pathcheck_workitemcallback(struct work_struct *work)
2715 struct delayed_work *dwork = container_of(work,struct delayed_work,work);
2716 struct r8192_priv *priv = container_of(dwork,struct r8192_priv,rfpath_check_wq);
2717 struct net_device *dev =priv->ieee80211->dev;
2718 //bool bactually_set = false;
2722 /* 2008/01/30 MH After discussing with SD3 Jerry, 0xc04/0xd04 register will
2723 always be the same. We only read 0xc04 now. */
2724 read_nic_byte(dev, 0xc04, &rfpath);
2726 // Check Bit 0-3, it means if RF A-D is enabled.
2727 for (i = 0; i < RF90_PATH_MAX; i++)
2729 if (rfpath & (0x01<<i))
2730 priv->brfpath_rxenable[i] = 1;
2732 priv->brfpath_rxenable[i] = 0;
2734 if(!DM_RxPathSelTable.Enable)
2737 dm_rxpath_sel_byrssi(dev);
2738 } /* DM_RFPathCheckWorkItemCallBack */
2740 static void dm_init_rxpath_selection(struct net_device *dev)
2743 struct r8192_priv *priv = ieee80211_priv(dev);
2744 DM_RxPathSelTable.Enable = 1; //default enabled
2745 DM_RxPathSelTable.SS_TH_low = RxPathSelection_SS_TH_low;
2746 DM_RxPathSelTable.diff_TH = RxPathSelection_diff_TH;
2747 if(priv->CustomerID == RT_CID_819x_Netcore)
2748 DM_RxPathSelTable.cck_method = CCK_Rx_Version_2;
2750 DM_RxPathSelTable.cck_method = CCK_Rx_Version_1;
2751 DM_RxPathSelTable.DbgMode = DM_DBG_OFF;
2752 DM_RxPathSelTable.disabledRF = 0;
2755 DM_RxPathSelTable.rf_rssi[i] = 50;
2756 DM_RxPathSelTable.cck_pwdb_sta[i] = -64;
2757 DM_RxPathSelTable.rf_enable_rssi_th[i] = 100;
2761 static void dm_rxpath_sel_byrssi(struct net_device *dev)
2763 struct r8192_priv *priv = ieee80211_priv(dev);
2764 u8 i, max_rssi_index=0, min_rssi_index=0, sec_rssi_index=0, rf_num=0;
2765 u8 tmp_max_rssi=0, tmp_min_rssi=0, tmp_sec_rssi=0;
2766 u8 cck_default_Rx=0x2; //RF-C
2767 u8 cck_optional_Rx=0x3;//RF-D
2768 long tmp_cck_max_pwdb=0, tmp_cck_min_pwdb=0, tmp_cck_sec_pwdb=0;
2769 u8 cck_rx_ver2_max_index=0, cck_rx_ver2_min_index=0, cck_rx_ver2_sec_index=0;
2772 static u8 disabled_rf_cnt, cck_Rx_Path_initialized;
2773 u8 update_cck_rx_path;
2775 if(priv->rf_type != RF_2T4R)
2778 if(!cck_Rx_Path_initialized)
2780 read_nic_byte(dev, 0xa07, &DM_RxPathSelTable.cck_Rx_path);
2781 DM_RxPathSelTable.cck_Rx_path &= 0xf;
2782 cck_Rx_Path_initialized = 1;
2785 read_nic_byte(dev, 0xc04, &DM_RxPathSelTable.disabledRF);
2786 DM_RxPathSelTable.disabledRF = ~DM_RxPathSelTable.disabledRF & 0xf;
2788 if(priv->ieee80211->mode == WIRELESS_MODE_B)
2790 DM_RxPathSelTable.cck_method = CCK_Rx_Version_2; //pure B mode, fixed cck version2
2791 //DbgPrint("Pure B mode, use cck rx version2 \n");
2794 //decide max/sec/min rssi index
2795 for (i=0; i<RF90_PATH_MAX; i++)
2797 if(!DM_RxPathSelTable.DbgMode)
2798 DM_RxPathSelTable.rf_rssi[i] = priv->stats.rx_rssi_percentage[i];
2800 if(priv->brfpath_rxenable[i])
2803 cur_rf_rssi = DM_RxPathSelTable.rf_rssi[i];
2805 if(rf_num == 1) // find first enabled rf path and the rssi values
2806 { //initialize, set all rssi index to the same one
2807 max_rssi_index = min_rssi_index = sec_rssi_index = i;
2808 tmp_max_rssi = tmp_min_rssi = tmp_sec_rssi = cur_rf_rssi;
2810 else if(rf_num == 2)
2811 { // we pick up the max index first, and let sec and min to be the same one
2812 if(cur_rf_rssi >= tmp_max_rssi)
2814 tmp_max_rssi = cur_rf_rssi;
2819 tmp_sec_rssi = tmp_min_rssi = cur_rf_rssi;
2820 sec_rssi_index = min_rssi_index = i;
2825 if(cur_rf_rssi > tmp_max_rssi)
2827 tmp_sec_rssi = tmp_max_rssi;
2828 sec_rssi_index = max_rssi_index;
2829 tmp_max_rssi = cur_rf_rssi;
2832 else if(cur_rf_rssi == tmp_max_rssi)
2833 { // let sec and min point to the different index
2834 tmp_sec_rssi = cur_rf_rssi;
2837 else if((cur_rf_rssi < tmp_max_rssi) &&(cur_rf_rssi > tmp_sec_rssi))
2839 tmp_sec_rssi = cur_rf_rssi;
2842 else if(cur_rf_rssi == tmp_sec_rssi)
2844 if(tmp_sec_rssi == tmp_min_rssi)
2845 { // let sec and min point to the different index
2846 tmp_sec_rssi = cur_rf_rssi;
2851 // This case we don't need to set any index
2854 else if((cur_rf_rssi < tmp_sec_rssi) && (cur_rf_rssi > tmp_min_rssi))
2856 // This case we don't need to set any index
2858 else if(cur_rf_rssi == tmp_min_rssi)
2860 if(tmp_sec_rssi == tmp_min_rssi)
2861 { // let sec and min point to the different index
2862 tmp_min_rssi = cur_rf_rssi;
2867 // This case we don't need to set any index
2870 else if(cur_rf_rssi < tmp_min_rssi)
2872 tmp_min_rssi = cur_rf_rssi;
2880 // decide max/sec/min cck pwdb index
2881 if(DM_RxPathSelTable.cck_method == CCK_Rx_Version_2)
2883 for (i=0; i<RF90_PATH_MAX; i++)
2885 if(priv->brfpath_rxenable[i])
2888 cur_cck_pwdb = DM_RxPathSelTable.cck_pwdb_sta[i];
2890 if(rf_num == 1) // find first enabled rf path and the rssi values
2891 { //initialize, set all rssi index to the same one
2892 cck_rx_ver2_max_index = cck_rx_ver2_min_index = cck_rx_ver2_sec_index = i;
2893 tmp_cck_max_pwdb = tmp_cck_min_pwdb = tmp_cck_sec_pwdb = cur_cck_pwdb;
2895 else if(rf_num == 2)
2896 { // we pick up the max index first, and let sec and min to be the same one
2897 if(cur_cck_pwdb >= tmp_cck_max_pwdb)
2899 tmp_cck_max_pwdb = cur_cck_pwdb;
2900 cck_rx_ver2_max_index = i;
2904 tmp_cck_sec_pwdb = tmp_cck_min_pwdb = cur_cck_pwdb;
2905 cck_rx_ver2_sec_index = cck_rx_ver2_min_index = i;
2910 if(cur_cck_pwdb > tmp_cck_max_pwdb)
2912 tmp_cck_sec_pwdb = tmp_cck_max_pwdb;
2913 cck_rx_ver2_sec_index = cck_rx_ver2_max_index;
2914 tmp_cck_max_pwdb = cur_cck_pwdb;
2915 cck_rx_ver2_max_index = i;
2917 else if(cur_cck_pwdb == tmp_cck_max_pwdb)
2918 { // let sec and min point to the different index
2919 tmp_cck_sec_pwdb = cur_cck_pwdb;
2920 cck_rx_ver2_sec_index = i;
2922 else if((cur_cck_pwdb < tmp_cck_max_pwdb) &&(cur_cck_pwdb > tmp_cck_sec_pwdb))
2924 tmp_cck_sec_pwdb = cur_cck_pwdb;
2925 cck_rx_ver2_sec_index = i;
2927 else if(cur_cck_pwdb == tmp_cck_sec_pwdb)
2929 if(tmp_cck_sec_pwdb == tmp_cck_min_pwdb)
2930 { // let sec and min point to the different index
2931 tmp_cck_sec_pwdb = cur_cck_pwdb;
2932 cck_rx_ver2_sec_index = i;
2936 // This case we don't need to set any index
2939 else if((cur_cck_pwdb < tmp_cck_sec_pwdb) && (cur_cck_pwdb > tmp_cck_min_pwdb))
2941 // This case we don't need to set any index
2943 else if(cur_cck_pwdb == tmp_cck_min_pwdb)
2945 if(tmp_cck_sec_pwdb == tmp_cck_min_pwdb)
2946 { // let sec and min point to the different index
2947 tmp_cck_min_pwdb = cur_cck_pwdb;
2948 cck_rx_ver2_min_index = i;
2952 // This case we don't need to set any index
2955 else if(cur_cck_pwdb < tmp_cck_min_pwdb)
2957 tmp_cck_min_pwdb = cur_cck_pwdb;
2958 cck_rx_ver2_min_index = i;
2968 // reg0xA07[3:2]=cck default rx path, reg0xa07[1:0]=cck optional rx path.
2969 update_cck_rx_path = 0;
2970 if(DM_RxPathSelTable.cck_method == CCK_Rx_Version_2)
2972 cck_default_Rx = cck_rx_ver2_max_index;
2973 cck_optional_Rx = cck_rx_ver2_sec_index;
2974 if(tmp_cck_max_pwdb != -64)
2975 update_cck_rx_path = 1;
2978 if(tmp_min_rssi < DM_RxPathSelTable.SS_TH_low && disabled_rf_cnt < 2)
2980 if((tmp_max_rssi - tmp_min_rssi) >= DM_RxPathSelTable.diff_TH)
2982 //record the enabled rssi threshold
2983 DM_RxPathSelTable.rf_enable_rssi_th[min_rssi_index] = tmp_max_rssi+5;
2984 //disable the BB Rx path, OFDM
2985 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x1<<min_rssi_index, 0x0); // 0xc04[3:0]
2986 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x1<<min_rssi_index, 0x0); // 0xd04[3:0]
2989 if(DM_RxPathSelTable.cck_method == CCK_Rx_Version_1)
2991 cck_default_Rx = max_rssi_index;
2992 cck_optional_Rx = sec_rssi_index;
2994 update_cck_rx_path = 1;
2998 if(update_cck_rx_path)
3000 DM_RxPathSelTable.cck_Rx_path = (cck_default_Rx<<2)|(cck_optional_Rx);
3001 rtl8192_setBBreg(dev, rCCK0_AFESetting, 0x0f000000, DM_RxPathSelTable.cck_Rx_path);
3004 if(DM_RxPathSelTable.disabledRF)
3008 if((DM_RxPathSelTable.disabledRF>>i) & 0x1) //disabled rf
3010 if(tmp_max_rssi >= DM_RxPathSelTable.rf_enable_rssi_th[i])
3012 //enable the BB Rx path
3013 //DbgPrint("RF-%d is enabled. \n", 0x1<<i);
3014 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x1<<i, 0x1); // 0xc04[3:0]
3015 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x1<<i, 0x1); // 0xd04[3:0]
3016 DM_RxPathSelTable.rf_enable_rssi_th[i] = 100;
3024 /*-----------------------------------------------------------------------------
3025 * Function: dm_check_rx_path_selection()
3027 * Overview: Call a workitem to check current RXRF path and Rx Path selection by RSSI.
3037 * 05/28/2008 amy Create Version 0 porting from windows code.
3039 *---------------------------------------------------------------------------*/
3040 static void dm_check_rx_path_selection(struct net_device *dev)
3042 struct r8192_priv *priv = ieee80211_priv(dev);
3043 queue_delayed_work(priv->priv_wq,&priv->rfpath_check_wq,0);
3044 } /* dm_CheckRxRFPath */
3047 static void dm_init_fsync (struct net_device *dev)
3049 struct r8192_priv *priv = ieee80211_priv(dev);
3051 priv->ieee80211->fsync_time_interval = 500;
3052 priv->ieee80211->fsync_rate_bitmap = 0x0f000800;
3053 priv->ieee80211->fsync_rssi_threshold = 30;
3054 priv->ieee80211->bfsync_enable = false;
3055 priv->ieee80211->fsync_multiple_timeinterval = 3;
3056 priv->ieee80211->fsync_firstdiff_ratethreshold= 100;
3057 priv->ieee80211->fsync_seconddiff_ratethreshold= 200;
3058 priv->ieee80211->fsync_state = Default_Fsync;
3059 priv->framesyncMonitor = 1; // current default 0xc38 monitor on
3061 init_timer(&priv->fsync_timer);
3062 priv->fsync_timer.data = (unsigned long)dev;
3063 priv->fsync_timer.function = dm_fsync_timer_callback;
3067 static void dm_deInit_fsync(struct net_device *dev)
3069 struct r8192_priv *priv = ieee80211_priv(dev);
3070 del_timer_sync(&priv->fsync_timer);
3073 void dm_fsync_timer_callback(unsigned long data)
3075 struct net_device *dev = (struct net_device *)data;
3076 struct r8192_priv *priv = ieee80211_priv((struct net_device *)data);
3077 u32 rate_index, rate_count = 0, rate_count_diff=0;
3078 bool bSwitchFromCountDiff = false;
3079 bool bDoubleTimeInterval = false;
3081 if(priv->ieee80211->state == IEEE80211_LINKED &&
3082 priv->ieee80211->bfsync_enable &&
3083 (priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_CDD_FSYNC))
3085 // Count rate 54, MCS [7], [12, 13, 14, 15]
3087 for(rate_index = 0; rate_index <= 27; rate_index++)
3089 rate_bitmap = 1 << rate_index;
3090 if(priv->ieee80211->fsync_rate_bitmap & rate_bitmap)
3091 rate_count+= priv->stats.received_rate_histogram[1][rate_index];
3094 if(rate_count < priv->rate_record)
3095 rate_count_diff = 0xffffffff - rate_count + priv->rate_record;
3097 rate_count_diff = rate_count - priv->rate_record;
3098 if(rate_count_diff < priv->rateCountDiffRecord)
3101 u32 DiffNum = priv->rateCountDiffRecord - rate_count_diff;
3103 if(DiffNum >= priv->ieee80211->fsync_seconddiff_ratethreshold)
3104 priv->ContinueDiffCount++;
3106 priv->ContinueDiffCount = 0;
3108 // Continue count over
3109 if(priv->ContinueDiffCount >=2)
3111 bSwitchFromCountDiff = true;
3112 priv->ContinueDiffCount = 0;
3117 // Stop the continued count
3118 priv->ContinueDiffCount = 0;
3121 //If Count diff <= FsyncRateCountThreshold
3122 if(rate_count_diff <= priv->ieee80211->fsync_firstdiff_ratethreshold)
3124 bSwitchFromCountDiff = true;
3125 priv->ContinueDiffCount = 0;
3127 priv->rate_record = rate_count;
3128 priv->rateCountDiffRecord = rate_count_diff;
3129 RT_TRACE(COMP_HALDM, "rateRecord %d rateCount %d, rateCountdiff %d bSwitchFsync %d\n", priv->rate_record, rate_count, rate_count_diff , priv->bswitch_fsync);
3130 // if we never receive those mcs rate and rssi > 30 % then switch fsyn
3131 if(priv->undecorated_smoothed_pwdb > priv->ieee80211->fsync_rssi_threshold && bSwitchFromCountDiff)
3133 bDoubleTimeInterval = true;
3134 priv->bswitch_fsync = !priv->bswitch_fsync;
3135 if(priv->bswitch_fsync)
3137 write_nic_byte(dev, 0xC36, 0x1c);
3138 write_nic_byte(dev, 0xC3e, 0x90);
3142 write_nic_byte(dev, 0xC36, 0x5c);
3143 write_nic_byte(dev, 0xC3e, 0x96);
3146 else if(priv->undecorated_smoothed_pwdb <= priv->ieee80211->fsync_rssi_threshold)
3148 if(priv->bswitch_fsync)
3150 priv->bswitch_fsync = false;
3151 write_nic_byte(dev, 0xC36, 0x5c);
3152 write_nic_byte(dev, 0xC3e, 0x96);
3155 if(bDoubleTimeInterval){
3156 if(timer_pending(&priv->fsync_timer))
3157 del_timer_sync(&priv->fsync_timer);
3158 priv->fsync_timer.expires = jiffies + MSECS(priv->ieee80211->fsync_time_interval*priv->ieee80211->fsync_multiple_timeinterval);
3159 add_timer(&priv->fsync_timer);
3162 if(timer_pending(&priv->fsync_timer))
3163 del_timer_sync(&priv->fsync_timer);
3164 priv->fsync_timer.expires = jiffies + MSECS(priv->ieee80211->fsync_time_interval);
3165 add_timer(&priv->fsync_timer);
3170 // Let Register return to default value;
3171 if(priv->bswitch_fsync)
3173 priv->bswitch_fsync = false;
3174 write_nic_byte(dev, 0xC36, 0x5c);
3175 write_nic_byte(dev, 0xC3e, 0x96);
3177 priv->ContinueDiffCount = 0;
3178 write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd);
3180 RT_TRACE(COMP_HALDM, "ContinueDiffCount %d\n", priv->ContinueDiffCount);
3181 RT_TRACE(COMP_HALDM, "rateRecord %d rateCount %d, rateCountdiff %d bSwitchFsync %d\n", priv->rate_record, rate_count, rate_count_diff , priv->bswitch_fsync);
3184 static void dm_StartHWFsync(struct net_device *dev)
3186 RT_TRACE(COMP_HALDM, "%s\n", __func__);
3187 write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c12cf);
3188 write_nic_byte(dev, 0xc3b, 0x41);
3191 static void dm_EndSWFsync(struct net_device *dev)
3193 struct r8192_priv *priv = ieee80211_priv(dev);
3195 RT_TRACE(COMP_HALDM, "%s\n", __func__);
3196 del_timer_sync(&(priv->fsync_timer));
3198 // Let Register return to default value;
3199 if(priv->bswitch_fsync)
3201 priv->bswitch_fsync = false;
3203 write_nic_byte(dev, 0xC36, 0x5c);
3205 write_nic_byte(dev, 0xC3e, 0x96);
3208 priv->ContinueDiffCount = 0;
3209 write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd);
3213 static void dm_StartSWFsync(struct net_device *dev)
3215 struct r8192_priv *priv = ieee80211_priv(dev);
3219 RT_TRACE(COMP_HALDM, "%s\n", __func__);
3220 // Initial rate record to zero, start to record.
3221 priv->rate_record = 0;
3222 // Initialize continue diff count to zero, start to record.
3223 priv->ContinueDiffCount = 0;
3224 priv->rateCountDiffRecord = 0;
3225 priv->bswitch_fsync = false;
3227 if(priv->ieee80211->mode == WIRELESS_MODE_N_24G)
3229 priv->ieee80211->fsync_firstdiff_ratethreshold= 600;
3230 priv->ieee80211->fsync_seconddiff_ratethreshold = 0xffff;
3234 priv->ieee80211->fsync_firstdiff_ratethreshold= 200;
3235 priv->ieee80211->fsync_seconddiff_ratethreshold = 200;
3237 for(rateIndex = 0; rateIndex <= 27; rateIndex++)
3239 rateBitmap = 1 << rateIndex;
3240 if(priv->ieee80211->fsync_rate_bitmap & rateBitmap)
3241 priv->rate_record += priv->stats.received_rate_histogram[1][rateIndex];
3243 if(timer_pending(&priv->fsync_timer))
3244 del_timer_sync(&priv->fsync_timer);
3245 priv->fsync_timer.expires = jiffies + MSECS(priv->ieee80211->fsync_time_interval);
3246 add_timer(&priv->fsync_timer);
3248 write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c12cd);
3252 static void dm_EndHWFsync(struct net_device *dev)
3254 RT_TRACE(COMP_HALDM, "%s\n", __func__);
3255 write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd);
3256 write_nic_byte(dev, 0xc3b, 0x49);
3260 void dm_check_fsync(struct net_device *dev)
3262 #define RegC38_Default 0
3263 #define RegC38_NonFsync_Other_AP 1
3264 #define RegC38_Fsync_AP_BCM 2
3265 struct r8192_priv *priv = ieee80211_priv(dev);
3267 static u8 reg_c38_State=RegC38_Default;
3268 static u32 reset_cnt;
3270 RT_TRACE(COMP_HALDM, "RSSI %d TimeInterval %d MultipleTimeInterval %d\n", priv->ieee80211->fsync_rssi_threshold, priv->ieee80211->fsync_time_interval, priv->ieee80211->fsync_multiple_timeinterval);
3271 RT_TRACE(COMP_HALDM, "RateBitmap 0x%x FirstDiffRateThreshold %d SecondDiffRateThreshold %d\n", priv->ieee80211->fsync_rate_bitmap, priv->ieee80211->fsync_firstdiff_ratethreshold, priv->ieee80211->fsync_seconddiff_ratethreshold);
3273 if(priv->ieee80211->state == IEEE80211_LINKED &&
3274 (priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_CDD_FSYNC))
3276 if(priv->ieee80211->bfsync_enable == 0)
3278 switch (priv->ieee80211->fsync_state)
3281 dm_StartHWFsync(dev);
3282 priv->ieee80211->fsync_state = HW_Fsync;
3286 dm_StartHWFsync(dev);
3287 priv->ieee80211->fsync_state = HW_Fsync;
3296 switch (priv->ieee80211->fsync_state)
3299 dm_StartSWFsync(dev);
3300 priv->ieee80211->fsync_state = SW_Fsync;
3304 dm_StartSWFsync(dev);
3305 priv->ieee80211->fsync_state = SW_Fsync;
3313 if(priv->framesyncMonitor)
3315 if(reg_c38_State != RegC38_Fsync_AP_BCM)
3316 { //For broadcom AP we write different default value
3317 write_nic_byte(dev, rOFDM0_RxDetector3, 0x95);
3319 reg_c38_State = RegC38_Fsync_AP_BCM;
3325 switch (priv->ieee80211->fsync_state)
3329 priv->ieee80211->fsync_state = Default_Fsync;
3333 priv->ieee80211->fsync_state = Default_Fsync;
3340 if(priv->framesyncMonitor)
3342 if(priv->ieee80211->state == IEEE80211_LINKED)
3344 if(priv->undecorated_smoothed_pwdb <= RegC38_TH)
3346 if(reg_c38_State != RegC38_NonFsync_Other_AP)
3348 write_nic_byte(dev, rOFDM0_RxDetector3, 0x90);
3350 reg_c38_State = RegC38_NonFsync_Other_AP;
3353 else if(priv->undecorated_smoothed_pwdb >= (RegC38_TH+5))
3357 write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
3358 reg_c38_State = RegC38_Default;
3359 //DbgPrint("Fsync is idle, rssi>=40, write 0xc38 = 0x%x \n", pHalData->framesync);
3367 write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
3368 reg_c38_State = RegC38_Default;
3369 //DbgPrint("Fsync is idle, not connected, write 0xc38 = 0x%x \n", pHalData->framesync);
3374 if(priv->framesyncMonitor)
3376 if(priv->reset_count != reset_cnt)
3377 { //After silent reset, the reg_c38_State will be returned to default value
3378 write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
3379 reg_c38_State = RegC38_Default;
3380 reset_cnt = priv->reset_count;
3381 //DbgPrint("reg_c38_State = 0 for silent reset. \n");
3388 write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
3389 reg_c38_State = RegC38_Default;
3390 //DbgPrint("framesync no monitor, write 0xc38 = 0x%x \n", pHalData->framesync);
3396 /*-----------------------------------------------------------------------------
3397 * Function: dm_shadow_init()
3399 * Overview: Store all NIC MAC/BB register content.
3409 * 05/29/2008 amy Create Version 0 porting from windows code.
3411 *---------------------------------------------------------------------------*/
3412 void dm_shadow_init(struct net_device *dev)
3417 for (page = 0; page < 5; page++)
3418 for (offset = 0; offset < 256; offset++)
3420 read_nic_byte(dev, offset+page*256, &dm_shadow[page][offset]);
3421 //DbgPrint("P-%d/O-%02x=%02x\r\n", page, offset, DM_Shadow[page][offset]);
3424 for (page = 8; page < 11; page++)
3425 for (offset = 0; offset < 256; offset++)
3426 read_nic_byte(dev, offset+page*256, &dm_shadow[page][offset]);
3428 for (page = 12; page < 15; page++)
3429 for (offset = 0; offset < 256; offset++)
3430 read_nic_byte(dev, offset+page*256, &dm_shadow[page][offset]);
3432 } /* dm_shadow_init */
3434 /*---------------------------Define function prototype------------------------*/
3435 /*-----------------------------------------------------------------------------
3436 * Function: DM_DynamicTxPower()
3438 * Overview: Detect Signal strength to control TX Registry
3439 Tx Power Control For Near/Far Range
3449 * 03/06/2008 Jacken Create Version 0.
3451 *---------------------------------------------------------------------------*/
3452 static void dm_init_dynamic_txpower(struct net_device *dev)
3454 struct r8192_priv *priv = ieee80211_priv(dev);
3456 //Initial TX Power Control for near/far range , add by amy 2008/05/15, porting from windows code.
3457 priv->ieee80211->bdynamic_txpower_enable = true; //Default to enable Tx Power Control
3458 priv->bLastDTPFlag_High = false;
3459 priv->bLastDTPFlag_Low = false;
3460 priv->bDynamicTxHighPower = false;
3461 priv->bDynamicTxLowPower = false;
3464 static void dm_dynamic_txpower(struct net_device *dev)
3466 struct r8192_priv *priv = ieee80211_priv(dev);
3467 unsigned int txhipower_threshhold=0;
3468 unsigned int txlowpower_threshold=0;
3469 if(priv->ieee80211->bdynamic_txpower_enable != true)
3471 priv->bDynamicTxHighPower = false;
3472 priv->bDynamicTxLowPower = false;
3475 //printk("priv->ieee80211->current_network.unknown_cap_exist is %d ,priv->ieee80211->current_network.broadcom_cap_exist is %d\n",priv->ieee80211->current_network.unknown_cap_exist,priv->ieee80211->current_network.broadcom_cap_exist);
3476 if((priv->ieee80211->current_network.atheros_cap_exist) && (priv->ieee80211->mode == IEEE_G)){
3477 txhipower_threshhold = TX_POWER_ATHEROAP_THRESH_HIGH;
3478 txlowpower_threshold = TX_POWER_ATHEROAP_THRESH_LOW;
3482 txhipower_threshhold = TX_POWER_NEAR_FIELD_THRESH_HIGH;
3483 txlowpower_threshold = TX_POWER_NEAR_FIELD_THRESH_LOW;
3486 // printk("=======>%s(): txhipower_threshhold is %d,txlowpower_threshold is %d\n",__func__,txhipower_threshhold,txlowpower_threshold);
3487 RT_TRACE(COMP_TXAGC,"priv->undecorated_smoothed_pwdb = %ld \n" , priv->undecorated_smoothed_pwdb);
3489 if(priv->ieee80211->state == IEEE80211_LINKED)
3491 if(priv->undecorated_smoothed_pwdb >= txhipower_threshhold)
3493 priv->bDynamicTxHighPower = true;
3494 priv->bDynamicTxLowPower = false;
3498 // high power state check
3499 if(priv->undecorated_smoothed_pwdb < txlowpower_threshold && priv->bDynamicTxHighPower == true)
3501 priv->bDynamicTxHighPower = false;
3503 // low power state check
3504 if(priv->undecorated_smoothed_pwdb < 35)
3506 priv->bDynamicTxLowPower = true;
3508 else if(priv->undecorated_smoothed_pwdb >= 40)
3510 priv->bDynamicTxLowPower = false;
3516 //pHalData->bTXPowerCtrlforNearFarRange = !pHalData->bTXPowerCtrlforNearFarRange;
3517 priv->bDynamicTxHighPower = false;
3518 priv->bDynamicTxLowPower = false;
3521 if((priv->bDynamicTxHighPower != priv->bLastDTPFlag_High) ||
3522 (priv->bDynamicTxLowPower != priv->bLastDTPFlag_Low))
3524 RT_TRACE(COMP_TXAGC,"SetTxPowerLevel8190() channel = %d \n" , priv->ieee80211->current_network.channel);
3526 #if defined(RTL8190P) || defined(RTL8192E)
3527 SetTxPowerLevel8190(Adapter,pHalData->CurrentChannel);
3530 rtl8192_phy_setTxPower(dev,priv->ieee80211->current_network.channel);
3531 //pHalData->bStartTxCtrlByTPCNFR = FALSE; //Clear th flag of Set TX Power from Sitesurvey
3533 priv->bLastDTPFlag_High = priv->bDynamicTxHighPower;
3534 priv->bLastDTPFlag_Low = priv->bDynamicTxLowPower;
3536 } /* dm_dynamic_txpower */
3538 //added by vivi, for read tx rate and retrycount
3539 static void dm_check_txrateandretrycount(struct net_device *dev)
3541 struct r8192_priv *priv = ieee80211_priv(dev);
3542 struct ieee80211_device *ieee = priv->ieee80211;
3544 // priv->stats.CurrentShowTxate = read_nic_byte(dev, Current_Tx_Rate_Reg);
3545 read_nic_byte(dev, Current_Tx_Rate_Reg, &ieee->softmac_stats.CurrentShowTxate);
3546 //printk("=============>tx_rate_reg:%x\n", ieee->softmac_stats.CurrentShowTxate);
3547 //for initial tx rate
3548 // priv->stats.last_packet_rate = read_nic_byte(dev, Initial_Tx_Rate_Reg);
3549 read_nic_byte(dev, Initial_Tx_Rate_Reg, &ieee->softmac_stats.last_packet_rate);
3550 //for tx tx retry count
3551 // priv->stats.txretrycount = read_nic_dword(dev, Tx_Retry_Count_Reg);
3552 read_nic_dword(dev, Tx_Retry_Count_Reg, &ieee->softmac_stats.txretrycount);
3555 static void dm_send_rssi_tofw(struct net_device *dev)
3557 DCMD_TXCMD_T tx_cmd;
3558 struct r8192_priv *priv = ieee80211_priv(dev);
3560 // If we test chariot, we should stop the TX command ?
3561 // Because 92E will always silent reset when we send tx command. We use register
3562 // 0x1e0(byte) to notify driver.
3563 write_nic_byte(dev, DRIVER_RSSI, (u8)priv->undecorated_smoothed_pwdb);
3565 tx_cmd.Op = TXCMD_SET_RX_RSSI;
3567 tx_cmd.Value = priv->undecorated_smoothed_pwdb;
3570 /*---------------------------Define function prototype------------------------*/