3 #include "r819xU_phy.h"
4 #include "r819xU_phyreg.h"
5 #include "r8190_rtl8256.h"
7 #include "r819xU_firmware_img.h"
10 #include <linux/bitops.h>
12 static u32 RF_CHANNEL_TABLE_ZEBRA[] = {
31 #define rtl819XPHY_REG_1T2RArray Rtl8192UsbPHY_REG_1T2RArray
32 #define rtl819XMACPHY_Array_PG Rtl8192UsbMACPHY_Array_PG
33 #define rtl819XMACPHY_Array Rtl8192UsbMACPHY_Array
34 #define rtl819XRadioA_Array Rtl8192UsbRadioA_Array
35 #define rtl819XRadioB_Array Rtl8192UsbRadioB_Array
36 #define rtl819XRadioC_Array Rtl8192UsbRadioC_Array
37 #define rtl819XRadioD_Array Rtl8192UsbRadioD_Array
38 #define rtl819XAGCTAB_Array Rtl8192UsbAGCTAB_Array
40 /******************************************************************************
41 * function: This function reads BB parameters from header file we generate,
42 * and does register read/write
43 * input: u32 bitmask //taget bit pos in the addr to be modified
45 * return: u32 return the shift bit position of the mask
46 ******************************************************************************/
47 static u32 rtl8192_CalculateBitShift(u32 bitmask)
55 /******************************************************************************
56 * function: This function checks different RF type to execute legal judgement.
57 * If RF Path is illegal, we will return false.
58 * input: net_device *dev
61 * return: 0(illegal, false), 1(legal, true)
62 *****************************************************************************/
63 u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 eRFPath)
66 struct r8192_priv *priv = ieee80211_priv(dev);
68 if (priv->rf_type == RF_2T4R) {
70 } else if (priv->rf_type == RF_1T2R) {
71 if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B)
73 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
79 /******************************************************************************
80 * function: This function sets specific bits to BB register
81 * input: net_device *dev
82 * u32 reg_addr //target addr to be modified
83 * u32 bitmask //taget bit pos to be modified
84 * u32 data //value to be write
88 ******************************************************************************/
89 void rtl8192_setBBreg(struct net_device *dev, u32 reg_addr, u32 bitmask,
95 if (bitmask != bMaskDWord) {
96 read_nic_dword(dev, reg_addr, ®);
97 bitshift = rtl8192_CalculateBitShift(bitmask);
99 reg |= data << bitshift;
100 write_nic_dword(dev, reg_addr, reg);
102 write_nic_dword(dev, reg_addr, data);
106 /******************************************************************************
107 * function: This function reads specific bits from BB register
108 * input: net_device *dev
109 * u32 reg_addr //target addr to be readback
110 * u32 bitmask //taget bit pos to be readback
112 * return: u32 data //the readback register value
114 ******************************************************************************/
115 u32 rtl8192_QueryBBReg(struct net_device *dev, u32 reg_addr, u32 bitmask)
119 read_nic_dword(dev, reg_addr, ®);
120 bitshift = rtl8192_CalculateBitShift(bitmask);
122 return (reg & bitmask) >> bitshift;
125 static u32 phy_FwRFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
128 static void phy_FwRFSerialWrite(struct net_device *dev,
129 RF90_RADIO_PATH_E eRFPath, u32 offset,
132 /******************************************************************************
133 * function: This function reads register from RF chip
134 * input: net_device *dev
135 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
136 * u32 offset //target address to be read
138 * return: u32 readback value
139 * notice: There are three types of serial operations:
140 * (1) Software serial write.
141 * (2)Hardware LSSI-Low Speed Serial Interface.
142 * (3)Hardware HSSI-High speed serial write.
143 * Driver here need to implement (1) and (2)
144 * ---need more spec for this information.
145 ******************************************************************************/
146 static u32 rtl8192_phy_RFSerialRead(struct net_device *dev,
147 RF90_RADIO_PATH_E eRFPath, u32 offset)
149 struct r8192_priv *priv = ieee80211_priv(dev);
152 BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
154 rtl8192_setBBreg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData, 0);
155 /* Make sure RF register offset is correct */
158 /* Switch page for 8256 RF IC */
159 if (priv->rf_chip == RF_8256) {
161 priv->RfReg0Value[eRFPath] |= 0x140;
162 /* Switch to Reg_Mode2 for Reg 31-45 */
163 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
165 priv->RfReg0Value[eRFPath]<<16);
167 new_offset = offset - 30;
168 } else if (offset >= 16) {
169 priv->RfReg0Value[eRFPath] |= 0x100;
170 priv->RfReg0Value[eRFPath] &= (~0x40);
171 /* Switch to Reg_Mode1 for Reg16-30 */
172 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
174 priv->RfReg0Value[eRFPath]<<16);
176 new_offset = offset - 15;
181 RT_TRACE((COMP_PHY|COMP_ERR),
182 "check RF type here, need to be 8256\n");
185 /* Put desired read addr to LSSI control Register */
186 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress,
188 /* Issue a posedge trigger */
189 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0);
190 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1);
193 /* TODO: we should not delay such a long time. Ask for help from SD3 */
194 usleep_range(1000, 1000);
196 ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack,
200 /* Switch back to Reg_Mode0 */
201 if (priv->rf_chip == RF_8256) {
202 priv->RfReg0Value[eRFPath] &= 0xebf;
204 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord,
205 priv->RfReg0Value[eRFPath] << 16);
211 /******************************************************************************
212 * function: This function writes data to RF register
213 * input: net_device *dev
214 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
215 * u32 offset //target address to be written
216 * u32 data //the new register data to be written
219 * notice: For RF8256 only.
220 * ===========================================================================
221 * Reg Mode RegCTL[1] RegCTL[0] Note
222 * (Reg00[12]) (Reg00[10])
223 * ===========================================================================
224 * Reg_Mode0 0 x Reg 0 ~ 15(0x0 ~ 0xf)
225 * ---------------------------------------------------------------------------
226 * Reg_Mode1 1 0 Reg 16 ~ 30(0x1 ~ 0xf)
227 * ---------------------------------------------------------------------------
228 * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf)
229 * ---------------------------------------------------------------------------
230 *****************************************************************************/
231 static void rtl8192_phy_RFSerialWrite(struct net_device *dev,
232 RF90_RADIO_PATH_E eRFPath, u32 offset,
235 struct r8192_priv *priv = ieee80211_priv(dev);
236 u32 DataAndAddr = 0, new_offset = 0;
237 BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
240 if (priv->rf_chip == RF_8256) {
243 priv->RfReg0Value[eRFPath] |= 0x140;
244 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
246 priv->RfReg0Value[eRFPath] << 16);
247 new_offset = offset - 30;
248 } else if (offset >= 16) {
249 priv->RfReg0Value[eRFPath] |= 0x100;
250 priv->RfReg0Value[eRFPath] &= (~0x40);
251 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
253 priv->RfReg0Value[eRFPath]<<16);
254 new_offset = offset - 15;
259 RT_TRACE((COMP_PHY|COMP_ERR),
260 "check RF type here, need to be 8256\n");
264 /* Put write addr in [5:0] and write data in [31:16] */
265 DataAndAddr = (data<<16) | (new_offset&0x3f);
267 /* Write operation */
268 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
272 priv->RfReg0Value[eRFPath] = data;
274 /* Switch back to Reg_Mode0 */
275 if (priv->rf_chip == RF_8256) {
277 priv->RfReg0Value[eRFPath] &= 0xebf;
278 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
280 priv->RfReg0Value[eRFPath] << 16);
285 /******************************************************************************
286 * function: This function set specific bits to RF register
287 * input: net_device dev
288 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
289 * u32 reg_addr //target addr to be modified
290 * u32 bitmask //taget bit pos to be modified
291 * u32 data //value to be written
295 *****************************************************************************/
296 void rtl8192_phy_SetRFReg(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
297 u32 reg_addr, u32 bitmask, u32 data)
299 struct r8192_priv *priv = ieee80211_priv(dev);
302 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
305 if (priv->Rf_Mode == RF_OP_By_FW) {
306 if (bitmask != bMask12Bits) {
307 /* RF data is 12 bits only */
308 reg = phy_FwRFSerialRead(dev, eRFPath, reg_addr);
309 bitshift = rtl8192_CalculateBitShift(bitmask);
311 reg |= data << bitshift;
313 phy_FwRFSerialWrite(dev, eRFPath, reg_addr, reg);
315 phy_FwRFSerialWrite(dev, eRFPath, reg_addr, data);
321 if (bitmask != bMask12Bits) {
322 /* RF data is 12 bits only */
323 reg = rtl8192_phy_RFSerialRead(dev, eRFPath, reg_addr);
324 bitshift = rtl8192_CalculateBitShift(bitmask);
326 reg |= data << bitshift;
328 rtl8192_phy_RFSerialWrite(dev, eRFPath, reg_addr, reg);
330 rtl8192_phy_RFSerialWrite(dev, eRFPath, reg_addr, data);
335 /******************************************************************************
336 * function: This function reads specific bits from RF register
337 * input: net_device *dev
338 * u32 reg_addr //target addr to be readback
339 * u32 bitmask //taget bit pos to be readback
341 * return: u32 data //the readback register value
343 *****************************************************************************/
344 u32 rtl8192_phy_QueryRFReg(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
345 u32 reg_addr, u32 bitmask)
348 struct r8192_priv *priv = ieee80211_priv(dev);
351 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
353 if (priv->Rf_Mode == RF_OP_By_FW) {
354 reg = phy_FwRFSerialRead(dev, eRFPath, reg_addr);
355 bitshift = rtl8192_CalculateBitShift(bitmask);
356 reg = (reg & bitmask) >> bitshift;
360 reg = rtl8192_phy_RFSerialRead(dev, eRFPath, reg_addr);
361 bitshift = rtl8192_CalculateBitShift(bitmask);
362 reg = (reg & bitmask) >> bitshift;
367 /******************************************************************************
368 * function: We support firmware to execute RF-R/W.
369 * input: net_device *dev
370 * RF90_RADIO_PATH_E eRFPath
375 ****************************************************************************/
376 static u32 phy_FwRFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
384 /* Firmware RF Write control.
385 * We can not execute the scheme in the initial step.
386 * Otherwise, RF-R/W will waste much time.
387 * This is only for site survey. */
388 /* 1. Read operation need not insert data. bit 0-11 */
389 /* 2. Write RF register address. bit 12-19 */
390 data |= ((offset&0xFF)<<12);
391 /* 3. Write RF path. bit 20-21 */
392 data |= ((eRFPath&0x3)<<20);
393 /* 4. Set RF read indicator. bit 22=0 */
394 /* 5. Trigger Fw to operate the command. bit 31 */
396 /* 6. We can not execute read operation if bit 31 is 1. */
397 read_nic_dword(dev, QPNR, &tmp);
398 while (tmp & 0x80000000) {
399 /* If FW can not finish RF-R/W for more than ?? times.
403 read_nic_dword(dev, QPNR, &tmp);
408 /* 7. Execute read operation. */
409 write_nic_dword(dev, QPNR, data);
410 /* 8. Check if firmware send back RF content. */
411 read_nic_dword(dev, QPNR, &tmp);
412 while (tmp & 0x80000000) {
413 /* If FW can not finish RF-R/W for more than ?? times.
417 read_nic_dword(dev, QPNR, &tmp);
422 read_nic_dword(dev, RF_DATA, ®);
427 /******************************************************************************
428 * function: We support firmware to execute RF-R/W.
429 * input: net_device *dev
430 * RF90_RADIO_PATH_E eRFPath
436 ****************************************************************************/
437 static void phy_FwRFSerialWrite(struct net_device *dev,
438 RF90_RADIO_PATH_E eRFPath, u32 offset, u32 data)
443 /* Firmware RF Write control.
444 * We can not execute the scheme in the initial step.
445 * Otherwise, RF-R/W will waste much time.
446 * This is only for site survey. */
448 /* 1. Set driver write bit and 12 bit data. bit 0-11 */
449 /* 2. Write RF register address. bit 12-19 */
450 data |= ((offset&0xFF)<<12);
451 /* 3. Write RF path. bit 20-21 */
452 data |= ((eRFPath&0x3)<<20);
453 /* 4. Set RF write indicator. bit 22=1 */
455 /* 5. Trigger Fw to operate the command. bit 31=1 */
458 /* 6. Write operation. We can not write if bit 31 is 1. */
459 read_nic_dword(dev, QPNR, &tmp);
460 while (tmp & 0x80000000) {
461 /* If FW can not finish RF-R/W for more than ?? times.
465 read_nic_dword(dev, QPNR, &tmp);
470 /* 7. No matter check bit. We always force the write.
471 Because FW will not accept the command. */
472 write_nic_dword(dev, QPNR, data);
473 /* According to test, we must delay 20us to wait firmware
474 to finish RF write operation. */
475 /* We support delay in firmware side now. */
478 /******************************************************************************
479 * function: This function reads BB parameters from header file we generate,
480 * and do register read/write
481 * input: net_device *dev
484 * notice: BB parameters may change all the time, so please make
485 * sure it has been synced with the newest.
486 *****************************************************************************/
487 void rtl8192_phy_configmac(struct net_device *dev)
489 u32 dwArrayLen = 0, i;
490 u32 *pdwArray = NULL;
491 struct r8192_priv *priv = ieee80211_priv(dev);
493 if (priv->btxpowerdata_readfromEEPORM) {
494 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n");
495 dwArrayLen = MACPHY_Array_PGLength;
496 pdwArray = rtl819XMACPHY_Array_PG;
499 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array\n");
500 dwArrayLen = MACPHY_ArrayLength;
501 pdwArray = rtl819XMACPHY_Array;
503 for (i = 0; i < dwArrayLen; i = i+3) {
504 if (pdwArray[i] == 0x318)
505 pdwArray[i+2] = 0x00000800;
508 "Rtl8190MACPHY_Array[0]=%x Rtl8190MACPHY_Array[1]=%x Rtl8190MACPHY_Array[2]=%x\n",
509 pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
510 rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1],
515 /******************************************************************************
516 * function: This function does dirty work
517 * input: net_device *dev
521 * notice: BB parameters may change all the time, so please make
522 * sure it has been synced with the newest.
523 *****************************************************************************/
524 void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType)
529 u32 *rtl8192PhyRegArrayTable = NULL, *rtl8192AgcTabArrayTable = NULL;
531 if (Adapter->bInHctTest) {
532 PHY_REGArrayLen = PHY_REGArrayLengthDTM;
533 AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM;
534 Rtl8190PHY_REGArray_Table = Rtl819XPHY_REGArrayDTM;
535 Rtl8190AGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM;
538 if (ConfigType == BaseBand_Config_PHY_REG) {
539 for (i = 0; i < PHY_REG_1T2RArrayLength; i += 2) {
540 rtl8192_setBBreg(dev, rtl819XPHY_REG_1T2RArray[i],
542 rtl819XPHY_REG_1T2RArray[i+1]);
544 "i: %x, Rtl819xUsbPHY_REGArray[0]=%x Rtl819xUsbPHY_REGArray[1]=%x\n",
545 i, rtl819XPHY_REG_1T2RArray[i],
546 rtl819XPHY_REG_1T2RArray[i+1]);
548 } else if (ConfigType == BaseBand_Config_AGC_TAB) {
549 for (i = 0; i < AGCTAB_ArrayLength; i += 2) {
550 rtl8192_setBBreg(dev, rtl819XAGCTAB_Array[i],
551 bMaskDWord, rtl819XAGCTAB_Array[i+1]);
553 "i: %x, rtl819XAGCTAB_Array[0]=%x rtl819XAGCTAB_Array[1]=%x\n",
554 i, rtl819XAGCTAB_Array[i],
555 rtl819XAGCTAB_Array[i+1]);
560 /******************************************************************************
561 * function: This function initializes Register definition offset for
563 * input: net_device *dev
566 * notice: Initialization value here is constant and it should never
568 *****************************************************************************/
569 static void rtl8192_InitBBRFRegDef(struct net_device *dev)
571 struct r8192_priv *priv = ieee80211_priv(dev);
573 /* RF Interface Software Control */
574 /* 16 LSBs if read 32-bit from 0x870 */
575 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW;
576 /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */
577 priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW;
578 /* 16 LSBs if read 32-bit from 0x874 */
579 priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;
580 /* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */
581 priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;
583 /* RF Interface Readback Value */
584 /* 16 LSBs if read 32-bit from 0x8E0 */
585 priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB;
586 /* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */
587 priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;
588 /* 16 LSBs if read 32-bit from 0x8E4 */
589 priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;
590 /* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */
591 priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;
593 /* RF Interface Output (and Enable) */
594 /* 16 LSBs if read 32-bit from 0x860 */
595 priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE;
596 /* 16 LSBs if read 32-bit from 0x864 */
597 priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE;
598 /* 16 LSBs if read 32-bit from 0x868 */
599 priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;
600 /* 16 LSBs if read 32-bit from 0x86C */
601 priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;
603 /* RF Interface (Output and) Enable */
604 /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */
605 priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE;
606 /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */
607 priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE;
608 /* 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A) */
609 priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;
610 /* 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E) */
611 priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;
613 /* Addr of LSSI. Write RF register by driver */
614 priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter;
615 priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
616 priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
617 priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
621 priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter;
622 priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
623 priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
624 priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
626 /* Tx AGC Gain Stage (same for all path. Should we remove this?) */
627 priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage;
628 priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage;
629 priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage;
630 priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage;
632 /* Tranceiver A~D HSSI Parameter-1 */
633 /* wire control parameter1 */
634 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;
635 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;
636 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1;
637 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1;
639 /* Tranceiver A~D HSSI Parameter-2 */
640 /* wire control parameter2 */
641 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;
642 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;
643 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2;
644 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2;
646 /* RF Switch Control */
647 /* TR/Ant switch control */
648 priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl;
649 priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
650 priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
651 priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
654 priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
655 priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
656 priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
657 priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
660 priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
661 priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
662 priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
663 priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
665 /* RX AFE control 1 */
666 priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
667 priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
668 priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
669 priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
671 /* RX AFE control 1 */
672 priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
673 priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
674 priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
675 priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
677 /* Tx AFE control 1 */
678 priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
679 priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
680 priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
681 priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
683 /* Tx AFE control 2 */
684 priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
685 priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
686 priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
687 priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
689 /* Tranceiver LSSI Readback */
690 priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
691 priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
692 priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
693 priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
696 /******************************************************************************
697 * function: This function is to write register and then readback to make
698 * sure whether BB and RF is OK
699 * input: net_device *dev
700 * HW90_BLOCK_E CheckBlock
701 * RF90_RADIO_PATH_E eRFPath //only used when checkblock is
704 * return: return whether BB and RF is ok (0:OK, 1:Fail)
705 * notice: This function may be removed in the ASIC
706 ******************************************************************************/
707 u8 rtl8192_phy_checkBBAndRF(struct net_device *dev, HW90_BLOCK_E CheckBlock,
708 RF90_RADIO_PATH_E eRFPath)
711 u32 i, CheckTimes = 4, reg = 0;
713 u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
715 /* Initialize register address offset to be checked */
716 WriteAddr[HW90_BLOCK_MAC] = 0x100;
717 WriteAddr[HW90_BLOCK_PHY0] = 0x900;
718 WriteAddr[HW90_BLOCK_PHY1] = 0x800;
719 WriteAddr[HW90_BLOCK_RF] = 0x3;
720 RT_TRACE(COMP_PHY, "%s(), CheckBlock: %d\n", __func__, CheckBlock);
721 for (i = 0; i < CheckTimes; i++) {
723 /* Write data to register and readback */
724 switch (CheckBlock) {
727 "PHY_CheckBBRFOK(): Never Write 0x100 here!\n");
730 case HW90_BLOCK_PHY0:
731 case HW90_BLOCK_PHY1:
732 write_nic_dword(dev, WriteAddr[CheckBlock],
734 read_nic_dword(dev, WriteAddr[CheckBlock], ®);
738 WriteData[i] &= 0xfff;
739 rtl8192_phy_SetRFReg(dev, eRFPath,
740 WriteAddr[HW90_BLOCK_RF],
741 bMask12Bits, WriteData[i]);
742 /* TODO: we should not delay for such a long time.
744 usleep_range(1000, 1000);
745 reg = rtl8192_phy_QueryRFReg(dev, eRFPath,
746 WriteAddr[HW90_BLOCK_RF],
748 usleep_range(1000, 1000);
757 /* Check whether readback data is correct */
758 if (reg != WriteData[i]) {
759 RT_TRACE((COMP_PHY|COMP_ERR),
760 "error reg: %x, WriteData: %x\n",
770 /******************************************************************************
771 * function: This function initializes BB&RF
772 * input: net_device *dev
775 * notice: Initialization value may change all the time, so please make
776 * sure it has been synced with the newest.
777 ******************************************************************************/
778 static void rtl8192_BB_Config_ParaFile(struct net_device *dev)
780 struct r8192_priv *priv = ieee80211_priv(dev);
781 u8 reg_u8 = 0, eCheckItem = 0, status = 0;
784 /**************************************
785 * <1> Initialize BaseBand
786 *************************************/
788 /* --set BB Global Reset-- */
789 read_nic_byte(dev, BB_GLOBAL_RESET, ®_u8);
790 write_nic_byte(dev, BB_GLOBAL_RESET, (reg_u8|BB_GLOBAL_RESET_BIT));
792 /* ---set BB reset Active--- */
793 read_nic_dword(dev, CPU_GEN, ®_u32);
794 write_nic_dword(dev, CPU_GEN, (reg_u32&(~CPU_GEN_BB_RST)));
796 /* ----Ckeck FPGAPHY0 and PHY1 board is OK---- */
797 /* TODO: this function should be removed on ASIC */
798 for (eCheckItem = (HW90_BLOCK_E)HW90_BLOCK_PHY0;
799 eCheckItem <= HW90_BLOCK_PHY1; eCheckItem++) {
800 /* don't care RF path */
801 status = rtl8192_phy_checkBBAndRF(dev, (HW90_BLOCK_E)eCheckItem,
802 (RF90_RADIO_PATH_E)0);
804 RT_TRACE((COMP_ERR | COMP_PHY),
805 "PHY_RF8256_Config(): Check PHY%d Fail!!\n",
810 /* ---- Set CCK and OFDM Block "OFF"---- */
811 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0);
812 /* ----BB Register Initilazation---- */
813 /* ==m==>Set PHY REG From Header<==m== */
814 rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG);
816 /* ----Set BB reset de-Active---- */
817 read_nic_dword(dev, CPU_GEN, ®_u32);
818 write_nic_dword(dev, CPU_GEN, (reg_u32|CPU_GEN_BB_RST));
820 /* ----BB AGC table Initialization---- */
821 /* ==m==>Set PHY REG From Header<==m== */
822 rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB);
824 /* ----Enable XSTAL ---- */
825 write_nic_byte_E(dev, 0x5e, 0x00);
826 if (priv->card_8192_version == (u8)VERSION_819xU_A) {
827 /* Antenna gain offset from B/C/D to A */
828 reg_u32 = (priv->AntennaTxPwDiff[1]<<4 |
829 priv->AntennaTxPwDiff[0]);
830 rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC),
834 reg_u32 = priv->CrystalCap & 0xf;
835 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap,
839 /* Check if the CCK HighPower is turned ON.
840 This is used to calculate PWDB. */
841 priv->bCckHighPower = (u8)rtl8192_QueryBBReg(dev,
842 rFPGA0_XA_HSSIParameter2,
846 /******************************************************************************
847 * function: This function initializes BB&RF
848 * input: net_device *dev
851 * notice: Initialization value may change all the time, so please make
852 * sure it has been synced with the newest.
853 *****************************************************************************/
854 void rtl8192_BBConfig(struct net_device *dev)
856 rtl8192_InitBBRFRegDef(dev);
857 /* config BB&RF. As hardCode based initialization has not been well
858 * implemented, so use file first.
859 * FIXME: should implement it for hardcode? */
860 rtl8192_BB_Config_ParaFile(dev);
864 /******************************************************************************
865 * function: This function obtains the initialization value of Tx power Level
867 * input: net_device *dev
870 *****************************************************************************/
871 void rtl8192_phy_getTxPower(struct net_device *dev)
873 struct r8192_priv *priv = ieee80211_priv(dev);
876 read_nic_dword(dev, rTxAGC_Rate18_06,
877 &priv->MCSTxPowerLevelOriginalOffset[0]);
878 read_nic_dword(dev, rTxAGC_Rate54_24,
879 &priv->MCSTxPowerLevelOriginalOffset[1]);
880 read_nic_dword(dev, rTxAGC_Mcs03_Mcs00,
881 &priv->MCSTxPowerLevelOriginalOffset[2]);
882 read_nic_dword(dev, rTxAGC_Mcs07_Mcs04,
883 &priv->MCSTxPowerLevelOriginalOffset[3]);
884 read_nic_dword(dev, rTxAGC_Mcs11_Mcs08,
885 &priv->MCSTxPowerLevelOriginalOffset[4]);
886 read_nic_dword(dev, rTxAGC_Mcs15_Mcs12,
887 &priv->MCSTxPowerLevelOriginalOffset[5]);
889 /* Read rx initial gain */
890 read_nic_byte(dev, rOFDM0_XAAGCCore1, &priv->DefaultInitialGain[0]);
891 read_nic_byte(dev, rOFDM0_XBAGCCore1, &priv->DefaultInitialGain[1]);
892 read_nic_byte(dev, rOFDM0_XCAGCCore1, &priv->DefaultInitialGain[2]);
893 read_nic_byte(dev, rOFDM0_XDAGCCore1, &priv->DefaultInitialGain[3]);
895 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n",
896 priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
897 priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
900 read_nic_byte(dev, rOFDM0_RxDetector3, &priv->framesync);
901 read_nic_byte(dev, rOFDM0_RxDetector2, &tmp);
902 priv->framesyncC34 = tmp;
903 RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n",
904 rOFDM0_RxDetector3, priv->framesync);
906 /* Read SIFS (save the value read fome MACPHY_REG.txt) */
907 read_nic_word(dev, SIFS, &priv->SifsTime);
910 /******************************************************************************
911 * function: This function sets the initialization value of Tx power Level
913 * input: net_device *dev
917 ******************************************************************************/
918 void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel)
920 struct r8192_priv *priv = ieee80211_priv(dev);
921 u8 powerlevel = priv->TxPowerLevelCCK[channel-1];
922 u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
924 switch (priv->rf_chip) {
926 /* need further implement */
927 PHY_SetRF8256CCKTxPower(dev, powerlevel);
928 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
931 RT_TRACE((COMP_PHY|COMP_ERR),
932 "error RF chipID(8225 or 8258) in function %s()\n",
938 /******************************************************************************
939 * function: This function checks Rf chip to do RF config
940 * input: net_device *dev
942 * return: only 8256 is supported
943 ******************************************************************************/
944 void rtl8192_phy_RFConfig(struct net_device *dev)
946 struct r8192_priv *priv = ieee80211_priv(dev);
948 switch (priv->rf_chip) {
950 PHY_RF8256_Config(dev);
953 RT_TRACE(COMP_ERR, "error chip id\n");
958 /******************************************************************************
959 * function: This function updates Initial gain
960 * input: net_device *dev
962 * return: As Windows has not implemented this, wait for complement
963 ******************************************************************************/
964 void rtl8192_phy_updateInitGain(struct net_device *dev)
968 /******************************************************************************
969 * function: This function read RF parameters from general head file,
971 * input: net_device *dev
972 * RF90_RADIO_PATH_E eRFPath
974 * return: return code show if RF configuration is successful(0:pass, 1:fail)
975 * notice: Delay may be required for RF configuration
976 *****************************************************************************/
977 u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev,
978 RF90_RADIO_PATH_E eRFPath)
985 for (i = 0; i < RadioA_ArrayLength; i = i+2) {
987 if (rtl819XRadioA_Array[i] == 0xfe) {
991 rtl8192_phy_SetRFReg(dev, eRFPath,
992 rtl819XRadioA_Array[i],
994 rtl819XRadioA_Array[i+1]);
1000 for (i = 0; i < RadioB_ArrayLength; i = i+2) {
1002 if (rtl819XRadioB_Array[i] == 0xfe) {
1006 rtl8192_phy_SetRFReg(dev, eRFPath,
1007 rtl819XRadioB_Array[i],
1009 rtl819XRadioB_Array[i+1]);
1015 for (i = 0; i < RadioC_ArrayLength; i = i+2) {
1017 if (rtl819XRadioC_Array[i] == 0xfe) {
1021 rtl8192_phy_SetRFReg(dev, eRFPath,
1022 rtl819XRadioC_Array[i],
1024 rtl819XRadioC_Array[i+1]);
1030 for (i = 0; i < RadioD_ArrayLength; i = i+2) {
1032 if (rtl819XRadioD_Array[i] == 0xfe) {
1036 rtl8192_phy_SetRFReg(dev, eRFPath,
1037 rtl819XRadioD_Array[i],
1039 rtl819XRadioD_Array[i+1]);
1052 /******************************************************************************
1053 * function: This function sets Tx Power of the channel
1054 * input: net_device *dev
1059 ******************************************************************************/
1060 static void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel)
1062 struct r8192_priv *priv = ieee80211_priv(dev);
1063 u8 powerlevel = priv->TxPowerLevelCCK[channel-1];
1064 u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
1066 switch (priv->rf_chip) {
1069 PHY_SetRF8225CckTxPower(Adapter, powerlevel);
1070 PHY_SetRF8225OfdmTxPower(Adapter, powerlevelOFDM24G);
1075 PHY_SetRF8256CCKTxPower(dev, powerlevel);
1076 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
1082 RT_TRACE(COMP_ERR, "unknown rf chip ID in %s()\n", __func__);
1087 /******************************************************************************
1088 * function: This function sets RF state on or off
1089 * input: net_device *dev
1090 * RT_RF_POWER_STATE eRFPowerState //Power State to set
1094 *****************************************************************************/
1095 bool rtl8192_SetRFPowerState(struct net_device *dev,
1096 RT_RF_POWER_STATE eRFPowerState)
1098 bool bResult = true;
1099 struct r8192_priv *priv = ieee80211_priv(dev);
1101 if (eRFPowerState == priv->ieee80211->eRFPowerState)
1104 if (priv->SetRFPowerStateInProgress == true)
1107 priv->SetRFPowerStateInProgress = true;
1109 switch (priv->rf_chip) {
1111 switch (eRFPowerState) {
1114 /* enable RF-Chip A/B - 0x860[4] */
1115 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4,
1117 /* analog to digital on - 0x88c[9:8] */
1118 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300,
1120 /* digital to analog on - 0x880[4:3] */
1121 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18,
1123 /* rx antenna on - 0xc04[1:0] */
1124 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3);
1125 /* rx antenna on - 0xd04[1:0] */
1126 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3);
1127 /* analog to digital part2 on - 0x880[6:5] */
1128 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60,
1139 /* disable RF-Chip A/B - 0x860[4] */
1140 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4,
1142 /* analog to digital off, for power save */
1143 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00,
1144 0x0); /* 0x88c[11:8] */
1145 /* digital to analog off, for power save - 0x880[4:3] */
1146 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18,
1148 /* rx antenna off - 0xc04[3:0] */
1149 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0);
1150 /* rx antenna off - 0xd04[3:0] */
1151 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);
1152 /* analog to digital part2 off, for power save */
1153 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60,
1154 0x0); /* 0x880[6:5] */
1160 RT_TRACE(COMP_ERR, "%s(): unknown state to set: 0x%X\n",
1161 __func__, eRFPowerState);
1166 RT_TRACE(COMP_ERR, "Not support rf_chip(%x)\n", priv->rf_chip);
1171 /* Update current RF state variable. */
1172 pHalData->eRFPowerState = eRFPowerState;
1173 switch (pHalData->RFChipID) {
1175 switch (pHalData->eRFPowerState) {
1177 /* If Rf off reason is from IPS,
1178 LED should blink with no link */
1179 if (pMgntInfo->RfOffReason == RF_CHANGE_BY_IPS)
1180 Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_NO_LINK);
1182 /* Turn off LED if RF is not ON. */
1183 Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_POWER_OFF);
1187 /* Turn on RF we are still linked, which might
1188 happen when we quickly turn off and on HW RF.
1190 if (pMgntInfo->bMediaConnect == TRUE)
1191 Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_LINK);
1193 /* Turn off LED if RF is not ON. */
1194 Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_NO_LINK);
1203 RT_TRACE(COMP_RF, DBG_LOUD, "%s(): Unknown RF type\n",
1210 priv->SetRFPowerStateInProgress = false;
1215 /******************************************************************************
1216 * function: This function sets command table variable (struct SwChnlCmd).
1217 * input: SwChnlCmd *CmdTable //table to be set
1218 * u32 CmdTableIdx //variable index in table to be set
1219 * u32 CmdTableSz //table size
1220 * SwChnlCmdID CmdID //command ID to set
1225 * return: true if finished, false otherwise
1227 ******************************************************************************/
1228 static u8 rtl8192_phy_SetSwChnlCmdArray(SwChnlCmd *CmdTable, u32 CmdTableIdx,
1229 u32 CmdTableSz, SwChnlCmdID CmdID,
1230 u32 Para1, u32 Para2, u32 msDelay)
1234 if (CmdTable == NULL) {
1235 RT_TRACE(COMP_ERR, "%s(): CmdTable cannot be NULL\n", __func__);
1238 if (CmdTableIdx >= CmdTableSz) {
1239 RT_TRACE(COMP_ERR, "%s(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n",
1240 __func__, CmdTableIdx, CmdTableSz);
1244 pCmd = CmdTable + CmdTableIdx;
1245 pCmd->CmdID = CmdID;
1246 pCmd->Para1 = Para1;
1247 pCmd->Para2 = Para2;
1248 pCmd->msDelay = msDelay;
1253 /******************************************************************************
1254 * function: This function sets channel step by step
1255 * input: net_device *dev
1257 * u8 *stage //3 stages
1259 * u32 *delay //whether need to delay
1260 * output: store new stage, step and delay for next step
1261 * (combine with function above)
1262 * return: true if finished, false otherwise
1263 * notice: Wait for simpler function to replace it
1264 *****************************************************************************/
1265 static u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel,
1266 u8 *stage, u8 *step, u32 *delay)
1268 struct r8192_priv *priv = ieee80211_priv(dev);
1269 SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT];
1270 u32 PreCommonCmdCnt;
1271 SwChnlCmd PostCommonCmd[MAX_POSTCMD_CNT];
1272 u32 PostCommonCmdCnt;
1273 SwChnlCmd RfDependCmd[MAX_RFDEPENDCMD_CNT];
1275 SwChnlCmd *CurrentCmd = NULL;
1278 RT_TRACE(COMP_CH, "%s() stage: %d, step: %d, channel: %d\n",
1279 __func__, *stage, *step, channel);
1280 if (!IsLegalChannel(priv->ieee80211, channel)) {
1281 RT_TRACE(COMP_ERR, "set to illegal channel: %d\n", channel);
1282 /* return true to tell upper caller function this channel
1283 setting is finished! Or it will in while loop. */
1286 /* FIXME: need to check whether channel is legal or not here */
1289 /* <1> Fill up pre common command. */
1290 PreCommonCmdCnt = 0;
1291 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++,
1292 MAX_PRECMD_CNT, CmdID_SetTxPowerLevel,
1294 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++,
1295 MAX_PRECMD_CNT, CmdID_End, 0, 0, 0);
1297 /* <2> Fill up post common command. */
1298 PostCommonCmdCnt = 0;
1300 rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++,
1301 MAX_POSTCMD_CNT, CmdID_End, 0, 0, 0);
1303 /* <3> Fill up RF dependent command. */
1305 switch (priv->rf_chip) {
1307 if (!(channel >= 1 && channel <= 14)) {
1309 "illegal channel for Zebra 8225: %d\n",
1313 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1314 MAX_RFDEPENDCMD_CNT,
1317 RF_CHANNEL_TABLE_ZEBRA[channel],
1319 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1320 MAX_RFDEPENDCMD_CNT,
1321 CmdID_End, 0, 0, 0);
1325 /* TEST!! This is not the table for 8256!! */
1326 if (!(channel >= 1 && channel <= 14)) {
1328 "illegal channel for Zebra 8256: %d\n",
1332 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1333 MAX_RFDEPENDCMD_CNT,
1335 rZebra1_Channel, channel, 10);
1336 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1337 MAX_RFDEPENDCMD_CNT,
1338 CmdID_End, 0, 0, 0);
1345 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
1354 CurrentCmd = &PreCommonCmd[*step];
1357 CurrentCmd = &RfDependCmd[*step];
1360 CurrentCmd = &PostCommonCmd[*step];
1364 if (CurrentCmd->CmdID == CmdID_End) {
1365 if ((*stage) == 2) {
1366 (*delay) = CurrentCmd->msDelay;
1375 switch (CurrentCmd->CmdID) {
1376 case CmdID_SetTxPowerLevel:
1377 if (priv->card_8192_version == (u8)VERSION_819xU_A)
1378 /* consider it later! */
1379 rtl8192_SetTxPowerLevel(dev, channel);
1381 case CmdID_WritePortUlong:
1382 write_nic_dword(dev, CurrentCmd->Para1,
1385 case CmdID_WritePortUshort:
1386 write_nic_word(dev, CurrentCmd->Para1,
1387 (u16)CurrentCmd->Para2);
1389 case CmdID_WritePortUchar:
1390 write_nic_byte(dev, CurrentCmd->Para1,
1391 (u8)CurrentCmd->Para2);
1393 case CmdID_RF_WriteReg:
1394 for (eRFPath = 0; eRFPath < RF90_PATH_MAX; eRFPath++) {
1395 rtl8192_phy_SetRFReg(dev,
1396 (RF90_RADIO_PATH_E)eRFPath,
1409 (*delay) = CurrentCmd->msDelay;
1414 /******************************************************************************
1415 * function: This function does actually set channel work
1416 * input: net_device *dev
1420 * notice: We should not call this function directly
1421 *****************************************************************************/
1422 static void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel)
1424 struct r8192_priv *priv = ieee80211_priv(dev);
1427 while (!rtl8192_phy_SwChnlStepByStep(dev, channel, &priv->SwChnlStage,
1428 &priv->SwChnlStep, &delay)) {
1434 /******************************************************************************
1435 * function: Callback routine of the work item for switch channel.
1436 * input: net_device *dev
1440 *****************************************************************************/
1441 void rtl8192_SwChnl_WorkItem(struct net_device *dev)
1444 struct r8192_priv *priv = ieee80211_priv(dev);
1446 RT_TRACE(COMP_CH, "==> SwChnlCallback819xUsbWorkItem(), chan:%d\n",
1450 rtl8192_phy_FinishSwChnlNow(dev, priv->chan);
1452 RT_TRACE(COMP_CH, "<== SwChnlCallback819xUsbWorkItem()\n");
1455 /******************************************************************************
1456 * function: This function scheduled actual work item to set channel
1457 * input: net_device *dev
1458 * u8 channel //channel to set
1460 * return: return code show if workitem is scheduled (1:pass, 0:fail)
1461 * notice: Delay may be required for RF configuration
1462 ******************************************************************************/
1463 u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel)
1465 struct r8192_priv *priv = ieee80211_priv(dev);
1466 RT_TRACE(COMP_CH, "%s(), SwChnlInProgress: %d\n", __func__,
1467 priv->SwChnlInProgress);
1470 if (priv->SwChnlInProgress)
1473 /* -------------------------------------------- */
1474 switch (priv->ieee80211->mode) {
1475 case WIRELESS_MODE_A:
1476 case WIRELESS_MODE_N_5G:
1477 if (channel <= 14) {
1478 RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14\n");
1482 case WIRELESS_MODE_B:
1484 RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14\n");
1488 case WIRELESS_MODE_G:
1489 case WIRELESS_MODE_N_24G:
1491 RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14\n");
1496 /* -------------------------------------------- */
1498 priv->SwChnlInProgress = true;
1502 priv->chan = channel;
1504 priv->SwChnlStage = 0;
1505 priv->SwChnlStep = 0;
1507 rtl8192_SwChnl_WorkItem(dev);
1509 priv->SwChnlInProgress = false;
1513 /******************************************************************************
1514 * function: Callback routine of the work item for set bandwidth mode.
1515 * input: net_device *dev
1518 * notice: I doubt whether SetBWModeInProgress flag is necessary as we can
1519 * test whether current work in the queue or not.//do I?
1520 *****************************************************************************/
1521 void rtl8192_SetBWModeWorkItem(struct net_device *dev)
1524 struct r8192_priv *priv = ieee80211_priv(dev);
1527 RT_TRACE(COMP_SWBW, "%s() Switch to %s bandwidth\n", __func__,
1528 priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz");
1531 if (priv->rf_chip == RF_PSEUDO_11N) {
1532 priv->SetBWModeInProgress = false;
1536 /* <1> Set MAC register */
1537 read_nic_byte(dev, BW_OPMODE, ®BwOpMode);
1539 switch (priv->CurrentChannelBW) {
1540 case HT_CHANNEL_WIDTH_20:
1541 regBwOpMode |= BW_OPMODE_20MHZ;
1542 /* We have not verify whether this register works */
1543 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1546 case HT_CHANNEL_WIDTH_20_40:
1547 regBwOpMode &= ~BW_OPMODE_20MHZ;
1548 /* We have not verify whether this register works */
1549 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1554 "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",
1555 priv->CurrentChannelBW);
1559 /* <2> Set PHY related register */
1560 switch (priv->CurrentChannelBW) {
1561 case HT_CHANNEL_WIDTH_20:
1562 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
1563 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
1564 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1,
1567 /* Correct the tx power for CCK rate in 20M. */
1568 priv->cck_present_attentuation =
1569 priv->cck_present_attentuation_20Mdefault +
1570 priv->cck_present_attentuation_difference;
1572 if (priv->cck_present_attentuation > 22)
1573 priv->cck_present_attentuation = 22;
1574 if (priv->cck_present_attentuation < 0)
1575 priv->cck_present_attentuation = 0;
1577 "20M, pHalData->CCKPresentAttentuation = %d\n",
1578 priv->cck_present_attentuation);
1580 if (priv->chan == 14 && !priv->bcck_in_ch14) {
1581 priv->bcck_in_ch14 = TRUE;
1582 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1583 } else if (priv->chan != 14 && priv->bcck_in_ch14) {
1584 priv->bcck_in_ch14 = FALSE;
1585 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1587 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1591 case HT_CHANNEL_WIDTH_20_40:
1592 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
1593 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
1594 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand,
1595 priv->nCur40MhzPrimeSC>>1);
1596 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
1597 rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00,
1598 priv->nCur40MhzPrimeSC);
1599 priv->cck_present_attentuation =
1600 priv->cck_present_attentuation_40Mdefault +
1601 priv->cck_present_attentuation_difference;
1603 if (priv->cck_present_attentuation > 22)
1604 priv->cck_present_attentuation = 22;
1605 if (priv->cck_present_attentuation < 0)
1606 priv->cck_present_attentuation = 0;
1609 "40M, pHalData->CCKPresentAttentuation = %d\n",
1610 priv->cck_present_attentuation);
1611 if (priv->chan == 14 && !priv->bcck_in_ch14) {
1612 priv->bcck_in_ch14 = true;
1613 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1614 } else if (priv->chan != 14 && priv->bcck_in_ch14) {
1615 priv->bcck_in_ch14 = false;
1616 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1618 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1624 "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",
1625 priv->CurrentChannelBW);
1629 /* Skip over setting of J-mode in BB register here.
1630 Default value is "None J mode". */
1632 /* <3> Set RF related register */
1633 switch (priv->rf_chip) {
1636 PHY_SetRF8225Bandwidth(Adapter, pHalData->CurrentChannelBW);
1641 PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
1651 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
1654 priv->SetBWModeInProgress = false;
1656 RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb(), %d\n",
1657 atomic_read(&priv->ieee80211->atm_swbw));
1660 /******************************************************************************
1661 * function: This function schedules bandwidth switch work.
1662 * input: struct net_deviceq *dev
1663 * HT_CHANNEL_WIDTH bandwidth //20M or 40M
1664 * HT_EXTCHNL_OFFSET offset //Upper, Lower, or Don't care
1667 * notice: I doubt whether SetBWModeInProgress flag is necessary as we can
1668 * test whether current work in the queue or not.//do I?
1669 *****************************************************************************/
1670 void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH bandwidth,
1671 HT_EXTCHNL_OFFSET offset)
1673 struct r8192_priv *priv = ieee80211_priv(dev);
1675 if (priv->SetBWModeInProgress)
1677 priv->SetBWModeInProgress = true;
1679 priv->CurrentChannelBW = bandwidth;
1681 if (offset == HT_EXTCHNL_OFFSET_LOWER)
1682 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
1683 else if (offset == HT_EXTCHNL_OFFSET_UPPER)
1684 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
1686 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
1688 rtl8192_SetBWModeWorkItem(dev);
1692 void InitialGain819xUsb(struct net_device *dev, u8 Operation)
1694 struct r8192_priv *priv = ieee80211_priv(dev);
1696 priv->InitialGainOperateType = Operation;
1699 queue_delayed_work(priv->priv_wq, &priv->initialgain_operate_wq, 0);
1702 void InitialGainOperateWorkItemCallBack(struct work_struct *work)
1704 struct delayed_work *dwork = container_of(work, struct delayed_work,
1706 struct r8192_priv *priv = container_of(dwork, struct r8192_priv,
1707 initialgain_operate_wq);
1708 struct net_device *dev = priv->ieee80211->dev;
1709 #define SCAN_RX_INITIAL_GAIN 0x17
1710 #define POWER_DETECTION_TH 0x08
1715 Operation = priv->InitialGainOperateType;
1717 switch (Operation) {
1719 RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n");
1720 initial_gain = SCAN_RX_INITIAL_GAIN;
1721 bitmask = bMaskByte0;
1722 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1724 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);
1725 priv->initgain_backup.xaagccore1 =
1726 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bitmask);
1727 priv->initgain_backup.xbagccore1 =
1728 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bitmask);
1729 priv->initgain_backup.xcagccore1 =
1730 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bitmask);
1731 priv->initgain_backup.xdagccore1 =
1732 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bitmask);
1733 bitmask = bMaskByte2;
1734 priv->initgain_backup.cca =
1735 (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, bitmask);
1737 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",
1738 priv->initgain_backup.xaagccore1);
1739 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",
1740 priv->initgain_backup.xbagccore1);
1741 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",
1742 priv->initgain_backup.xcagccore1);
1743 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",
1744 priv->initgain_backup.xdagccore1);
1745 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",
1746 priv->initgain_backup.cca);
1748 RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n",
1750 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
1751 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
1752 write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
1753 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
1754 RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n",
1755 POWER_DETECTION_TH);
1756 write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH);
1759 RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n");
1760 bitmask = 0x7f; /* Bit0 ~ Bit6 */
1761 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1763 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);
1765 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bitmask,
1766 (u32)priv->initgain_backup.xaagccore1);
1767 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bitmask,
1768 (u32)priv->initgain_backup.xbagccore1);
1769 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, bitmask,
1770 (u32)priv->initgain_backup.xcagccore1);
1771 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, bitmask,
1772 (u32)priv->initgain_backup.xdagccore1);
1773 bitmask = bMaskByte2;
1774 rtl8192_setBBreg(dev, rCCK0_CCA, bitmask,
1775 (u32)priv->initgain_backup.cca);
1777 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",
1778 priv->initgain_backup.xaagccore1);
1779 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",
1780 priv->initgain_backup.xbagccore1);
1781 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",
1782 priv->initgain_backup.xcagccore1);
1783 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",
1784 priv->initgain_backup.xdagccore1);
1785 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",
1786 priv->initgain_backup.cca);
1788 rtl8192_phy_setTxPower(dev, priv->ieee80211->current_network.channel);
1790 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1792 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1);
1795 RT_TRACE(COMP_SCAN, "Unknown IG Operation. \n");