3 #include "r819xU_phy.h"
4 #include "r819xU_phyreg.h"
5 #include "r8190_rtl8256.h"
7 #include "r819xU_firmware_img.h"
10 #include <linux/bitops.h>
12 static u32 RF_CHANNEL_TABLE_ZEBRA[] = {
31 #define rtl819XPHY_REG_1T2RArray Rtl8192UsbPHY_REG_1T2RArray
32 #define rtl819XMACPHY_Array_PG Rtl8192UsbMACPHY_Array_PG
33 #define rtl819XMACPHY_Array Rtl8192UsbMACPHY_Array
34 #define rtl819XRadioA_Array Rtl8192UsbRadioA_Array
35 #define rtl819XRadioB_Array Rtl8192UsbRadioB_Array
36 #define rtl819XRadioC_Array Rtl8192UsbRadioC_Array
37 #define rtl819XRadioD_Array Rtl8192UsbRadioD_Array
38 #define rtl819XAGCTAB_Array Rtl8192UsbAGCTAB_Array
40 /******************************************************************************
41 * function: This function reads BB parameters from header file we generate,
42 * and does register read/write
43 * input: u32 bitmask //taget bit pos in the addr to be modified
45 * return: u32 return the shift bit position of the mask
46 ******************************************************************************/
47 static u32 rtl8192_CalculateBitShift(u32 bitmask)
55 /******************************************************************************
56 * function: This function checks different RF type to execute legal judgement.
57 * If RF Path is illegal, we will return false.
58 * input: net_device *dev
61 * return: 0(illegal, false), 1(legal, true)
62 *****************************************************************************/
63 u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 eRFPath)
66 struct r8192_priv *priv = ieee80211_priv(dev);
68 if (priv->rf_type == RF_2T4R) {
70 } else if (priv->rf_type == RF_1T2R) {
71 if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B)
73 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
79 /******************************************************************************
80 * function: This function sets specific bits to BB register
81 * input: net_device *dev
82 * u32 reg_addr //target addr to be modified
83 * u32 bitmask //taget bit pos to be modified
84 * u32 data //value to be write
88 ******************************************************************************/
89 void rtl8192_setBBreg(struct net_device *dev, u32 reg_addr, u32 bitmask,
95 if (bitmask != bMaskDWord) {
96 read_nic_dword(dev, reg_addr, ®);
97 bitshift = rtl8192_CalculateBitShift(bitmask);
99 reg |= data << bitshift;
100 write_nic_dword(dev, reg_addr, reg);
102 write_nic_dword(dev, reg_addr, data);
106 /******************************************************************************
107 * function: This function reads specific bits from BB register
108 * input: net_device *dev
109 * u32 reg_addr //target addr to be readback
110 * u32 bitmask //taget bit pos to be readback
112 * return: u32 data //the readback register value
114 ******************************************************************************/
115 u32 rtl8192_QueryBBReg(struct net_device *dev, u32 reg_addr, u32 bitmask)
119 read_nic_dword(dev, reg_addr, ®);
120 bitshift = rtl8192_CalculateBitShift(bitmask);
122 return (reg & bitmask) >> bitshift;
125 static u32 phy_FwRFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
128 static void phy_FwRFSerialWrite(struct net_device *dev,
129 RF90_RADIO_PATH_E eRFPath, u32 offset,
132 /******************************************************************************
133 * function: This function reads register from RF chip
134 * input: net_device *dev
135 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
136 * u32 offset //target address to be read
138 * return: u32 readback value
139 * notice: There are three types of serial operations:
140 * (1) Software serial write.
141 * (2)Hardware LSSI-Low Speed Serial Interface.
142 * (3)Hardware HSSI-High speed serial write.
143 * Driver here need to implement (1) and (2)
144 * ---need more spec for this information.
145 ******************************************************************************/
146 static u32 rtl8192_phy_RFSerialRead(struct net_device *dev,
147 RF90_RADIO_PATH_E eRFPath, u32 offset)
149 struct r8192_priv *priv = ieee80211_priv(dev);
152 BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
154 rtl8192_setBBreg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData, 0);
155 /* Make sure RF register offset is correct */
158 /* Switch page for 8256 RF IC */
159 if (priv->rf_chip == RF_8256) {
161 priv->RfReg0Value[eRFPath] |= 0x140;
162 /* Switch to Reg_Mode2 for Reg 31-45 */
163 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
165 priv->RfReg0Value[eRFPath]<<16);
167 new_offset = offset - 30;
168 } else if (offset >= 16) {
169 priv->RfReg0Value[eRFPath] |= 0x100;
170 priv->RfReg0Value[eRFPath] &= (~0x40);
171 /* Switch to Reg_Mode1 for Reg16-30 */
172 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
174 priv->RfReg0Value[eRFPath]<<16);
176 new_offset = offset - 15;
181 RT_TRACE((COMP_PHY|COMP_ERR),
182 "check RF type here, need to be 8256\n");
185 /* Put desired read addr to LSSI control Register */
186 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress,
188 /* Issue a posedge trigger */
189 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0);
190 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1);
193 /* TODO: we should not delay such a long time. Ask for help from SD3 */
194 usleep_range(1000, 1000);
196 ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack,
200 /* Switch back to Reg_Mode0 */
201 if (priv->rf_chip == RF_8256) {
202 priv->RfReg0Value[eRFPath] &= 0xebf;
204 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord,
205 priv->RfReg0Value[eRFPath] << 16);
211 /******************************************************************************
212 * function: This function writes data to RF register
213 * input: net_device *dev
214 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
215 * u32 offset //target address to be written
216 * u32 data //the new register data to be written
219 * notice: For RF8256 only.
220 * ===========================================================================
221 * Reg Mode RegCTL[1] RegCTL[0] Note
222 * (Reg00[12]) (Reg00[10])
223 * ===========================================================================
224 * Reg_Mode0 0 x Reg 0 ~ 15(0x0 ~ 0xf)
225 * ---------------------------------------------------------------------------
226 * Reg_Mode1 1 0 Reg 16 ~ 30(0x1 ~ 0xf)
227 * ---------------------------------------------------------------------------
228 * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf)
229 * ---------------------------------------------------------------------------
230 *****************************************************************************/
231 static void rtl8192_phy_RFSerialWrite(struct net_device *dev,
232 RF90_RADIO_PATH_E eRFPath, u32 offset,
235 struct r8192_priv *priv = ieee80211_priv(dev);
236 u32 DataAndAddr = 0, new_offset = 0;
237 BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
240 if (priv->rf_chip == RF_8256) {
243 priv->RfReg0Value[eRFPath] |= 0x140;
244 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
246 priv->RfReg0Value[eRFPath] << 16);
247 new_offset = offset - 30;
248 } else if (offset >= 16) {
249 priv->RfReg0Value[eRFPath] |= 0x100;
250 priv->RfReg0Value[eRFPath] &= (~0x40);
251 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
253 priv->RfReg0Value[eRFPath]<<16);
254 new_offset = offset - 15;
259 RT_TRACE((COMP_PHY|COMP_ERR),
260 "check RF type here, need to be 8256\n");
264 /* Put write addr in [5:0] and write data in [31:16] */
265 DataAndAddr = (data<<16) | (new_offset&0x3f);
267 /* Write operation */
268 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
272 priv->RfReg0Value[eRFPath] = data;
274 /* Switch back to Reg_Mode0 */
275 if (priv->rf_chip == RF_8256) {
277 priv->RfReg0Value[eRFPath] &= 0xebf;
278 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
280 priv->RfReg0Value[eRFPath] << 16);
285 /******************************************************************************
286 * function: This function set specific bits to RF register
287 * input: net_device dev
288 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
289 * u32 reg_addr //target addr to be modified
290 * u32 bitmask //taget bit pos to be modified
291 * u32 data //value to be written
295 *****************************************************************************/
296 void rtl8192_phy_SetRFReg(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
297 u32 reg_addr, u32 bitmask, u32 data)
299 struct r8192_priv *priv = ieee80211_priv(dev);
302 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
305 if (priv->Rf_Mode == RF_OP_By_FW) {
306 if (bitmask != bMask12Bits) {
307 /* RF data is 12 bits only */
308 reg = phy_FwRFSerialRead(dev, eRFPath, reg_addr);
309 bitshift = rtl8192_CalculateBitShift(bitmask);
311 reg |= data << bitshift;
313 phy_FwRFSerialWrite(dev, eRFPath, reg_addr, reg);
315 phy_FwRFSerialWrite(dev, eRFPath, reg_addr, data);
321 if (bitmask != bMask12Bits) {
322 /* RF data is 12 bits only */
323 reg = rtl8192_phy_RFSerialRead(dev, eRFPath, reg_addr);
324 bitshift = rtl8192_CalculateBitShift(bitmask);
326 reg |= data << bitshift;
328 rtl8192_phy_RFSerialWrite(dev, eRFPath, reg_addr, reg);
330 rtl8192_phy_RFSerialWrite(dev, eRFPath, reg_addr, data);
335 /******************************************************************************
336 * function: This function reads specific bits from RF register
337 * input: net_device *dev
338 * u32 reg_addr //target addr to be readback
339 * u32 bitmask //taget bit pos to be readback
341 * return: u32 data //the readback register value
343 *****************************************************************************/
344 u32 rtl8192_phy_QueryRFReg(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
345 u32 reg_addr, u32 bitmask)
348 struct r8192_priv *priv = ieee80211_priv(dev);
351 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
353 if (priv->Rf_Mode == RF_OP_By_FW) {
354 reg = phy_FwRFSerialRead(dev, eRFPath, reg_addr);
357 reg = rtl8192_phy_RFSerialRead(dev, eRFPath, reg_addr);
359 bitshift = rtl8192_CalculateBitShift(bitmask);
360 reg = (reg & bitmask) >> bitshift;
365 /******************************************************************************
366 * function: We support firmware to execute RF-R/W.
367 * input: net_device *dev
368 * RF90_RADIO_PATH_E eRFPath
373 ****************************************************************************/
374 static u32 phy_FwRFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
382 /* Firmware RF Write control.
383 * We can not execute the scheme in the initial step.
384 * Otherwise, RF-R/W will waste much time.
385 * This is only for site survey. */
386 /* 1. Read operation need not insert data. bit 0-11 */
387 /* 2. Write RF register address. bit 12-19 */
388 data |= ((offset&0xFF)<<12);
389 /* 3. Write RF path. bit 20-21 */
390 data |= ((eRFPath&0x3)<<20);
391 /* 4. Set RF read indicator. bit 22=0 */
392 /* 5. Trigger Fw to operate the command. bit 31 */
394 /* 6. We can not execute read operation if bit 31 is 1. */
395 read_nic_dword(dev, QPNR, &tmp);
396 while (tmp & 0x80000000) {
397 /* If FW can not finish RF-R/W for more than ?? times.
401 read_nic_dword(dev, QPNR, &tmp);
406 /* 7. Execute read operation. */
407 write_nic_dword(dev, QPNR, data);
408 /* 8. Check if firmware send back RF content. */
409 read_nic_dword(dev, QPNR, &tmp);
410 while (tmp & 0x80000000) {
411 /* If FW can not finish RF-R/W for more than ?? times.
415 read_nic_dword(dev, QPNR, &tmp);
420 read_nic_dword(dev, RF_DATA, ®);
425 /******************************************************************************
426 * function: We support firmware to execute RF-R/W.
427 * input: net_device *dev
428 * RF90_RADIO_PATH_E eRFPath
434 ****************************************************************************/
435 static void phy_FwRFSerialWrite(struct net_device *dev,
436 RF90_RADIO_PATH_E eRFPath, u32 offset, u32 data)
441 /* Firmware RF Write control.
442 * We can not execute the scheme in the initial step.
443 * Otherwise, RF-R/W will waste much time.
444 * This is only for site survey. */
446 /* 1. Set driver write bit and 12 bit data. bit 0-11 */
447 /* 2. Write RF register address. bit 12-19 */
448 data |= ((offset&0xFF)<<12);
449 /* 3. Write RF path. bit 20-21 */
450 data |= ((eRFPath&0x3)<<20);
451 /* 4. Set RF write indicator. bit 22=1 */
453 /* 5. Trigger Fw to operate the command. bit 31=1 */
456 /* 6. Write operation. We can not write if bit 31 is 1. */
457 read_nic_dword(dev, QPNR, &tmp);
458 while (tmp & 0x80000000) {
459 /* If FW can not finish RF-R/W for more than ?? times.
463 read_nic_dword(dev, QPNR, &tmp);
468 /* 7. No matter check bit. We always force the write.
469 Because FW will not accept the command. */
470 write_nic_dword(dev, QPNR, data);
471 /* According to test, we must delay 20us to wait firmware
472 to finish RF write operation. */
473 /* We support delay in firmware side now. */
476 /******************************************************************************
477 * function: This function reads BB parameters from header file we generate,
478 * and do register read/write
479 * input: net_device *dev
482 * notice: BB parameters may change all the time, so please make
483 * sure it has been synced with the newest.
484 *****************************************************************************/
485 void rtl8192_phy_configmac(struct net_device *dev)
487 u32 dwArrayLen = 0, i;
488 u32 *pdwArray = NULL;
489 struct r8192_priv *priv = ieee80211_priv(dev);
491 if (priv->btxpowerdata_readfromEEPORM) {
492 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n");
493 dwArrayLen = MACPHY_Array_PGLength;
494 pdwArray = rtl819XMACPHY_Array_PG;
497 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array\n");
498 dwArrayLen = MACPHY_ArrayLength;
499 pdwArray = rtl819XMACPHY_Array;
501 for (i = 0; i < dwArrayLen; i = i+3) {
502 if (pdwArray[i] == 0x318)
503 pdwArray[i+2] = 0x00000800;
506 "Rtl8190MACPHY_Array[0]=%x Rtl8190MACPHY_Array[1]=%x Rtl8190MACPHY_Array[2]=%x\n",
507 pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
508 rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1],
513 /******************************************************************************
514 * function: This function does dirty work
515 * input: net_device *dev
519 * notice: BB parameters may change all the time, so please make
520 * sure it has been synced with the newest.
521 *****************************************************************************/
522 void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType)
527 u32 *rtl8192PhyRegArrayTable = NULL, *rtl8192AgcTabArrayTable = NULL;
529 if (Adapter->bInHctTest) {
530 PHY_REGArrayLen = PHY_REGArrayLengthDTM;
531 AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM;
532 Rtl8190PHY_REGArray_Table = Rtl819XPHY_REGArrayDTM;
533 Rtl8190AGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM;
536 if (ConfigType == BaseBand_Config_PHY_REG) {
537 for (i = 0; i < PHY_REG_1T2RArrayLength; i += 2) {
538 rtl8192_setBBreg(dev, rtl819XPHY_REG_1T2RArray[i],
540 rtl819XPHY_REG_1T2RArray[i+1]);
542 "i: %x, Rtl819xUsbPHY_REGArray[0]=%x Rtl819xUsbPHY_REGArray[1]=%x\n",
543 i, rtl819XPHY_REG_1T2RArray[i],
544 rtl819XPHY_REG_1T2RArray[i+1]);
546 } else if (ConfigType == BaseBand_Config_AGC_TAB) {
547 for (i = 0; i < AGCTAB_ArrayLength; i += 2) {
548 rtl8192_setBBreg(dev, rtl819XAGCTAB_Array[i],
549 bMaskDWord, rtl819XAGCTAB_Array[i+1]);
551 "i: %x, rtl819XAGCTAB_Array[0]=%x rtl819XAGCTAB_Array[1]=%x\n",
552 i, rtl819XAGCTAB_Array[i],
553 rtl819XAGCTAB_Array[i+1]);
558 /******************************************************************************
559 * function: This function initializes Register definition offset for
561 * input: net_device *dev
564 * notice: Initialization value here is constant and it should never
566 *****************************************************************************/
567 static void rtl8192_InitBBRFRegDef(struct net_device *dev)
569 struct r8192_priv *priv = ieee80211_priv(dev);
571 /* RF Interface Software Control */
572 /* 16 LSBs if read 32-bit from 0x870 */
573 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW;
574 /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */
575 priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW;
576 /* 16 LSBs if read 32-bit from 0x874 */
577 priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;
578 /* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */
579 priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;
581 /* RF Interface Readback Value */
582 /* 16 LSBs if read 32-bit from 0x8E0 */
583 priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB;
584 /* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */
585 priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;
586 /* 16 LSBs if read 32-bit from 0x8E4 */
587 priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;
588 /* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */
589 priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;
591 /* RF Interface Output (and Enable) */
592 /* 16 LSBs if read 32-bit from 0x860 */
593 priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE;
594 /* 16 LSBs if read 32-bit from 0x864 */
595 priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE;
596 /* 16 LSBs if read 32-bit from 0x868 */
597 priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;
598 /* 16 LSBs if read 32-bit from 0x86C */
599 priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;
601 /* RF Interface (Output and) Enable */
602 /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */
603 priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE;
604 /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */
605 priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE;
606 /* 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A) */
607 priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;
608 /* 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E) */
609 priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;
611 /* Addr of LSSI. Write RF register by driver */
612 priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter;
613 priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
614 priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
615 priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
619 priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter;
620 priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
621 priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
622 priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
624 /* Tx AGC Gain Stage (same for all path. Should we remove this?) */
625 priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage;
626 priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage;
627 priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage;
628 priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage;
630 /* Tranceiver A~D HSSI Parameter-1 */
631 /* wire control parameter1 */
632 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;
633 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;
634 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1;
635 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1;
637 /* Tranceiver A~D HSSI Parameter-2 */
638 /* wire control parameter2 */
639 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;
640 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;
641 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2;
642 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2;
644 /* RF Switch Control */
645 /* TR/Ant switch control */
646 priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl;
647 priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
648 priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
649 priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
652 priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
653 priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
654 priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
655 priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
658 priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
659 priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
660 priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
661 priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
663 /* RX AFE control 1 */
664 priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
665 priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
666 priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
667 priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
669 /* RX AFE control 1 */
670 priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
671 priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
672 priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
673 priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
675 /* Tx AFE control 1 */
676 priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
677 priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
678 priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
679 priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
681 /* Tx AFE control 2 */
682 priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
683 priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
684 priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
685 priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
687 /* Tranceiver LSSI Readback */
688 priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
689 priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
690 priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
691 priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
694 /******************************************************************************
695 * function: This function is to write register and then readback to make
696 * sure whether BB and RF is OK
697 * input: net_device *dev
698 * HW90_BLOCK_E CheckBlock
699 * RF90_RADIO_PATH_E eRFPath //only used when checkblock is
702 * return: return whether BB and RF is ok (0:OK, 1:Fail)
703 * notice: This function may be removed in the ASIC
704 ******************************************************************************/
705 u8 rtl8192_phy_checkBBAndRF(struct net_device *dev, HW90_BLOCK_E CheckBlock,
706 RF90_RADIO_PATH_E eRFPath)
709 u32 i, CheckTimes = 4, reg = 0;
711 u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
713 /* Initialize register address offset to be checked */
714 WriteAddr[HW90_BLOCK_MAC] = 0x100;
715 WriteAddr[HW90_BLOCK_PHY0] = 0x900;
716 WriteAddr[HW90_BLOCK_PHY1] = 0x800;
717 WriteAddr[HW90_BLOCK_RF] = 0x3;
718 RT_TRACE(COMP_PHY, "%s(), CheckBlock: %d\n", __func__, CheckBlock);
719 for (i = 0; i < CheckTimes; i++) {
721 /* Write data to register and readback */
722 switch (CheckBlock) {
725 "PHY_CheckBBRFOK(): Never Write 0x100 here!\n");
728 case HW90_BLOCK_PHY0:
729 case HW90_BLOCK_PHY1:
730 write_nic_dword(dev, WriteAddr[CheckBlock],
732 read_nic_dword(dev, WriteAddr[CheckBlock], ®);
736 WriteData[i] &= 0xfff;
737 rtl8192_phy_SetRFReg(dev, eRFPath,
738 WriteAddr[HW90_BLOCK_RF],
739 bMask12Bits, WriteData[i]);
740 /* TODO: we should not delay for such a long time.
742 usleep_range(1000, 1000);
743 reg = rtl8192_phy_QueryRFReg(dev, eRFPath,
744 WriteAddr[HW90_BLOCK_RF],
746 usleep_range(1000, 1000);
755 /* Check whether readback data is correct */
756 if (reg != WriteData[i]) {
757 RT_TRACE((COMP_PHY|COMP_ERR),
758 "error reg: %x, WriteData: %x\n",
768 /******************************************************************************
769 * function: This function initializes BB&RF
770 * input: net_device *dev
773 * notice: Initialization value may change all the time, so please make
774 * sure it has been synced with the newest.
775 ******************************************************************************/
776 static void rtl8192_BB_Config_ParaFile(struct net_device *dev)
778 struct r8192_priv *priv = ieee80211_priv(dev);
779 u8 reg_u8 = 0, eCheckItem = 0, status = 0;
782 /**************************************
783 * <1> Initialize BaseBand
784 *************************************/
786 /* --set BB Global Reset-- */
787 read_nic_byte(dev, BB_GLOBAL_RESET, ®_u8);
788 write_nic_byte(dev, BB_GLOBAL_RESET, (reg_u8|BB_GLOBAL_RESET_BIT));
790 /* ---set BB reset Active--- */
791 read_nic_dword(dev, CPU_GEN, ®_u32);
792 write_nic_dword(dev, CPU_GEN, (reg_u32&(~CPU_GEN_BB_RST)));
794 /* ----Ckeck FPGAPHY0 and PHY1 board is OK---- */
795 /* TODO: this function should be removed on ASIC */
796 for (eCheckItem = (HW90_BLOCK_E)HW90_BLOCK_PHY0;
797 eCheckItem <= HW90_BLOCK_PHY1; eCheckItem++) {
798 /* don't care RF path */
799 status = rtl8192_phy_checkBBAndRF(dev, (HW90_BLOCK_E)eCheckItem,
800 (RF90_RADIO_PATH_E)0);
802 RT_TRACE((COMP_ERR | COMP_PHY),
803 "PHY_RF8256_Config(): Check PHY%d Fail!!\n",
808 /* ---- Set CCK and OFDM Block "OFF"---- */
809 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0);
810 /* ----BB Register Initilazation---- */
811 /* ==m==>Set PHY REG From Header<==m== */
812 rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG);
814 /* ----Set BB reset de-Active---- */
815 read_nic_dword(dev, CPU_GEN, ®_u32);
816 write_nic_dword(dev, CPU_GEN, (reg_u32|CPU_GEN_BB_RST));
818 /* ----BB AGC table Initialization---- */
819 /* ==m==>Set PHY REG From Header<==m== */
820 rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB);
822 /* ----Enable XSTAL ---- */
823 write_nic_byte_E(dev, 0x5e, 0x00);
824 if (priv->card_8192_version == (u8)VERSION_819xU_A) {
825 /* Antenna gain offset from B/C/D to A */
826 reg_u32 = priv->AntennaTxPwDiff[1]<<4 |
827 priv->AntennaTxPwDiff[0];
828 rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC),
832 reg_u32 = priv->CrystalCap & 0xf;
833 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap,
837 /* Check if the CCK HighPower is turned ON.
838 This is used to calculate PWDB. */
839 priv->bCckHighPower = (u8)rtl8192_QueryBBReg(dev,
840 rFPGA0_XA_HSSIParameter2,
844 /******************************************************************************
845 * function: This function initializes BB&RF
846 * input: net_device *dev
849 * notice: Initialization value may change all the time, so please make
850 * sure it has been synced with the newest.
851 *****************************************************************************/
852 void rtl8192_BBConfig(struct net_device *dev)
854 rtl8192_InitBBRFRegDef(dev);
855 /* config BB&RF. As hardCode based initialization has not been well
856 * implemented, so use file first.
857 * FIXME: should implement it for hardcode? */
858 rtl8192_BB_Config_ParaFile(dev);
862 /******************************************************************************
863 * function: This function obtains the initialization value of Tx power Level
865 * input: net_device *dev
868 *****************************************************************************/
869 void rtl8192_phy_getTxPower(struct net_device *dev)
871 struct r8192_priv *priv = ieee80211_priv(dev);
874 read_nic_dword(dev, rTxAGC_Rate18_06,
875 &priv->MCSTxPowerLevelOriginalOffset[0]);
876 read_nic_dword(dev, rTxAGC_Rate54_24,
877 &priv->MCSTxPowerLevelOriginalOffset[1]);
878 read_nic_dword(dev, rTxAGC_Mcs03_Mcs00,
879 &priv->MCSTxPowerLevelOriginalOffset[2]);
880 read_nic_dword(dev, rTxAGC_Mcs07_Mcs04,
881 &priv->MCSTxPowerLevelOriginalOffset[3]);
882 read_nic_dword(dev, rTxAGC_Mcs11_Mcs08,
883 &priv->MCSTxPowerLevelOriginalOffset[4]);
884 read_nic_dword(dev, rTxAGC_Mcs15_Mcs12,
885 &priv->MCSTxPowerLevelOriginalOffset[5]);
887 /* Read rx initial gain */
888 read_nic_byte(dev, rOFDM0_XAAGCCore1, &priv->DefaultInitialGain[0]);
889 read_nic_byte(dev, rOFDM0_XBAGCCore1, &priv->DefaultInitialGain[1]);
890 read_nic_byte(dev, rOFDM0_XCAGCCore1, &priv->DefaultInitialGain[2]);
891 read_nic_byte(dev, rOFDM0_XDAGCCore1, &priv->DefaultInitialGain[3]);
893 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n",
894 priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
895 priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
898 read_nic_byte(dev, rOFDM0_RxDetector3, &priv->framesync);
899 read_nic_byte(dev, rOFDM0_RxDetector2, &tmp);
900 priv->framesyncC34 = tmp;
901 RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x\n",
902 rOFDM0_RxDetector3, priv->framesync);
904 /* Read SIFS (save the value read fome MACPHY_REG.txt) */
905 read_nic_word(dev, SIFS, &priv->SifsTime);
908 /******************************************************************************
909 * function: This function sets the initialization value of Tx power Level
911 * input: net_device *dev
915 ******************************************************************************/
916 void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel)
918 struct r8192_priv *priv = ieee80211_priv(dev);
919 u8 powerlevel = priv->TxPowerLevelCCK[channel-1];
920 u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
922 switch (priv->rf_chip) {
924 /* need further implement */
925 PHY_SetRF8256CCKTxPower(dev, powerlevel);
926 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
929 RT_TRACE((COMP_PHY|COMP_ERR),
930 "error RF chipID(8225 or 8258) in function %s()\n",
936 /******************************************************************************
937 * function: This function checks Rf chip to do RF config
938 * input: net_device *dev
940 * return: only 8256 is supported
941 ******************************************************************************/
942 void rtl8192_phy_RFConfig(struct net_device *dev)
944 struct r8192_priv *priv = ieee80211_priv(dev);
946 switch (priv->rf_chip) {
948 PHY_RF8256_Config(dev);
951 RT_TRACE(COMP_ERR, "error chip id\n");
956 /******************************************************************************
957 * function: This function updates Initial gain
958 * input: net_device *dev
960 * return: As Windows has not implemented this, wait for complement
961 ******************************************************************************/
962 void rtl8192_phy_updateInitGain(struct net_device *dev)
966 /******************************************************************************
967 * function: This function read RF parameters from general head file,
969 * input: net_device *dev
970 * RF90_RADIO_PATH_E eRFPath
972 * return: return code show if RF configuration is successful(0:pass, 1:fail)
973 * notice: Delay may be required for RF configuration
974 *****************************************************************************/
975 u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev,
976 RF90_RADIO_PATH_E eRFPath)
983 for (i = 0; i < RadioA_ArrayLength; i = i+2) {
985 if (rtl819XRadioA_Array[i] == 0xfe) {
989 rtl8192_phy_SetRFReg(dev, eRFPath,
990 rtl819XRadioA_Array[i],
992 rtl819XRadioA_Array[i+1]);
998 for (i = 0; i < RadioB_ArrayLength; i = i+2) {
1000 if (rtl819XRadioB_Array[i] == 0xfe) {
1004 rtl8192_phy_SetRFReg(dev, eRFPath,
1005 rtl819XRadioB_Array[i],
1007 rtl819XRadioB_Array[i+1]);
1013 for (i = 0; i < RadioC_ArrayLength; i = i+2) {
1015 if (rtl819XRadioC_Array[i] == 0xfe) {
1019 rtl8192_phy_SetRFReg(dev, eRFPath,
1020 rtl819XRadioC_Array[i],
1022 rtl819XRadioC_Array[i+1]);
1028 for (i = 0; i < RadioD_ArrayLength; i = i+2) {
1030 if (rtl819XRadioD_Array[i] == 0xfe) {
1034 rtl8192_phy_SetRFReg(dev, eRFPath,
1035 rtl819XRadioD_Array[i],
1037 rtl819XRadioD_Array[i+1]);
1050 /******************************************************************************
1051 * function: This function sets Tx Power of the channel
1052 * input: net_device *dev
1057 ******************************************************************************/
1058 static void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel)
1060 struct r8192_priv *priv = ieee80211_priv(dev);
1061 u8 powerlevel = priv->TxPowerLevelCCK[channel-1];
1062 u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
1064 switch (priv->rf_chip) {
1067 PHY_SetRF8225CckTxPower(Adapter, powerlevel);
1068 PHY_SetRF8225OfdmTxPower(Adapter, powerlevelOFDM24G);
1073 PHY_SetRF8256CCKTxPower(dev, powerlevel);
1074 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
1080 RT_TRACE(COMP_ERR, "unknown rf chip ID in %s()\n", __func__);
1085 /******************************************************************************
1086 * function: This function sets RF state on or off
1087 * input: net_device *dev
1088 * RT_RF_POWER_STATE eRFPowerState //Power State to set
1092 *****************************************************************************/
1093 bool rtl8192_SetRFPowerState(struct net_device *dev,
1094 RT_RF_POWER_STATE eRFPowerState)
1096 bool bResult = true;
1097 struct r8192_priv *priv = ieee80211_priv(dev);
1099 if (eRFPowerState == priv->ieee80211->eRFPowerState)
1102 if (priv->SetRFPowerStateInProgress)
1105 priv->SetRFPowerStateInProgress = true;
1107 switch (priv->rf_chip) {
1109 switch (eRFPowerState) {
1112 /* enable RF-Chip A/B - 0x860[4] */
1113 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT(4),
1115 /* analog to digital on - 0x88c[9:8] */
1116 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300,
1118 /* digital to analog on - 0x880[4:3] */
1119 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18,
1121 /* rx antenna on - 0xc04[1:0] */
1122 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3);
1123 /* rx antenna on - 0xd04[1:0] */
1124 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3);
1125 /* analog to digital part2 on - 0x880[6:5] */
1126 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60,
1137 /* disable RF-Chip A/B - 0x860[4] */
1138 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT(4),
1140 /* analog to digital off, for power save */
1141 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00,
1142 0x0); /* 0x88c[11:8] */
1143 /* digital to analog off, for power save - 0x880[4:3] */
1144 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18,
1146 /* rx antenna off - 0xc04[3:0] */
1147 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0);
1148 /* rx antenna off - 0xd04[3:0] */
1149 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);
1150 /* analog to digital part2 off, for power save */
1151 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60,
1152 0x0); /* 0x880[6:5] */
1158 RT_TRACE(COMP_ERR, "%s(): unknown state to set: 0x%X\n",
1159 __func__, eRFPowerState);
1164 RT_TRACE(COMP_ERR, "Not support rf_chip(%x)\n", priv->rf_chip);
1169 /* Update current RF state variable. */
1170 pHalData->eRFPowerState = eRFPowerState;
1171 switch (pHalData->RFChipID) {
1173 switch (pHalData->eRFPowerState) {
1175 /* If Rf off reason is from IPS,
1176 LED should blink with no link */
1177 if (pMgntInfo->RfOffReason == RF_CHANGE_BY_IPS)
1178 Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_NO_LINK);
1180 /* Turn off LED if RF is not ON. */
1181 Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_POWER_OFF);
1185 /* Turn on RF we are still linked, which might
1186 happen when we quickly turn off and on HW RF.
1188 if (pMgntInfo->bMediaConnect)
1189 Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_LINK);
1191 /* Turn off LED if RF is not ON. */
1192 Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_NO_LINK);
1201 RT_TRACE(COMP_RF, DBG_LOUD, "%s(): Unknown RF type\n",
1208 priv->SetRFPowerStateInProgress = false;
1213 /******************************************************************************
1214 * function: This function sets command table variable (struct SwChnlCmd).
1215 * input: SwChnlCmd *CmdTable //table to be set
1216 * u32 CmdTableIdx //variable index in table to be set
1217 * u32 CmdTableSz //table size
1218 * SwChnlCmdID CmdID //command ID to set
1223 * return: true if finished, false otherwise
1225 ******************************************************************************/
1226 static u8 rtl8192_phy_SetSwChnlCmdArray(SwChnlCmd *CmdTable, u32 CmdTableIdx,
1227 u32 CmdTableSz, SwChnlCmdID CmdID,
1228 u32 Para1, u32 Para2, u32 msDelay)
1232 if (CmdTable == NULL) {
1233 RT_TRACE(COMP_ERR, "%s(): CmdTable cannot be NULL\n", __func__);
1236 if (CmdTableIdx >= CmdTableSz) {
1237 RT_TRACE(COMP_ERR, "%s(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n",
1238 __func__, CmdTableIdx, CmdTableSz);
1242 pCmd = CmdTable + CmdTableIdx;
1243 pCmd->CmdID = CmdID;
1244 pCmd->Para1 = Para1;
1245 pCmd->Para2 = Para2;
1246 pCmd->msDelay = msDelay;
1251 /******************************************************************************
1252 * function: This function sets channel step by step
1253 * input: net_device *dev
1255 * u8 *stage //3 stages
1257 * u32 *delay //whether need to delay
1258 * output: store new stage, step and delay for next step
1259 * (combine with function above)
1260 * return: true if finished, false otherwise
1261 * notice: Wait for simpler function to replace it
1262 *****************************************************************************/
1263 static u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel,
1264 u8 *stage, u8 *step, u32 *delay)
1266 struct r8192_priv *priv = ieee80211_priv(dev);
1267 SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT];
1268 u32 PreCommonCmdCnt;
1269 SwChnlCmd PostCommonCmd[MAX_POSTCMD_CNT];
1270 u32 PostCommonCmdCnt;
1271 SwChnlCmd RfDependCmd[MAX_RFDEPENDCMD_CNT];
1273 SwChnlCmd *CurrentCmd = NULL;
1276 RT_TRACE(COMP_CH, "%s() stage: %d, step: %d, channel: %d\n",
1277 __func__, *stage, *step, channel);
1278 if (!IsLegalChannel(priv->ieee80211, channel)) {
1279 RT_TRACE(COMP_ERR, "set to illegal channel: %d\n", channel);
1280 /* return true to tell upper caller function this channel
1281 setting is finished! Or it will in while loop. */
1284 /* FIXME: need to check whether channel is legal or not here */
1287 /* <1> Fill up pre common command. */
1288 PreCommonCmdCnt = 0;
1289 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++,
1290 MAX_PRECMD_CNT, CmdID_SetTxPowerLevel,
1292 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++,
1293 MAX_PRECMD_CNT, CmdID_End, 0, 0, 0);
1295 /* <2> Fill up post common command. */
1296 PostCommonCmdCnt = 0;
1298 rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++,
1299 MAX_POSTCMD_CNT, CmdID_End, 0, 0, 0);
1301 /* <3> Fill up RF dependent command. */
1303 switch (priv->rf_chip) {
1305 if (!(channel >= 1 && channel <= 14)) {
1307 "illegal channel for Zebra 8225: %d\n",
1311 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1312 MAX_RFDEPENDCMD_CNT,
1315 RF_CHANNEL_TABLE_ZEBRA[channel],
1317 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1318 MAX_RFDEPENDCMD_CNT,
1319 CmdID_End, 0, 0, 0);
1323 /* TEST!! This is not the table for 8256!! */
1324 if (!(channel >= 1 && channel <= 14)) {
1326 "illegal channel for Zebra 8256: %d\n",
1330 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1331 MAX_RFDEPENDCMD_CNT,
1333 rZebra1_Channel, channel, 10);
1334 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++,
1335 MAX_RFDEPENDCMD_CNT,
1336 CmdID_End, 0, 0, 0);
1343 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
1351 CurrentCmd = &PreCommonCmd[*step];
1354 CurrentCmd = &RfDependCmd[*step];
1357 CurrentCmd = &PostCommonCmd[*step];
1361 if (CurrentCmd->CmdID == CmdID_End) {
1362 if ((*stage) == 2) {
1363 (*delay) = CurrentCmd->msDelay;
1371 switch (CurrentCmd->CmdID) {
1372 case CmdID_SetTxPowerLevel:
1373 if (priv->card_8192_version == (u8)VERSION_819xU_A)
1374 /* consider it later! */
1375 rtl8192_SetTxPowerLevel(dev, channel);
1377 case CmdID_WritePortUlong:
1378 write_nic_dword(dev, CurrentCmd->Para1,
1381 case CmdID_WritePortUshort:
1382 write_nic_word(dev, CurrentCmd->Para1,
1383 (u16)CurrentCmd->Para2);
1385 case CmdID_WritePortUchar:
1386 write_nic_byte(dev, CurrentCmd->Para1,
1387 (u8)CurrentCmd->Para2);
1389 case CmdID_RF_WriteReg:
1390 for (eRFPath = 0; eRFPath < RF90_PATH_MAX; eRFPath++) {
1391 rtl8192_phy_SetRFReg(dev,
1392 (RF90_RADIO_PATH_E)eRFPath,
1405 (*delay) = CurrentCmd->msDelay;
1410 /******************************************************************************
1411 * function: This function does actually set channel work
1412 * input: net_device *dev
1416 * notice: We should not call this function directly
1417 *****************************************************************************/
1418 static void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel)
1420 struct r8192_priv *priv = ieee80211_priv(dev);
1423 while (!rtl8192_phy_SwChnlStepByStep(dev, channel, &priv->SwChnlStage,
1424 &priv->SwChnlStep, &delay)) {
1430 /******************************************************************************
1431 * function: Callback routine of the work item for switch channel.
1432 * input: net_device *dev
1436 *****************************************************************************/
1437 void rtl8192_SwChnl_WorkItem(struct net_device *dev)
1440 struct r8192_priv *priv = ieee80211_priv(dev);
1442 RT_TRACE(COMP_CH, "==> SwChnlCallback819xUsbWorkItem(), chan:%d\n",
1446 rtl8192_phy_FinishSwChnlNow(dev, priv->chan);
1448 RT_TRACE(COMP_CH, "<== SwChnlCallback819xUsbWorkItem()\n");
1451 /******************************************************************************
1452 * function: This function scheduled actual work item to set channel
1453 * input: net_device *dev
1454 * u8 channel //channel to set
1456 * return: return code show if workitem is scheduled (1:pass, 0:fail)
1457 * notice: Delay may be required for RF configuration
1458 ******************************************************************************/
1459 u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel)
1461 struct r8192_priv *priv = ieee80211_priv(dev);
1463 RT_TRACE(COMP_CH, "%s(), SwChnlInProgress: %d\n", __func__,
1464 priv->SwChnlInProgress);
1467 if (priv->SwChnlInProgress)
1470 /* -------------------------------------------- */
1471 switch (priv->ieee80211->mode) {
1472 case WIRELESS_MODE_A:
1473 case WIRELESS_MODE_N_5G:
1474 if (channel <= 14) {
1475 RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14\n");
1479 case WIRELESS_MODE_B:
1481 RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14\n");
1485 case WIRELESS_MODE_G:
1486 case WIRELESS_MODE_N_24G:
1488 RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14\n");
1493 /* -------------------------------------------- */
1495 priv->SwChnlInProgress = true;
1499 priv->chan = channel;
1501 priv->SwChnlStage = 0;
1502 priv->SwChnlStep = 0;
1504 rtl8192_SwChnl_WorkItem(dev);
1506 priv->SwChnlInProgress = false;
1510 /******************************************************************************
1511 * function: Callback routine of the work item for set bandwidth mode.
1512 * input: net_device *dev
1515 * notice: I doubt whether SetBWModeInProgress flag is necessary as we can
1516 * test whether current work in the queue or not.//do I?
1517 *****************************************************************************/
1518 void rtl8192_SetBWModeWorkItem(struct net_device *dev)
1521 struct r8192_priv *priv = ieee80211_priv(dev);
1524 RT_TRACE(COMP_SWBW, "%s() Switch to %s bandwidth\n", __func__,
1525 priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz");
1528 if (priv->rf_chip == RF_PSEUDO_11N) {
1529 priv->SetBWModeInProgress = false;
1533 /* <1> Set MAC register */
1534 read_nic_byte(dev, BW_OPMODE, ®BwOpMode);
1536 switch (priv->CurrentChannelBW) {
1537 case HT_CHANNEL_WIDTH_20:
1538 regBwOpMode |= BW_OPMODE_20MHZ;
1539 /* We have not verify whether this register works */
1540 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1543 case HT_CHANNEL_WIDTH_20_40:
1544 regBwOpMode &= ~BW_OPMODE_20MHZ;
1545 /* We have not verify whether this register works */
1546 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
1551 "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",
1552 priv->CurrentChannelBW);
1556 /* <2> Set PHY related register */
1557 switch (priv->CurrentChannelBW) {
1558 case HT_CHANNEL_WIDTH_20:
1559 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
1560 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
1561 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1,
1564 /* Correct the tx power for CCK rate in 20M. */
1565 priv->cck_present_attentuation =
1566 priv->cck_present_attentuation_20Mdefault +
1567 priv->cck_present_attentuation_difference;
1569 if (priv->cck_present_attentuation > 22)
1570 priv->cck_present_attentuation = 22;
1571 if (priv->cck_present_attentuation < 0)
1572 priv->cck_present_attentuation = 0;
1574 "20M, pHalData->CCKPresentAttentuation = %d\n",
1575 priv->cck_present_attentuation);
1577 if (priv->chan == 14 && !priv->bcck_in_ch14) {
1578 priv->bcck_in_ch14 = true;
1579 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1580 } else if (priv->chan != 14 && priv->bcck_in_ch14) {
1581 priv->bcck_in_ch14 = false;
1582 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1584 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1588 case HT_CHANNEL_WIDTH_20_40:
1589 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
1590 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
1591 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand,
1592 priv->nCur40MhzPrimeSC>>1);
1593 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
1594 rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00,
1595 priv->nCur40MhzPrimeSC);
1596 priv->cck_present_attentuation =
1597 priv->cck_present_attentuation_40Mdefault +
1598 priv->cck_present_attentuation_difference;
1600 if (priv->cck_present_attentuation > 22)
1601 priv->cck_present_attentuation = 22;
1602 if (priv->cck_present_attentuation < 0)
1603 priv->cck_present_attentuation = 0;
1606 "40M, pHalData->CCKPresentAttentuation = %d\n",
1607 priv->cck_present_attentuation);
1608 if (priv->chan == 14 && !priv->bcck_in_ch14) {
1609 priv->bcck_in_ch14 = true;
1610 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1611 } else if (priv->chan != 14 && priv->bcck_in_ch14) {
1612 priv->bcck_in_ch14 = false;
1613 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1615 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1621 "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",
1622 priv->CurrentChannelBW);
1626 /* Skip over setting of J-mode in BB register here.
1627 Default value is "None J mode". */
1629 /* <3> Set RF related register */
1630 switch (priv->rf_chip) {
1633 PHY_SetRF8225Bandwidth(Adapter, pHalData->CurrentChannelBW);
1638 PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
1648 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
1651 priv->SetBWModeInProgress = false;
1653 RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb(), %d\n",
1654 atomic_read(&priv->ieee80211->atm_swbw));
1657 /******************************************************************************
1658 * function: This function schedules bandwidth switch work.
1659 * input: struct net_deviceq *dev
1660 * HT_CHANNEL_WIDTH bandwidth //20M or 40M
1661 * HT_EXTCHNL_OFFSET offset //Upper, Lower, or Don't care
1664 * notice: I doubt whether SetBWModeInProgress flag is necessary as we can
1665 * test whether current work in the queue or not.//do I?
1666 *****************************************************************************/
1667 void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH bandwidth,
1668 HT_EXTCHNL_OFFSET offset)
1670 struct r8192_priv *priv = ieee80211_priv(dev);
1672 if (priv->SetBWModeInProgress)
1674 priv->SetBWModeInProgress = true;
1676 priv->CurrentChannelBW = bandwidth;
1678 if (offset == HT_EXTCHNL_OFFSET_LOWER)
1679 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
1680 else if (offset == HT_EXTCHNL_OFFSET_UPPER)
1681 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
1683 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
1685 rtl8192_SetBWModeWorkItem(dev);
1689 void InitialGain819xUsb(struct net_device *dev, u8 Operation)
1691 struct r8192_priv *priv = ieee80211_priv(dev);
1693 priv->InitialGainOperateType = Operation;
1696 queue_delayed_work(priv->priv_wq, &priv->initialgain_operate_wq, 0);
1699 void InitialGainOperateWorkItemCallBack(struct work_struct *work)
1701 struct delayed_work *dwork = container_of(work, struct delayed_work,
1703 struct r8192_priv *priv = container_of(dwork, struct r8192_priv,
1704 initialgain_operate_wq);
1705 struct net_device *dev = priv->ieee80211->dev;
1706 #define SCAN_RX_INITIAL_GAIN 0x17
1707 #define POWER_DETECTION_TH 0x08
1712 Operation = priv->InitialGainOperateType;
1714 switch (Operation) {
1716 RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n");
1717 initial_gain = SCAN_RX_INITIAL_GAIN;
1718 bitmask = bMaskByte0;
1719 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1721 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);
1722 priv->initgain_backup.xaagccore1 =
1723 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bitmask);
1724 priv->initgain_backup.xbagccore1 =
1725 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bitmask);
1726 priv->initgain_backup.xcagccore1 =
1727 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bitmask);
1728 priv->initgain_backup.xdagccore1 =
1729 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bitmask);
1730 bitmask = bMaskByte2;
1731 priv->initgain_backup.cca =
1732 (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, bitmask);
1734 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",
1735 priv->initgain_backup.xaagccore1);
1736 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",
1737 priv->initgain_backup.xbagccore1);
1738 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",
1739 priv->initgain_backup.xcagccore1);
1740 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",
1741 priv->initgain_backup.xdagccore1);
1742 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",
1743 priv->initgain_backup.cca);
1745 RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x\n",
1747 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
1748 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
1749 write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
1750 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
1751 RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x\n",
1752 POWER_DETECTION_TH);
1753 write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH);
1756 RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n");
1757 bitmask = 0x7f; /* Bit0 ~ Bit6 */
1758 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1760 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);
1762 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bitmask,
1763 (u32)priv->initgain_backup.xaagccore1);
1764 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bitmask,
1765 (u32)priv->initgain_backup.xbagccore1);
1766 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, bitmask,
1767 (u32)priv->initgain_backup.xcagccore1);
1768 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, bitmask,
1769 (u32)priv->initgain_backup.xdagccore1);
1770 bitmask = bMaskByte2;
1771 rtl8192_setBBreg(dev, rCCK0_CCA, bitmask,
1772 (u32)priv->initgain_backup.cca);
1774 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",
1775 priv->initgain_backup.xaagccore1);
1776 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",
1777 priv->initgain_backup.xbagccore1);
1778 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",
1779 priv->initgain_backup.xcagccore1);
1780 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",
1781 priv->initgain_backup.xdagccore1);
1782 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",
1783 priv->initgain_backup.cca);
1785 rtl8192_phy_setTxPower(dev, priv->ieee80211->current_network.channel);
1787 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1789 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1);
1792 RT_TRACE(COMP_SCAN, "Unknown IG Operation.\n");