1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 ******************************************************************************/
15 #include <osdep_service.h>
16 #include <drv_types.h>
20 #include <rtl8723a_hal.h>
21 #include <usb_ops_linux.h>
25 void dump_chip_info23a(struct hal_version ChipVersion)
30 cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8723A_");
32 cnt += sprintf((buf + cnt), "%s_", IS_NORMAL_CHIP(ChipVersion) ?
33 "Normal_Chip" : "Test_Chip");
34 cnt += sprintf((buf + cnt), "%s_",
35 IS_CHIP_VENDOR_TSMC(ChipVersion) ? "TSMC" : "UMC");
36 if (IS_A_CUT(ChipVersion))
37 cnt += sprintf((buf + cnt), "A_CUT_");
38 else if (IS_B_CUT(ChipVersion))
39 cnt += sprintf((buf + cnt), "B_CUT_");
40 else if (IS_C_CUT(ChipVersion))
41 cnt += sprintf((buf + cnt), "C_CUT_");
42 else if (IS_D_CUT(ChipVersion))
43 cnt += sprintf((buf + cnt), "D_CUT_");
44 else if (IS_E_CUT(ChipVersion))
45 cnt += sprintf((buf + cnt), "E_CUT_");
47 cnt += sprintf((buf + cnt), "UNKNOWN_CUT(%d)_",
48 ChipVersion.CUTVersion);
50 if (IS_1T1R(ChipVersion))
51 cnt += sprintf((buf + cnt), "1T1R_");
52 else if (IS_1T2R(ChipVersion))
53 cnt += sprintf((buf + cnt), "1T2R_");
54 else if (IS_2T2R(ChipVersion))
55 cnt += sprintf((buf + cnt), "2T2R_");
57 cnt += sprintf((buf + cnt), "UNKNOWN_RFTYPE(%d)_",
60 cnt += sprintf((buf + cnt), "RomVer(%d)\n", ChipVersion.ROMVer);
65 #define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80
67 /* return the final channel plan decision */
68 /* hw_channel_plan: channel plan from HW (efuse/eeprom) */
69 /* sw_channel_plan: channel plan from SW (registry/module param) */
70 /* def_channel_plan: channel plan used when the former two is invalid */
71 u8 hal_com_get_channel_plan23a(struct rtw_adapter *padapter, u8 hw_channel_plan,
72 u8 sw_channel_plan, u8 def_channel_plan,
80 if (!rtw_is_channel_plan_valid(sw_channel_plan))
82 if (hw_channel_plan & EEPROM_CHANNEL_PLAN_BY_HW_MASK)
87 chnlPlan = sw_channel_plan;
89 chnlPlan = hw_channel_plan & (~EEPROM_CHANNEL_PLAN_BY_HW_MASK);
91 if (!rtw_is_channel_plan_valid(chnlPlan))
92 chnlPlan = def_channel_plan;
97 u8 MRateToHwRate23a(u8 rate)
102 /* CCK and OFDM non-HT rates */
103 case IEEE80211_CCK_RATE_1MB:
106 case IEEE80211_CCK_RATE_2MB:
109 case IEEE80211_CCK_RATE_5MB:
112 case IEEE80211_CCK_RATE_11MB:
115 case IEEE80211_OFDM_RATE_6MB:
118 case IEEE80211_OFDM_RATE_9MB:
121 case IEEE80211_OFDM_RATE_12MB:
124 case IEEE80211_OFDM_RATE_18MB:
127 case IEEE80211_OFDM_RATE_24MB:
130 case IEEE80211_OFDM_RATE_36MB:
133 case IEEE80211_OFDM_RATE_48MB:
136 case IEEE80211_OFDM_RATE_54MB:
140 /* HT rates since here */
141 /* case MGN_MCS0: ret = DESC_RATEMCS0; break; */
142 /* case MGN_MCS1: ret = DESC_RATEMCS1; break; */
143 /* case MGN_MCS2: ret = DESC_RATEMCS2; break; */
144 /* case MGN_MCS3: ret = DESC_RATEMCS3; break; */
145 /* case MGN_MCS4: ret = DESC_RATEMCS4; break; */
146 /* case MGN_MCS5: ret = DESC_RATEMCS5; break; */
147 /* case MGN_MCS6: ret = DESC_RATEMCS6; break; */
148 /* case MGN_MCS7: ret = DESC_RATEMCS7; break; */
156 void HalSetBrateCfg23a(struct rtw_adapter *padapter, u8 *mBratesOS)
158 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
159 u8 i, is_brate, brate;
163 for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) {
164 is_brate = mBratesOS[i] & IEEE80211_BASIC_RATE_MASK;
165 brate = mBratesOS[i] & 0x7f;
169 case IEEE80211_CCK_RATE_1MB:
170 brate_cfg |= RATE_1M;
172 case IEEE80211_CCK_RATE_2MB:
173 brate_cfg |= RATE_2M;
175 case IEEE80211_CCK_RATE_5MB:
176 brate_cfg |= RATE_5_5M;
178 case IEEE80211_CCK_RATE_11MB:
179 brate_cfg |= RATE_11M;
181 case IEEE80211_OFDM_RATE_6MB:
182 brate_cfg |= RATE_6M;
184 case IEEE80211_OFDM_RATE_9MB:
185 brate_cfg |= RATE_9M;
187 case IEEE80211_OFDM_RATE_12MB:
188 brate_cfg |= RATE_12M;
190 case IEEE80211_OFDM_RATE_18MB:
191 brate_cfg |= RATE_18M;
193 case IEEE80211_OFDM_RATE_24MB:
194 brate_cfg |= RATE_24M;
196 case IEEE80211_OFDM_RATE_36MB:
197 brate_cfg |= RATE_36M;
199 case IEEE80211_OFDM_RATE_48MB:
200 brate_cfg |= RATE_48M;
202 case IEEE80211_OFDM_RATE_54MB:
203 brate_cfg |= RATE_54M;
209 /* 2007.01.16, by Emily */
210 /* Select RRSR (in Legacy-OFDM and CCK) */
211 /* For 8190, we select only 24M, 12M, 6M, 11M, 5.5M, 2M,
212 and 1M from the Basic rate. */
213 /* We do not use other rates. */
214 /* 2011.03.30 add by Luke Lee */
215 /* CCK 2M ACK should be disabled for some BCM and Atheros AP IOT */
216 /* because CCK 2M has poor TXEVM */
217 /* CCK 5.5M & 11M ACK should be enabled for better
220 brate_cfg = (brate_cfg | 0xd) & 0x15d;
221 pHalData->BasicRateSet = brate_cfg;
222 brate_cfg |= 0x01; /* default enable 1M ACK rate */
223 DBG_8723A("HW_VAR_BASIC_RATE: BrateCfg(%#x)\n", brate_cfg);
225 /* Set RRSR rate table. */
226 rtl8723au_write8(padapter, REG_RRSR, brate_cfg & 0xff);
227 rtl8723au_write8(padapter, REG_RRSR + 1, (brate_cfg >> 8) & 0xff);
228 rtl8723au_write8(padapter, REG_RRSR + 2,
229 rtl8723au_read8(padapter, REG_RRSR + 2) & 0xf0);
232 /* Set RTS initial rate */
233 while (brate_cfg > 0x1) {
234 brate_cfg = (brate_cfg >> 1);
238 rtl8723au_write8(padapter, REG_INIRTS_RATE_SEL, rate_index);
243 static void _OneOutPipeMapping(struct rtw_adapter *pAdapter)
245 struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(pAdapter);
247 pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0]; /* VO */
248 pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0]; /* VI */
249 pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[0]; /* BE */
250 pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0]; /* BK */
252 pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0]; /* BCN */
253 pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0]; /* MGT */
254 pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0]; /* HIGH */
255 pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0]; /* TXCMD */
258 static void _TwoOutPipeMapping(struct rtw_adapter *pAdapter, bool bWIFICfg)
260 struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(pAdapter);
262 if (bWIFICfg) { /* WMM */
263 /* BK, BE, VI, VO, BCN, CMD, MGT, HIGH, HCCA */
264 /* 0, 1, 0, 1, 0, 0, 0, 0, 0 }; */
266 pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[1]; /* VO */
267 pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0]; /* VI */
268 pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1]; /* BE */
269 pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0]; /* BK */
271 pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0]; /* BCN */
272 pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0]; /* MGT */
273 pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0]; /* HIGH */
274 pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0]; /* TXCMD*/
275 } else { /* typical setting */
276 /* BK, BE, VI, VO, BCN, CMD, MGT, HIGH, HCCA */
277 /* 1, 1, 0, 0, 0, 0, 0, 0, 0 }; */
279 pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0]; /* VO */
280 pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0]; /* VI */
281 pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1]; /* BE */
282 pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1]; /* BK */
284 pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0]; /* BCN */
285 pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0]; /* MGT */
286 pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0]; /* HIGH */
287 pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0]; /* TXCMD*/
291 static void _ThreeOutPipeMapping(struct rtw_adapter *pAdapter, bool bWIFICfg)
293 struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(pAdapter);
295 if (bWIFICfg) { /* for WMM */
296 /* BK, BE, VI, VO, BCN, CMD, MGT, HIGH, HCCA */
297 /* 1, 2, 1, 0, 0, 0, 0, 0, 0 }; */
299 pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0]; /* VO */
300 pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1]; /* VI */
301 pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2]; /* BE */
302 pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1]; /* BK */
304 pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0]; /* BCN */
305 pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0]; /* MGT */
306 pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0]; /* HIGH */
307 pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0]; /* TXCMD*/
308 } else { /* typical setting */
309 /* BK, BE, VI, VO, BCN, CMD, MGT, HIGH, HCCA */
310 /* 2, 2, 1, 0, 0, 0, 0, 0, 0 }; */
312 pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0]; /* VO */
313 pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1]; /* VI */
314 pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2]; /* BE */
315 pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[2]; /* BK */
317 pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0]; /* BCN */
318 pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0]; /* MGT */
319 pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0]; /* HIGH */
320 pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0]; /* TXCMD*/
324 bool Hal_MappingOutPipe23a(struct rtw_adapter *pAdapter, u8 NumOutPipe)
326 struct registry_priv *pregistrypriv = &pAdapter->registrypriv;
327 bool bWIFICfg = (pregistrypriv->wifi_spec) ? true : false;
330 switch (NumOutPipe) {
332 _TwoOutPipeMapping(pAdapter, bWIFICfg);
335 _ThreeOutPipeMapping(pAdapter, bWIFICfg);
338 _OneOutPipeMapping(pAdapter);
350 * Field TRIGGER CONTENT CMD_SEQ CMD_LEN CMD_ID
351 * BITS [127:120] [119:16] [15:8] [7:4] [3:0]
354 void c2h_evt_clear23a(struct rtw_adapter *adapter)
356 rtl8723au_write8(adapter, REG_C2HEVT_CLEAR, C2H_EVT_HOST_CLOSE);
359 int c2h_evt_read23a(struct rtw_adapter *adapter, u8 *buf)
362 struct c2h_evt_hdr *c2h_evt;
369 trigger = rtl8723au_read8(adapter, REG_C2HEVT_CLEAR);
371 if (trigger == C2H_EVT_HOST_CLOSE)
372 goto exit; /* Not ready */
373 else if (trigger != C2H_EVT_FW_CLOSE)
374 goto clear_evt; /* Not a valid value */
376 c2h_evt = (struct c2h_evt_hdr *)buf;
378 memset(c2h_evt, 0, 16);
380 *buf = rtl8723au_read8(adapter, REG_C2HEVT_MSG_NORMAL);
381 *(buf + 1) = rtl8723au_read8(adapter, REG_C2HEVT_MSG_NORMAL + 1);
383 RT_PRINT_DATA(_module_hal_init_c_, _drv_info_, "c2h_evt_read23a(): ",
384 &c2h_evt, sizeof(c2h_evt));
387 DBG_8723A("%s id:%u, len:%u, seq:%u, trigger:0x%02x\n",
388 __func__, c2h_evt->id, c2h_evt->plen, c2h_evt->seq,
392 /* Read the content */
393 for (i = 0; i < c2h_evt->plen; i++)
394 c2h_evt->payload[i] = rtl8723au_read8(adapter,
395 REG_C2HEVT_MSG_NORMAL +
396 sizeof(*c2h_evt) + i);
398 RT_PRINT_DATA(_module_hal_init_c_, _drv_info_,
399 "c2h_evt_read23a(): Command Content:\n", c2h_evt->payload,
406 * Clear event to notify FW we have read the command.
407 * If this field isn't clear, the FW won't update the
408 * next command message.
410 c2h_evt_clear23a(adapter);
416 rtl8723a_set_ampdu_min_space(struct rtw_adapter *padapter, u8 MinSpacingToSet)
420 if (MinSpacingToSet <= 7) {
421 switch (padapter->securitypriv.dot11PrivacyAlgrthm) {
423 case WLAN_CIPHER_SUITE_CCMP:
427 case WLAN_CIPHER_SUITE_WEP40:
428 case WLAN_CIPHER_SUITE_WEP104:
429 case WLAN_CIPHER_SUITE_TKIP:
437 if (MinSpacingToSet < SecMinSpace)
438 MinSpacingToSet = SecMinSpace;
440 /* RT_TRACE(COMP_MLME, DBG_LOUD,
441 ("Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
442 padapter->MgntInfo.MinSpaceCfg)); */
444 rtl8723au_read8(padapter, REG_AMPDU_MIN_SPACE) & 0xf8;
445 rtl8723au_write8(padapter, REG_AMPDU_MIN_SPACE,
450 void rtl8723a_set_ampdu_factor(struct rtw_adapter *padapter, u8 FactorToSet)
452 u8 RegToSet_Normal[4] = { 0x41, 0xa8, 0x72, 0xb9 };
457 pRegToSet = RegToSet_Normal; /* 0xb972a841; */
458 #ifdef CONFIG_8723AU_BT_COEXIST
459 if ((BT_IsBtDisabled(padapter) == false) &&
460 (BT_1Ant(padapter) == true)) {
463 #endif /* CONFIG_8723AU_BT_COEXIST */
468 if (FactorToSet <= 3) {
469 FactorToSet = (1 << (FactorToSet + 2));
470 if (FactorToSet > MaxAggNum)
471 FactorToSet = MaxAggNum;
473 for (index = 0; index < 4; index++) {
474 if ((pRegToSet[index] & 0xf0) > (FactorToSet << 4))
475 pRegToSet[index] = (pRegToSet[index] & 0x0f) |
478 if ((pRegToSet[index] & 0x0f) > FactorToSet)
479 pRegToSet[index] = (pRegToSet[index] & 0xf0) |
482 rtl8723au_write8(padapter, REG_AGGLEN_LMT + index,
486 /* RT_TRACE(COMP_MLME, DBG_LOUD,
487 ("Set HW_VAR_AMPDU_FACTOR: %#x\n", FactorToSet)); */
491 void rtl8723a_set_acm_ctrl(struct rtw_adapter *padapter, u8 ctrl)
496 hwctrl |= AcmHw_HwEn;
498 if (ctrl & BIT(1)) /* BE */
499 hwctrl |= AcmHw_BeqEn;
501 if (ctrl & BIT(2)) /* VI */
502 hwctrl |= AcmHw_ViqEn;
504 if (ctrl & BIT(3)) /* VO */
505 hwctrl |= AcmHw_VoqEn;
508 DBG_8723A("[HW_VAR_ACM_CTRL] Write 0x%02X\n", hwctrl);
509 rtl8723au_write8(padapter, REG_ACMHWCTRL, hwctrl);
512 void rtl8723a_set_media_status(struct rtw_adapter *padapter, u8 status)
516 val8 = rtl8723au_read8(padapter, MSR) & 0x0c;
518 rtl8723au_write8(padapter, MSR, val8);
521 void rtl8723a_set_media_status1(struct rtw_adapter *padapter, u8 status)
525 val8 = rtl8723au_read8(padapter, MSR) & 0x03;
527 rtl8723au_write8(padapter, MSR, val8);
530 void rtl8723a_set_bcn_func(struct rtw_adapter *padapter, u8 val)
533 SetBcnCtrlReg23a(padapter, EN_BCN_FUNCTION | EN_TXBCN_RPT, 0);
535 SetBcnCtrlReg23a(padapter, 0, EN_BCN_FUNCTION | EN_TXBCN_RPT);
538 void rtl8723a_check_bssid(struct rtw_adapter *padapter, u8 val)
541 val32 = rtl8723au_read32(padapter, REG_RCR);
543 val32 |= RCR_CBSSID_DATA | RCR_CBSSID_BCN;
545 val32 &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);
546 rtl8723au_write32(padapter, REG_RCR, val32);
549 void rtl8723a_mlme_sitesurvey(struct rtw_adapter *padapter, u8 flag)
551 if (flag) { /* under sitesurvey */
554 /* config RCR to receive different BSSID & not
555 to receive data frame */
556 v32 = rtl8723au_read32(padapter, REG_RCR);
557 v32 &= ~(RCR_CBSSID_BCN);
558 rtl8723au_write32(padapter, REG_RCR, v32);
559 /* reject all data frame */
560 rtl8723au_write16(padapter, REG_RXFLTMAP2, 0);
562 /* disable update TSF */
563 SetBcnCtrlReg23a(padapter, DIS_TSF_UDT, 0);
564 } else { /* sitesurvey done */
566 struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
567 struct mlme_ext_info *pmlmeinfo;
570 pmlmeinfo = &pmlmeext->mlmext_info;
572 if ((is_client_associated_to_ap23a(padapter) == true) ||
573 ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) ||
574 ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)) {
575 /* enable to rx data frame */
576 rtl8723au_write16(padapter, REG_RXFLTMAP2, 0xFFFF);
578 /* enable update TSF */
579 SetBcnCtrlReg23a(padapter, 0, DIS_TSF_UDT);
582 v32 = rtl8723au_read32(padapter, REG_RCR);
583 v32 |= RCR_CBSSID_BCN;
584 rtl8723au_write32(padapter, REG_RCR, v32);
587 #ifdef CONFIG_8723AU_BT_COEXIST
588 BT_WifiScanNotify(padapter, flag ? true : false);
592 void rtl8723a_on_rcr_am(struct rtw_adapter *padapter)
594 rtl8723au_write32(padapter, REG_RCR,
595 rtl8723au_read32(padapter, REG_RCR) | RCR_AM);
596 DBG_8723A("%s, %d, RCR = %x \n", __FUNCTION__, __LINE__,
597 rtl8723au_read32(padapter, REG_RCR));
600 void rtl8723a_off_rcr_am(struct rtw_adapter *padapter)
602 rtl8723au_write32(padapter, REG_RCR,
603 rtl8723au_read32(padapter, REG_RCR) & (~RCR_AM));
604 DBG_8723A("%s, %d, RCR = %x \n", __FUNCTION__, __LINE__,
605 rtl8723au_read32(padapter, REG_RCR));
608 void rtl8723a_set_slot_time(struct rtw_adapter *padapter, u8 slottime)
610 u8 u1bAIFS, aSifsTime;
611 struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
612 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
614 rtl8723au_write8(padapter, REG_SLOT, slottime);
616 if (pmlmeinfo->WMM_enable == 0) {
617 if (pmlmeext->cur_wireless_mode == WIRELESS_11B)
622 u1bAIFS = aSifsTime + (2 * pmlmeinfo->slotTime);
624 /* <Roger_EXP> Temporary removed, 2008.06.20. */
625 rtl8723au_write8(padapter, REG_EDCA_VO_PARAM, u1bAIFS);
626 rtl8723au_write8(padapter, REG_EDCA_VI_PARAM, u1bAIFS);
627 rtl8723au_write8(padapter, REG_EDCA_BE_PARAM, u1bAIFS);
628 rtl8723au_write8(padapter, REG_EDCA_BK_PARAM, u1bAIFS);
632 void rtl8723a_ack_preamble(struct rtw_adapter *padapter, u8 bShortPreamble)
634 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
637 /* Joseph marked out for Netgear 3500 TKIP
638 channel 7 issue.(Temporarily) */
639 regTmp = (pHalData->nCur40MhzPrimeSC) << 5;
643 rtl8723au_write8(padapter, REG_RRSR + 2, regTmp);
646 void rtl8723a_set_sec_cfg(struct rtw_adapter *padapter, u8 sec)
648 rtl8723au_write8(padapter, REG_SECCFG, sec);
651 void rtl8723a_cam_empty_entry(struct rtw_adapter *padapter, u8 ucIndex)
656 u32 ulEncAlgo = CAM_AES;
658 for (i = 0; i < CAM_CONTENT_COUNT; i++) {
659 /* filled id in CAM config 2 byte */
661 ulContent |= (ucIndex & 0x03) |
662 ((u16) (ulEncAlgo) << 2);
663 /* ulContent |= CAM_VALID; */
667 /* polling bit, and No Write enable, and address */
668 ulCommand = CAM_CONTENT_COUNT * ucIndex + i;
669 ulCommand = ulCommand | CAM_POLLINIG | CAM_WRITE;
670 /* write content 0 is equall to mark invalid */
672 rtl8723au_write32(padapter, WCAMI, ulContent);
673 /* RT_TRACE(COMP_SEC, DBG_LOUD,
674 ("rtl8723a_cam_empty_entry(): WRITE A4: %lx \n",
677 rtl8723au_write32(padapter, RWCAM, ulCommand);
678 /* RT_TRACE(COMP_SEC, DBG_LOUD,
679 ("rtl8723a_cam_empty_entry(): WRITE A0: %lx \n",
684 void rtl8723a_cam_invalid_all(struct rtw_adapter *padapter)
686 rtl8723au_write32(padapter, RWCAM, BIT(31) | BIT(30));
689 void rtl8723a_cam_write(struct rtw_adapter *padapter,
690 u8 entry, u16 ctrl, const u8 *mac, const u8 *key)
693 unsigned int i, val, addr;
698 for (j = 5; j >= 0; j--) {
701 val = ctrl | (mac[0] << 16) | (mac[1] << 24);
704 val = mac[2] | (mac[3] << 8) |
705 (mac[4] << 16) | (mac[5] << 24);
709 val = key[i] | (key[i+1] << 8) |
710 (key[i+2] << 16) | (key[i+3] << 24);
714 rtl8723au_write32(padapter, WCAMI, val);
715 cmd = CAM_POLLINIG | CAM_WRITE | (addr + j);
716 rtl8723au_write32(padapter, RWCAM, cmd);
718 /* DBG_8723A("%s => cam write: %x, %x\n", __func__, cmd, val);*/
722 void rtl8723a_fifo_cleanup(struct rtw_adapter *padapter)
724 #define RW_RELEASE_EN BIT(18)
725 #define RXDMA_IDLE BIT(17)
727 struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
731 rtl8723au_write8(padapter, REG_TXPAUSE, 0xff);
734 padapter->xmitpriv.nqos_ssn = rtl8723au_read16(padapter, REG_NQOS_SEQ);
736 if (pwrpriv->bkeepfwalive != true) {
740 v32 = rtl8723au_read32(padapter, REG_RXPKT_NUM);
741 v32 |= RW_RELEASE_EN;
742 rtl8723au_write32(padapter, REG_RXPKT_NUM, v32);
744 v32 = rtl8723au_read32(padapter,
745 REG_RXPKT_NUM) & RXDMA_IDLE;
750 DBG_8723A("Stop RX DMA failed......\n");
754 rtl8723au_write16(padapter, REG_RQPN_NPQ, 0);
755 rtl8723au_write32(padapter, REG_RQPN, 0x80000000);
760 void rtl8723a_bcn_valid(struct rtw_adapter *padapter)
762 /* BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2,
763 write 1 to clear, Clear by sw */
764 rtl8723au_write8(padapter, REG_TDECTRL + 2,
765 rtl8723au_read8(padapter, REG_TDECTRL + 2) | BIT(0));
768 bool rtl8723a_get_bcn_valid(struct rtw_adapter *padapter)
772 retval = (rtl8723au_read8(padapter, REG_TDECTRL + 2) & BIT(0)) ? true : false;
777 void rtl8723a_set_beacon_interval(struct rtw_adapter *padapter, u16 interval)
779 rtl8723au_write16(padapter, REG_BCN_INTERVAL, interval);
782 void rtl8723a_set_resp_sifs(struct rtw_adapter *padapter,
783 u8 r2t1, u8 r2t2, u8 t2t1, u8 t2t2)
785 /* SIFS_Timer = 0x0a0a0808; */
786 /* RESP_SIFS for CCK */
787 /* SIFS_T2T_CCK (0x08) */
788 rtl8723au_write8(padapter, REG_R2T_SIFS, r2t1);
789 /* SIFS_R2T_CCK(0x08) */
790 rtl8723au_write8(padapter, REG_R2T_SIFS + 1, r2t2);
791 /* RESP_SIFS for OFDM */
792 /* SIFS_T2T_OFDM (0x0a) */
793 rtl8723au_write8(padapter, REG_T2T_SIFS, t2t1);
794 /* SIFS_R2T_OFDM(0x0a) */
795 rtl8723au_write8(padapter, REG_T2T_SIFS + 1, t2t2);
798 void rtl8723a_set_ac_param_vo(struct rtw_adapter *padapter, u32 vo)
800 rtl8723au_write32(padapter, REG_EDCA_VO_PARAM, vo);
803 void rtl8723a_set_ac_param_vi(struct rtw_adapter *padapter, u32 vi)
805 rtl8723au_write32(padapter, REG_EDCA_VI_PARAM, vi);
808 void rtl8723a_set_ac_param_be(struct rtw_adapter *padapter, u32 be)
810 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
812 pHalData->AcParam_BE = be;
813 rtl8723au_write32(padapter, REG_EDCA_BE_PARAM, be);
816 void rtl8723a_set_ac_param_bk(struct rtw_adapter *padapter, u32 bk)
818 rtl8723au_write32(padapter, REG_EDCA_BK_PARAM, bk);
821 void rtl8723a_set_rxdma_agg_pg_th(struct rtw_adapter *padapter, u8 val)
823 rtl8723au_write8(padapter, REG_RXDMA_AGG_PG_TH, val);
826 void rtl8723a_set_nav_upper(struct rtw_adapter *padapter, u32 usNavUpper)
828 if (usNavUpper > HAL_8723A_NAV_UPPER_UNIT * 0xFF) {
829 RT_TRACE(_module_hal_init_c_, _drv_notice_,
830 ("The setting value (0x%08X us) of NAV_UPPER "
831 "is larger than (%d * 0xFF)!!!\n",
832 usNavUpper, HAL_8723A_NAV_UPPER_UNIT));
836 /* The value of ((usNavUpper + HAL_8723A_NAV_UPPER_UNIT - 1) /
837 HAL_8723A_NAV_UPPER_UNIT) */
838 /* is getting the upper integer. */
839 usNavUpper = (usNavUpper + HAL_8723A_NAV_UPPER_UNIT - 1) /
840 HAL_8723A_NAV_UPPER_UNIT;
841 rtl8723au_write8(padapter, REG_NAV_UPPER, (u8) usNavUpper);
844 void rtl8723a_set_initial_gain(struct rtw_adapter *padapter, u32 rx_gain)
846 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
847 struct dig_t *pDigTable = &pHalData->odmpriv.DM_DigTable;
849 if (rx_gain == 0xff) /* restore rx gain */
850 ODM_Write_DIG23a(&pHalData->odmpriv, pDigTable->BackupIGValue);
852 pDigTable->BackupIGValue = pDigTable->CurIGValue;
853 ODM_Write_DIG23a(&pHalData->odmpriv, rx_gain);
857 void rtl8723a_odm_support_ability_restore(struct rtw_adapter *padapter)
859 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
861 pHalData->odmpriv.SupportAbility = pHalData->odmpriv.BK_SupportAbility;
864 void rtl8723a_odm_support_ability_backup(struct rtw_adapter *padapter)
866 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
868 pHalData->odmpriv.BK_SupportAbility = pHalData->odmpriv.SupportAbility;
871 void rtl8723a_odm_support_ability_set(struct rtw_adapter *padapter, u32 val)
873 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
875 if (val == DYNAMIC_ALL_FUNC_ENABLE) {
876 pHalData->dmpriv.DMFlag = pHalData->dmpriv.InitDMFlag;
877 pHalData->odmpriv.SupportAbility = pHalData->dmpriv.InitODMFlag;
879 pHalData->odmpriv.SupportAbility |= val;
883 void rtl8723a_odm_support_ability_clr(struct rtw_adapter *padapter, u32 val)
885 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
887 pHalData->odmpriv.SupportAbility &= val;
890 void rtl8723a_set_rpwm(struct rtw_adapter *padapter, u8 val)
892 rtl8723au_write8(padapter, REG_USB_HRPWM, val);
895 u8 rtl8723a_get_rf_type(struct rtw_adapter *padapter)
897 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
899 return pHalData->rf_type;
902 bool rtl8723a_get_fwlps_rf_on(struct rtw_adapter *padapter)
907 /* When we halt NIC, we should check if FW LPS is leave. */
909 if ((padapter->bSurpriseRemoved == true) ||
910 (padapter->pwrctrlpriv.rf_pwrstate == rf_off)) {
911 /* If it is in HW/SW Radio OFF or IPS state, we do
912 not check Fw LPS Leave, because Fw is unload. */
915 valRCR = rtl8723au_read32(padapter, REG_RCR);
916 if (valRCR & 0x00070000)
925 bool rtl8723a_chk_hi_queue_empty(struct rtw_adapter *padapter)
929 hgq = rtl8723au_read32(padapter, REG_HGQ_INFORMATION);
931 return ((hgq & 0x0000ff00) == 0) ? true : false;