drivers/staging/rtl8723au/hal/odm.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  ******************************************************************************/
  15
  16 #include "odm_precomp.h"
  17 #include "usb_ops_linux.h"
  18
  19 static const u16 dB_Invert_Table[8][12] = {
  20         {1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4},
  21         {4, 5, 6, 6, 7, 8, 9, 10, 11, 13, 14, 16},
  22         {18, 20, 22, 25, 28, 32, 35, 40, 45, 50, 56, 63},
  23         {71, 79, 89, 100, 112, 126, 141, 158, 178, 200, 224, 251},
  24         {282, 316, 355, 398, 447, 501, 562, 631, 708, 794, 891, 1000},
  25         {1122, 1259, 1413, 1585, 1778, 1995, 2239, 2512, 2818, 3162, 3548, 3981},
  26         {4467, 5012, 5623, 6310, 7079, 7943, 8913, 10000, 11220, 12589, 14125, 15849},
  27         {17783, 19953, 22387, 25119, 28184, 31623, 35481, 39811, 44668, 50119, 56234, 65535}
  28 };
  29
  30 static u32 EDCAParam[HT_IOT_PEER_MAX][3] = {          /*  UL                    DL */
  31         {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 0:unknown AP */
  32         {0xa44f, 0x5ea44f, 0x5e431c}, /*  1:realtek AP */
  33         {0x5ea42b, 0x5ea42b, 0x5ea42b}, /*  2:unknown AP => realtek_92SE */
  34         {0x5ea32b, 0x5ea42b, 0x5e4322}, /*  3:broadcom AP */
  35         {0x5ea422, 0x00a44f, 0x00a44f}, /*  4:ralink AP */
  36         {0x5ea322, 0x00a630, 0x00a44f}, /*  5:atheros AP */
  37         {0x5e4322, 0x5e4322, 0x5e4322},/*  6:cisco AP */
  38         {0x5ea44f, 0x00a44f, 0x5ea42b}, /*  8:marvell AP */
  39         {0x5ea42b, 0x5ea42b, 0x5ea42b}, /*  10:unknown AP => 92U AP */
  40         {0x5ea42b, 0xa630, 0x5e431c}, /*  11:airgocap AP */
  41 };
  42
  43 /*  EDCA Paramter for AP/ADSL   by Mingzhi 2011-11-22 */
  44
  45 /*  Global var */
  46 u32 OFDMSwingTable23A[OFDM_TABLE_SIZE_92D] = {
  47         0x7f8001fe, /*  0, +6.0dB */
  48         0x788001e2, /*  1, +5.5dB */
  49         0x71c001c7, /*  2, +5.0dB */
  50         0x6b8001ae, /*  3, +4.5dB */
  51         0x65400195, /*  4, +4.0dB */
  52         0x5fc0017f, /*  5, +3.5dB */
  53         0x5a400169, /*  6, +3.0dB */
  54         0x55400155, /*  7, +2.5dB */
  55         0x50800142, /*  8, +2.0dB */
  56         0x4c000130, /*  9, +1.5dB */
  57         0x47c0011f, /*  10, +1.0dB */
  58         0x43c0010f, /*  11, +0.5dB */
  59         0x40000100, /*  12, +0dB */
  60         0x3c8000f2, /*  13, -0.5dB */
  61         0x390000e4, /*  14, -1.0dB */
  62         0x35c000d7, /*  15, -1.5dB */
  63         0x32c000cb, /*  16, -2.0dB */
  64         0x300000c0, /*  17, -2.5dB */
  65         0x2d4000b5, /*  18, -3.0dB */
  66         0x2ac000ab, /*  19, -3.5dB */
  67         0x288000a2, /*  20, -4.0dB */
  68         0x26000098, /*  21, -4.5dB */
  69         0x24000090, /*  22, -5.0dB */
  70         0x22000088, /*  23, -5.5dB */
  71         0x20000080, /*  24, -6.0dB */
  72         0x1e400079, /*  25, -6.5dB */
  73         0x1c800072, /*  26, -7.0dB */
  74         0x1b00006c, /*  27. -7.5dB */
  75         0x19800066, /*  28, -8.0dB */
  76         0x18000060, /*  29, -8.5dB */
  77         0x16c0005b, /*  30, -9.0dB */
  78         0x15800056, /*  31, -9.5dB */
  79         0x14400051, /*  32, -10.0dB */
  80         0x1300004c, /*  33, -10.5dB */
  81         0x12000048, /*  34, -11.0dB */
  82         0x11000044, /*  35, -11.5dB */
  83         0x10000040, /*  36, -12.0dB */
  84         0x0f00003c,/*  37, -12.5dB */
  85         0x0e400039,/*  38, -13.0dB */
  86         0x0d800036,/*  39, -13.5dB */
  87         0x0cc00033,/*  40, -14.0dB */
  88         0x0c000030,/*  41, -14.5dB */
  89         0x0b40002d,/*  42, -15.0dB */
  90 };
  91
  92 u8 CCKSwingTable_Ch1_Ch1323A[CCK_TABLE_SIZE][8] = {
  93         {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /*  0, +0dB */
  94         {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /*  1, -0.5dB */
  95         {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /*  2, -1.0dB */
  96         {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /*  3, -1.5dB */
  97         {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /*  4, -2.0dB */
  98         {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /*  5, -2.5dB */
  99         {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /*  6, -3.0dB */
 100         {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /*  7, -3.5dB */
 101         {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /*  8, -4.0dB */
 102         {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /*  9, -4.5dB */
 103         {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /*  10, -5.0dB */
 104         {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /*  11, -5.5dB */
 105         {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /*  12, -6.0dB */
 106         {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /*  13, -6.5dB */
 107         {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /*  14, -7.0dB */
 108         {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /*  15, -7.5dB */
 109         {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /*  16, -8.0dB */
 110         {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /*  17, -8.5dB */
 111         {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /*  18, -9.0dB */
 112         {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /*  19, -9.5dB */
 113         {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /*  20, -10.0dB */
 114         {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /*  21, -10.5dB */
 115         {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /*  22, -11.0dB */
 116         {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /*  23, -11.5dB */
 117         {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /*  24, -12.0dB */
 118         {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /*  25, -12.5dB */
 119         {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /*  26, -13.0dB */
 120         {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /*  27, -13.5dB */
 121         {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /*  28, -14.0dB */
 122         {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /*  29, -14.5dB */
 123         {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /*  30, -15.0dB */
 124         {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /*  31, -15.5dB */
 125         {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}        /*  32, -16.0dB */
 126 };
 127
 128 u8 CCKSwingTable_Ch1423A[CCK_TABLE_SIZE][8] = {
 129         {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /*  0, +0dB */
 130         {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /*  1, -0.5dB */
 131         {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /*  2, -1.0dB */
 132         {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /*  3, -1.5dB */
 133         {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /*  4, -2.0dB */
 134         {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /*  5, -2.5dB */
 135         {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /*  6, -3.0dB */
 136         {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /*  7, -3.5dB */
 137         {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /*  8, -4.0dB */
 138         {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /*  9, -4.5dB */
 139         {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /*  10, -5.0dB */
 140         {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /*  11, -5.5dB */
 141         {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /*  12, -6.0dB */
 142         {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /*  13, -6.5dB */
 143         {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /*  14, -7.0dB */
 144         {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /*  15, -7.5dB */
 145         {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /*  16, -8.0dB */
 146         {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /*  17, -8.5dB */
 147         {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /*  18, -9.0dB */
 148         {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /*  19, -9.5dB */
 149         {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /*  20, -10.0dB */
 150         {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /*  21, -10.5dB */
 151         {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /*  22, -11.0dB */
 152         {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /*  23, -11.5dB */
 153         {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /*  24, -12.0dB */
 154         {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /*  25, -12.5dB */
 155         {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /*  26, -13.0dB */
 156         {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /*  27, -13.5dB */
 157         {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /*  28, -14.0dB */
 158         {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /*  29, -14.5dB */
 159         {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /*  30, -15.0dB */
 160         {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /*  31, -15.5dB */
 161         {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}        /*  32, -16.0dB */
 162 };
 163
 164 /*  Local Function predefine. */
 165
 166 /* START------------COMMON INFO RELATED--------------- */
 167 void odm_CommonInfoSelfInit23a(struct dm_odm_t *pDM_Odm);
 168
 169 static void odm_CommonInfoSelfUpdate(struct hal_data_8723a *pHalData);
 170
 171 void odm_CmnInfoInit_Debug23a(struct dm_odm_t *pDM_Odm);
 172
 173 void odm_CmnInfoUpdate_Debug23a(struct dm_odm_t *pDM_Odm);
 174
 175 /* START---------------DIG--------------------------- */
 176 void odm_FalseAlarmCounterStatistics23a(struct dm_odm_t *pDM_Odm);
 177
 178 void odm_DIG23aInit(struct dm_odm_t *pDM_Odm);
 179
 180 void odm_DIG23a(struct rtw_adapter *adapter);
 181
 182 void odm_CCKPacketDetectionThresh23a(struct dm_odm_t *pDM_Odm);
 183 /* END---------------DIG--------------------------- */
 184
 185 /* START-------BB POWER SAVE----------------------- */
 186 void odm23a_DynBBPSInit(struct dm_odm_t *pDM_Odm);
 187
 188 void odm_DynamicBBPowerSaving23a(struct dm_odm_t *pDM_Odm);
 189
 190 /* END---------BB POWER SAVE----------------------- */
 191
 192 void odm_DynamicTxPower23aInit(struct dm_odm_t *pDM_Odm);
 193
 194 void odm_RSSIMonitorCheck23aCE(struct dm_odm_t *pDM_Odm);
 195 void odm_RSSIMonitorCheck23a(struct dm_odm_t *pDM_Odm);
 196 void odm_DynamicTxPower23a(struct dm_odm_t *pDM_Odm);
 197
 198 void odm_RefreshRateAdaptiveMask23a(struct dm_odm_t *pDM_Odm);
 199
 200 void ODM_TXPowerTrackingCheck23a(struct dm_odm_t *pDM_Odm);
 201
 202 void odm_RateAdaptiveMaskInit23a(struct dm_odm_t *pDM_Odm);
 203
 204 void odm_TXPowerTrackingThermalMeterInit23a(struct dm_odm_t *pDM_Odm);
 205
 206 void odm_TXPowerTrackingInit23a(struct dm_odm_t *pDM_Odm);
 207
 208 void odm_TXPowerTrackingCheckCE23a(struct dm_odm_t *pDM_Odm);
 209
 210 static void odm_EdcaTurboCheck23a(struct dm_odm_t *pDM_Odm);
 211 static void ODM_EdcaTurboInit23a(struct dm_odm_t *pDM_Odm);
 212
 213 #define         RxDefaultAnt1           0x65a9
 214 #define RxDefaultAnt2           0x569a
 215
 216 bool odm_StaDefAntSel(struct dm_odm_t *pDM_Odm,
 217         u32 OFDM_Ant1_Cnt,
 218         u32 OFDM_Ant2_Cnt,
 219         u32 CCK_Ant1_Cnt,
 220         u32 CCK_Ant2_Cnt,
 221         u8 *pDefAnt
 222         );
 223
 224 void odm_SetRxIdleAnt(struct dm_odm_t *pDM_Odm,
 225         u8 Ant,
 226         bool   bDualPath
 227 );
 228
 229 /* 3 Export Interface */
 230
 231 /*  2011/09/21 MH Add to describe different team necessary resource allocate?? */
 232 void ODM23a_DMInit(struct dm_odm_t *pDM_Odm)
 233 {
 234         /* For all IC series */
 235         odm_CommonInfoSelfInit23a(pDM_Odm);
 236         odm_CmnInfoInit_Debug23a(pDM_Odm);
 237         odm_DIG23aInit(pDM_Odm);
 238         odm_RateAdaptiveMaskInit23a(pDM_Odm);
 239
 240         odm23a_DynBBPSInit(pDM_Odm);
 241         odm_DynamicTxPower23aInit(pDM_Odm);
 242         odm_TXPowerTrackingInit23a(pDM_Odm);
 243         ODM_EdcaTurboInit23a(pDM_Odm);
 244 }
 245
 246 /*  2011/09/20 MH This is the entry pointer for all team to execute HW out source DM. */
 247 /*  You can not add any dummy function here, be care, you can only use DM structure */
 248 /*  to perform any new ODM_DM. */
 249 void ODM_DMWatchdog23a(struct rtw_adapter *adapter)
 250 {
 251         struct hal_data_8723a *pHalData = GET_HAL_DATA(adapter);
 252         struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
 253         struct pwrctrl_priv *pwrctrlpriv = &adapter->pwrctrlpriv;
 254
 255         /* 2012.05.03 Luke: For all IC series */
 256         odm_CmnInfoUpdate_Debug23a(pDM_Odm);
 257         odm_CommonInfoSelfUpdate(pHalData);
 258         odm_FalseAlarmCounterStatistics23a(pDM_Odm);
 259         odm_RSSIMonitorCheck23a(pDM_Odm);
 260
 261         /* 8723A or 8189ES platform */
 262         /* NeilChen--2012--08--24-- */
 263         /* Fix Leave LPS issue */
 264         if ((pDM_Odm->Adapter->pwrctrlpriv.pwr_mode != PS_MODE_ACTIVE) &&/*  in LPS mode */
 265             (pDM_Odm->SupportICType & ODM_RTL8723A)) {
 266                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("----Step1: odm_DIG23a is in LPS mode\n"));
 267                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("---Step2: 8723AS is in LPS mode\n"));
 268                         odm_DIG23abyRSSI_LPS(pDM_Odm);
 269         } else {
 270                 odm_DIG23a(adapter);
 271         }
 272
 273         odm_CCKPacketDetectionThresh23a(pDM_Odm);
 274
 275         if (pwrctrlpriv->bpower_saving)
 276                 return;
 277
 278         odm_RefreshRateAdaptiveMask23a(pDM_Odm);
 279
 280         odm_DynamicBBPowerSaving23a(pDM_Odm);
 281
 282         ODM_TXPowerTrackingCheck23a(pDM_Odm);
 283         odm_EdcaTurboCheck23a(pDM_Odm);
 284
 285         odm_dtc(pDM_Odm);
 286 }
 287
 288 /*  */
 289 /*  Init /.. Fixed HW value. Only init time. */
 290 /*  */
 291 void ODM_CmnInfoInit23a(struct dm_odm_t *pDM_Odm,
 292                 enum odm_cmninfo CmnInfo,
 293                 u32 Value
 294         )
 295 {
 296         /* ODM_RT_TRACE(pDM_Odm,); */
 297
 298         /*  */
 299         /*  This section is used for init value */
 300         /*  */
 301         switch  (CmnInfo) {
 302         /*  Fixed ODM value. */
 303         case    ODM_CMNINFO_PLATFORM:
 304                 break;
 305         case    ODM_CMNINFO_INTERFACE:
 306                 pDM_Odm->SupportInterface = (u8)Value;
 307                 break;
 308         case    ODM_CMNINFO_MP_TEST_CHIP:
 309                 pDM_Odm->bIsMPChip = (u8)Value;
 310                 break;
 311         case    ODM_CMNINFO_IC_TYPE:
 312                 pDM_Odm->SupportICType = Value;
 313                 break;
 314         case    ODM_CMNINFO_CUT_VER:
 315                 pDM_Odm->CutVersion = (u8)Value;
 316                 break;
 317         case    ODM_CMNINFO_FAB_VER:
 318                 pDM_Odm->FabVersion = (u8)Value;
 319                 break;
 320         case    ODM_CMNINFO_BOARD_TYPE:
 321                 pDM_Odm->BoardType = (u8)Value;
 322                 break;
 323         case    ODM_CMNINFO_EXT_LNA:
 324                 pDM_Odm->ExtLNA = (u8)Value;
 325                 break;
 326         case    ODM_CMNINFO_EXT_PA:
 327                 pDM_Odm->ExtPA = (u8)Value;
 328                 break;
 329         case    ODM_CMNINFO_EXT_TRSW:
 330                 pDM_Odm->ExtTRSW = (u8)Value;
 331                 break;
 332         case    ODM_CMNINFO_PATCH_ID:
 333                 pDM_Odm->PatchID = (u8)Value;
 334                 break;
 335         case    ODM_CMNINFO_BINHCT_TEST:
 336                 pDM_Odm->bInHctTest = (bool)Value;
 337                 break;
 338         case    ODM_CMNINFO_BWIFI_TEST:
 339                 pDM_Odm->bWIFITest = (bool)Value;
 340                 break;
 341         case    ODM_CMNINFO_SMART_CONCURRENT:
 342                 pDM_Odm->bDualMacSmartConcurrent = (bool)Value;
 343                 break;
 344         /* To remove the compiler warning, must add an empty default statement to handle the other values. */
 345         default:
 346                 /* do nothing */
 347                 break;
 348         }
 349
 350         /*  */
 351         /*  Tx power tracking BB swing table. */
 352         /*  The base index = 12. +((12-n)/2)dB 13~?? = decrease tx pwr by -((n-12)/2)dB */
 353         /*  */
 354         pDM_Odm->BbSwingIdxOfdm                 = 12; /*  Set defalut value as index 12. */
 355         pDM_Odm->BbSwingIdxOfdmCurrent  = 12;
 356         pDM_Odm->BbSwingFlagOfdm                = false;
 357
 358 }
 359
 360 void ODM_CmnInfoPtrArrayHook23a(struct dm_odm_t *pDM_Odm, enum odm_cmninfo CmnInfo,
 361                                 u16 Index, void *pValue)
 362 {
 363         /*  Hook call by reference pointer. */
 364         switch  (CmnInfo) {
 365         /*  Dynamic call by reference pointer. */
 366         case    ODM_CMNINFO_STA_STATUS:
 367                 pDM_Odm->pODM_StaInfo[Index] = (struct sta_info *)pValue;
 368                 break;
 369         /* To remove the compiler warning, must add an empty default statement to handle the other values. */
 370         default:
 371                 /* do nothing */
 372                 break;
 373         }
 374 }
 375
 376 /*  Update Band/CHannel/.. The values are dynamic but non-per-packet. */
 377 void ODM_CmnInfoUpdate23a(struct dm_odm_t *pDM_Odm, u32 CmnInfo, u64 Value)
 378 {
 379         /*  This init variable may be changed in run time. */
 380         switch  (CmnInfo) {
 381         case    ODM_CMNINFO_WIFI_DIRECT:
 382                 pDM_Odm->bWIFI_Direct = (bool)Value;
 383                 break;
 384         case    ODM_CMNINFO_WIFI_DISPLAY:
 385                 pDM_Odm->bWIFI_Display = (bool)Value;
 386                 break;
 387         case    ODM_CMNINFO_LINK:
 388                 pDM_Odm->bLinked = (bool)Value;
 389                 break;
 390         case    ODM_CMNINFO_RSSI_MIN:
 391                 pDM_Odm->RSSI_Min = (u8)Value;
 392                 break;
 393         case    ODM_CMNINFO_DBG_COMP:
 394                 pDM_Odm->DebugComponents = Value;
 395                 break;
 396         case    ODM_CMNINFO_DBG_LEVEL:
 397                 pDM_Odm->DebugLevel = (u32)Value;
 398                 break;
 399         case    ODM_CMNINFO_RA_THRESHOLD_HIGH:
 400                 pDM_Odm->RateAdaptive.HighRSSIThresh = (u8)Value;
 401                 break;
 402         case    ODM_CMNINFO_RA_THRESHOLD_LOW:
 403                 pDM_Odm->RateAdaptive.LowRSSIThresh = (u8)Value;
 404                 break;
 405         }
 406
 407 }
 408
 409 void odm_CommonInfoSelfInit23a(struct dm_odm_t *pDM_Odm
 410         )
 411 {
 412         pDM_Odm->bCckHighPower =
 413                 (bool) ODM_GetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter2, BIT(9));
 414         pDM_Odm->RFPathRxEnable =
 415                 (u8) ODM_GetBBReg(pDM_Odm, rOFDM0_TRxPathEnable, 0x0F);
 416
 417         ODM_InitDebugSetting23a(pDM_Odm);
 418 }
 419
 420 static void odm_CommonInfoSelfUpdate(struct hal_data_8723a *pHalData)
 421 {
 422         struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
 423         struct sta_info *pEntry;
 424         u8 EntryCnt = 0;
 425         u8 i;
 426
 427         if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40) {
 428                 if (pHalData->nCur40MhzPrimeSC == 1)
 429                         pDM_Odm->ControlChannel = pHalData->CurrentChannel - 2;
 430                 else if (pHalData->nCur40MhzPrimeSC == 2)
 431                         pDM_Odm->ControlChannel = pHalData->CurrentChannel + 2;
 432         } else {
 433                 pDM_Odm->ControlChannel = pHalData->CurrentChannel;
 434         }
 435
 436         for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
 437                 pEntry = pDM_Odm->pODM_StaInfo[i];
 438                 if (pEntry)
 439                         EntryCnt++;
 440         }
 441         if (EntryCnt == 1)
 442                 pDM_Odm->bOneEntryOnly = true;
 443         else
 444                 pDM_Odm->bOneEntryOnly = false;
 445 }
 446
 447 void odm_CmnInfoInit_Debug23a(struct dm_odm_t *pDM_Odm)
 448 {
 449         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoInit_Debug23a ==>\n"));
 450         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportAbility = 0x%x\n", pDM_Odm->SupportAbility));
 451         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportInterface =%d\n", pDM_Odm->SupportInterface));
 452         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportICType = 0x%x\n", pDM_Odm->SupportICType));
 453         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("CutVersion =%d\n", pDM_Odm->CutVersion));
 454         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("FabVersion =%d\n", pDM_Odm->FabVersion));
 455         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("BoardType =%d\n", pDM_Odm->BoardType));
 456         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtLNA =%d\n", pDM_Odm->ExtLNA));
 457         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtPA =%d\n", pDM_Odm->ExtPA));
 458         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtTRSW =%d\n", pDM_Odm->ExtTRSW));
 459         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("PatchID =%d\n", pDM_Odm->PatchID));
 460         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bInHctTest =%d\n", pDM_Odm->bInHctTest));
 461         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFITest =%d\n", pDM_Odm->bWIFITest));
 462         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bDualMacSmartConcurrent =%d\n", pDM_Odm->bDualMacSmartConcurrent));
 463
 464 }
 465
 466 void odm_CmnInfoUpdate_Debug23a(struct dm_odm_t *pDM_Odm)
 467 {
 468         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoUpdate_Debug23a ==>\n"));
 469         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Direct =%d\n", pDM_Odm->bWIFI_Direct));
 470         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Display =%d\n", pDM_Odm->bWIFI_Display));
 471         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bLinked =%d\n", pDM_Odm->bLinked));
 472         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RSSI_Min =%d\n", pDM_Odm->RSSI_Min));
 473 }
 474
 475 void ODM_Write_DIG23a(struct dm_odm_t *pDM_Odm,
 476         u8 CurrentIGI
 477         )
 478 {
 479         struct dig_t *pDM_DigTable = &pDM_Odm->DM_DigTable;
 480
 481         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("ODM_REG(IGI_A, pDM_Odm) = 0x%x, ODM_BIT(IGI, pDM_Odm) = 0x%x \n",
 482                 ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm)));
 483
 484         if (pDM_DigTable->CurIGValue != CurrentIGI) {
 485                 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI);
 486                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("CurrentIGI(0x%02x). \n", CurrentIGI));
 487                 pDM_DigTable->CurIGValue = CurrentIGI;
 488         }
 489         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
 490                      ("ODM_Write_DIG23a():CurrentIGI = 0x%x \n", CurrentIGI));
 491 }
 492
 493 /* Need LPS mode for CE platform --2012--08--24--- */
 494 /* 8723AS/8189ES */
 495 void odm_DIG23abyRSSI_LPS(struct dm_odm_t *pDM_Odm)
 496 {
 497         struct rtw_adapter *pAdapter = pDM_Odm->Adapter;
 498         struct false_alarm_stats *pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
 499         u8 RSSI_Lower = DM_DIG_MIN_NIC;   /* 0x1E or 0x1C */
 500         u8 bFwCurrentInPSMode = false;
 501         u8 CurrentIGI = pDM_Odm->RSSI_Min;
 502
 503         if (!(pDM_Odm->SupportICType & ODM_RTL8723A))
 504                 return;
 505
 506         CurrentIGI = CurrentIGI+RSSI_OFFSET_DIG;
 507         bFwCurrentInPSMode = pAdapter->pwrctrlpriv.bFwCurrentInPSMode;
 508
 509         /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG_LPS, ODM_DBG_LOUD, ("odm_DIG23a() ==>\n")); */
 510
 511         /*  Using FW PS mode to make IGI */
 512         if (bFwCurrentInPSMode) {
 513                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("---Neil---odm_DIG23a is in LPS mode\n"));
 514                 /* Adjust by  FA in LPS MODE */
 515                 if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2_LPS)
 516                         CurrentIGI = CurrentIGI+2;
 517                 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1_LPS)
 518                         CurrentIGI = CurrentIGI+1;
 519                 else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0_LPS)
 520                         CurrentIGI = CurrentIGI-1;
 521         } else {
 522                 CurrentIGI = RSSI_Lower;
 523         }
 524
 525         /* Lower bound checking */
 526
 527         /* RSSI Lower bound check */
 528         if ((pDM_Odm->RSSI_Min-10) > DM_DIG_MIN_NIC)
 529                 RSSI_Lower = (pDM_Odm->RSSI_Min-10);
 530         else
 531                 RSSI_Lower = DM_DIG_MIN_NIC;
 532
 533         /* Upper and Lower Bound checking */
 534          if (CurrentIGI > DM_DIG_MAX_NIC)
 535                 CurrentIGI = DM_DIG_MAX_NIC;
 536          else if (CurrentIGI < RSSI_Lower)
 537                 CurrentIGI = RSSI_Lower;
 538
 539         ODM_Write_DIG23a(pDM_Odm, CurrentIGI);/* ODM_Write_DIG23a(pDM_Odm, pDM_DigTable->CurIGValue); */
 540
 541 }
 542
 543 void odm_DIG23aInit(struct dm_odm_t *pDM_Odm)
 544 {
 545         struct dig_t *pDM_DigTable = &pDM_Odm->DM_DigTable;
 546
 547         pDM_DigTable->CurIGValue = (u8) ODM_GetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm));
 548         pDM_DigTable->RssiLowThresh     = DM_DIG_THRESH_LOW;
 549         pDM_DigTable->RssiHighThresh    = DM_DIG_THRESH_HIGH;
 550         pDM_DigTable->FALowThresh       = DM_FALSEALARM_THRESH_LOW;
 551         pDM_DigTable->FAHighThresh      = DM_FALSEALARM_THRESH_HIGH;
 552         if (pDM_Odm->BoardType == ODM_BOARD_HIGHPWR) {
 553                 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
 554                 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC;
 555         } else {
 556                 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
 557                 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC;
 558         }
 559         pDM_DigTable->BackoffVal = DM_DIG_BACKOFF_DEFAULT;
 560         pDM_DigTable->BackoffVal_range_max = DM_DIG_BACKOFF_MAX;
 561         pDM_DigTable->BackoffVal_range_min = DM_DIG_BACKOFF_MIN;
 562         pDM_DigTable->PreCCK_CCAThres = 0xFF;
 563         pDM_DigTable->CurCCK_CCAThres = 0x83;
 564         pDM_DigTable->ForbiddenIGI = DM_DIG_MIN_NIC;
 565         pDM_DigTable->LargeFAHit = 0;
 566         pDM_DigTable->Recover_cnt = 0;
 567         pDM_DigTable->DIG_Dynamic_MIN_0 = DM_DIG_MIN_NIC;
 568         pDM_DigTable->DIG_Dynamic_MIN_1 = DM_DIG_MIN_NIC;
 569         pDM_DigTable->bMediaConnect_0 = false;
 570         pDM_DigTable->bMediaConnect_1 = false;
 571 }
 572
 573 void odm_DIG23a(struct rtw_adapter *adapter)
 574 {
 575         struct hal_data_8723a *pHalData = GET_HAL_DATA(adapter);
 576         struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
 577         struct dig_t *pDM_DigTable = &pDM_Odm->DM_DigTable;
 578         struct false_alarm_stats *pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
 579         u8 DIG_Dynamic_MIN;
 580         u8 DIG_MaxOfMin;
 581         bool FirstConnect, FirstDisConnect;
 582         u8 dm_dig_max, dm_dig_min;
 583         u8 CurrentIGI = pDM_DigTable->CurIGValue;
 584
 585         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a() ==>\n"));
 586         if (adapter->mlmepriv.bScanInProcess) {
 587                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a() Return: In Scan Progress \n"));
 588                 return;
 589         }
 590
 591         DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0;
 592         FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_0);
 593         FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0);
 594
 595         /* 1 Boundary Decision */
 596         if ((pDM_Odm->SupportICType & ODM_RTL8723A) &&
 597             ((pDM_Odm->BoardType == ODM_BOARD_HIGHPWR) || pDM_Odm->ExtLNA)) {
 598                 dm_dig_max = DM_DIG_MAX_NIC_HP;
 599                 dm_dig_min = DM_DIG_MIN_NIC_HP;
 600                 DIG_MaxOfMin = DM_DIG_MAX_AP_HP;
 601         } else {
 602                 dm_dig_max = DM_DIG_MAX_NIC;
 603                 dm_dig_min = DM_DIG_MIN_NIC;
 604                 DIG_MaxOfMin = DM_DIG_MAX_AP;
 605         }
 606
 607         if (pDM_Odm->bLinked) {
 608               /* 2 8723A Series, offset need to be 10 */
 609                 if (pDM_Odm->SupportICType == ODM_RTL8723A) {
 610                         /* 2 Upper Bound */
 611                         if ((pDM_Odm->RSSI_Min + 10) > DM_DIG_MAX_NIC)
 612                                 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
 613                         else if ((pDM_Odm->RSSI_Min + 10) < DM_DIG_MIN_NIC)
 614                                 pDM_DigTable->rx_gain_range_max = DM_DIG_MIN_NIC;
 615                         else
 616                                 pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 10;
 617
 618                         /* 2 If BT is Concurrent, need to set Lower Bound */
 619                         DIG_Dynamic_MIN = DM_DIG_MIN_NIC;
 620                 } else {
 621                         /* 2 Modify DIG upper bound */
 622                         if ((pDM_Odm->RSSI_Min + 20) > dm_dig_max)
 623                                 pDM_DigTable->rx_gain_range_max = dm_dig_max;
 624                         else if ((pDM_Odm->RSSI_Min + 20) < dm_dig_min)
 625                                 pDM_DigTable->rx_gain_range_max = dm_dig_min;
 626                         else
 627                                 pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 20;
 628
 629                         /* 2 Modify DIG lower bound */
 630                         if (pDM_Odm->bOneEntryOnly) {
 631                                 if (pDM_Odm->RSSI_Min < dm_dig_min)
 632                                         DIG_Dynamic_MIN = dm_dig_min;
 633                                 else if (pDM_Odm->RSSI_Min > DIG_MaxOfMin)
 634                                         DIG_Dynamic_MIN = DIG_MaxOfMin;
 635                                 else
 636                                         DIG_Dynamic_MIN = pDM_Odm->RSSI_Min;
 637                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
 638                                              ("odm_DIG23a() : bOneEntryOnly = true,  DIG_Dynamic_MIN = 0x%x\n",
 639                                              DIG_Dynamic_MIN));
 640                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
 641                                              ("odm_DIG23a() : pDM_Odm->RSSI_Min =%d\n",
 642                                              pDM_Odm->RSSI_Min));
 643                         } else {
 644                                 DIG_Dynamic_MIN = dm_dig_min;
 645                         }
 646                 }
 647         } else {
 648                 pDM_DigTable->rx_gain_range_max = dm_dig_max;
 649                 DIG_Dynamic_MIN = dm_dig_min;
 650                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a() : No Link\n"));
 651         }
 652
 653         /* 1 Modify DIG lower bound, deal with abnormally large false alarm */
 654         if (pFalseAlmCnt->Cnt_all > 10000) {
 655                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
 656                              ("dm_DIG(): Abnornally false alarm case. \n"));
 657
 658                 if (pDM_DigTable->LargeFAHit != 3)
 659                         pDM_DigTable->LargeFAHit++;
 660                 if (pDM_DigTable->ForbiddenIGI < CurrentIGI) {
 661                         pDM_DigTable->ForbiddenIGI = CurrentIGI;
 662                         pDM_DigTable->LargeFAHit = 1;
 663                 }
 664
 665                 if (pDM_DigTable->LargeFAHit >= 3) {
 666                         if ((pDM_DigTable->ForbiddenIGI+1) > pDM_DigTable->rx_gain_range_max)
 667                                 pDM_DigTable->rx_gain_range_min = pDM_DigTable->rx_gain_range_max;
 668                         else
 669                                 pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1);
 670                         pDM_DigTable->Recover_cnt = 3600; /* 3600 = 2hr */
 671                 }
 672         } else {
 673                 /* Recovery mechanism for IGI lower bound */
 674                 if (pDM_DigTable->Recover_cnt != 0) {
 675                         pDM_DigTable->Recover_cnt--;
 676                 } else {
 677                         if (pDM_DigTable->LargeFAHit < 3) {
 678                                 if ((pDM_DigTable->ForbiddenIGI - 1) < DIG_Dynamic_MIN) {
 679                                         pDM_DigTable->ForbiddenIGI = DIG_Dynamic_MIN; /* DM_DIG_MIN; */
 680                                         pDM_DigTable->rx_gain_range_min = DIG_Dynamic_MIN; /* DM_DIG_MIN; */
 681                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
 682                                                      ("odm_DIG23a(): Normal Case: At Lower Bound\n"));
 683                                 } else {
 684                                         pDM_DigTable->ForbiddenIGI--;
 685                                         pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1);
 686                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
 687                                                      ("odm_DIG23a(): Normal Case: Approach Lower Bound\n"));
 688                                 }
 689                         } else {
 690                                 pDM_DigTable->LargeFAHit = 0;
 691                         }
 692                 }
 693         }
 694         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): pDM_DigTable->LargeFAHit =%d\n", pDM_DigTable->LargeFAHit));
 695
 696         /* 1 Adjust initial gain by false alarm */
 697         if (pDM_Odm->bLinked) {
 698                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): DIG AfterLink\n"));
 699                 if (FirstConnect) {
 700                         CurrentIGI = pDM_Odm->RSSI_Min;
 701                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: First Connect\n"));
 702                 } else {
 703                         if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2)
 704                                 CurrentIGI = CurrentIGI + 4;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */
 705                         else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1)
 706                                 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */
 707                         else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0)
 708                                 CurrentIGI = CurrentIGI - 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue-1; */
 709                 }
 710         } else {
 711                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): DIG BeforeLink\n"));
 712                 if (FirstDisConnect) {
 713                         CurrentIGI = pDM_DigTable->rx_gain_range_min;
 714                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): First DisConnect \n"));
 715                 } else {
 716                         /* 2012.03.30 LukeLee: enable DIG before link but with very high thresholds */
 717                         if (pFalseAlmCnt->Cnt_all > 10000)
 718                                 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */
 719                         else if (pFalseAlmCnt->Cnt_all > 8000)
 720                                 CurrentIGI = CurrentIGI + 1;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */
 721                         else if (pFalseAlmCnt->Cnt_all < 500)
 722                                 CurrentIGI = CurrentIGI - 1;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue-1; */
 723                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): England DIG \n"));
 724                 }
 725         }
 726         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): DIG End Adjust IGI\n"));
 727         /* 1 Check initial gain by upper/lower bound */
 728         if (CurrentIGI > pDM_DigTable->rx_gain_range_max)
 729                 CurrentIGI = pDM_DigTable->rx_gain_range_max;
 730         if (CurrentIGI < pDM_DigTable->rx_gain_range_min)
 731                 CurrentIGI = pDM_DigTable->rx_gain_range_min;
 732
 733         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): rx_gain_range_max = 0x%x, rx_gain_range_min = 0x%x\n",
 734                 pDM_DigTable->rx_gain_range_max, pDM_DigTable->rx_gain_range_min));
 735         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): TotalFA =%d\n", pFalseAlmCnt->Cnt_all));
 736         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): CurIGValue = 0x%x\n", CurrentIGI));
 737
 738         /* 2 High power RSSI threshold */
 739
 740         ODM_Write_DIG23a(pDM_Odm, CurrentIGI);/* ODM_Write_DIG23a(pDM_Odm, pDM_DigTable->CurIGValue); */
 741         pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked;
 742         pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN;
 743 }
 744
 745 /* 3 ============================================================ */
 746 /* 3 FASLE ALARM CHECK */
 747 /* 3 ============================================================ */
 748
 749 void odm_FalseAlarmCounterStatistics23a(struct dm_odm_t *pDM_Odm)
 750 {
 751         u32 ret_value;
 752         struct false_alarm_stats *FalseAlmCnt = &pDM_Odm->FalseAlmCnt;
 753
 754         /* hold ofdm counter */
 755          /* hold page C counter */
 756         ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT(31), 1);
 757         /* hold page D counter */
 758         ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(31), 1);
 759         ret_value =
 760                 ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE1_11N, bMaskDWord);
 761         FalseAlmCnt->Cnt_Fast_Fsync = (ret_value&0xffff);
 762         FalseAlmCnt->Cnt_SB_Search_fail = ((ret_value&0xffff0000)>>16);
 763         ret_value =
 764                 ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE2_11N, bMaskDWord);
 765         FalseAlmCnt->Cnt_OFDM_CCA = (ret_value&0xffff);
 766         FalseAlmCnt->Cnt_Parity_Fail = ((ret_value&0xffff0000)>>16);
 767         ret_value =
 768                 ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE3_11N, bMaskDWord);
 769         FalseAlmCnt->Cnt_Rate_Illegal = (ret_value&0xffff);
 770         FalseAlmCnt->Cnt_Crc8_fail = ((ret_value&0xffff0000)>>16);
 771         ret_value =
 772                 ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE4_11N, bMaskDWord);
 773         FalseAlmCnt->Cnt_Mcs_fail = (ret_value&0xffff);
 774
 775         FalseAlmCnt->Cnt_Ofdm_fail = FalseAlmCnt->Cnt_Parity_Fail +
 776                 FalseAlmCnt->Cnt_Rate_Illegal +
 777                 FalseAlmCnt->Cnt_Crc8_fail +
 778                 FalseAlmCnt->Cnt_Mcs_fail +
 779                 FalseAlmCnt->Cnt_Fast_Fsync +
 780                 FalseAlmCnt->Cnt_SB_Search_fail;
 781         /* hold cck counter */
 782         ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT(12), 1);
 783         ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT(14), 1);
 784
 785         ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_LSB_11N, bMaskByte0);
 786         FalseAlmCnt->Cnt_Cck_fail = ret_value;
 787         ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_MSB_11N, bMaskByte3);
 788         FalseAlmCnt->Cnt_Cck_fail +=  (ret_value & 0xff) << 8;
 789
 790         ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_CCA_CNT_11N, bMaskDWord);
 791         FalseAlmCnt->Cnt_CCK_CCA =
 792                 ((ret_value&0xFF)<<8) | ((ret_value&0xFF00)>>8);
 793
 794         FalseAlmCnt->Cnt_all = (FalseAlmCnt->Cnt_Fast_Fsync +
 795                                 FalseAlmCnt->Cnt_SB_Search_fail +
 796                                 FalseAlmCnt->Cnt_Parity_Fail +
 797                                 FalseAlmCnt->Cnt_Rate_Illegal +
 798                                 FalseAlmCnt->Cnt_Crc8_fail +
 799                                 FalseAlmCnt->Cnt_Mcs_fail +
 800                                 FalseAlmCnt->Cnt_Cck_fail);
 801
 802         FalseAlmCnt->Cnt_CCA_all =
 803                 FalseAlmCnt->Cnt_OFDM_CCA + FalseAlmCnt->Cnt_CCK_CCA;
 804
 805         if (pDM_Odm->SupportICType >= ODM_RTL8723A) {
 806                 /* reset false alarm counter registers */
 807                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT(31), 1);
 808                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT(31), 0);
 809                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(27), 1);
 810                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(27), 0);
 811                 /* update ofdm counter */
 812                  /* update page C counter */
 813                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT(31), 0);
 814                  /* update page D counter */
 815                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(31), 0);
 816
 817                 /* reset CCK CCA counter */
 818                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N,
 819                              BIT(13) | BIT(12), 0);
 820                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N,
 821                              BIT(13) | BIT(12), 2);
 822                 /* reset CCK FA counter */
 823                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N,
 824                              BIT(15) | BIT(14), 0);
 825                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N,
 826                              BIT(15) | BIT(14), 2);
 827         }
 828
 829         ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD,
 830                      ("Enter odm_FalseAlarmCounterStatistics23a\n"));
 831         ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD,
 832                      ("Cnt_Fast_Fsync =%d, Cnt_SB_Search_fail =%d\n",
 833                       FalseAlmCnt->Cnt_Fast_Fsync,
 834                       FalseAlmCnt->Cnt_SB_Search_fail));
 835         ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD,
 836                      ("Cnt_Parity_Fail =%d, Cnt_Rate_Illegal =%d\n",
 837                       FalseAlmCnt->Cnt_Parity_Fail,
 838                       FalseAlmCnt->Cnt_Rate_Illegal));
 839         ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD,
 840                      ("Cnt_Crc8_fail =%d, Cnt_Mcs_fail =%d\n",
 841                       FalseAlmCnt->Cnt_Crc8_fail, FalseAlmCnt->Cnt_Mcs_fail));
 842
 843         ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Cck_fail =%d\n", FalseAlmCnt->Cnt_Cck_fail));
 844         ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Ofdm_fail =%d\n", FalseAlmCnt->Cnt_Ofdm_fail));
 845         ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Total False Alarm =%d\n", FalseAlmCnt->Cnt_all));
 846 }
 847
 848 /* 3 ============================================================ */
 849 /* 3 CCK Packet Detect Threshold */
 850 /* 3 ============================================================ */
 851
 852 void odm_CCKPacketDetectionThresh23a(struct dm_odm_t *pDM_Odm)
 853 {
 854         struct false_alarm_stats *FalseAlmCnt = &pDM_Odm->FalseAlmCnt;
 855         u8 CurCCK_CCAThres;
 856
 857         if (!(pDM_Odm->SupportAbility & ODM_BB_CCK_PD))
 858                 return;
 859
 860         if (pDM_Odm->ExtLNA)
 861                 return;
 862
 863         if (pDM_Odm->bLinked) {
 864                 if (pDM_Odm->RSSI_Min > 25) {
 865                         CurCCK_CCAThres = 0xcd;
 866                 } else if ((pDM_Odm->RSSI_Min <= 25) && (pDM_Odm->RSSI_Min > 10)) {
 867                         CurCCK_CCAThres = 0x83;
 868                 } else {
 869                         if (FalseAlmCnt->Cnt_Cck_fail > 1000)
 870                                 CurCCK_CCAThres = 0x83;
 871                         else
 872                                 CurCCK_CCAThres = 0x40;
 873                 }
 874         } else {
 875                 if (FalseAlmCnt->Cnt_Cck_fail > 1000)
 876                         CurCCK_CCAThres = 0x83;
 877                 else
 878                         CurCCK_CCAThres = 0x40;
 879         }
 880
 881         ODM_Write_CCK_CCA_Thres23a(pDM_Odm, CurCCK_CCAThres);
 882 }
 883
 884 void ODM_Write_CCK_CCA_Thres23a(struct dm_odm_t *pDM_Odm, u8 CurCCK_CCAThres)
 885 {
 886         struct dig_t *pDM_DigTable = &pDM_Odm->DM_DigTable;
 887
 888         if (pDM_DigTable->CurCCK_CCAThres != CurCCK_CCAThres)
 889                 ODM_Write1Byte(pDM_Odm, ODM_REG(CCK_CCA, pDM_Odm), CurCCK_CCAThres);
 890         pDM_DigTable->PreCCK_CCAThres = pDM_DigTable->CurCCK_CCAThres;
 891         pDM_DigTable->CurCCK_CCAThres = CurCCK_CCAThres;
 892
 893 }
 894
 895 /* 3 ============================================================ */
 896 /* 3 BB Power Save */
 897 /* 3 ============================================================ */
 898 void odm23a_DynBBPSInit(struct dm_odm_t *pDM_Odm)
 899 {
 900         struct dynamic_pwr_sav *pDM_PSTable = &pDM_Odm->DM_PSTable;
 901
 902         pDM_PSTable->PreCCAState = CCA_MAX;
 903         pDM_PSTable->CurCCAState = CCA_MAX;
 904         pDM_PSTable->PreRFState = RF_MAX;
 905         pDM_PSTable->CurRFState = RF_MAX;
 906         pDM_PSTable->Rssi_val_min = 0;
 907         pDM_PSTable->initialize = 0;
 908 }
 909
 910 void odm_DynamicBBPowerSaving23a(struct dm_odm_t *pDM_Odm)
 911 {
 912         return;
 913 }
 914
 915 void ODM_RF_Saving23a(struct dm_odm_t *pDM_Odm, u8 bForceInNormal)
 916 {
 917         struct dynamic_pwr_sav *pDM_PSTable = &pDM_Odm->DM_PSTable;
 918         u8 Rssi_Up_bound = 30;
 919         u8 Rssi_Low_bound = 25;
 920         if (pDM_Odm->PatchID == 40) { /* RT_CID_819x_FUNAI_TV */
 921                 Rssi_Up_bound = 50;
 922                 Rssi_Low_bound = 45;
 923         }
 924         if (pDM_PSTable->initialize == 0) {
 925
 926                 pDM_PSTable->Reg874 = (ODM_GetBBReg(pDM_Odm, 0x874, bMaskDWord)&0x1CC000)>>14;
 927                 pDM_PSTable->RegC70 =
 928                         (ODM_GetBBReg(pDM_Odm, 0xc70, bMaskDWord) & BIT(3)) >>3;
 929                 pDM_PSTable->Reg85C = (ODM_GetBBReg(pDM_Odm, 0x85c, bMaskDWord)&0xFF000000)>>24;
 930                 pDM_PSTable->RegA74 = (ODM_GetBBReg(pDM_Odm, 0xa74, bMaskDWord)&0xF000)>>12;
 931                 /* Reg818 = PHY_QueryBBReg(pAdapter, 0x818, bMaskDWord); */
 932                 pDM_PSTable->initialize = 1;
 933         }
 934
 935         if (!bForceInNormal) {
 936                 if (pDM_Odm->RSSI_Min != 0xFF) {
 937                         if (pDM_PSTable->PreRFState == RF_Normal) {
 938                                 if (pDM_Odm->RSSI_Min >= Rssi_Up_bound)
 939                                         pDM_PSTable->CurRFState = RF_Save;
 940                                 else
 941                                         pDM_PSTable->CurRFState = RF_Normal;
 942                         } else {
 943                                 if (pDM_Odm->RSSI_Min <= Rssi_Low_bound)
 944                                         pDM_PSTable->CurRFState = RF_Normal;
 945                                 else
 946                                         pDM_PSTable->CurRFState = RF_Save;
 947                         }
 948                 } else {
 949                         pDM_PSTable->CurRFState = RF_MAX;
 950                 }
 951         } else {
 952                 pDM_PSTable->CurRFState = RF_Normal;
 953         }
 954
 955         if (pDM_PSTable->PreRFState != pDM_PSTable->CurRFState) {
 956                 if (pDM_PSTable->CurRFState == RF_Save) {
 957                         /*  <tynli_note> 8723 RSSI report will be wrong. Set 0x874[5]= 1 when enter BB power saving mode. */
 958                         /*  Suggested by SD3 Yu-Nan. 2011.01.20. */
 959                         if (pDM_Odm->SupportICType == ODM_RTL8723A)
 960                                 ODM_SetBBReg(pDM_Odm, 0x874, BIT(5), 0x1); /* Reg874[5]= 1b'1 */
 961                         ODM_SetBBReg(pDM_Odm, 0x874, 0x1C0000, 0x2); /* Reg874[20:18]= 3'b010 */
 962                         ODM_SetBBReg(pDM_Odm, 0xc70, BIT(3), 0); /* RegC70[3]= 1'b0 */
 963                         ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, 0x63); /* Reg85C[31:24]= 0x63 */
 964                         ODM_SetBBReg(pDM_Odm, 0x874, 0xC000, 0x2); /* Reg874[15:14]= 2'b10 */
 965                         ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, 0x3); /* RegA75[7:4]= 0x3 */
 966                         ODM_SetBBReg(pDM_Odm, 0x818, BIT(28), 0x0); /* Reg818[28]= 1'b0 */
 967                         ODM_SetBBReg(pDM_Odm, 0x818, BIT(28), 0x1); /* Reg818[28]= 1'b1 */
 968                 } else {
 969                         ODM_SetBBReg(pDM_Odm, 0x874, 0x1CC000, pDM_PSTable->Reg874);
 970                         ODM_SetBBReg(pDM_Odm, 0xc70, BIT(3), pDM_PSTable->RegC70);
 971                         ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, pDM_PSTable->Reg85C);
 972                         ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, pDM_PSTable->RegA74);
 973                         ODM_SetBBReg(pDM_Odm, 0x818, BIT(28), 0x0);
 974
 975                         if (pDM_Odm->SupportICType == ODM_RTL8723A)
 976                                 ODM_SetBBReg(pDM_Odm, 0x874, BIT(5), 0x0); /* Reg874[5]= 1b'0 */
 977                 }
 978                 pDM_PSTable->PreRFState = pDM_PSTable->CurRFState;
 979         }
 980 }
 981
 982 /* 3 ============================================================ */
 983 /* 3 RATR MASK */
 984 /* 3 ============================================================ */
 985 /* 3 ============================================================ */
 986 /* 3 Rate Adaptive */
 987 /* 3 ============================================================ */
 988
 989 void odm_RateAdaptiveMaskInit23a(struct dm_odm_t *pDM_Odm)
 990 {
 991         struct odm_rate_adapt *pOdmRA = &pDM_Odm->RateAdaptive;
 992
 993         pOdmRA->Type = DM_Type_ByDriver;
 994
 995         pOdmRA->RATRState = DM_RATR_STA_INIT;
 996         pOdmRA->HighRSSIThresh = 50;
 997         pOdmRA->LowRSSIThresh = 20;
 998 }
 999
1000 u32 ODM_Get_Rate_Bitmap23a(struct hal_data_8723a *pHalData, u32 macid,
1001                            u32 ra_mask, u8 rssi_level)
1002 {
1003         struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
1004         struct sta_info *pEntry;
1005         u32 rate_bitmap = 0x0fffffff;
1006         u8 WirelessMode;
1007
1008         pEntry = pDM_Odm->pODM_StaInfo[macid];
1009         if (!pEntry)
1010                 return ra_mask;
1011
1012         WirelessMode = pEntry->wireless_mode;
1013
1014         switch (WirelessMode) {
1015         case ODM_WM_B:
1016                 if (ra_mask & 0x0000000c)               /* 11M or 5.5M enable */
1017                         rate_bitmap = 0x0000000d;
1018                 else
1019                         rate_bitmap = 0x0000000f;
1020                 break;
1021         case (ODM_WM_A|ODM_WM_G):
1022                 if (rssi_level == DM_RATR_STA_HIGH)
1023                         rate_bitmap = 0x00000f00;
1024                 else
1025                         rate_bitmap = 0x00000ff0;
1026                 break;
1027         case (ODM_WM_B|ODM_WM_G):
1028                 if (rssi_level == DM_RATR_STA_HIGH)
1029                         rate_bitmap = 0x00000f00;
1030                 else if (rssi_level == DM_RATR_STA_MIDDLE)
1031                         rate_bitmap = 0x00000ff0;
1032                 else
1033                         rate_bitmap = 0x00000ff5;
1034                 break;
1035         case (ODM_WM_B|ODM_WM_G|ODM_WM_N24G):
1036         case (ODM_WM_A|ODM_WM_B|ODM_WM_G|ODM_WM_N24G):
1037                 if (pHalData->rf_type == RF_1T2R ||
1038                     pHalData->rf_type == RF_1T1R) {
1039                         if (rssi_level == DM_RATR_STA_HIGH) {
1040                                 rate_bitmap = 0x000f0000;
1041                         } else if (rssi_level == DM_RATR_STA_MIDDLE) {
1042                                 rate_bitmap = 0x000ff000;
1043                         } else {
1044                                 if (pHalData->CurrentChannelBW ==
1045                                     HT_CHANNEL_WIDTH_40)
1046                                         rate_bitmap = 0x000ff015;
1047                                 else
1048                                         rate_bitmap = 0x000ff005;
1049                         }
1050                 } else {
1051                         if (rssi_level == DM_RATR_STA_HIGH) {
1052                                 rate_bitmap = 0x0f8f0000;
1053                         } else if (rssi_level == DM_RATR_STA_MIDDLE) {
1054                                 rate_bitmap = 0x0f8ff000;
1055                         } else {
1056                                 if (pHalData->CurrentChannelBW ==
1057                                     HT_CHANNEL_WIDTH_40)
1058                                         rate_bitmap = 0x0f8ff015;
1059                                 else
1060                                         rate_bitmap = 0x0f8ff005;
1061                         }
1062                 }
1063                 break;
1064         default:
1065                 /* case WIRELESS_11_24N: */
1066                 /* case WIRELESS_11_5N: */
1067                 if (pHalData->rf_type == RF_1T2R)
1068                         rate_bitmap = 0x000fffff;
1069                 else
1070                         rate_bitmap = 0x0fffffff;
1071                 break;
1072         }
1073
1074         /* printk("%s ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x \n", __func__, rssi_level, WirelessMode, rate_bitmap); */
1075         ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, (" ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x \n", rssi_level, WirelessMode, rate_bitmap));
1076
1077         return rate_bitmap;
1078
1079 }
1080
1081 /*-----------------------------------------------------------------------------
1082  * Function:    odm_RefreshRateAdaptiveMask23a()
1083  *
1084  * Overview:    Update rate table mask according to rssi
1085  *
1086  * Input:               NONE
1087  *
1088  * Output:              NONE
1089  *
1090  * Return:              NONE
1091  *
1092  * Revised History:
1093  *When          Who             Remark
1094  *05/27/2009    hpfan   Create Version 0.
1095  *
1096  *---------------------------------------------------------------------------*/
1097 void odm_RefreshRateAdaptiveMask23a(struct dm_odm_t *pDM_Odm)
1098 {
1099         u8 i;
1100         struct rtw_adapter *pAdapter     =  pDM_Odm->Adapter;
1101
1102         if (pAdapter->bDriverStopped) {
1103                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE,
1104                              ("<---- %s: driver is going to unload\n",
1105                               __func__));
1106                 return;
1107         }
1108
1109         for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
1110                 struct sta_info *pstat = pDM_Odm->pODM_StaInfo[i];
1111                 if (pstat) {
1112                         if (ODM_RAStateCheck23a(pDM_Odm, pstat->rssi_stat.UndecoratedSmoothedPWDB, false, &pstat->rssi_level)) {
1113                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD,
1114                                              ("RSSI:%d, RSSI_LEVEL:%d\n",
1115                                              pstat->rssi_stat.UndecoratedSmoothedPWDB,
1116                                              pstat->rssi_level));
1117                                 rtw_hal_update_ra_mask23a(pstat, pstat->rssi_level);
1118                         }
1119
1120                 }
1121         }
1122
1123 }
1124
1125 /*  Return Value: bool */
1126 /*  - true: RATRState is changed. */
1127 bool ODM_RAStateCheck23a(struct dm_odm_t *pDM_Odm, s32 RSSI, bool bForceUpdate,
1128                          u8 *pRATRState)
1129 {
1130         struct odm_rate_adapt *pRA = &pDM_Odm->RateAdaptive;
1131         const u8 GoUpGap = 5;
1132         u8 HighRSSIThreshForRA = pRA->HighRSSIThresh;
1133         u8 LowRSSIThreshForRA = pRA->LowRSSIThresh;
1134         u8 RATRState;
1135
1136         /*  Threshold Adjustment: */
1137         /*  when RSSI state trends to go up one or two levels, make sure RSSI is high enough. */
1138         /*  Here GoUpGap is added to solve the boundary's level alternation issue. */
1139         switch (*pRATRState) {
1140         case DM_RATR_STA_INIT:
1141         case DM_RATR_STA_HIGH:
1142                 break;
1143         case DM_RATR_STA_MIDDLE:
1144                 HighRSSIThreshForRA += GoUpGap;
1145                 break;
1146         case DM_RATR_STA_LOW:
1147                 HighRSSIThreshForRA += GoUpGap;
1148                 LowRSSIThreshForRA += GoUpGap;
1149                 break;
1150         default:
1151                 ODM_RT_ASSERT(pDM_Odm, false, ("wrong rssi level setting %d !", *pRATRState));
1152                 break;
1153         }
1154
1155         /*  Decide RATRState by RSSI. */
1156         if (RSSI > HighRSSIThreshForRA)
1157                 RATRState = DM_RATR_STA_HIGH;
1158         else if (RSSI > LowRSSIThreshForRA)
1159                 RATRState = DM_RATR_STA_MIDDLE;
1160         else
1161                 RATRState = DM_RATR_STA_LOW;
1162
1163         if (*pRATRState != RATRState || bForceUpdate) {
1164                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD,
1165                              ("RSSI Level %d -> %d\n", *pRATRState, RATRState));
1166                 *pRATRState = RATRState;
1167                 return true;
1168         }
1169         return false;
1170 }
1171
1172 /* 3 ============================================================ */
1173 /* 3 Dynamic Tx Power */
1174 /* 3 ============================================================ */
1175
1176 void odm_DynamicTxPower23aInit(struct dm_odm_t *pDM_Odm)
1177 {
1178         struct rtw_adapter *Adapter = pDM_Odm->Adapter;
1179         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1180         struct dm_priv *pdmpriv = &pHalData->dmpriv;
1181
1182         /*
1183          * This is never changed, so we should be able to clean up the
1184          * code checking for different values in rtl8723a_rf6052.c
1185          */
1186         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
1187 }
1188
1189 void odm_RSSIMonitorCheck23a(struct dm_odm_t *pDM_Odm)
1190 {
1191         /*  For AP/ADSL use struct rtl8723a_priv * */
1192         /*  For CE/NIC use struct rtw_adapter * */
1193
1194         if (!(pDM_Odm->SupportAbility & ODM_BB_RSSI_MONITOR))
1195                 return;
1196
1197         /*  2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1198         /*  at the same time. In the stage2/3, we need to prive universal interface and merge all */
1199         /*  HW dynamic mechanism. */
1200         odm_RSSIMonitorCheck23aCE(pDM_Odm);
1201 }       /*  odm_RSSIMonitorCheck23a */
1202
1203 static void
1204 FindMinimumRSSI(
1205         struct rtw_adapter *pAdapter
1206         )
1207 {
1208         struct hal_data_8723a *pHalData = GET_HAL_DATA(pAdapter);
1209         struct dm_priv *pdmpriv = &pHalData->dmpriv;
1210         struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
1211
1212         /* 1 1.Determine the minimum RSSI */
1213
1214         if ((!pDM_Odm->bLinked) &&
1215             (pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0))
1216                 pdmpriv->MinUndecoratedPWDBForDM = 0;
1217         else
1218                 pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
1219 }
1220
1221 void odm_RSSIMonitorCheck23aCE(struct dm_odm_t *pDM_Odm)
1222 {
1223         struct rtw_adapter *Adapter = pDM_Odm->Adapter;
1224         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1225         struct dm_priv *pdmpriv = &pHalData->dmpriv;
1226         int     i;
1227         int     tmpEntryMaxPWDB = 0, tmpEntryMinPWDB = 0xff;
1228         u8 sta_cnt = 0;
1229         u32 PWDB_rssi[NUM_STA] = {0};/* 0~15]:MACID, [16~31]:PWDB_rssi */
1230         struct sta_info *psta;
1231
1232         if (!pDM_Odm->bLinked)
1233                 return;
1234
1235         for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
1236                 psta = pDM_Odm->pODM_StaInfo[i];
1237                 if (psta) {
1238                         if (psta->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB)
1239                                 tmpEntryMinPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
1240
1241                         if (psta->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB)
1242                                 tmpEntryMaxPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
1243
1244                         if (psta->rssi_stat.UndecoratedSmoothedPWDB != (-1))
1245                                 PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16));
1246                 }
1247         }
1248
1249         for (i = 0; i < sta_cnt; i++) {
1250                 if (PWDB_rssi[i] != (0)) {
1251                         rtl8723a_set_rssi_cmd(Adapter, (u8 *)&PWDB_rssi[i]);
1252                 }
1253         }
1254
1255         if (tmpEntryMaxPWDB != 0)       /*  If associated entry is found */
1256                 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = tmpEntryMaxPWDB;
1257         else
1258                 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = 0;
1259
1260         if (tmpEntryMinPWDB != 0xff) /*  If associated entry is found */
1261                 pdmpriv->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB;
1262         else
1263                 pdmpriv->EntryMinUndecoratedSmoothedPWDB = 0;
1264
1265         FindMinimumRSSI(Adapter);/* get pdmpriv->MinUndecoratedPWDBForDM */
1266
1267         ODM_CmnInfoUpdate23a(&pHalData->odmpriv, ODM_CMNINFO_RSSI_MIN, pdmpriv->MinUndecoratedPWDBForDM);
1268 }
1269
1270 /* endif */
1271 /* 3 ============================================================ */
1272 /* 3 Tx Power Tracking */
1273 /* 3 ============================================================ */
1274
1275 void odm_TXPowerTrackingInit23a(struct dm_odm_t *pDM_Odm)
1276 {
1277         odm_TXPowerTrackingThermalMeterInit23a(pDM_Odm);
1278 }
1279
1280 void odm_TXPowerTrackingThermalMeterInit23a(struct dm_odm_t *pDM_Odm)
1281 {
1282         struct rtw_adapter *Adapter = pDM_Odm->Adapter;
1283         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1284         struct dm_priv *pdmpriv = &pHalData->dmpriv;
1285
1286         pdmpriv->bTXPowerTracking = true;
1287         pdmpriv->TXPowercount = 0;
1288         pdmpriv->bTXPowerTrackingInit = false;
1289         pdmpriv->TxPowerTrackControl = true;
1290         MSG_8723A("pdmpriv->TxPowerTrackControl = %d\n", pdmpriv->TxPowerTrackControl);
1291
1292         pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = true;
1293 }
1294
1295 void ODM_TXPowerTrackingCheck23a(struct dm_odm_t *pDM_Odm)
1296 {
1297         /*  For AP/ADSL use struct rtl8723a_priv * */
1298         /*  For CE/NIC use struct rtw_adapter * */
1299
1300         /*  2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1301         /*  at the same time. In the stage2/3, we need to prive universal interface and merge all */
1302         /*  HW dynamic mechanism. */
1303         odm_TXPowerTrackingCheckCE23a(pDM_Odm);
1304 }
1305
1306 void odm_TXPowerTrackingCheckCE23a(struct dm_odm_t *pDM_Odm)
1307 {
1308 }
1309
1310 /* EDCA Turbo */
1311 static void ODM_EdcaTurboInit23a(struct dm_odm_t *pDM_Odm)
1312 {
1313
1314         struct rtw_adapter *Adapter = pDM_Odm->Adapter;
1315
1316         pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false;
1317         pDM_Odm->DM_EDCA_Table.bIsCurRDLState = false;
1318         Adapter->recvpriv.bIsAnyNonBEPkts = false;
1319
1320         ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VO PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_VO_PARAM)));
1321         ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VI PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_VI_PARAM)));
1322         ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BE PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_BE_PARAM)));
1323         ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BK PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_BK_PARAM)));
1324
1325 }       /*  ODM_InitEdcaTurbo */
1326
1327 static void odm_EdcaTurboCheck23a(struct dm_odm_t *pDM_Odm)
1328 {
1329         struct rtw_adapter *Adapter = pDM_Odm->Adapter;
1330         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1331         struct xmit_priv *pxmitpriv = &Adapter->xmitpriv;
1332         struct recv_priv *precvpriv = &Adapter->recvpriv;
1333         struct registry_priv *pregpriv = &Adapter->registrypriv;
1334         struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
1335         struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
1336         u32 trafficIndex;
1337         u32 edca_param;
1338         u64 cur_tx_bytes;
1339         u64 cur_rx_bytes;
1340
1341         /*  For AP/ADSL use struct rtl8723a_priv * */
1342         /*  For CE/NIC use struct rtw_adapter * */
1343
1344         /*  2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1345         /*  at the same time. In the stage2/3, we need to prive universal interface and merge all */
1346         /*  HW dynamic mechanism. */
1347
1348         if ((pregpriv->wifi_spec == 1))/*  (pmlmeinfo->HT_enable == 0)) */
1349                 goto dm_CheckEdcaTurbo_EXIT;
1350
1351         if (pmlmeinfo->assoc_AP_vendor >=  HT_IOT_PEER_MAX)
1352                 goto dm_CheckEdcaTurbo_EXIT;
1353
1354         if (rtl8723a_BT_disable_EDCA_turbo(Adapter))
1355                 goto dm_CheckEdcaTurbo_EXIT;
1356
1357         /*  Check if the status needs to be changed. */
1358         if (!precvpriv->bIsAnyNonBEPkts) {
1359                 cur_tx_bytes = pxmitpriv->tx_bytes - pxmitpriv->last_tx_bytes;
1360                 cur_rx_bytes = precvpriv->rx_bytes - precvpriv->last_rx_bytes;
1361
1362                 /* traffic, TX or RX */
1363                 if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_RALINK) ||
1364                     (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_ATHEROS)) {
1365                         if (cur_tx_bytes > (cur_rx_bytes << 2)) {
1366                                 /*  Uplink TP is present. */
1367                                 trafficIndex = UP_LINK;
1368                         } else { /*  Balance TP is present. */
1369                                 trafficIndex = DOWN_LINK;
1370                         }
1371                 } else {
1372                         if (cur_rx_bytes > (cur_tx_bytes << 2)) {
1373                                 /*  Downlink TP is present. */
1374                                 trafficIndex = DOWN_LINK;
1375                         } else { /*  Balance TP is present. */
1376                                 trafficIndex = UP_LINK;
1377                         }
1378                 }
1379
1380                 if ((pDM_Odm->DM_EDCA_Table.prv_traffic_idx != trafficIndex) ||
1381                     (!pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA)) {
1382                         if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_CISCO) &&
1383                             (pmlmeext->cur_wireless_mode & WIRELESS_11_24N))
1384                                 edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex];
1385                         else
1386                                 edca_param = EDCAParam[HT_IOT_PEER_UNKNOWN][trafficIndex];
1387                         rtl8723au_write32(Adapter, REG_EDCA_BE_PARAM,
1388                                           edca_param);
1389
1390                         pDM_Odm->DM_EDCA_Table.prv_traffic_idx = trafficIndex;
1391                 }
1392
1393                 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = true;
1394         } else {
1395                 /*  Turn Off EDCA turbo here. */
1396                 /*  Restore original EDCA according to the declaration of AP. */
1397                 if (pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA) {
1398                         rtl8723au_write32(Adapter, REG_EDCA_BE_PARAM,
1399                                           pHalData->AcParam_BE);
1400                         pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false;
1401                 }
1402         }
1403
1404 dm_CheckEdcaTurbo_EXIT:
1405         /*  Set variables for next time. */
1406         precvpriv->bIsAnyNonBEPkts = false;
1407         pxmitpriv->last_tx_bytes = pxmitpriv->tx_bytes;
1408         precvpriv->last_rx_bytes = precvpriv->rx_bytes;
1409 }
1410
1411 u32 GetPSDData(struct dm_odm_t *pDM_Odm, unsigned int point, u8 initial_gain_psd)
1412 {
1413         u32 psd_report;
1414
1415         /* Set DCO frequency index, offset = (40MHz/SamplePts)*point */
1416         ODM_SetBBReg(pDM_Odm, 0x808, 0x3FF, point);
1417
1418         /* Start PSD calculation, Reg808[22]= 0->1 */
1419         ODM_SetBBReg(pDM_Odm, 0x808, BIT(22), 1);
1420         /* Need to wait for HW PSD report */
1421         udelay(30);
1422         ODM_SetBBReg(pDM_Odm, 0x808, BIT(22), 0);
1423         /* Read PSD report, Reg8B4[15:0] */
1424         psd_report = ODM_GetBBReg(pDM_Odm, 0x8B4, bMaskDWord) & 0x0000FFFF;
1425
1426         psd_report = (u32)(ConvertTo_dB23a(psd_report))+(u32)(initial_gain_psd-0x1c);
1427
1428         return psd_report;
1429 }
1430
1431 u32
1432 ConvertTo_dB23a(
1433         u32 Value)
1434 {
1435         u8 i;
1436         u8 j;
1437         u32 dB;
1438
1439         Value = Value & 0xFFFF;
1440
1441         for (i = 0; i < 8; i++) {
1442                 if (Value <= dB_Invert_Table[i][11])
1443                         break;
1444         }
1445
1446         if (i >= 8)
1447                 return 96;      /*  maximum 96 dB */
1448
1449         for (j = 0; j < 12; j++) {
1450                 if (Value <= dB_Invert_Table[i][j])
1451                         break;
1452         }
1453
1454         dB = i*12 + j + 1;
1455
1456         return dB;
1457 }
1458
1459 /*  */
1460 /*  Description: */
1461 /*Set Single/Dual Antenna default setting for products that do not do detection in advance. */
1462 /*  */
1463 /*  Added by Joseph, 2012.03.22 */
1464 /*  */
1465 void ODM_SingleDualAntennaDefaultSetting(struct dm_odm_t *pDM_Odm)
1466 {
1467         struct sw_ant_sw *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
1468
1469         pDM_SWAT_Table->ANTA_ON = true;
1470         pDM_SWAT_Table->ANTB_ON = true;
1471 }
1472
1473 /* 2 8723A ANT DETECT */
1474
1475 static void odm_PHY_SaveAFERegisters(
1476         struct dm_odm_t *pDM_Odm,
1477         u32 *AFEReg,
1478         u32 *AFEBackup,
1479         u32 RegisterNum
1480         )
1481 {
1482         u32 i;
1483
1484         /* RTPRINT(FINIT, INIT_IQK, ("Save ADDA parameters.\n")); */
1485         for (i = 0 ; i < RegisterNum ; i++)
1486                 AFEBackup[i] = ODM_GetBBReg(pDM_Odm, AFEReg[i], bMaskDWord);
1487 }
1488
1489 static void odm_PHY_ReloadAFERegisters(struct dm_odm_t *pDM_Odm, u32 *AFEReg,
1490                                        u32 *AFEBackup, u32 RegiesterNum)
1491 {
1492         u32 i;
1493
1494         for (i = 0 ; i < RegiesterNum; i++)
1495                 ODM_SetBBReg(pDM_Odm, AFEReg[i], bMaskDWord, AFEBackup[i]);
1496 }
1497
1498 /* 2 8723A ANT DETECT */
1499 /*  Description: */
1500 /* Implement IQK single tone for RF DPK loopback and BB PSD scanning. */
1501 /* This function is cooperated with BB team Neil. */
1502 bool ODM_SingleDualAntennaDetection(struct dm_odm_t *pDM_Odm, u8 mode)
1503 {
1504         struct sw_ant_sw *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
1505         u32 CurrentChannel, RfLoopReg;
1506         u8 n;
1507         u32 Reg88c, Regc08, Reg874, Regc50;
1508         u8 initial_gain = 0x5a;
1509         u32 PSD_report_tmp;
1510         u32 AntA_report = 0x0, AntB_report = 0x0, AntO_report = 0x0;
1511         bool bResult = true;
1512         u32 AFE_Backup[16];
1513         u32 AFE_REG_8723A[16] = {
1514                 rRx_Wait_CCA, rTx_CCK_RFON,
1515                 rTx_CCK_BBON, rTx_OFDM_RFON,
1516                 rTx_OFDM_BBON, rTx_To_Rx,
1517                 rTx_To_Tx, rRx_CCK,
1518                 rRx_OFDM, rRx_Wait_RIFS,
1519                 rRx_TO_Rx, rStandby,
1520                 rSleep, rPMPD_ANAEN,
1521                 rFPGA0_XCD_SwitchControl, rBlue_Tooth};
1522
1523         if (!(pDM_Odm->SupportICType & ODM_RTL8723A))
1524                 return bResult;
1525
1526         if (!(pDM_Odm->SupportAbility&ODM_BB_ANT_DIV))
1527                 return bResult;
1528         /* 1 Backup Current RF/BB Settings */
1529
1530         CurrentChannel = ODM_GetRFReg(pDM_Odm, RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask);
1531         RfLoopReg = ODM_GetRFReg(pDM_Odm, RF_PATH_A, 0x00, bRFRegOffsetMask);
1532         ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, ODM_DPDT, Antenna_A);  /*  change to Antenna A */
1533         /*  Step 1: USE IQK to transmitter single tone */
1534
1535         udelay(10);
1536
1537         /* Store A Path Register 88c, c08, 874, c50 */
1538         Reg88c = ODM_GetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord);
1539         Regc08 = ODM_GetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord);
1540         Reg874 = ODM_GetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord);
1541         Regc50 = ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord);
1542
1543         /*  Store AFE Registers */
1544         odm_PHY_SaveAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16);
1545
1546         /* Set PSD 128 pts */
1547         ODM_SetBBReg(pDM_Odm, rFPGA0_PSDFunction, BIT(14) | BIT(15), 0x0);
1548
1549         /*  To SET CH1 to do */
1550         ODM_SetRFReg(pDM_Odm, RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask, 0x01);     /* Channel 1 */
1551
1552         /*  AFE all on step */
1553         ODM_SetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord, 0x6FDB25A4);
1554         ODM_SetBBReg(pDM_Odm, rTx_CCK_RFON, bMaskDWord, 0x6FDB25A4);
1555         ODM_SetBBReg(pDM_Odm, rTx_CCK_BBON, bMaskDWord, 0x6FDB25A4);
1556         ODM_SetBBReg(pDM_Odm, rTx_OFDM_RFON, bMaskDWord, 0x6FDB25A4);
1557         ODM_SetBBReg(pDM_Odm, rTx_OFDM_BBON, bMaskDWord, 0x6FDB25A4);
1558         ODM_SetBBReg(pDM_Odm, rTx_To_Rx, bMaskDWord, 0x6FDB25A4);
1559         ODM_SetBBReg(pDM_Odm, rTx_To_Tx, bMaskDWord, 0x6FDB25A4);
1560         ODM_SetBBReg(pDM_Odm, rRx_CCK, bMaskDWord, 0x6FDB25A4);
1561         ODM_SetBBReg(pDM_Odm, rRx_OFDM, bMaskDWord, 0x6FDB25A4);
1562         ODM_SetBBReg(pDM_Odm, rRx_Wait_RIFS, bMaskDWord, 0x6FDB25A4);
1563         ODM_SetBBReg(pDM_Odm, rRx_TO_Rx, bMaskDWord, 0x6FDB25A4);
1564         ODM_SetBBReg(pDM_Odm, rStandby, bMaskDWord, 0x6FDB25A4);
1565         ODM_SetBBReg(pDM_Odm, rSleep, bMaskDWord, 0x6FDB25A4);
1566         ODM_SetBBReg(pDM_Odm, rPMPD_ANAEN, bMaskDWord, 0x6FDB25A4);
1567         ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_SwitchControl, bMaskDWord, 0x6FDB25A4);
1568         ODM_SetBBReg(pDM_Odm, rBlue_Tooth, bMaskDWord, 0x6FDB25A4);
1569
1570         /*  3 wire Disable */
1571         ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, 0xCCF000C0);
1572
1573         /* BB IQK Setting */
1574         ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800E4);
1575         ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22208000);
1576
1577         /* IQK setting tone@ 4.34Mhz */
1578         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008C1C);
1579         ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00);
1580
1581         /* Page B init */
1582         ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00080000);
1583         ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000);
1584         ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800);
1585         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1f);
1586         ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82150008);
1587         ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28150008);
1588         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x001028d0);
1589
1590         /* RF loop Setting */
1591         ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x0, 0xFFFFF, 0x50008);
1592
1593         /* IQK Single tone start */
1594         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80800000);
1595         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
1596         udelay(1000);
1597         PSD_report_tmp = 0x0;
1598
1599         for (n = 0; n < 2; n++) {
1600                 PSD_report_tmp =  GetPSDData(pDM_Odm, 14, initial_gain);
1601                 if (PSD_report_tmp > AntA_report)
1602                         AntA_report = PSD_report_tmp;
1603         }
1604
1605         PSD_report_tmp = 0x0;
1606
1607         ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_B);  /*  change to Antenna B */
1608         udelay(10);
1609
1610         for (n = 0; n < 2; n++) {
1611                 PSD_report_tmp =  GetPSDData(pDM_Odm, 14, initial_gain);
1612                 if (PSD_report_tmp > AntB_report)
1613                         AntB_report = PSD_report_tmp;
1614         }
1615
1616         /*  change to open case */
1617         ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, 0);  /*  change to Ant A and B all open case */
1618         udelay(10);
1619
1620         for (n = 0; n < 2; n++) {
1621                 PSD_report_tmp =  GetPSDData(pDM_Odm, 14, initial_gain);
1622                 if (PSD_report_tmp > AntO_report)
1623                         AntO_report = PSD_report_tmp;
1624         }
1625
1626         /* Close IQK Single Tone function */
1627         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
1628         PSD_report_tmp = 0x0;
1629
1630         /* 1 Return to antanna A */
1631         ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_A);
1632         ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, Reg88c);
1633         ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, Regc08);
1634         ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, Reg874);
1635         ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, 0x7F, 0x40);
1636         ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord, Regc50);
1637         ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, CurrentChannel);
1638         ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x00, bRFRegOffsetMask, RfLoopReg);
1639
1640         /* Reload AFE Registers */
1641         odm_PHY_ReloadAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16);
1642
1643         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_A[%d]= %d \n", 2416, AntA_report));
1644         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_B[%d]= %d \n", 2416, AntB_report));
1645         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_O[%d]= %d \n", 2416, AntO_report));
1646
1647         /* 2 Test Ant B based on Ant A is ON */
1648         if (mode == ANTTESTB) {
1649                 if (AntA_report >= 100) {
1650                         if (AntB_report > (AntA_report+1)) {
1651                                 pDM_SWAT_Table->ANTB_ON = false;
1652                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Single Antenna A\n"));
1653                         } else {
1654                                 pDM_SWAT_Table->ANTB_ON = true;
1655                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Dual Antenna is A and B\n"));
1656                         }
1657                 } else {
1658                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n"));
1659                         pDM_SWAT_Table->ANTB_ON = false; /*  Set Antenna B off as default */
1660                         bResult = false;
1661                 }
1662         } else if (mode == ANTTESTALL) {
1663                 /* 2 Test Ant A and B based on DPDT Open */
1664                 if ((AntO_report >= 100) & (AntO_report < 118)) {
1665                         if (AntA_report > (AntO_report+1)) {
1666                                 pDM_SWAT_Table->ANTA_ON = false;
1667                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant A is OFF"));
1668                         } else {
1669                                 pDM_SWAT_Table->ANTA_ON = true;
1670                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant A is ON"));
1671                         }
1672
1673                         if (AntB_report > (AntO_report+2)) {
1674                                 pDM_SWAT_Table->ANTB_ON = false;
1675                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant B is OFF"));
1676                         } else {
1677                                 pDM_SWAT_Table->ANTB_ON = true;
1678                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant B is ON"));
1679                         }
1680                 }
1681         } else {
1682                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n"));
1683                 pDM_SWAT_Table->ANTA_ON = true; /*  Set Antenna A on as default */
1684                 pDM_SWAT_Table->ANTB_ON = false; /*  Set Antenna B off as default */
1685                 bResult = false;
1686         }
1687         return bResult;
1688 }
1689
1690 /* Justin: According to the current RRSI to adjust Response Frame TX power, 2012/11/05 */
1691 void odm_dtc(struct dm_odm_t *pDM_Odm)
1692 {
1693 }