drivers/staging/rtl8723au/hal/odm.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  ******************************************************************************/
  15
  16 #include "odm_precomp.h"
  17 #include "usb_ops_linux.h"
  18
  19 static const u16 dB_Invert_Table[8][12] = {
  20         {1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4},
  21         {4, 5, 6, 6, 7, 8, 9, 10, 11, 13, 14, 16},
  22         {18, 20, 22, 25, 28, 32, 35, 40, 45, 50, 56, 63},
  23         {71, 79, 89, 100, 112, 126, 141, 158, 178, 200, 224, 251},
  24         {282, 316, 355, 398, 447, 501, 562, 631, 708, 794, 891, 1000},
  25         {1122, 1259, 1413, 1585, 1778, 1995, 2239, 2512, 2818, 3162, 3548, 3981},
  26         {4467, 5012, 5623, 6310, 7079, 7943, 8913, 10000, 11220, 12589, 14125, 15849},
  27         {17783, 19953, 22387, 25119, 28184, 31623, 35481, 39811, 44668, 50119, 56234, 65535}
  28 };
  29
  30 static u32 EDCAParam[HT_IOT_PEER_MAX][3] = {          /*  UL                    DL */
  31         {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 0:unknown AP */
  32         {0xa44f, 0x5ea44f, 0x5e431c}, /*  1:realtek AP */
  33         {0x5ea42b, 0x5ea42b, 0x5ea42b}, /*  2:unknown AP => realtek_92SE */
  34         {0x5ea32b, 0x5ea42b, 0x5e4322}, /*  3:broadcom AP */
  35         {0x5ea422, 0x00a44f, 0x00a44f}, /*  4:ralink AP */
  36         {0x5ea322, 0x00a630, 0x00a44f}, /*  5:atheros AP */
  37         {0x5e4322, 0x5e4322, 0x5e4322},/*  6:cisco AP */
  38         {0x5ea44f, 0x00a44f, 0x5ea42b}, /*  8:marvell AP */
  39         {0x5ea42b, 0x5ea42b, 0x5ea42b}, /*  10:unknown AP => 92U AP */
  40         {0x5ea42b, 0xa630, 0x5e431c}, /*  11:airgocap AP */
  41 };
  42
  43 /*  EDCA Paramter for AP/ADSL   by Mingzhi 2011-11-22 */
  44
  45 /*  Global var */
  46 u32 OFDMSwingTable23A[OFDM_TABLE_SIZE_92D] = {
  47         0x7f8001fe, /*  0, +6.0dB */
  48         0x788001e2, /*  1, +5.5dB */
  49         0x71c001c7, /*  2, +5.0dB */
  50         0x6b8001ae, /*  3, +4.5dB */
  51         0x65400195, /*  4, +4.0dB */
  52         0x5fc0017f, /*  5, +3.5dB */
  53         0x5a400169, /*  6, +3.0dB */
  54         0x55400155, /*  7, +2.5dB */
  55         0x50800142, /*  8, +2.0dB */
  56         0x4c000130, /*  9, +1.5dB */
  57         0x47c0011f, /*  10, +1.0dB */
  58         0x43c0010f, /*  11, +0.5dB */
  59         0x40000100, /*  12, +0dB */
  60         0x3c8000f2, /*  13, -0.5dB */
  61         0x390000e4, /*  14, -1.0dB */
  62         0x35c000d7, /*  15, -1.5dB */
  63         0x32c000cb, /*  16, -2.0dB */
  64         0x300000c0, /*  17, -2.5dB */
  65         0x2d4000b5, /*  18, -3.0dB */
  66         0x2ac000ab, /*  19, -3.5dB */
  67         0x288000a2, /*  20, -4.0dB */
  68         0x26000098, /*  21, -4.5dB */
  69         0x24000090, /*  22, -5.0dB */
  70         0x22000088, /*  23, -5.5dB */
  71         0x20000080, /*  24, -6.0dB */
  72         0x1e400079, /*  25, -6.5dB */
  73         0x1c800072, /*  26, -7.0dB */
  74         0x1b00006c, /*  27. -7.5dB */
  75         0x19800066, /*  28, -8.0dB */
  76         0x18000060, /*  29, -8.5dB */
  77         0x16c0005b, /*  30, -9.0dB */
  78         0x15800056, /*  31, -9.5dB */
  79         0x14400051, /*  32, -10.0dB */
  80         0x1300004c, /*  33, -10.5dB */
  81         0x12000048, /*  34, -11.0dB */
  82         0x11000044, /*  35, -11.5dB */
  83         0x10000040, /*  36, -12.0dB */
  84         0x0f00003c,/*  37, -12.5dB */
  85         0x0e400039,/*  38, -13.0dB */
  86         0x0d800036,/*  39, -13.5dB */
  87         0x0cc00033,/*  40, -14.0dB */
  88         0x0c000030,/*  41, -14.5dB */
  89         0x0b40002d,/*  42, -15.0dB */
  90 };
  91
  92 u8 CCKSwingTable_Ch1_Ch1323A[CCK_TABLE_SIZE][8] = {
  93         {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /*  0, +0dB */
  94         {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /*  1, -0.5dB */
  95         {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /*  2, -1.0dB */
  96         {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /*  3, -1.5dB */
  97         {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /*  4, -2.0dB */
  98         {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /*  5, -2.5dB */
  99         {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /*  6, -3.0dB */
 100         {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /*  7, -3.5dB */
 101         {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /*  8, -4.0dB */
 102         {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /*  9, -4.5dB */
 103         {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /*  10, -5.0dB */
 104         {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /*  11, -5.5dB */
 105         {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /*  12, -6.0dB */
 106         {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /*  13, -6.5dB */
 107         {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /*  14, -7.0dB */
 108         {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /*  15, -7.5dB */
 109         {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /*  16, -8.0dB */
 110         {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /*  17, -8.5dB */
 111         {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /*  18, -9.0dB */
 112         {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /*  19, -9.5dB */
 113         {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /*  20, -10.0dB */
 114         {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /*  21, -10.5dB */
 115         {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /*  22, -11.0dB */
 116         {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /*  23, -11.5dB */
 117         {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /*  24, -12.0dB */
 118         {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /*  25, -12.5dB */
 119         {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /*  26, -13.0dB */
 120         {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /*  27, -13.5dB */
 121         {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /*  28, -14.0dB */
 122         {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /*  29, -14.5dB */
 123         {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /*  30, -15.0dB */
 124         {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /*  31, -15.5dB */
 125         {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}        /*  32, -16.0dB */
 126 };
 127
 128 u8 CCKSwingTable_Ch1423A[CCK_TABLE_SIZE][8] = {
 129         {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /*  0, +0dB */
 130         {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /*  1, -0.5dB */
 131         {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /*  2, -1.0dB */
 132         {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /*  3, -1.5dB */
 133         {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /*  4, -2.0dB */
 134         {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /*  5, -2.5dB */
 135         {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /*  6, -3.0dB */
 136         {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /*  7, -3.5dB */
 137         {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /*  8, -4.0dB */
 138         {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /*  9, -4.5dB */
 139         {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /*  10, -5.0dB */
 140         {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /*  11, -5.5dB */
 141         {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /*  12, -6.0dB */
 142         {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /*  13, -6.5dB */
 143         {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /*  14, -7.0dB */
 144         {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /*  15, -7.5dB */
 145         {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /*  16, -8.0dB */
 146         {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /*  17, -8.5dB */
 147         {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /*  18, -9.0dB */
 148         {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /*  19, -9.5dB */
 149         {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /*  20, -10.0dB */
 150         {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /*  21, -10.5dB */
 151         {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /*  22, -11.0dB */
 152         {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /*  23, -11.5dB */
 153         {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /*  24, -12.0dB */
 154         {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /*  25, -12.5dB */
 155         {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /*  26, -13.0dB */
 156         {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /*  27, -13.5dB */
 157         {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /*  28, -14.0dB */
 158         {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /*  29, -14.5dB */
 159         {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /*  30, -15.0dB */
 160         {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /*  31, -15.5dB */
 161         {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}        /*  32, -16.0dB */
 162 };
 163
 164 /*  Local Function predefine. */
 165
 166 /* START------------COMMON INFO RELATED--------------- */
 167 void odm_CommonInfoSelfInit23a(struct dm_odm_t *pDM_Odm);
 168
 169 static void odm_CommonInfoSelfUpdate(struct hal_data_8723a *pHalData);
 170
 171 void odm_CmnInfoInit_Debug23a(struct dm_odm_t *pDM_Odm);
 172
 173 void odm_CmnInfoUpdate_Debug23a(struct dm_odm_t *pDM_Odm);
 174
 175 /* START---------------DIG--------------------------- */
 176 void odm_FalseAlarmCounterStatistics23a(struct dm_odm_t *pDM_Odm);
 177
 178 void odm_DIG23aInit(struct dm_odm_t *pDM_Odm);
 179
 180 void odm_DIG23a(struct rtw_adapter *adapter);
 181
 182 void odm_CCKPacketDetectionThresh23a(struct dm_odm_t *pDM_Odm);
 183 /* END---------------DIG--------------------------- */
 184
 185 /* START-------BB POWER SAVE----------------------- */
 186 void odm23a_DynBBPSInit(struct dm_odm_t *pDM_Odm);
 187
 188 void odm_DynamicBBPowerSaving23a(struct dm_odm_t *pDM_Odm);
 189
 190 void odm_1R_CCA23a(struct dm_odm_t *pDM_Odm);
 191 /* END---------BB POWER SAVE----------------------- */
 192
 193 void odm_RefreshRateAdaptiveMask23aMP23a(struct dm_odm_t *pDM_Odm);
 194
 195 void odm_RefreshRateAdaptiveMask23aCE23a(struct dm_odm_t *pDM_Odm);
 196
 197 void odm_RefreshRateAdaptiveMask23aAPADSL23a(struct dm_odm_t *pDM_Odm);
 198
 199 void odm_DynamicTxPower23aInit(struct dm_odm_t *pDM_Odm);
 200
 201 void odm_RSSIMonitorInit(struct dm_odm_t *pDM_Odm);
 202
 203 void odm_RSSIMonitorCheck23aMP(struct dm_odm_t *pDM_Odm);
 204
 205 void odm_RSSIMonitorCheck23aCE(struct dm_odm_t *pDM_Odm);
 206 void odm_RSSIMonitorCheck23aAP(struct dm_odm_t *pDM_Odm);
 207
 208 void odm_RSSIMonitorCheck23a(struct dm_odm_t *pDM_Odm);
 209 void odm_DynamicTxPower23a(struct dm_odm_t *pDM_Odm);
 210
 211 void odm_SwAntDivInit(struct dm_odm_t *pDM_Odm);
 212
 213 void odm_SwAntDivInit_NIC(struct dm_odm_t *pDM_Odm);
 214
 215 void odm_SwAntDivChkAntSwitch(struct dm_odm_t *pDM_Odm, u8 Step);
 216
 217 void odm_SwAntDivChkAntSwitchNIC(struct dm_odm_t *pDM_Odm,
 218                 u8 Step
 219         );
 220
 221 void odm_SwAntDivChkAntSwitchCallback23a(unsigned long data);
 222
 223 void odm_RefreshRateAdaptiveMask23a(struct dm_odm_t *pDM_Odm);
 224
 225 void ODM_TXPowerTrackingCheck23a(struct dm_odm_t *pDM_Odm);
 226
 227 void odm_TXPowerTrackingCheckAP(struct dm_odm_t *pDM_Odm);
 228
 229 void odm_RateAdaptiveMaskInit23a(struct dm_odm_t *pDM_Odm);
 230
 231 void odm_TXPowerTrackingThermalMeterInit23a(struct dm_odm_t *pDM_Odm);
 232
 233 void odm_TXPowerTrackingInit23a(struct dm_odm_t *pDM_Odm);
 234
 235 void odm_TXPowerTrackingCheckMP(struct dm_odm_t *pDM_Odm);
 236
 237 void odm_TXPowerTrackingCheckCE23a(struct dm_odm_t *pDM_Odm);
 238
 239 static void odm_EdcaTurboCheck23a(struct dm_odm_t *pDM_Odm);
 240 static void ODM_EdcaTurboInit23a(struct dm_odm_t *pDM_Odm);
 241
 242 #define         RxDefaultAnt1           0x65a9
 243 #define RxDefaultAnt2           0x569a
 244
 245 void odm_InitHybridAntDiv23a(struct dm_odm_t *pDM_Odm);
 246
 247 bool odm_StaDefAntSel(struct dm_odm_t *pDM_Odm,
 248  u32 OFDM_Ant1_Cnt,
 249  u32 OFDM_Ant2_Cnt,
 250  u32 CCK_Ant1_Cnt,
 251  u32 CCK_Ant2_Cnt,
 252  u8 *pDefAnt
 253         );
 254
 255 void odm_SetRxIdleAnt(struct dm_odm_t *pDM_Odm,
 256         u8 Ant,
 257    bool   bDualPath
 258 );
 259
 260 void odm_HwAntDiv23a(struct dm_odm_t *pDM_Odm);
 261
 262 /* 3 Export Interface */
 263
 264 /*  2011/09/21 MH Add to describe different team necessary resource allocate?? */
 265 void ODM23a_DMInit(struct dm_odm_t *pDM_Odm)
 266 {
 267         /* For all IC series */
 268         odm_CommonInfoSelfInit23a(pDM_Odm);
 269         odm_CmnInfoInit_Debug23a(pDM_Odm);
 270         odm_DIG23aInit(pDM_Odm);
 271         odm_RateAdaptiveMaskInit23a(pDM_Odm);
 272
 273         odm23a_DynBBPSInit(pDM_Odm);
 274         odm_DynamicTxPower23aInit(pDM_Odm);
 275         odm_TXPowerTrackingInit23a(pDM_Odm);
 276         ODM_EdcaTurboInit23a(pDM_Odm);
 277         if ((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)   ||
 278             (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV)  ||
 279             (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV))
 280                 odm_InitHybridAntDiv23a(pDM_Odm);
 281         else if (pDM_Odm->AntDivType == CGCS_RX_SW_ANTDIV)
 282                 odm_SwAntDivInit(pDM_Odm);
 283 }
 284
 285 /*  2011/09/20 MH This is the entry pointer for all team to execute HW out source DM. */
 286 /*  You can not add any dummy function here, be care, you can only use DM structure */
 287 /*  to perform any new ODM_DM. */
 288 void ODM_DMWatchdog23a(struct rtw_adapter *adapter)
 289 {
 290         struct hal_data_8723a *pHalData = GET_HAL_DATA(adapter);
 291         struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
 292         struct pwrctrl_priv *pwrctrlpriv = &adapter->pwrctrlpriv;
 293
 294         /* 2012.05.03 Luke: For all IC series */
 295         odm_CmnInfoUpdate_Debug23a(pDM_Odm);
 296         odm_CommonInfoSelfUpdate(pHalData);
 297         odm_FalseAlarmCounterStatistics23a(pDM_Odm);
 298         odm_RSSIMonitorCheck23a(pDM_Odm);
 299
 300         /* 8723A or 8189ES platform */
 301         /* NeilChen--2012--08--24-- */
 302         /* Fix Leave LPS issue */
 303         if ((pDM_Odm->Adapter->pwrctrlpriv.pwr_mode != PS_MODE_ACTIVE) &&/*  in LPS mode */
 304             (pDM_Odm->SupportICType & ODM_RTL8723A)) {
 305                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("----Step1: odm_DIG23a is in LPS mode\n"));
 306                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("---Step2: 8723AS is in LPS mode\n"));
 307                         odm_DIG23abyRSSI_LPS(pDM_Odm);
 308         } else {
 309                 odm_DIG23a(adapter);
 310         }
 311
 312         odm_CCKPacketDetectionThresh23a(pDM_Odm);
 313
 314         if (pwrctrlpriv->bpower_saving)
 315                 return;
 316
 317         odm_RefreshRateAdaptiveMask23a(pDM_Odm);
 318
 319         odm_DynamicBBPowerSaving23a(pDM_Odm);
 320         if ((pDM_Odm->AntDivType ==  CG_TRX_HW_ANTDIV)  ||
 321             (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV)  ||
 322             (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV))
 323                 odm_HwAntDiv23a(pDM_Odm);
 324         else if (pDM_Odm->AntDivType == CGCS_RX_SW_ANTDIV)
 325                 odm_SwAntDivChkAntSwitch(pDM_Odm, SWAW_STEP_PEAK);
 326
 327         ODM_TXPowerTrackingCheck23a(pDM_Odm);
 328         odm_EdcaTurboCheck23a(pDM_Odm);
 329
 330         odm_dtc(pDM_Odm);
 331 }
 332
 333 /*  */
 334 /*  Init /.. Fixed HW value. Only init time. */
 335 /*  */
 336 void ODM_CmnInfoInit23a(struct dm_odm_t *pDM_Odm,
 337                 enum odm_cmninfo CmnInfo,
 338                 u32 Value
 339         )
 340 {
 341         /* ODM_RT_TRACE(pDM_Odm,); */
 342
 343         /*  */
 344         /*  This section is used for init value */
 345         /*  */
 346         switch  (CmnInfo) {
 347         /*  Fixed ODM value. */
 348         case    ODM_CMNINFO_PLATFORM:
 349                 break;
 350         case    ODM_CMNINFO_INTERFACE:
 351                 pDM_Odm->SupportInterface = (u8)Value;
 352                 break;
 353         case    ODM_CMNINFO_MP_TEST_CHIP:
 354                 pDM_Odm->bIsMPChip = (u8)Value;
 355                 break;
 356         case    ODM_CMNINFO_IC_TYPE:
 357                 pDM_Odm->SupportICType = Value;
 358                 break;
 359         case    ODM_CMNINFO_CUT_VER:
 360                 pDM_Odm->CutVersion = (u8)Value;
 361                 break;
 362         case    ODM_CMNINFO_FAB_VER:
 363                 pDM_Odm->FabVersion = (u8)Value;
 364                 break;
 365         case    ODM_CMNINFO_RF_TYPE:
 366                 pDM_Odm->RFType = (u8)Value;
 367                 break;
 368         case    ODM_CMNINFO_RF_ANTENNA_TYPE:
 369                 pDM_Odm->AntDivType = (u8)Value;
 370                 break;
 371         case    ODM_CMNINFO_BOARD_TYPE:
 372                 pDM_Odm->BoardType = (u8)Value;
 373                 break;
 374         case    ODM_CMNINFO_EXT_LNA:
 375                 pDM_Odm->ExtLNA = (u8)Value;
 376                 break;
 377         case    ODM_CMNINFO_EXT_PA:
 378                 pDM_Odm->ExtPA = (u8)Value;
 379                 break;
 380         case    ODM_CMNINFO_EXT_TRSW:
 381                 pDM_Odm->ExtTRSW = (u8)Value;
 382                 break;
 383         case    ODM_CMNINFO_PATCH_ID:
 384                 pDM_Odm->PatchID = (u8)Value;
 385                 break;
 386         case    ODM_CMNINFO_BINHCT_TEST:
 387                 pDM_Odm->bInHctTest = (bool)Value;
 388                 break;
 389         case    ODM_CMNINFO_BWIFI_TEST:
 390                 pDM_Odm->bWIFITest = (bool)Value;
 391                 break;
 392         case    ODM_CMNINFO_SMART_CONCURRENT:
 393                 pDM_Odm->bDualMacSmartConcurrent = (bool)Value;
 394                 break;
 395         /* To remove the compiler warning, must add an empty default statement to handle the other values. */
 396         default:
 397                 /* do nothing */
 398                 break;
 399         }
 400
 401         /*  */
 402         /*  Tx power tracking BB swing table. */
 403         /*  The base index = 12. +((12-n)/2)dB 13~?? = decrease tx pwr by -((n-12)/2)dB */
 404         /*  */
 405         pDM_Odm->BbSwingIdxOfdm                 = 12; /*  Set defalut value as index 12. */
 406         pDM_Odm->BbSwingIdxOfdmCurrent  = 12;
 407         pDM_Odm->BbSwingFlagOfdm                = false;
 408
 409 }
 410
 411 void ODM23a_CmnInfoHook(struct dm_odm_t *pDM_Odm,
 412                 enum odm_cmninfo CmnInfo,
 413                 void *pValue
 414         )
 415 {
 416         /*  Hook call by reference pointer. */
 417         switch  (CmnInfo) {
 418         /*  Dynamic call by reference pointer. */
 419         /* To remove the compiler warning, must add an empty default statement to handle the other values. */
 420         default:
 421                 /* do nothing */
 422                 break;
 423         }
 424 }
 425
 426 void ODM_CmnInfoPtrArrayHook23a(struct dm_odm_t *pDM_Odm, enum odm_cmninfo CmnInfo,
 427                                 u16 Index, void *pValue)
 428 {
 429         /*  Hook call by reference pointer. */
 430         switch  (CmnInfo) {
 431         /*  Dynamic call by reference pointer. */
 432         case    ODM_CMNINFO_STA_STATUS:
 433                 pDM_Odm->pODM_StaInfo[Index] = (struct sta_info *)pValue;
 434                 break;
 435         /* To remove the compiler warning, must add an empty default statement to handle the other values. */
 436         default:
 437                 /* do nothing */
 438                 break;
 439         }
 440 }
 441
 442 /*  Update Band/CHannel/.. The values are dynamic but non-per-packet. */
 443 void ODM_CmnInfoUpdate23a(struct dm_odm_t *pDM_Odm, u32 CmnInfo, u64 Value)
 444 {
 445         /*  This init variable may be changed in run time. */
 446         switch  (CmnInfo) {
 447         case    ODM_CMNINFO_RF_TYPE:
 448                 pDM_Odm->RFType = (u8)Value;
 449                 break;
 450         case    ODM_CMNINFO_WIFI_DIRECT:
 451                 pDM_Odm->bWIFI_Direct = (bool)Value;
 452                 break;
 453         case    ODM_CMNINFO_WIFI_DISPLAY:
 454                 pDM_Odm->bWIFI_Display = (bool)Value;
 455                 break;
 456         case    ODM_CMNINFO_LINK:
 457                 pDM_Odm->bLinked = (bool)Value;
 458                 break;
 459         case    ODM_CMNINFO_RSSI_MIN:
 460                 pDM_Odm->RSSI_Min = (u8)Value;
 461                 break;
 462         case    ODM_CMNINFO_DBG_COMP:
 463                 pDM_Odm->DebugComponents = Value;
 464                 break;
 465         case    ODM_CMNINFO_DBG_LEVEL:
 466                 pDM_Odm->DebugLevel = (u32)Value;
 467                 break;
 468         case    ODM_CMNINFO_RA_THRESHOLD_HIGH:
 469                 pDM_Odm->RateAdaptive.HighRSSIThresh = (u8)Value;
 470                 break;
 471         case    ODM_CMNINFO_RA_THRESHOLD_LOW:
 472                 pDM_Odm->RateAdaptive.LowRSSIThresh = (u8)Value;
 473                 break;
 474         }
 475
 476 }
 477
 478 void odm_CommonInfoSelfInit23a(struct dm_odm_t *pDM_Odm
 479         )
 480 {
 481         pDM_Odm->bCckHighPower = (bool) ODM_GetBBReg(pDM_Odm, 0x824, BIT(9));
 482         pDM_Odm->RFPathRxEnable = (u8) ODM_GetBBReg(pDM_Odm, 0xc04, 0x0F);
 483         if (pDM_Odm->SupportICType & ODM_RTL8723A)
 484                 pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;
 485
 486         ODM_InitDebugSetting23a(pDM_Odm);
 487 }
 488
 489 static void odm_CommonInfoSelfUpdate(struct hal_data_8723a *pHalData)
 490 {
 491         struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
 492         struct sta_info *pEntry;
 493         u8 EntryCnt = 0;
 494         u8 i;
 495
 496         if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40) {
 497                 if (pHalData->nCur40MhzPrimeSC == 1)
 498                         pDM_Odm->ControlChannel = pHalData->CurrentChannel - 2;
 499                 else if (pHalData->nCur40MhzPrimeSC == 2)
 500                         pDM_Odm->ControlChannel = pHalData->CurrentChannel + 2;
 501         } else {
 502                 pDM_Odm->ControlChannel = pHalData->CurrentChannel;
 503         }
 504
 505         for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
 506                 pEntry = pDM_Odm->pODM_StaInfo[i];
 507                 if (pEntry)
 508                         EntryCnt++;
 509         }
 510         if (EntryCnt == 1)
 511                 pDM_Odm->bOneEntryOnly = true;
 512         else
 513                 pDM_Odm->bOneEntryOnly = false;
 514 }
 515
 516 void odm_CmnInfoInit_Debug23a(struct dm_odm_t *pDM_Odm)
 517 {
 518         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoInit_Debug23a ==>\n"));
 519         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportAbility = 0x%x\n", pDM_Odm->SupportAbility));
 520         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportInterface =%d\n", pDM_Odm->SupportInterface));
 521         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportICType = 0x%x\n", pDM_Odm->SupportICType));
 522         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("CutVersion =%d\n", pDM_Odm->CutVersion));
 523         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("FabVersion =%d\n", pDM_Odm->FabVersion));
 524         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RFType =%d\n", pDM_Odm->RFType));
 525         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("BoardType =%d\n", pDM_Odm->BoardType));
 526         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtLNA =%d\n", pDM_Odm->ExtLNA));
 527         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtPA =%d\n", pDM_Odm->ExtPA));
 528         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtTRSW =%d\n", pDM_Odm->ExtTRSW));
 529         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("PatchID =%d\n", pDM_Odm->PatchID));
 530         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bInHctTest =%d\n", pDM_Odm->bInHctTest));
 531         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFITest =%d\n", pDM_Odm->bWIFITest));
 532         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bDualMacSmartConcurrent =%d\n", pDM_Odm->bDualMacSmartConcurrent));
 533
 534 }
 535
 536 void odm_CmnInfoUpdate_Debug23a(struct dm_odm_t *pDM_Odm)
 537 {
 538         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoUpdate_Debug23a ==>\n"));
 539         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Direct =%d\n", pDM_Odm->bWIFI_Direct));
 540         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Display =%d\n", pDM_Odm->bWIFI_Display));
 541         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bLinked =%d\n", pDM_Odm->bLinked));
 542         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RSSI_Min =%d\n", pDM_Odm->RSSI_Min));
 543 }
 544
 545 void ODM_Write_DIG23a(struct dm_odm_t *pDM_Odm,
 546         u8 CurrentIGI
 547         )
 548 {
 549         struct dig_t *pDM_DigTable = &pDM_Odm->DM_DigTable;
 550
 551         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("ODM_REG(IGI_A, pDM_Odm) = 0x%x, ODM_BIT(IGI, pDM_Odm) = 0x%x \n",
 552                 ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm)));
 553
 554         if (pDM_DigTable->CurIGValue != CurrentIGI) {
 555                 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI);
 556                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("CurrentIGI(0x%02x). \n", CurrentIGI));
 557                 pDM_DigTable->CurIGValue = CurrentIGI;
 558         }
 559         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
 560                      ("ODM_Write_DIG23a():CurrentIGI = 0x%x \n", CurrentIGI));
 561 }
 562
 563 /* Need LPS mode for CE platform --2012--08--24--- */
 564 /* 8723AS/8189ES */
 565 void odm_DIG23abyRSSI_LPS(struct dm_odm_t *pDM_Odm)
 566 {
 567         struct rtw_adapter *pAdapter = pDM_Odm->Adapter;
 568         struct false_alarm_stats *pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
 569         u8 RSSI_Lower = DM_DIG_MIN_NIC;   /* 0x1E or 0x1C */
 570         u8 bFwCurrentInPSMode = false;
 571         u8 CurrentIGI = pDM_Odm->RSSI_Min;
 572
 573         if (!(pDM_Odm->SupportICType & ODM_RTL8723A))
 574                 return;
 575
 576         CurrentIGI = CurrentIGI+RSSI_OFFSET_DIG;
 577         bFwCurrentInPSMode = pAdapter->pwrctrlpriv.bFwCurrentInPSMode;
 578
 579         /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG_LPS, ODM_DBG_LOUD, ("odm_DIG23a() ==>\n")); */
 580
 581         /*  Using FW PS mode to make IGI */
 582         if (bFwCurrentInPSMode) {
 583                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("---Neil---odm_DIG23a is in LPS mode\n"));
 584                 /* Adjust by  FA in LPS MODE */
 585                 if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2_LPS)
 586                         CurrentIGI = CurrentIGI+2;
 587                 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1_LPS)
 588                         CurrentIGI = CurrentIGI+1;
 589                 else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0_LPS)
 590                         CurrentIGI = CurrentIGI-1;
 591         } else {
 592                 CurrentIGI = RSSI_Lower;
 593         }
 594
 595         /* Lower bound checking */
 596
 597         /* RSSI Lower bound check */
 598         if ((pDM_Odm->RSSI_Min-10) > DM_DIG_MIN_NIC)
 599                 RSSI_Lower = (pDM_Odm->RSSI_Min-10);
 600         else
 601                 RSSI_Lower = DM_DIG_MIN_NIC;
 602
 603         /* Upper and Lower Bound checking */
 604          if (CurrentIGI > DM_DIG_MAX_NIC)
 605                 CurrentIGI = DM_DIG_MAX_NIC;
 606          else if (CurrentIGI < RSSI_Lower)
 607                 CurrentIGI = RSSI_Lower;
 608
 609         ODM_Write_DIG23a(pDM_Odm, CurrentIGI);/* ODM_Write_DIG23a(pDM_Odm, pDM_DigTable->CurIGValue); */
 610
 611 }
 612
 613 void odm_DIG23aInit(struct dm_odm_t *pDM_Odm)
 614 {
 615         struct dig_t *pDM_DigTable = &pDM_Odm->DM_DigTable;
 616
 617         pDM_DigTable->CurIGValue = (u8) ODM_GetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm));
 618         pDM_DigTable->RssiLowThresh     = DM_DIG_THRESH_LOW;
 619         pDM_DigTable->RssiHighThresh    = DM_DIG_THRESH_HIGH;
 620         pDM_DigTable->FALowThresh       = DM_FALSEALARM_THRESH_LOW;
 621         pDM_DigTable->FAHighThresh      = DM_FALSEALARM_THRESH_HIGH;
 622         if (pDM_Odm->BoardType == ODM_BOARD_HIGHPWR) {
 623                 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
 624                 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC;
 625         } else {
 626                 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
 627                 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC;
 628         }
 629         pDM_DigTable->BackoffVal = DM_DIG_BACKOFF_DEFAULT;
 630         pDM_DigTable->BackoffVal_range_max = DM_DIG_BACKOFF_MAX;
 631         pDM_DigTable->BackoffVal_range_min = DM_DIG_BACKOFF_MIN;
 632         pDM_DigTable->PreCCK_CCAThres = 0xFF;
 633         pDM_DigTable->CurCCK_CCAThres = 0x83;
 634         pDM_DigTable->ForbiddenIGI = DM_DIG_MIN_NIC;
 635         pDM_DigTable->LargeFAHit = 0;
 636         pDM_DigTable->Recover_cnt = 0;
 637         pDM_DigTable->DIG_Dynamic_MIN_0 = DM_DIG_MIN_NIC;
 638         pDM_DigTable->DIG_Dynamic_MIN_1 = DM_DIG_MIN_NIC;
 639         pDM_DigTable->bMediaConnect_0 = false;
 640         pDM_DigTable->bMediaConnect_1 = false;
 641 }
 642
 643 void odm_DIG23a(struct rtw_adapter *adapter)
 644 {
 645         struct hal_data_8723a *pHalData = GET_HAL_DATA(adapter);
 646         struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
 647         struct dig_t *pDM_DigTable = &pDM_Odm->DM_DigTable;
 648         struct false_alarm_stats *pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
 649         u8 DIG_Dynamic_MIN;
 650         u8 DIG_MaxOfMin;
 651         bool FirstConnect, FirstDisConnect;
 652         u8 dm_dig_max, dm_dig_min;
 653         u8 CurrentIGI = pDM_DigTable->CurIGValue;
 654
 655         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a() ==>\n"));
 656         /* if (!(pDM_Odm->SupportAbility & (ODM_BB_DIG|ODM_BB_FA_CNT))) */
 657         if ((!(pDM_Odm->SupportAbility&ODM_BB_DIG)) || (!(pDM_Odm->SupportAbility&ODM_BB_FA_CNT))) {
 658                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
 659                              ("odm_DIG23a() Return: SupportAbility ODM_BB_DIG or ODM_BB_FA_CNT is disabled\n"));
 660                 return;
 661         }
 662
 663         if (adapter->mlmepriv.bScanInProcess) {
 664                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a() Return: In Scan Progress \n"));
 665                 return;
 666         }
 667
 668         DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0;
 669         FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_0);
 670         FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0);
 671
 672         /* 1 Boundary Decision */
 673         if ((pDM_Odm->SupportICType & ODM_RTL8723A) &&
 674             ((pDM_Odm->BoardType == ODM_BOARD_HIGHPWR) || pDM_Odm->ExtLNA)) {
 675                 dm_dig_max = DM_DIG_MAX_NIC_HP;
 676                 dm_dig_min = DM_DIG_MIN_NIC_HP;
 677                 DIG_MaxOfMin = DM_DIG_MAX_AP_HP;
 678         } else {
 679                 dm_dig_max = DM_DIG_MAX_NIC;
 680                 dm_dig_min = DM_DIG_MIN_NIC;
 681                 DIG_MaxOfMin = DM_DIG_MAX_AP;
 682         }
 683
 684         if (pDM_Odm->bLinked) {
 685               /* 2 8723A Series, offset need to be 10 */
 686                 if (pDM_Odm->SupportICType == ODM_RTL8723A) {
 687                         /* 2 Upper Bound */
 688                         if ((pDM_Odm->RSSI_Min + 10) > DM_DIG_MAX_NIC)
 689                                 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
 690                         else if ((pDM_Odm->RSSI_Min + 10) < DM_DIG_MIN_NIC)
 691                                 pDM_DigTable->rx_gain_range_max = DM_DIG_MIN_NIC;
 692                         else
 693                                 pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 10;
 694
 695                         /* 2 If BT is Concurrent, need to set Lower Bound */
 696                         DIG_Dynamic_MIN = DM_DIG_MIN_NIC;
 697                 } else {
 698                         /* 2 Modify DIG upper bound */
 699                         if ((pDM_Odm->RSSI_Min + 20) > dm_dig_max)
 700                                 pDM_DigTable->rx_gain_range_max = dm_dig_max;
 701                         else if ((pDM_Odm->RSSI_Min + 20) < dm_dig_min)
 702                                 pDM_DigTable->rx_gain_range_max = dm_dig_min;
 703                         else
 704                                 pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 20;
 705
 706                         /* 2 Modify DIG lower bound */
 707                         if (pDM_Odm->bOneEntryOnly) {
 708                                 if (pDM_Odm->RSSI_Min < dm_dig_min)
 709                                         DIG_Dynamic_MIN = dm_dig_min;
 710                                 else if (pDM_Odm->RSSI_Min > DIG_MaxOfMin)
 711                                         DIG_Dynamic_MIN = DIG_MaxOfMin;
 712                                 else
 713                                         DIG_Dynamic_MIN = pDM_Odm->RSSI_Min;
 714                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
 715                                              ("odm_DIG23a() : bOneEntryOnly = true,  DIG_Dynamic_MIN = 0x%x\n",
 716                                              DIG_Dynamic_MIN));
 717                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
 718                                              ("odm_DIG23a() : pDM_Odm->RSSI_Min =%d\n",
 719                                              pDM_Odm->RSSI_Min));
 720                         } else {
 721                                 DIG_Dynamic_MIN = dm_dig_min;
 722                         }
 723                 }
 724         } else {
 725                 pDM_DigTable->rx_gain_range_max = dm_dig_max;
 726                 DIG_Dynamic_MIN = dm_dig_min;
 727                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a() : No Link\n"));
 728         }
 729
 730         /* 1 Modify DIG lower bound, deal with abnormally large false alarm */
 731         if (pFalseAlmCnt->Cnt_all > 10000) {
 732                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
 733                              ("dm_DIG(): Abnornally false alarm case. \n"));
 734
 735                 if (pDM_DigTable->LargeFAHit != 3)
 736                         pDM_DigTable->LargeFAHit++;
 737                 if (pDM_DigTable->ForbiddenIGI < CurrentIGI) {
 738                         pDM_DigTable->ForbiddenIGI = CurrentIGI;
 739                         pDM_DigTable->LargeFAHit = 1;
 740                 }
 741
 742                 if (pDM_DigTable->LargeFAHit >= 3) {
 743                         if ((pDM_DigTable->ForbiddenIGI+1) > pDM_DigTable->rx_gain_range_max)
 744                                 pDM_DigTable->rx_gain_range_min = pDM_DigTable->rx_gain_range_max;
 745                         else
 746                                 pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1);
 747                         pDM_DigTable->Recover_cnt = 3600; /* 3600 = 2hr */
 748                 }
 749         } else {
 750                 /* Recovery mechanism for IGI lower bound */
 751                 if (pDM_DigTable->Recover_cnt != 0) {
 752                         pDM_DigTable->Recover_cnt--;
 753                 } else {
 754                         if (pDM_DigTable->LargeFAHit < 3) {
 755                                 if ((pDM_DigTable->ForbiddenIGI - 1) < DIG_Dynamic_MIN) {
 756                                         pDM_DigTable->ForbiddenIGI = DIG_Dynamic_MIN; /* DM_DIG_MIN; */
 757                                         pDM_DigTable->rx_gain_range_min = DIG_Dynamic_MIN; /* DM_DIG_MIN; */
 758                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
 759                                                      ("odm_DIG23a(): Normal Case: At Lower Bound\n"));
 760                                 } else {
 761                                         pDM_DigTable->ForbiddenIGI--;
 762                                         pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1);
 763                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
 764                                                      ("odm_DIG23a(): Normal Case: Approach Lower Bound\n"));
 765                                 }
 766                         } else {
 767                                 pDM_DigTable->LargeFAHit = 0;
 768                         }
 769                 }
 770         }
 771         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): pDM_DigTable->LargeFAHit =%d\n", pDM_DigTable->LargeFAHit));
 772
 773         /* 1 Adjust initial gain by false alarm */
 774         if (pDM_Odm->bLinked) {
 775                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): DIG AfterLink\n"));
 776                 if (FirstConnect) {
 777                         CurrentIGI = pDM_Odm->RSSI_Min;
 778                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: First Connect\n"));
 779                 } else {
 780                         if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2)
 781                                 CurrentIGI = CurrentIGI + 4;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */
 782                         else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1)
 783                                 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */
 784                         else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0)
 785                                 CurrentIGI = CurrentIGI - 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue-1; */
 786                 }
 787         } else {
 788                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): DIG BeforeLink\n"));
 789                 if (FirstDisConnect) {
 790                         CurrentIGI = pDM_DigTable->rx_gain_range_min;
 791                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): First DisConnect \n"));
 792                 } else {
 793                         /* 2012.03.30 LukeLee: enable DIG before link but with very high thresholds */
 794                         if (pFalseAlmCnt->Cnt_all > 10000)
 795                                 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */
 796                         else if (pFalseAlmCnt->Cnt_all > 8000)
 797                                 CurrentIGI = CurrentIGI + 1;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */
 798                         else if (pFalseAlmCnt->Cnt_all < 500)
 799                                 CurrentIGI = CurrentIGI - 1;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue-1; */
 800                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): England DIG \n"));
 801                 }
 802         }
 803         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): DIG End Adjust IGI\n"));
 804         /* 1 Check initial gain by upper/lower bound */
 805         if (CurrentIGI > pDM_DigTable->rx_gain_range_max)
 806                 CurrentIGI = pDM_DigTable->rx_gain_range_max;
 807         if (CurrentIGI < pDM_DigTable->rx_gain_range_min)
 808                 CurrentIGI = pDM_DigTable->rx_gain_range_min;
 809
 810         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): rx_gain_range_max = 0x%x, rx_gain_range_min = 0x%x\n",
 811                 pDM_DigTable->rx_gain_range_max, pDM_DigTable->rx_gain_range_min));
 812         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): TotalFA =%d\n", pFalseAlmCnt->Cnt_all));
 813         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): CurIGValue = 0x%x\n", CurrentIGI));
 814
 815         /* 2 High power RSSI threshold */
 816
 817         ODM_Write_DIG23a(pDM_Odm, CurrentIGI);/* ODM_Write_DIG23a(pDM_Odm, pDM_DigTable->CurIGValue); */
 818         pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked;
 819         pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN;
 820 }
 821
 822 /* 3 ============================================================ */
 823 /* 3 FASLE ALARM CHECK */
 824 /* 3 ============================================================ */
 825
 826 void odm_FalseAlarmCounterStatistics23a(struct dm_odm_t *pDM_Odm)
 827 {
 828         u32 ret_value;
 829         struct false_alarm_stats *FalseAlmCnt = &pDM_Odm->FalseAlmCnt;
 830
 831         if (!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT))
 832                 return;
 833
 834         /* hold ofdm counter */
 835          /* hold page C counter */
 836         ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT(31), 1);
 837         /* hold page D counter */
 838         ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(31), 1);
 839         ret_value =
 840                 ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE1_11N, bMaskDWord);
 841         FalseAlmCnt->Cnt_Fast_Fsync = (ret_value&0xffff);
 842         FalseAlmCnt->Cnt_SB_Search_fail = ((ret_value&0xffff0000)>>16);
 843         ret_value =
 844                 ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE2_11N, bMaskDWord);
 845         FalseAlmCnt->Cnt_OFDM_CCA = (ret_value&0xffff);
 846         FalseAlmCnt->Cnt_Parity_Fail = ((ret_value&0xffff0000)>>16);
 847         ret_value =
 848                 ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE3_11N, bMaskDWord);
 849         FalseAlmCnt->Cnt_Rate_Illegal = (ret_value&0xffff);
 850         FalseAlmCnt->Cnt_Crc8_fail = ((ret_value&0xffff0000)>>16);
 851         ret_value =
 852                 ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE4_11N, bMaskDWord);
 853         FalseAlmCnt->Cnt_Mcs_fail = (ret_value&0xffff);
 854
 855         FalseAlmCnt->Cnt_Ofdm_fail = FalseAlmCnt->Cnt_Parity_Fail +
 856                 FalseAlmCnt->Cnt_Rate_Illegal +
 857                 FalseAlmCnt->Cnt_Crc8_fail +
 858                 FalseAlmCnt->Cnt_Mcs_fail +
 859                 FalseAlmCnt->Cnt_Fast_Fsync +
 860                 FalseAlmCnt->Cnt_SB_Search_fail;
 861         /* hold cck counter */
 862         ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT(12), 1);
 863         ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT(14), 1);
 864
 865         ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_LSB_11N, bMaskByte0);
 866         FalseAlmCnt->Cnt_Cck_fail = ret_value;
 867         ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_MSB_11N, bMaskByte3);
 868         FalseAlmCnt->Cnt_Cck_fail +=  (ret_value & 0xff) << 8;
 869
 870         ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_CCA_CNT_11N, bMaskDWord);
 871         FalseAlmCnt->Cnt_CCK_CCA =
 872                 ((ret_value&0xFF)<<8) | ((ret_value&0xFF00)>>8);
 873
 874         FalseAlmCnt->Cnt_all = (FalseAlmCnt->Cnt_Fast_Fsync +
 875                                 FalseAlmCnt->Cnt_SB_Search_fail +
 876                                 FalseAlmCnt->Cnt_Parity_Fail +
 877                                 FalseAlmCnt->Cnt_Rate_Illegal +
 878                                 FalseAlmCnt->Cnt_Crc8_fail +
 879                                 FalseAlmCnt->Cnt_Mcs_fail +
 880                                 FalseAlmCnt->Cnt_Cck_fail);
 881
 882         FalseAlmCnt->Cnt_CCA_all =
 883                 FalseAlmCnt->Cnt_OFDM_CCA + FalseAlmCnt->Cnt_CCK_CCA;
 884
 885         if (pDM_Odm->SupportICType >= ODM_RTL8723A) {
 886                 /* reset false alarm counter registers */
 887                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT(31), 1);
 888                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT(31), 0);
 889                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(27), 1);
 890                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(27), 0);
 891                 /* update ofdm counter */
 892                  /* update page C counter */
 893                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT(31), 0);
 894                  /* update page D counter */
 895                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(31), 0);
 896
 897                 /* reset CCK CCA counter */
 898                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N,
 899                              BIT(13) | BIT(12), 0);
 900                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N,
 901                              BIT(13) | BIT(12), 2);
 902                 /* reset CCK FA counter */
 903                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N,
 904                              BIT(15) | BIT(14), 0);
 905                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N,
 906                              BIT(15) | BIT(14), 2);
 907         }
 908
 909         ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD,
 910                      ("Enter odm_FalseAlarmCounterStatistics23a\n"));
 911         ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD,
 912                      ("Cnt_Fast_Fsync =%d, Cnt_SB_Search_fail =%d\n",
 913                       FalseAlmCnt->Cnt_Fast_Fsync,
 914                       FalseAlmCnt->Cnt_SB_Search_fail));
 915         ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD,
 916                      ("Cnt_Parity_Fail =%d, Cnt_Rate_Illegal =%d\n",
 917                       FalseAlmCnt->Cnt_Parity_Fail,
 918                       FalseAlmCnt->Cnt_Rate_Illegal));
 919         ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD,
 920                      ("Cnt_Crc8_fail =%d, Cnt_Mcs_fail =%d\n",
 921                       FalseAlmCnt->Cnt_Crc8_fail, FalseAlmCnt->Cnt_Mcs_fail));
 922
 923         ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Cck_fail =%d\n", FalseAlmCnt->Cnt_Cck_fail));
 924         ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Ofdm_fail =%d\n", FalseAlmCnt->Cnt_Ofdm_fail));
 925         ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Total False Alarm =%d\n", FalseAlmCnt->Cnt_all));
 926 }
 927
 928 /* 3 ============================================================ */
 929 /* 3 CCK Packet Detect Threshold */
 930 /* 3 ============================================================ */
 931
 932 void odm_CCKPacketDetectionThresh23a(struct dm_odm_t *pDM_Odm)
 933 {
 934         struct false_alarm_stats *FalseAlmCnt = &pDM_Odm->FalseAlmCnt;
 935         u8 CurCCK_CCAThres;
 936
 937         if (!(pDM_Odm->SupportAbility & (ODM_BB_CCK_PD|ODM_BB_FA_CNT)))
 938                 return;
 939
 940         if (pDM_Odm->ExtLNA)
 941                 return;
 942
 943         if (pDM_Odm->bLinked) {
 944                 if (pDM_Odm->RSSI_Min > 25) {
 945                         CurCCK_CCAThres = 0xcd;
 946                 } else if ((pDM_Odm->RSSI_Min <= 25) && (pDM_Odm->RSSI_Min > 10)) {
 947                         CurCCK_CCAThres = 0x83;
 948                 } else {
 949                         if (FalseAlmCnt->Cnt_Cck_fail > 1000)
 950                                 CurCCK_CCAThres = 0x83;
 951                         else
 952                                 CurCCK_CCAThres = 0x40;
 953                 }
 954         } else {
 955                 if (FalseAlmCnt->Cnt_Cck_fail > 1000)
 956                         CurCCK_CCAThres = 0x83;
 957                 else
 958                         CurCCK_CCAThres = 0x40;
 959         }
 960
 961         ODM_Write_CCK_CCA_Thres23a(pDM_Odm, CurCCK_CCAThres);
 962 }
 963
 964 void ODM_Write_CCK_CCA_Thres23a(struct dm_odm_t *pDM_Odm, u8 CurCCK_CCAThres)
 965 {
 966         struct dig_t *pDM_DigTable = &pDM_Odm->DM_DigTable;
 967
 968         if (pDM_DigTable->CurCCK_CCAThres != CurCCK_CCAThres)
 969                 ODM_Write1Byte(pDM_Odm, ODM_REG(CCK_CCA, pDM_Odm), CurCCK_CCAThres);
 970         pDM_DigTable->PreCCK_CCAThres = pDM_DigTable->CurCCK_CCAThres;
 971         pDM_DigTable->CurCCK_CCAThres = CurCCK_CCAThres;
 972
 973 }
 974
 975 /* 3 ============================================================ */
 976 /* 3 BB Power Save */
 977 /* 3 ============================================================ */
 978 void odm23a_DynBBPSInit(struct dm_odm_t *pDM_Odm)
 979 {
 980         struct dynamic_pwr_sav *pDM_PSTable = &pDM_Odm->DM_PSTable;
 981
 982         pDM_PSTable->PreCCAState = CCA_MAX;
 983         pDM_PSTable->CurCCAState = CCA_MAX;
 984         pDM_PSTable->PreRFState = RF_MAX;
 985         pDM_PSTable->CurRFState = RF_MAX;
 986         pDM_PSTable->Rssi_val_min = 0;
 987         pDM_PSTable->initialize = 0;
 988 }
 989
 990 void odm_DynamicBBPowerSaving23a(struct dm_odm_t *pDM_Odm)
 991 {
 992         return;
 993 }
 994
 995 void odm_1R_CCA23a(struct dm_odm_t *pDM_Odm)
 996 {
 997         struct dynamic_pwr_sav *pDM_PSTable = &pDM_Odm->DM_PSTable;
 998
 999         if (pDM_Odm->RSSI_Min != 0xFF) {
1000                 if (pDM_PSTable->PreCCAState == CCA_2R) {
1001                         if (pDM_Odm->RSSI_Min >= 35)
1002                                 pDM_PSTable->CurCCAState = CCA_1R;
1003                         else
1004                                 pDM_PSTable->CurCCAState = CCA_2R;
1005                 } else {
1006                         if (pDM_Odm->RSSI_Min <= 30)
1007                                 pDM_PSTable->CurCCAState = CCA_2R;
1008                         else
1009                                 pDM_PSTable->CurCCAState = CCA_1R;
1010                 }
1011         } else {
1012                 pDM_PSTable->CurCCAState = CCA_MAX;
1013         }
1014
1015         if (pDM_PSTable->PreCCAState != pDM_PSTable->CurCCAState) {
1016                 if (pDM_PSTable->CurCCAState == CCA_1R) {
1017                         if (pDM_Odm->RFType == ODM_2T2R)
1018                                 ODM_SetBBReg(pDM_Odm, 0xc04, bMaskByte0, 0x13);
1019                         else
1020                                 ODM_SetBBReg(pDM_Odm, 0xc04, bMaskByte0, 0x23);
1021                 } else {
1022                         ODM_SetBBReg(pDM_Odm, 0xc04, bMaskByte0, 0x33);
1023                         /* PHY_SetBBReg(pAdapter, 0xe70, bMaskByte3, 0x63); */
1024                 }
1025                 pDM_PSTable->PreCCAState = pDM_PSTable->CurCCAState;
1026         }
1027 }
1028
1029 void ODM_RF_Saving23a(struct dm_odm_t *pDM_Odm, u8 bForceInNormal)
1030 {
1031         struct dynamic_pwr_sav *pDM_PSTable = &pDM_Odm->DM_PSTable;
1032         u8 Rssi_Up_bound = 30 ;
1033         u8 Rssi_Low_bound = 25;
1034         if (pDM_Odm->PatchID == 40) { /* RT_CID_819x_FUNAI_TV */
1035                 Rssi_Up_bound = 50 ;
1036                 Rssi_Low_bound = 45;
1037         }
1038         if (pDM_PSTable->initialize == 0) {
1039
1040                 pDM_PSTable->Reg874 = (ODM_GetBBReg(pDM_Odm, 0x874, bMaskDWord)&0x1CC000)>>14;
1041                 pDM_PSTable->RegC70 =
1042                         (ODM_GetBBReg(pDM_Odm, 0xc70, bMaskDWord) & BIT(3)) >>3;
1043                 pDM_PSTable->Reg85C = (ODM_GetBBReg(pDM_Odm, 0x85c, bMaskDWord)&0xFF000000)>>24;
1044                 pDM_PSTable->RegA74 = (ODM_GetBBReg(pDM_Odm, 0xa74, bMaskDWord)&0xF000)>>12;
1045                 /* Reg818 = PHY_QueryBBReg(pAdapter, 0x818, bMaskDWord); */
1046                 pDM_PSTable->initialize = 1;
1047         }
1048
1049         if (!bForceInNormal) {
1050                 if (pDM_Odm->RSSI_Min != 0xFF) {
1051                         if (pDM_PSTable->PreRFState == RF_Normal) {
1052                                 if (pDM_Odm->RSSI_Min >= Rssi_Up_bound)
1053                                         pDM_PSTable->CurRFState = RF_Save;
1054                                 else
1055                                         pDM_PSTable->CurRFState = RF_Normal;
1056                         } else {
1057                                 if (pDM_Odm->RSSI_Min <= Rssi_Low_bound)
1058                                         pDM_PSTable->CurRFState = RF_Normal;
1059                                 else
1060                                         pDM_PSTable->CurRFState = RF_Save;
1061                         }
1062                 } else {
1063                         pDM_PSTable->CurRFState = RF_MAX;
1064                 }
1065         } else {
1066                 pDM_PSTable->CurRFState = RF_Normal;
1067         }
1068
1069         if (pDM_PSTable->PreRFState != pDM_PSTable->CurRFState) {
1070                 if (pDM_PSTable->CurRFState == RF_Save) {
1071                         /*  <tynli_note> 8723 RSSI report will be wrong. Set 0x874[5]= 1 when enter BB power saving mode. */
1072                         /*  Suggested by SD3 Yu-Nan. 2011.01.20. */
1073                         if (pDM_Odm->SupportICType == ODM_RTL8723A)
1074                                 ODM_SetBBReg(pDM_Odm, 0x874, BIT(5), 0x1); /* Reg874[5]= 1b'1 */
1075                         ODM_SetBBReg(pDM_Odm, 0x874, 0x1C0000, 0x2); /* Reg874[20:18]= 3'b010 */
1076                         ODM_SetBBReg(pDM_Odm, 0xc70, BIT(3), 0); /* RegC70[3]= 1'b0 */
1077                         ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, 0x63); /* Reg85C[31:24]= 0x63 */
1078                         ODM_SetBBReg(pDM_Odm, 0x874, 0xC000, 0x2); /* Reg874[15:14]= 2'b10 */
1079                         ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, 0x3); /* RegA75[7:4]= 0x3 */
1080                         ODM_SetBBReg(pDM_Odm, 0x818, BIT(28), 0x0); /* Reg818[28]= 1'b0 */
1081                         ODM_SetBBReg(pDM_Odm, 0x818, BIT(28), 0x1); /* Reg818[28]= 1'b1 */
1082                 } else {
1083                         ODM_SetBBReg(pDM_Odm, 0x874, 0x1CC000, pDM_PSTable->Reg874);
1084                         ODM_SetBBReg(pDM_Odm, 0xc70, BIT(3), pDM_PSTable->RegC70);
1085                         ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, pDM_PSTable->Reg85C);
1086                         ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, pDM_PSTable->RegA74);
1087                         ODM_SetBBReg(pDM_Odm, 0x818, BIT(28), 0x0);
1088
1089                         if (pDM_Odm->SupportICType == ODM_RTL8723A)
1090                                 ODM_SetBBReg(pDM_Odm, 0x874, BIT(5), 0x0); /* Reg874[5]= 1b'0 */
1091                 }
1092                 pDM_PSTable->PreRFState = pDM_PSTable->CurRFState;
1093         }
1094 }
1095
1096 /* 3 ============================================================ */
1097 /* 3 RATR MASK */
1098 /* 3 ============================================================ */
1099 /* 3 ============================================================ */
1100 /* 3 Rate Adaptive */
1101 /* 3 ============================================================ */
1102
1103 void odm_RateAdaptiveMaskInit23a(struct dm_odm_t *pDM_Odm)
1104 {
1105         struct odm_rate_adapt *pOdmRA = &pDM_Odm->RateAdaptive;
1106
1107         pOdmRA->Type = DM_Type_ByDriver;
1108         if (pOdmRA->Type == DM_Type_ByDriver)
1109                 pDM_Odm->bUseRAMask = true;
1110         else
1111                 pDM_Odm->bUseRAMask = false;
1112
1113         pOdmRA->RATRState = DM_RATR_STA_INIT;
1114         pOdmRA->HighRSSIThresh = 50;
1115         pOdmRA->LowRSSIThresh = 20;
1116 }
1117
1118 u32 ODM_Get_Rate_Bitmap23a(struct hal_data_8723a *pHalData, u32 macid,
1119                            u32 ra_mask, u8 rssi_level)
1120 {
1121         struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
1122         struct sta_info *pEntry;
1123         u32 rate_bitmap = 0x0fffffff;
1124         u8 WirelessMode;
1125
1126         pEntry = pDM_Odm->pODM_StaInfo[macid];
1127         if (!pEntry)
1128                 return ra_mask;
1129
1130         WirelessMode = pEntry->wireless_mode;
1131
1132         switch (WirelessMode) {
1133         case ODM_WM_B:
1134                 if (ra_mask & 0x0000000c)               /* 11M or 5.5M enable */
1135                         rate_bitmap = 0x0000000d;
1136                 else
1137                         rate_bitmap = 0x0000000f;
1138                 break;
1139         case (ODM_WM_A|ODM_WM_G):
1140                 if (rssi_level == DM_RATR_STA_HIGH)
1141                         rate_bitmap = 0x00000f00;
1142                 else
1143                         rate_bitmap = 0x00000ff0;
1144                 break;
1145         case (ODM_WM_B|ODM_WM_G):
1146                 if (rssi_level == DM_RATR_STA_HIGH)
1147                         rate_bitmap = 0x00000f00;
1148                 else if (rssi_level == DM_RATR_STA_MIDDLE)
1149                         rate_bitmap = 0x00000ff0;
1150                 else
1151                         rate_bitmap = 0x00000ff5;
1152                 break;
1153         case (ODM_WM_B|ODM_WM_G|ODM_WM_N24G):
1154         case (ODM_WM_A|ODM_WM_B|ODM_WM_G|ODM_WM_N24G):
1155                 if (pDM_Odm->RFType == ODM_1T2R || pDM_Odm->RFType == ODM_1T1R) {
1156                         if (rssi_level == DM_RATR_STA_HIGH) {
1157                                 rate_bitmap = 0x000f0000;
1158                         } else if (rssi_level == DM_RATR_STA_MIDDLE) {
1159                                 rate_bitmap = 0x000ff000;
1160                         } else {
1161                                 if (pHalData->CurrentChannelBW ==
1162                                     HT_CHANNEL_WIDTH_40)
1163                                         rate_bitmap = 0x000ff015;
1164                                 else
1165                                         rate_bitmap = 0x000ff005;
1166                         }
1167                 } else {
1168                         if (rssi_level == DM_RATR_STA_HIGH) {
1169                                 rate_bitmap = 0x0f8f0000;
1170                         } else if (rssi_level == DM_RATR_STA_MIDDLE) {
1171                                 rate_bitmap = 0x0f8ff000;
1172                         } else {
1173                                 if (pHalData->CurrentChannelBW ==
1174                                     HT_CHANNEL_WIDTH_40)
1175                                         rate_bitmap = 0x0f8ff015;
1176                                 else
1177                                         rate_bitmap = 0x0f8ff005;
1178                         }
1179                 }
1180                 break;
1181         default:
1182                 /* case WIRELESS_11_24N: */
1183                 /* case WIRELESS_11_5N: */
1184                 if (pDM_Odm->RFType == RF_1T2R)
1185                         rate_bitmap = 0x000fffff;
1186                 else
1187                         rate_bitmap = 0x0fffffff;
1188                 break;
1189         }
1190
1191         /* printk("%s ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x \n", __func__, rssi_level, WirelessMode, rate_bitmap); */
1192         ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, (" ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x \n", rssi_level, WirelessMode, rate_bitmap));
1193
1194         return rate_bitmap;
1195
1196 }
1197
1198 /*-----------------------------------------------------------------------------
1199  * Function:    odm_RefreshRateAdaptiveMask23a()
1200  *
1201  * Overview:    Update rate table mask according to rssi
1202  *
1203  * Input:               NONE
1204  *
1205  * Output:              NONE
1206  *
1207  * Return:              NONE
1208  *
1209  * Revised History:
1210  *When          Who             Remark
1211  *05/27/2009    hpfan   Create Version 0.
1212  *
1213  *---------------------------------------------------------------------------*/
1214 void odm_RefreshRateAdaptiveMask23a(struct dm_odm_t *pDM_Odm)
1215 {
1216         if (!(pDM_Odm->SupportAbility & ODM_BB_RA_MASK))
1217                 return;
1218         /*  */
1219         /*  2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1220         /*  at the same time. In the stage2/3, we need to prive universal interface and merge all */
1221         /*  HW dynamic mechanism. */
1222         /*  */
1223         odm_RefreshRateAdaptiveMask23aCE23a(pDM_Odm);
1224 }
1225
1226 void odm_RefreshRateAdaptiveMask23aMP23a(struct dm_odm_t *pDM_Odm)
1227 {
1228 }
1229
1230 void odm_RefreshRateAdaptiveMask23aCE23a(struct dm_odm_t *pDM_Odm)
1231 {
1232         u8 i;
1233         struct rtw_adapter *pAdapter     =  pDM_Odm->Adapter;
1234
1235         if (pAdapter->bDriverStopped) {
1236                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE,
1237                              ("<---- odm_RefreshRateAdaptiveMask23a(): driver is going to unload\n"));
1238                 return;
1239         }
1240
1241         if (!pDM_Odm->bUseRAMask) {
1242                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD,
1243                              ("<---- odm_RefreshRateAdaptiveMask23a(): driver does not control rate adaptive mask\n"));
1244                 return;
1245         }
1246
1247         /* printk("==> %s \n", __func__); */
1248
1249         for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
1250                 struct sta_info *pstat = pDM_Odm->pODM_StaInfo[i];
1251                 if (pstat) {
1252                         if (ODM_RAStateCheck23a(pDM_Odm, pstat->rssi_stat.UndecoratedSmoothedPWDB, false, &pstat->rssi_level)) {
1253                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD,
1254                                              ("RSSI:%d, RSSI_LEVEL:%d\n",
1255                                              pstat->rssi_stat.UndecoratedSmoothedPWDB,
1256                                              pstat->rssi_level));
1257                                 rtw_hal_update_ra_mask23a(pstat, pstat->rssi_level);
1258                         }
1259
1260                 }
1261         }
1262
1263 }
1264
1265 void odm_RefreshRateAdaptiveMask23aAPADSL23a(struct dm_odm_t *pDM_Odm)
1266 {
1267 }
1268
1269 /*  Return Value: bool */
1270 /*  - true: RATRState is changed. */
1271 bool ODM_RAStateCheck23a(struct dm_odm_t *pDM_Odm, s32 RSSI, bool bForceUpdate,
1272                          u8 *pRATRState)
1273 {
1274         struct odm_rate_adapt *pRA = &pDM_Odm->RateAdaptive;
1275         const u8 GoUpGap = 5;
1276         u8 HighRSSIThreshForRA = pRA->HighRSSIThresh;
1277         u8 LowRSSIThreshForRA = pRA->LowRSSIThresh;
1278         u8 RATRState;
1279
1280         /*  Threshold Adjustment: */
1281         /*  when RSSI state trends to go up one or two levels, make sure RSSI is high enough. */
1282         /*  Here GoUpGap is added to solve the boundary's level alternation issue. */
1283         switch (*pRATRState) {
1284         case DM_RATR_STA_INIT:
1285         case DM_RATR_STA_HIGH:
1286                 break;
1287         case DM_RATR_STA_MIDDLE:
1288                 HighRSSIThreshForRA += GoUpGap;
1289                 break;
1290         case DM_RATR_STA_LOW:
1291                 HighRSSIThreshForRA += GoUpGap;
1292                 LowRSSIThreshForRA += GoUpGap;
1293                 break;
1294         default:
1295                 ODM_RT_ASSERT(pDM_Odm, false, ("wrong rssi level setting %d !", *pRATRState));
1296                 break;
1297         }
1298
1299         /*  Decide RATRState by RSSI. */
1300         if (RSSI > HighRSSIThreshForRA)
1301                 RATRState = DM_RATR_STA_HIGH;
1302         else if (RSSI > LowRSSIThreshForRA)
1303                 RATRState = DM_RATR_STA_MIDDLE;
1304         else
1305                 RATRState = DM_RATR_STA_LOW;
1306
1307         if (*pRATRState != RATRState || bForceUpdate) {
1308                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD,
1309                              ("RSSI Level %d -> %d\n", *pRATRState, RATRState));
1310                 *pRATRState = RATRState;
1311                 return true;
1312         }
1313         return false;
1314 }
1315
1316 /* 3 ============================================================ */
1317 /* 3 Dynamic Tx Power */
1318 /* 3 ============================================================ */
1319
1320 void odm_DynamicTxPower23aInit(struct dm_odm_t *pDM_Odm)
1321 {
1322         struct rtw_adapter *Adapter = pDM_Odm->Adapter;
1323         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1324         struct dm_priv *pdmpriv = &pHalData->dmpriv;
1325
1326         /*
1327          * This is never changed, so we should be able to clean up the
1328          * code checking for different values in rtl8723a_rf6052.c
1329          */
1330         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
1331 }
1332
1333 /* 3 ============================================================ */
1334 /* 3 RSSI Monitor */
1335 /* 3 ============================================================ */
1336
1337 void odm_RSSIMonitorInit(struct dm_odm_t *pDM_Odm)
1338 {
1339 }
1340
1341 void odm_RSSIMonitorCheck23a(struct dm_odm_t *pDM_Odm)
1342 {
1343         /*  For AP/ADSL use struct rtl8723a_priv * */
1344         /*  For CE/NIC use struct rtw_adapter * */
1345
1346         if (!(pDM_Odm->SupportAbility & ODM_BB_RSSI_MONITOR))
1347                 return;
1348
1349         /*  2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1350         /*  at the same time. In the stage2/3, we need to prive universal interface and merge all */
1351         /*  HW dynamic mechanism. */
1352         odm_RSSIMonitorCheck23aCE(pDM_Odm);
1353 }       /*  odm_RSSIMonitorCheck23a */
1354
1355 void odm_RSSIMonitorCheck23aMP(struct dm_odm_t *pDM_Odm)
1356 {
1357 }
1358
1359 static void
1360 FindMinimumRSSI(
1361         struct rtw_adapter *pAdapter
1362         )
1363 {
1364         struct hal_data_8723a *pHalData = GET_HAL_DATA(pAdapter);
1365         struct dm_priv *pdmpriv = &pHalData->dmpriv;
1366         struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
1367
1368         /* 1 1.Determine the minimum RSSI */
1369
1370         if ((!pDM_Odm->bLinked) &&
1371             (pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0))
1372                 pdmpriv->MinUndecoratedPWDBForDM = 0;
1373         else
1374                 pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
1375 }
1376
1377 void odm_RSSIMonitorCheck23aCE(struct dm_odm_t *pDM_Odm)
1378 {
1379         struct rtw_adapter *Adapter = pDM_Odm->Adapter;
1380         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1381         struct dm_priv *pdmpriv = &pHalData->dmpriv;
1382         int     i;
1383         int     tmpEntryMaxPWDB = 0, tmpEntryMinPWDB = 0xff;
1384         u8 sta_cnt = 0;
1385         u32 PWDB_rssi[NUM_STA] = {0};/* 0~15]:MACID, [16~31]:PWDB_rssi */
1386         struct sta_info *psta;
1387
1388         if (!pDM_Odm->bLinked)
1389                 return;
1390
1391         for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
1392                 psta = pDM_Odm->pODM_StaInfo[i];
1393                 if (psta) {
1394                         if (psta->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB)
1395                                 tmpEntryMinPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
1396
1397                         if (psta->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB)
1398                                 tmpEntryMaxPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
1399
1400                         if (psta->rssi_stat.UndecoratedSmoothedPWDB != (-1))
1401                                 PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16));
1402                 }
1403         }
1404
1405         for (i = 0; i < sta_cnt; i++) {
1406                 if (PWDB_rssi[i] != (0)) {
1407                         if (pHalData->fw_ractrl) /*  Report every sta's RSSI to FW */
1408                                 rtl8723a_set_rssi_cmd(Adapter, (u8 *)&PWDB_rssi[i]);
1409                 }
1410         }
1411
1412         if (tmpEntryMaxPWDB != 0)       /*  If associated entry is found */
1413                 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = tmpEntryMaxPWDB;
1414         else
1415                 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = 0;
1416
1417         if (tmpEntryMinPWDB != 0xff) /*  If associated entry is found */
1418                 pdmpriv->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB;
1419         else
1420                 pdmpriv->EntryMinUndecoratedSmoothedPWDB = 0;
1421
1422         FindMinimumRSSI(Adapter);/* get pdmpriv->MinUndecoratedPWDBForDM */
1423
1424         ODM_CmnInfoUpdate23a(&pHalData->odmpriv, ODM_CMNINFO_RSSI_MIN, pdmpriv->MinUndecoratedPWDBForDM);
1425 }
1426
1427 void odm_RSSIMonitorCheck23aAP(struct dm_odm_t *pDM_Odm)
1428 {
1429 }
1430
1431 /* endif */
1432 /* 3 ============================================================ */
1433 /* 3 Tx Power Tracking */
1434 /* 3 ============================================================ */
1435
1436 void odm_TXPowerTrackingInit23a(struct dm_odm_t *pDM_Odm)
1437 {
1438         odm_TXPowerTrackingThermalMeterInit23a(pDM_Odm);
1439 }
1440
1441 void odm_TXPowerTrackingThermalMeterInit23a(struct dm_odm_t *pDM_Odm)
1442 {
1443         struct rtw_adapter *Adapter = pDM_Odm->Adapter;
1444         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1445         struct dm_priv *pdmpriv = &pHalData->dmpriv;
1446
1447         pdmpriv->bTXPowerTracking = true;
1448         pdmpriv->TXPowercount = 0;
1449         pdmpriv->bTXPowerTrackingInit = false;
1450         pdmpriv->TxPowerTrackControl = true;
1451         MSG_8723A("pdmpriv->TxPowerTrackControl = %d\n", pdmpriv->TxPowerTrackControl);
1452
1453         pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = true;
1454 }
1455
1456 void ODM_TXPowerTrackingCheck23a(struct dm_odm_t *pDM_Odm)
1457 {
1458         /*  For AP/ADSL use struct rtl8723a_priv * */
1459         /*  For CE/NIC use struct rtw_adapter * */
1460
1461         /*  2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1462         /*  at the same time. In the stage2/3, we need to prive universal interface and merge all */
1463         /*  HW dynamic mechanism. */
1464         odm_TXPowerTrackingCheckCE23a(pDM_Odm);
1465 }
1466
1467 void odm_TXPowerTrackingCheckCE23a(struct dm_odm_t *pDM_Odm)
1468 {
1469 }
1470
1471 void odm_TXPowerTrackingCheckMP(struct dm_odm_t *pDM_Odm)
1472 {
1473 }
1474
1475 void odm_TXPowerTrackingCheckAP(struct dm_odm_t *pDM_Odm)
1476 {
1477 }
1478
1479 /* antenna mapping info */
1480 /*  1: right-side antenna */
1481 /*  2/0: left-side antenna */
1482 /* PpDM_SWAT_Table->CCK_Ant1_Cnt /OFDM_Ant1_Cnt:  for right-side antenna:   Ant:1    RxDefaultAnt1 */
1483 /* PpDM_SWAT_Table->CCK_Ant2_Cnt /OFDM_Ant2_Cnt:  for left-side antenna:     Ant:0    RxDefaultAnt2 */
1484 /*  We select left antenna as default antenna in initial process, modify it as needed */
1485 /*  */
1486
1487 /* 3 ============================================================ */
1488 /* 3 SW Antenna Diversity */
1489 /* 3 ============================================================ */
1490 void odm_SwAntDivInit(struct dm_odm_t *pDM_Odm)
1491 {
1492 }
1493
1494 void ODM_SwAntDivChkPerPktRssi(struct dm_odm_t *pDM_Odm, u8 StationID,
1495                                struct phy_info *pPhyInfo)
1496 {
1497 }
1498
1499 void odm_SwAntDivChkAntSwitch(struct dm_odm_t *pDM_Odm, u8 Step)
1500 {
1501 }
1502
1503 void ODM_SwAntDivRestAfterLink(struct dm_odm_t *pDM_Odm)
1504 {
1505 }
1506
1507 void odm_SwAntDivChkAntSwitchCallback23a(unsigned long data)
1508 {
1509 }
1510
1511 /* 3 ============================================================ */
1512 /* 3 SW Antenna Diversity */
1513 /* 3 ============================================================ */
1514
1515 void odm_InitHybridAntDiv23a(struct dm_odm_t *pDM_Odm)
1516 {
1517 }
1518
1519 void odm_HwAntDiv23a(struct dm_odm_t *pDM_Odm)
1520 {
1521 }
1522
1523 /* EDCA Turbo */
1524 static void ODM_EdcaTurboInit23a(struct dm_odm_t *pDM_Odm)
1525 {
1526
1527         struct rtw_adapter *Adapter = pDM_Odm->Adapter;
1528         pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false;
1529         pDM_Odm->DM_EDCA_Table.bIsCurRDLState = false;
1530         Adapter->recvpriv.bIsAnyNonBEPkts = false;
1531
1532         ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VO PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_VO_PARAM)));
1533         ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VI PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_VI_PARAM)));
1534         ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BE PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_BE_PARAM)));
1535         ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BK PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_BK_PARAM)));
1536
1537 }       /*  ODM_InitEdcaTurbo */
1538
1539 static void odm_EdcaTurboCheck23a(struct dm_odm_t *pDM_Odm)
1540 {
1541         struct rtw_adapter *Adapter = pDM_Odm->Adapter;
1542         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1543         struct xmit_priv *pxmitpriv = &Adapter->xmitpriv;
1544         struct recv_priv *precvpriv = &Adapter->recvpriv;
1545         struct registry_priv *pregpriv = &Adapter->registrypriv;
1546         struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
1547         struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
1548         u32 trafficIndex;
1549         u32 edca_param;
1550         u64 cur_tx_bytes = 0;
1551         u64 cur_rx_bytes = 0;
1552         u8 bbtchange = false;
1553
1554         /*  For AP/ADSL use struct rtl8723a_priv * */
1555         /*  For CE/NIC use struct rtw_adapter * */
1556
1557         /*  2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1558         /*  at the same time. In the stage2/3, we need to prive universal interface and merge all */
1559         /*  HW dynamic mechanism. */
1560
1561         if (!(pDM_Odm->SupportAbility & ODM_MAC_EDCA_TURBO))
1562                 return;
1563
1564         if ((pregpriv->wifi_spec == 1))/*  (pmlmeinfo->HT_enable == 0)) */
1565                 goto dm_CheckEdcaTurbo_EXIT;
1566
1567         if (pmlmeinfo->assoc_AP_vendor >=  HT_IOT_PEER_MAX)
1568                 goto dm_CheckEdcaTurbo_EXIT;
1569
1570         if (rtl8723a_BT_disable_EDCA_turbo(Adapter))
1571                 goto dm_CheckEdcaTurbo_EXIT;
1572
1573         /*  Check if the status needs to be changed. */
1574         if ((bbtchange) || (!precvpriv->bIsAnyNonBEPkts)) {
1575                 cur_tx_bytes = pxmitpriv->tx_bytes - pxmitpriv->last_tx_bytes;
1576                 cur_rx_bytes = precvpriv->rx_bytes - precvpriv->last_rx_bytes;
1577
1578                 /* traffic, TX or RX */
1579                 if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_RALINK) ||
1580                     (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_ATHEROS)) {
1581                         if (cur_tx_bytes > (cur_rx_bytes << 2)) {
1582                                 /*  Uplink TP is present. */
1583                                 trafficIndex = UP_LINK;
1584                         } else { /*  Balance TP is present. */
1585                                 trafficIndex = DOWN_LINK;
1586                         }
1587                 } else {
1588                         if (cur_rx_bytes > (cur_tx_bytes << 2)) {
1589                                 /*  Downlink TP is present. */
1590                                 trafficIndex = DOWN_LINK;
1591                         } else { /*  Balance TP is present. */
1592                                 trafficIndex = UP_LINK;
1593                         }
1594                 }
1595
1596                 if ((pDM_Odm->DM_EDCA_Table.prv_traffic_idx != trafficIndex) ||
1597                     (!pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA)) {
1598                         if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_CISCO) &&
1599                             (pmlmeext->cur_wireless_mode & WIRELESS_11_24N))
1600                                 edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex];
1601                         else
1602                                 edca_param = EDCAParam[HT_IOT_PEER_UNKNOWN][trafficIndex];
1603                         rtl8723au_write32(Adapter, REG_EDCA_BE_PARAM,
1604                                           edca_param);
1605
1606                         pDM_Odm->DM_EDCA_Table.prv_traffic_idx = trafficIndex;
1607                 }
1608
1609                 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = true;
1610         } else {
1611                 /*  Turn Off EDCA turbo here. */
1612                 /*  Restore original EDCA according to the declaration of AP. */
1613                 if (pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA) {
1614                         rtl8723au_write32(Adapter, REG_EDCA_BE_PARAM,
1615                                           pHalData->AcParam_BE);
1616                         pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false;
1617                 }
1618         }
1619
1620 dm_CheckEdcaTurbo_EXIT:
1621         /*  Set variables for next time. */
1622         precvpriv->bIsAnyNonBEPkts = false;
1623         pxmitpriv->last_tx_bytes = pxmitpriv->tx_bytes;
1624         precvpriv->last_rx_bytes = precvpriv->rx_bytes;
1625 }
1626
1627 u32 GetPSDData(struct dm_odm_t *pDM_Odm, unsigned int point, u8 initial_gain_psd)
1628 {
1629         u32 psd_report;
1630
1631         /* Set DCO frequency index, offset = (40MHz/SamplePts)*point */
1632         ODM_SetBBReg(pDM_Odm, 0x808, 0x3FF, point);
1633
1634         /* Start PSD calculation, Reg808[22]= 0->1 */
1635         ODM_SetBBReg(pDM_Odm, 0x808, BIT(22), 1);
1636         /* Need to wait for HW PSD report */
1637         udelay(30);
1638         ODM_SetBBReg(pDM_Odm, 0x808, BIT(22), 0);
1639         /* Read PSD report, Reg8B4[15:0] */
1640         psd_report = ODM_GetBBReg(pDM_Odm, 0x8B4, bMaskDWord) & 0x0000FFFF;
1641
1642         psd_report = (u32)(ConvertTo_dB23a(psd_report))+(u32)(initial_gain_psd-0x1c);
1643
1644         return psd_report;
1645 }
1646
1647 u32
1648 ConvertTo_dB23a(
1649         u32 Value)
1650 {
1651         u8 i;
1652         u8 j;
1653         u32 dB;
1654
1655         Value = Value & 0xFFFF;
1656
1657         for (i = 0; i < 8; i++) {
1658                 if (Value <= dB_Invert_Table[i][11])
1659                         break;
1660         }
1661
1662         if (i >= 8)
1663                 return 96;      /*  maximum 96 dB */
1664
1665         for (j = 0; j < 12; j++) {
1666                 if (Value <= dB_Invert_Table[i][j])
1667                         break;
1668         }
1669
1670         dB = i*12 + j + 1;
1671
1672         return dB;
1673 }
1674
1675 /*  */
1676 /*  Description: */
1677 /*Set Single/Dual Antenna default setting for products that do not do detection in advance. */
1678 /*  */
1679 /*  Added by Joseph, 2012.03.22 */
1680 /*  */
1681 void ODM_SingleDualAntennaDefaultSetting(struct dm_odm_t *pDM_Odm)
1682 {
1683         struct sw_ant_sw *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
1684         pDM_SWAT_Table->ANTA_ON = true;
1685         pDM_SWAT_Table->ANTB_ON = true;
1686 }
1687
1688 /* 2 8723A ANT DETECT */
1689
1690 static void odm_PHY_SaveAFERegisters(
1691         struct dm_odm_t *pDM_Odm,
1692         u32 *AFEReg,
1693         u32 *AFEBackup,
1694         u32 RegisterNum
1695         )
1696 {
1697         u32 i;
1698
1699         /* RTPRINT(FINIT, INIT_IQK, ("Save ADDA parameters.\n")); */
1700         for (i = 0 ; i < RegisterNum ; i++)
1701                 AFEBackup[i] = ODM_GetBBReg(pDM_Odm, AFEReg[i], bMaskDWord);
1702 }
1703
1704 static void odm_PHY_ReloadAFERegisters(struct dm_odm_t *pDM_Odm, u32 *AFEReg,
1705                                        u32 *AFEBackup, u32 RegiesterNum)
1706 {
1707         u32 i;
1708
1709         for (i = 0 ; i < RegiesterNum; i++)
1710                 ODM_SetBBReg(pDM_Odm, AFEReg[i], bMaskDWord, AFEBackup[i]);
1711 }
1712
1713 /* 2 8723A ANT DETECT */
1714 /*  Description: */
1715 /* Implement IQK single tone for RF DPK loopback and BB PSD scanning. */
1716 /* This function is cooperated with BB team Neil. */
1717 bool ODM_SingleDualAntennaDetection(struct dm_odm_t *pDM_Odm, u8 mode)
1718 {
1719         struct sw_ant_sw *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
1720         u32 CurrentChannel, RfLoopReg;
1721         u8 n;
1722         u32 Reg88c, Regc08, Reg874, Regc50;
1723         u8 initial_gain = 0x5a;
1724         u32 PSD_report_tmp;
1725         u32 AntA_report = 0x0, AntB_report = 0x0, AntO_report = 0x0;
1726         bool bResult = true;
1727         u32 AFE_Backup[16];
1728         u32 AFE_REG_8723A[16] = {
1729                 rRx_Wait_CCA, rTx_CCK_RFON,
1730                 rTx_CCK_BBON, rTx_OFDM_RFON,
1731                 rTx_OFDM_BBON, rTx_To_Rx,
1732                 rTx_To_Tx, rRx_CCK,
1733                 rRx_OFDM, rRx_Wait_RIFS,
1734                 rRx_TO_Rx, rStandby,
1735                 rSleep, rPMPD_ANAEN,
1736                 rFPGA0_XCD_SwitchControl, rBlue_Tooth};
1737
1738         if (!(pDM_Odm->SupportICType & ODM_RTL8723A))
1739                 return bResult;
1740
1741         if (!(pDM_Odm->SupportAbility&ODM_BB_ANT_DIV))
1742                 return bResult;
1743         /* 1 Backup Current RF/BB Settings */
1744
1745         CurrentChannel = ODM_GetRFReg(pDM_Odm, RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask);
1746         RfLoopReg = ODM_GetRFReg(pDM_Odm, RF_PATH_A, 0x00, bRFRegOffsetMask);
1747         ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, ODM_DPDT, Antenna_A);  /*  change to Antenna A */
1748         /*  Step 1: USE IQK to transmitter single tone */
1749
1750         udelay(10);
1751
1752         /* Store A Path Register 88c, c08, 874, c50 */
1753         Reg88c = ODM_GetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord);
1754         Regc08 = ODM_GetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord);
1755         Reg874 = ODM_GetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord);
1756         Regc50 = ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord);
1757
1758         /*  Store AFE Registers */
1759         odm_PHY_SaveAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16);
1760
1761         /* Set PSD 128 pts */
1762         ODM_SetBBReg(pDM_Odm, rFPGA0_PSDFunction, BIT(14) | BIT(15), 0x0);
1763
1764         /*  To SET CH1 to do */
1765         ODM_SetRFReg(pDM_Odm, RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask, 0x01);     /* Channel 1 */
1766
1767         /*  AFE all on step */
1768         ODM_SetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord, 0x6FDB25A4);
1769         ODM_SetBBReg(pDM_Odm, rTx_CCK_RFON, bMaskDWord, 0x6FDB25A4);
1770         ODM_SetBBReg(pDM_Odm, rTx_CCK_BBON, bMaskDWord, 0x6FDB25A4);
1771         ODM_SetBBReg(pDM_Odm, rTx_OFDM_RFON, bMaskDWord, 0x6FDB25A4);
1772         ODM_SetBBReg(pDM_Odm, rTx_OFDM_BBON, bMaskDWord, 0x6FDB25A4);
1773         ODM_SetBBReg(pDM_Odm, rTx_To_Rx, bMaskDWord, 0x6FDB25A4);
1774         ODM_SetBBReg(pDM_Odm, rTx_To_Tx, bMaskDWord, 0x6FDB25A4);
1775         ODM_SetBBReg(pDM_Odm, rRx_CCK, bMaskDWord, 0x6FDB25A4);
1776         ODM_SetBBReg(pDM_Odm, rRx_OFDM, bMaskDWord, 0x6FDB25A4);
1777         ODM_SetBBReg(pDM_Odm, rRx_Wait_RIFS, bMaskDWord, 0x6FDB25A4);
1778         ODM_SetBBReg(pDM_Odm, rRx_TO_Rx, bMaskDWord, 0x6FDB25A4);
1779         ODM_SetBBReg(pDM_Odm, rStandby, bMaskDWord, 0x6FDB25A4);
1780         ODM_SetBBReg(pDM_Odm, rSleep, bMaskDWord, 0x6FDB25A4);
1781         ODM_SetBBReg(pDM_Odm, rPMPD_ANAEN, bMaskDWord, 0x6FDB25A4);
1782         ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_SwitchControl, bMaskDWord, 0x6FDB25A4);
1783         ODM_SetBBReg(pDM_Odm, rBlue_Tooth, bMaskDWord, 0x6FDB25A4);
1784
1785         /*  3 wire Disable */
1786         ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, 0xCCF000C0);
1787
1788         /* BB IQK Setting */
1789         ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800E4);
1790         ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22208000);
1791
1792         /* IQK setting tone@ 4.34Mhz */
1793         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008C1C);
1794         ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00);
1795
1796         /* Page B init */
1797         ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00080000);
1798         ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000);
1799         ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800);
1800         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1f);
1801         ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82150008);
1802         ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28150008);
1803         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x001028d0);
1804
1805         /* RF loop Setting */
1806         ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x0, 0xFFFFF, 0x50008);
1807
1808         /* IQK Single tone start */
1809         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80800000);
1810         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
1811         udelay(1000);
1812         PSD_report_tmp = 0x0;
1813
1814         for (n = 0; n < 2; n++) {
1815                 PSD_report_tmp =  GetPSDData(pDM_Odm, 14, initial_gain);
1816                 if (PSD_report_tmp > AntA_report)
1817                         AntA_report = PSD_report_tmp;
1818         }
1819
1820         PSD_report_tmp = 0x0;
1821
1822         ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_B);  /*  change to Antenna B */
1823         udelay(10);
1824
1825         for (n = 0; n < 2; n++) {
1826                 PSD_report_tmp =  GetPSDData(pDM_Odm, 14, initial_gain);
1827                 if (PSD_report_tmp > AntB_report)
1828                         AntB_report = PSD_report_tmp;
1829         }
1830
1831         /*  change to open case */
1832         ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, 0);  /*  change to Ant A and B all open case */
1833         udelay(10);
1834
1835         for (n = 0; n < 2; n++) {
1836                 PSD_report_tmp =  GetPSDData(pDM_Odm, 14, initial_gain);
1837                 if (PSD_report_tmp > AntO_report)
1838                         AntO_report = PSD_report_tmp;
1839         }
1840
1841         /* Close IQK Single Tone function */
1842         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
1843         PSD_report_tmp = 0x0;
1844
1845         /* 1 Return to antanna A */
1846         ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_A);
1847         ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, Reg88c);
1848         ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, Regc08);
1849         ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, Reg874);
1850         ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, 0x7F, 0x40);
1851         ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord, Regc50);
1852         ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, CurrentChannel);
1853         ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x00, bRFRegOffsetMask, RfLoopReg);
1854
1855         /* Reload AFE Registers */
1856         odm_PHY_ReloadAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16);
1857
1858         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_A[%d]= %d \n", 2416, AntA_report));
1859         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_B[%d]= %d \n", 2416, AntB_report));
1860         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_O[%d]= %d \n", 2416, AntO_report));
1861
1862         /* 2 Test Ant B based on Ant A is ON */
1863         if (mode == ANTTESTB) {
1864                 if (AntA_report >= 100) {
1865                         if (AntB_report > (AntA_report+1)) {
1866                                 pDM_SWAT_Table->ANTB_ON = false;
1867                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Single Antenna A\n"));
1868                         } else {
1869                                 pDM_SWAT_Table->ANTB_ON = true;
1870                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Dual Antenna is A and B\n"));
1871                         }
1872                 } else {
1873                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n"));
1874                         pDM_SWAT_Table->ANTB_ON = false; /*  Set Antenna B off as default */
1875                         bResult = false;
1876                 }
1877         } else if (mode == ANTTESTALL) {
1878                 /* 2 Test Ant A and B based on DPDT Open */
1879                 if ((AntO_report >= 100) & (AntO_report < 118)) {
1880                         if (AntA_report > (AntO_report+1)) {
1881                                 pDM_SWAT_Table->ANTA_ON = false;
1882                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant A is OFF"));
1883                         } else {
1884                                 pDM_SWAT_Table->ANTA_ON = true;
1885                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant A is ON"));
1886                         }
1887
1888                         if (AntB_report > (AntO_report+2)) {
1889                                 pDM_SWAT_Table->ANTB_ON = false;
1890                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant B is OFF"));
1891                         } else {
1892                                 pDM_SWAT_Table->ANTB_ON = true;
1893                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant B is ON"));
1894                         }
1895                 }
1896         } else {
1897                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n"));
1898                 pDM_SWAT_Table->ANTA_ON = true; /*  Set Antenna A on as default */
1899                 pDM_SWAT_Table->ANTB_ON = false; /*  Set Antenna B off as default */
1900                 bResult = false;
1901         }
1902         return bResult;
1903 }
1904
1905 /* Justin: According to the current RRSI to adjust Response Frame TX power, 2012/11/05 */
1906 void odm_dtc(struct dm_odm_t *pDM_Odm)
1907 {
1908 }