drivers/staging/rtl8723au/hal/odm.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  ******************************************************************************/
  15
  16 #include "odm_precomp.h"
  17 #include "usb_ops_linux.h"
  18
  19 static const u16 dB_Invert_Table[8][12] = {
  20         {1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4},
  21         {4, 5, 6, 6, 7, 8, 9, 10, 11, 13, 14, 16},
  22         {18, 20, 22, 25, 28, 32, 35, 40, 45, 50, 56, 63},
  23         {71, 79, 89, 100, 112, 126, 141, 158, 178, 200, 224, 251},
  24         {282, 316, 355, 398, 447, 501, 562, 631, 708, 794, 891, 1000},
  25         {1122, 1259, 1413, 1585, 1778, 1995, 2239, 2512, 2818, 3162, 3548, 3981},
  26         {4467, 5012, 5623, 6310, 7079, 7943, 8913, 10000, 11220, 12589, 14125, 15849},
  27         {17783, 19953, 22387, 25119, 28184, 31623, 35481, 39811, 44668, 50119, 56234, 65535}
  28 };
  29
  30 static u32 EDCAParam[HT_IOT_PEER_MAX][3] = {          /*  UL                    DL */
  31         {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 0:unknown AP */
  32         {0xa44f, 0x5ea44f, 0x5e431c}, /*  1:realtek AP */
  33         {0x5ea42b, 0x5ea42b, 0x5ea42b}, /*  2:unknown AP => realtek_92SE */
  34         {0x5ea32b, 0x5ea42b, 0x5e4322}, /*  3:broadcom AP */
  35         {0x5ea422, 0x00a44f, 0x00a44f}, /*  4:ralink AP */
  36         {0x5ea322, 0x00a630, 0x00a44f}, /*  5:atheros AP */
  37         {0x5e4322, 0x5e4322, 0x5e4322},/*  6:cisco AP */
  38         {0x5ea44f, 0x00a44f, 0x5ea42b}, /*  8:marvell AP */
  39         {0x5ea42b, 0x5ea42b, 0x5ea42b}, /*  10:unknown AP => 92U AP */
  40         {0x5ea42b, 0xa630, 0x5e431c}, /*  11:airgocap AP */
  41 };
  42
  43 /*  EDCA Paramter for AP/ADSL   by Mingzhi 2011-11-22 */
  44
  45 /*  Global var */
  46 u32 OFDMSwingTable23A[OFDM_TABLE_SIZE_92D] = {
  47         0x7f8001fe, /*  0, +6.0dB */
  48         0x788001e2, /*  1, +5.5dB */
  49         0x71c001c7, /*  2, +5.0dB */
  50         0x6b8001ae, /*  3, +4.5dB */
  51         0x65400195, /*  4, +4.0dB */
  52         0x5fc0017f, /*  5, +3.5dB */
  53         0x5a400169, /*  6, +3.0dB */
  54         0x55400155, /*  7, +2.5dB */
  55         0x50800142, /*  8, +2.0dB */
  56         0x4c000130, /*  9, +1.5dB */
  57         0x47c0011f, /*  10, +1.0dB */
  58         0x43c0010f, /*  11, +0.5dB */
  59         0x40000100, /*  12, +0dB */
  60         0x3c8000f2, /*  13, -0.5dB */
  61         0x390000e4, /*  14, -1.0dB */
  62         0x35c000d7, /*  15, -1.5dB */
  63         0x32c000cb, /*  16, -2.0dB */
  64         0x300000c0, /*  17, -2.5dB */
  65         0x2d4000b5, /*  18, -3.0dB */
  66         0x2ac000ab, /*  19, -3.5dB */
  67         0x288000a2, /*  20, -4.0dB */
  68         0x26000098, /*  21, -4.5dB */
  69         0x24000090, /*  22, -5.0dB */
  70         0x22000088, /*  23, -5.5dB */
  71         0x20000080, /*  24, -6.0dB */
  72         0x1e400079, /*  25, -6.5dB */
  73         0x1c800072, /*  26, -7.0dB */
  74         0x1b00006c, /*  27. -7.5dB */
  75         0x19800066, /*  28, -8.0dB */
  76         0x18000060, /*  29, -8.5dB */
  77         0x16c0005b, /*  30, -9.0dB */
  78         0x15800056, /*  31, -9.5dB */
  79         0x14400051, /*  32, -10.0dB */
  80         0x1300004c, /*  33, -10.5dB */
  81         0x12000048, /*  34, -11.0dB */
  82         0x11000044, /*  35, -11.5dB */
  83         0x10000040, /*  36, -12.0dB */
  84         0x0f00003c,/*  37, -12.5dB */
  85         0x0e400039,/*  38, -13.0dB */
  86         0x0d800036,/*  39, -13.5dB */
  87         0x0cc00033,/*  40, -14.0dB */
  88         0x0c000030,/*  41, -14.5dB */
  89         0x0b40002d,/*  42, -15.0dB */
  90 };
  91
  92 u8 CCKSwingTable_Ch1_Ch1323A[CCK_TABLE_SIZE][8] = {
  93         {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /*  0, +0dB */
  94         {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /*  1, -0.5dB */
  95         {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /*  2, -1.0dB */
  96         {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /*  3, -1.5dB */
  97         {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /*  4, -2.0dB */
  98         {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /*  5, -2.5dB */
  99         {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /*  6, -3.0dB */
 100         {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /*  7, -3.5dB */
 101         {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /*  8, -4.0dB */
 102         {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /*  9, -4.5dB */
 103         {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /*  10, -5.0dB */
 104         {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /*  11, -5.5dB */
 105         {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /*  12, -6.0dB */
 106         {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /*  13, -6.5dB */
 107         {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /*  14, -7.0dB */
 108         {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /*  15, -7.5dB */
 109         {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /*  16, -8.0dB */
 110         {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /*  17, -8.5dB */
 111         {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /*  18, -9.0dB */
 112         {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /*  19, -9.5dB */
 113         {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /*  20, -10.0dB */
 114         {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /*  21, -10.5dB */
 115         {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /*  22, -11.0dB */
 116         {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /*  23, -11.5dB */
 117         {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /*  24, -12.0dB */
 118         {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /*  25, -12.5dB */
 119         {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /*  26, -13.0dB */
 120         {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /*  27, -13.5dB */
 121         {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /*  28, -14.0dB */
 122         {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /*  29, -14.5dB */
 123         {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /*  30, -15.0dB */
 124         {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /*  31, -15.5dB */
 125         {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}        /*  32, -16.0dB */
 126 };
 127
 128 u8 CCKSwingTable_Ch1423A[CCK_TABLE_SIZE][8] = {
 129         {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /*  0, +0dB */
 130         {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /*  1, -0.5dB */
 131         {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /*  2, -1.0dB */
 132         {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /*  3, -1.5dB */
 133         {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /*  4, -2.0dB */
 134         {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /*  5, -2.5dB */
 135         {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /*  6, -3.0dB */
 136         {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /*  7, -3.5dB */
 137         {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /*  8, -4.0dB */
 138         {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /*  9, -4.5dB */
 139         {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /*  10, -5.0dB */
 140         {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /*  11, -5.5dB */
 141         {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /*  12, -6.0dB */
 142         {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /*  13, -6.5dB */
 143         {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /*  14, -7.0dB */
 144         {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /*  15, -7.5dB */
 145         {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /*  16, -8.0dB */
 146         {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /*  17, -8.5dB */
 147         {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /*  18, -9.0dB */
 148         {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /*  19, -9.5dB */
 149         {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /*  20, -10.0dB */
 150         {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /*  21, -10.5dB */
 151         {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /*  22, -11.0dB */
 152         {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /*  23, -11.5dB */
 153         {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /*  24, -12.0dB */
 154         {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /*  25, -12.5dB */
 155         {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /*  26, -13.0dB */
 156         {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /*  27, -13.5dB */
 157         {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /*  28, -14.0dB */
 158         {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /*  29, -14.5dB */
 159         {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /*  30, -15.0dB */
 160         {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /*  31, -15.5dB */
 161         {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}        /*  32, -16.0dB */
 162 };
 163
 164 /*  Local Function predefine. */
 165
 166 /* START------------COMMON INFO RELATED--------------- */
 167 void odm_CommonInfoSelfInit23a(struct dm_odm_t *pDM_Odm);
 168
 169 static void odm_CommonInfoSelfUpdate(struct hal_data_8723a *pHalData);
 170
 171 void odm_CmnInfoInit_Debug23a(struct dm_odm_t *pDM_Odm);
 172
 173 void odm_CmnInfoUpdate_Debug23a(struct dm_odm_t *pDM_Odm);
 174
 175 /* START---------------DIG--------------------------- */
 176 void odm_FalseAlarmCounterStatistics23a(struct dm_odm_t *pDM_Odm);
 177
 178 void odm_DIG23aInit(struct dm_odm_t *pDM_Odm);
 179
 180 void odm_DIG23a(struct rtw_adapter *adapter);
 181
 182 void odm_CCKPacketDetectionThresh23a(struct dm_odm_t *pDM_Odm);
 183 /* END---------------DIG--------------------------- */
 184
 185 /* START-------BB POWER SAVE----------------------- */
 186 void odm23a_DynBBPSInit(struct dm_odm_t *pDM_Odm);
 187
 188 void odm_DynamicBBPowerSaving23a(struct dm_odm_t *pDM_Odm);
 189
 190 /* END---------BB POWER SAVE----------------------- */
 191
 192 void odm_RefreshRateAdaptiveMask23aCE23a(struct dm_odm_t *pDM_Odm);
 193
 194 void odm_DynamicTxPower23aInit(struct dm_odm_t *pDM_Odm);
 195
 196 void odm_RSSIMonitorCheck23aCE(struct dm_odm_t *pDM_Odm);
 197 void odm_RSSIMonitorCheck23a(struct dm_odm_t *pDM_Odm);
 198 void odm_DynamicTxPower23a(struct dm_odm_t *pDM_Odm);
 199
 200 void odm_RefreshRateAdaptiveMask23a(struct dm_odm_t *pDM_Odm);
 201
 202 void ODM_TXPowerTrackingCheck23a(struct dm_odm_t *pDM_Odm);
 203
 204 void odm_RateAdaptiveMaskInit23a(struct dm_odm_t *pDM_Odm);
 205
 206 void odm_TXPowerTrackingThermalMeterInit23a(struct dm_odm_t *pDM_Odm);
 207
 208 void odm_TXPowerTrackingInit23a(struct dm_odm_t *pDM_Odm);
 209
 210 void odm_TXPowerTrackingCheckCE23a(struct dm_odm_t *pDM_Odm);
 211
 212 static void odm_EdcaTurboCheck23a(struct dm_odm_t *pDM_Odm);
 213 static void ODM_EdcaTurboInit23a(struct dm_odm_t *pDM_Odm);
 214
 215 #define         RxDefaultAnt1           0x65a9
 216 #define RxDefaultAnt2           0x569a
 217
 218 bool odm_StaDefAntSel(struct dm_odm_t *pDM_Odm,
 219         u32 OFDM_Ant1_Cnt,
 220         u32 OFDM_Ant2_Cnt,
 221         u32 CCK_Ant1_Cnt,
 222         u32 CCK_Ant2_Cnt,
 223         u8 *pDefAnt
 224         );
 225
 226 void odm_SetRxIdleAnt(struct dm_odm_t *pDM_Odm,
 227         u8 Ant,
 228         bool   bDualPath
 229 );
 230
 231 /* 3 Export Interface */
 232
 233 /*  2011/09/21 MH Add to describe different team necessary resource allocate?? */
 234 void ODM23a_DMInit(struct dm_odm_t *pDM_Odm)
 235 {
 236         /* For all IC series */
 237         odm_CommonInfoSelfInit23a(pDM_Odm);
 238         odm_CmnInfoInit_Debug23a(pDM_Odm);
 239         odm_DIG23aInit(pDM_Odm);
 240         odm_RateAdaptiveMaskInit23a(pDM_Odm);
 241
 242         odm23a_DynBBPSInit(pDM_Odm);
 243         odm_DynamicTxPower23aInit(pDM_Odm);
 244         odm_TXPowerTrackingInit23a(pDM_Odm);
 245         ODM_EdcaTurboInit23a(pDM_Odm);
 246 }
 247
 248 /*  2011/09/20 MH This is the entry pointer for all team to execute HW out source DM. */
 249 /*  You can not add any dummy function here, be care, you can only use DM structure */
 250 /*  to perform any new ODM_DM. */
 251 void ODM_DMWatchdog23a(struct rtw_adapter *adapter)
 252 {
 253         struct hal_data_8723a *pHalData = GET_HAL_DATA(adapter);
 254         struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
 255         struct pwrctrl_priv *pwrctrlpriv = &adapter->pwrctrlpriv;
 256
 257         /* 2012.05.03 Luke: For all IC series */
 258         odm_CmnInfoUpdate_Debug23a(pDM_Odm);
 259         odm_CommonInfoSelfUpdate(pHalData);
 260         odm_FalseAlarmCounterStatistics23a(pDM_Odm);
 261         odm_RSSIMonitorCheck23a(pDM_Odm);
 262
 263         /* 8723A or 8189ES platform */
 264         /* NeilChen--2012--08--24-- */
 265         /* Fix Leave LPS issue */
 266         if ((pDM_Odm->Adapter->pwrctrlpriv.pwr_mode != PS_MODE_ACTIVE) &&/*  in LPS mode */
 267             (pDM_Odm->SupportICType & ODM_RTL8723A)) {
 268                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("----Step1: odm_DIG23a is in LPS mode\n"));
 269                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("---Step2: 8723AS is in LPS mode\n"));
 270                         odm_DIG23abyRSSI_LPS(pDM_Odm);
 271         } else {
 272                 odm_DIG23a(adapter);
 273         }
 274
 275         odm_CCKPacketDetectionThresh23a(pDM_Odm);
 276
 277         if (pwrctrlpriv->bpower_saving)
 278                 return;
 279
 280         odm_RefreshRateAdaptiveMask23a(pDM_Odm);
 281
 282         odm_DynamicBBPowerSaving23a(pDM_Odm);
 283
 284         ODM_TXPowerTrackingCheck23a(pDM_Odm);
 285         odm_EdcaTurboCheck23a(pDM_Odm);
 286
 287         odm_dtc(pDM_Odm);
 288 }
 289
 290 /*  */
 291 /*  Init /.. Fixed HW value. Only init time. */
 292 /*  */
 293 void ODM_CmnInfoInit23a(struct dm_odm_t *pDM_Odm,
 294                 enum odm_cmninfo CmnInfo,
 295                 u32 Value
 296         )
 297 {
 298         /* ODM_RT_TRACE(pDM_Odm,); */
 299
 300         /*  */
 301         /*  This section is used for init value */
 302         /*  */
 303         switch  (CmnInfo) {
 304         /*  Fixed ODM value. */
 305         case    ODM_CMNINFO_PLATFORM:
 306                 break;
 307         case    ODM_CMNINFO_INTERFACE:
 308                 pDM_Odm->SupportInterface = (u8)Value;
 309                 break;
 310         case    ODM_CMNINFO_MP_TEST_CHIP:
 311                 pDM_Odm->bIsMPChip = (u8)Value;
 312                 break;
 313         case    ODM_CMNINFO_IC_TYPE:
 314                 pDM_Odm->SupportICType = Value;
 315                 break;
 316         case    ODM_CMNINFO_CUT_VER:
 317                 pDM_Odm->CutVersion = (u8)Value;
 318                 break;
 319         case    ODM_CMNINFO_FAB_VER:
 320                 pDM_Odm->FabVersion = (u8)Value;
 321                 break;
 322         case    ODM_CMNINFO_BOARD_TYPE:
 323                 pDM_Odm->BoardType = (u8)Value;
 324                 break;
 325         case    ODM_CMNINFO_EXT_LNA:
 326                 pDM_Odm->ExtLNA = (u8)Value;
 327                 break;
 328         case    ODM_CMNINFO_EXT_PA:
 329                 pDM_Odm->ExtPA = (u8)Value;
 330                 break;
 331         case    ODM_CMNINFO_EXT_TRSW:
 332                 pDM_Odm->ExtTRSW = (u8)Value;
 333                 break;
 334         case    ODM_CMNINFO_PATCH_ID:
 335                 pDM_Odm->PatchID = (u8)Value;
 336                 break;
 337         case    ODM_CMNINFO_BINHCT_TEST:
 338                 pDM_Odm->bInHctTest = (bool)Value;
 339                 break;
 340         case    ODM_CMNINFO_BWIFI_TEST:
 341                 pDM_Odm->bWIFITest = (bool)Value;
 342                 break;
 343         case    ODM_CMNINFO_SMART_CONCURRENT:
 344                 pDM_Odm->bDualMacSmartConcurrent = (bool)Value;
 345                 break;
 346         /* To remove the compiler warning, must add an empty default statement to handle the other values. */
 347         default:
 348                 /* do nothing */
 349                 break;
 350         }
 351
 352         /*  */
 353         /*  Tx power tracking BB swing table. */
 354         /*  The base index = 12. +((12-n)/2)dB 13~?? = decrease tx pwr by -((n-12)/2)dB */
 355         /*  */
 356         pDM_Odm->BbSwingIdxOfdm                 = 12; /*  Set defalut value as index 12. */
 357         pDM_Odm->BbSwingIdxOfdmCurrent  = 12;
 358         pDM_Odm->BbSwingFlagOfdm                = false;
 359
 360 }
 361
 362 void ODM_CmnInfoPtrArrayHook23a(struct dm_odm_t *pDM_Odm, enum odm_cmninfo CmnInfo,
 363                                 u16 Index, void *pValue)
 364 {
 365         /*  Hook call by reference pointer. */
 366         switch  (CmnInfo) {
 367         /*  Dynamic call by reference pointer. */
 368         case    ODM_CMNINFO_STA_STATUS:
 369                 pDM_Odm->pODM_StaInfo[Index] = (struct sta_info *)pValue;
 370                 break;
 371         /* To remove the compiler warning, must add an empty default statement to handle the other values. */
 372         default:
 373                 /* do nothing */
 374                 break;
 375         }
 376 }
 377
 378 /*  Update Band/CHannel/.. The values are dynamic but non-per-packet. */
 379 void ODM_CmnInfoUpdate23a(struct dm_odm_t *pDM_Odm, u32 CmnInfo, u64 Value)
 380 {
 381         /*  This init variable may be changed in run time. */
 382         switch  (CmnInfo) {
 383         case    ODM_CMNINFO_WIFI_DIRECT:
 384                 pDM_Odm->bWIFI_Direct = (bool)Value;
 385                 break;
 386         case    ODM_CMNINFO_WIFI_DISPLAY:
 387                 pDM_Odm->bWIFI_Display = (bool)Value;
 388                 break;
 389         case    ODM_CMNINFO_LINK:
 390                 pDM_Odm->bLinked = (bool)Value;
 391                 break;
 392         case    ODM_CMNINFO_RSSI_MIN:
 393                 pDM_Odm->RSSI_Min = (u8)Value;
 394                 break;
 395         case    ODM_CMNINFO_DBG_COMP:
 396                 pDM_Odm->DebugComponents = Value;
 397                 break;
 398         case    ODM_CMNINFO_DBG_LEVEL:
 399                 pDM_Odm->DebugLevel = (u32)Value;
 400                 break;
 401         case    ODM_CMNINFO_RA_THRESHOLD_HIGH:
 402                 pDM_Odm->RateAdaptive.HighRSSIThresh = (u8)Value;
 403                 break;
 404         case    ODM_CMNINFO_RA_THRESHOLD_LOW:
 405                 pDM_Odm->RateAdaptive.LowRSSIThresh = (u8)Value;
 406                 break;
 407         }
 408
 409 }
 410
 411 void odm_CommonInfoSelfInit23a(struct dm_odm_t *pDM_Odm
 412         )
 413 {
 414         pDM_Odm->bCckHighPower =
 415                 (bool) ODM_GetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter2, BIT(9));
 416         pDM_Odm->RFPathRxEnable =
 417                 (u8) ODM_GetBBReg(pDM_Odm, rOFDM0_TRxPathEnable, 0x0F);
 418
 419         ODM_InitDebugSetting23a(pDM_Odm);
 420 }
 421
 422 static void odm_CommonInfoSelfUpdate(struct hal_data_8723a *pHalData)
 423 {
 424         struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
 425         struct sta_info *pEntry;
 426         u8 EntryCnt = 0;
 427         u8 i;
 428
 429         if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40) {
 430                 if (pHalData->nCur40MhzPrimeSC == 1)
 431                         pDM_Odm->ControlChannel = pHalData->CurrentChannel - 2;
 432                 else if (pHalData->nCur40MhzPrimeSC == 2)
 433                         pDM_Odm->ControlChannel = pHalData->CurrentChannel + 2;
 434         } else {
 435                 pDM_Odm->ControlChannel = pHalData->CurrentChannel;
 436         }
 437
 438         for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
 439                 pEntry = pDM_Odm->pODM_StaInfo[i];
 440                 if (pEntry)
 441                         EntryCnt++;
 442         }
 443         if (EntryCnt == 1)
 444                 pDM_Odm->bOneEntryOnly = true;
 445         else
 446                 pDM_Odm->bOneEntryOnly = false;
 447 }
 448
 449 void odm_CmnInfoInit_Debug23a(struct dm_odm_t *pDM_Odm)
 450 {
 451         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoInit_Debug23a ==>\n"));
 452         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportAbility = 0x%x\n", pDM_Odm->SupportAbility));
 453         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportInterface =%d\n", pDM_Odm->SupportInterface));
 454         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportICType = 0x%x\n", pDM_Odm->SupportICType));
 455         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("CutVersion =%d\n", pDM_Odm->CutVersion));
 456         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("FabVersion =%d\n", pDM_Odm->FabVersion));
 457         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("BoardType =%d\n", pDM_Odm->BoardType));
 458         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtLNA =%d\n", pDM_Odm->ExtLNA));
 459         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtPA =%d\n", pDM_Odm->ExtPA));
 460         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtTRSW =%d\n", pDM_Odm->ExtTRSW));
 461         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("PatchID =%d\n", pDM_Odm->PatchID));
 462         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bInHctTest =%d\n", pDM_Odm->bInHctTest));
 463         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFITest =%d\n", pDM_Odm->bWIFITest));
 464         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bDualMacSmartConcurrent =%d\n", pDM_Odm->bDualMacSmartConcurrent));
 465
 466 }
 467
 468 void odm_CmnInfoUpdate_Debug23a(struct dm_odm_t *pDM_Odm)
 469 {
 470         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoUpdate_Debug23a ==>\n"));
 471         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Direct =%d\n", pDM_Odm->bWIFI_Direct));
 472         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Display =%d\n", pDM_Odm->bWIFI_Display));
 473         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bLinked =%d\n", pDM_Odm->bLinked));
 474         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RSSI_Min =%d\n", pDM_Odm->RSSI_Min));
 475 }
 476
 477 void ODM_Write_DIG23a(struct dm_odm_t *pDM_Odm,
 478         u8 CurrentIGI
 479         )
 480 {
 481         struct dig_t *pDM_DigTable = &pDM_Odm->DM_DigTable;
 482
 483         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("ODM_REG(IGI_A, pDM_Odm) = 0x%x, ODM_BIT(IGI, pDM_Odm) = 0x%x \n",
 484                 ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm)));
 485
 486         if (pDM_DigTable->CurIGValue != CurrentIGI) {
 487                 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI);
 488                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("CurrentIGI(0x%02x). \n", CurrentIGI));
 489                 pDM_DigTable->CurIGValue = CurrentIGI;
 490         }
 491         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
 492                      ("ODM_Write_DIG23a():CurrentIGI = 0x%x \n", CurrentIGI));
 493 }
 494
 495 /* Need LPS mode for CE platform --2012--08--24--- */
 496 /* 8723AS/8189ES */
 497 void odm_DIG23abyRSSI_LPS(struct dm_odm_t *pDM_Odm)
 498 {
 499         struct rtw_adapter *pAdapter = pDM_Odm->Adapter;
 500         struct false_alarm_stats *pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
 501         u8 RSSI_Lower = DM_DIG_MIN_NIC;   /* 0x1E or 0x1C */
 502         u8 bFwCurrentInPSMode = false;
 503         u8 CurrentIGI = pDM_Odm->RSSI_Min;
 504
 505         if (!(pDM_Odm->SupportICType & ODM_RTL8723A))
 506                 return;
 507
 508         CurrentIGI = CurrentIGI+RSSI_OFFSET_DIG;
 509         bFwCurrentInPSMode = pAdapter->pwrctrlpriv.bFwCurrentInPSMode;
 510
 511         /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG_LPS, ODM_DBG_LOUD, ("odm_DIG23a() ==>\n")); */
 512
 513         /*  Using FW PS mode to make IGI */
 514         if (bFwCurrentInPSMode) {
 515                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("---Neil---odm_DIG23a is in LPS mode\n"));
 516                 /* Adjust by  FA in LPS MODE */
 517                 if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2_LPS)
 518                         CurrentIGI = CurrentIGI+2;
 519                 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1_LPS)
 520                         CurrentIGI = CurrentIGI+1;
 521                 else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0_LPS)
 522                         CurrentIGI = CurrentIGI-1;
 523         } else {
 524                 CurrentIGI = RSSI_Lower;
 525         }
 526
 527         /* Lower bound checking */
 528
 529         /* RSSI Lower bound check */
 530         if ((pDM_Odm->RSSI_Min-10) > DM_DIG_MIN_NIC)
 531                 RSSI_Lower = (pDM_Odm->RSSI_Min-10);
 532         else
 533                 RSSI_Lower = DM_DIG_MIN_NIC;
 534
 535         /* Upper and Lower Bound checking */
 536          if (CurrentIGI > DM_DIG_MAX_NIC)
 537                 CurrentIGI = DM_DIG_MAX_NIC;
 538          else if (CurrentIGI < RSSI_Lower)
 539                 CurrentIGI = RSSI_Lower;
 540
 541         ODM_Write_DIG23a(pDM_Odm, CurrentIGI);/* ODM_Write_DIG23a(pDM_Odm, pDM_DigTable->CurIGValue); */
 542
 543 }
 544
 545 void odm_DIG23aInit(struct dm_odm_t *pDM_Odm)
 546 {
 547         struct dig_t *pDM_DigTable = &pDM_Odm->DM_DigTable;
 548
 549         pDM_DigTable->CurIGValue = (u8) ODM_GetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm));
 550         pDM_DigTable->RssiLowThresh     = DM_DIG_THRESH_LOW;
 551         pDM_DigTable->RssiHighThresh    = DM_DIG_THRESH_HIGH;
 552         pDM_DigTable->FALowThresh       = DM_FALSEALARM_THRESH_LOW;
 553         pDM_DigTable->FAHighThresh      = DM_FALSEALARM_THRESH_HIGH;
 554         if (pDM_Odm->BoardType == ODM_BOARD_HIGHPWR) {
 555                 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
 556                 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC;
 557         } else {
 558                 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
 559                 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC;
 560         }
 561         pDM_DigTable->BackoffVal = DM_DIG_BACKOFF_DEFAULT;
 562         pDM_DigTable->BackoffVal_range_max = DM_DIG_BACKOFF_MAX;
 563         pDM_DigTable->BackoffVal_range_min = DM_DIG_BACKOFF_MIN;
 564         pDM_DigTable->PreCCK_CCAThres = 0xFF;
 565         pDM_DigTable->CurCCK_CCAThres = 0x83;
 566         pDM_DigTable->ForbiddenIGI = DM_DIG_MIN_NIC;
 567         pDM_DigTable->LargeFAHit = 0;
 568         pDM_DigTable->Recover_cnt = 0;
 569         pDM_DigTable->DIG_Dynamic_MIN_0 = DM_DIG_MIN_NIC;
 570         pDM_DigTable->DIG_Dynamic_MIN_1 = DM_DIG_MIN_NIC;
 571         pDM_DigTable->bMediaConnect_0 = false;
 572         pDM_DigTable->bMediaConnect_1 = false;
 573 }
 574
 575 void odm_DIG23a(struct rtw_adapter *adapter)
 576 {
 577         struct hal_data_8723a *pHalData = GET_HAL_DATA(adapter);
 578         struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
 579         struct dig_t *pDM_DigTable = &pDM_Odm->DM_DigTable;
 580         struct false_alarm_stats *pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
 581         u8 DIG_Dynamic_MIN;
 582         u8 DIG_MaxOfMin;
 583         bool FirstConnect, FirstDisConnect;
 584         u8 dm_dig_max, dm_dig_min;
 585         u8 CurrentIGI = pDM_DigTable->CurIGValue;
 586
 587         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a() ==>\n"));
 588         /* if (!(pDM_Odm->SupportAbility & (ODM_BB_DIG|ODM_BB_FA_CNT))) */
 589         if ((!(pDM_Odm->SupportAbility&ODM_BB_DIG)) || (!(pDM_Odm->SupportAbility&ODM_BB_FA_CNT))) {
 590                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
 591                              ("odm_DIG23a() Return: SupportAbility ODM_BB_DIG or ODM_BB_FA_CNT is disabled\n"));
 592                 return;
 593         }
 594
 595         if (adapter->mlmepriv.bScanInProcess) {
 596                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a() Return: In Scan Progress \n"));
 597                 return;
 598         }
 599
 600         DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0;
 601         FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_0);
 602         FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0);
 603
 604         /* 1 Boundary Decision */
 605         if ((pDM_Odm->SupportICType & ODM_RTL8723A) &&
 606             ((pDM_Odm->BoardType == ODM_BOARD_HIGHPWR) || pDM_Odm->ExtLNA)) {
 607                 dm_dig_max = DM_DIG_MAX_NIC_HP;
 608                 dm_dig_min = DM_DIG_MIN_NIC_HP;
 609                 DIG_MaxOfMin = DM_DIG_MAX_AP_HP;
 610         } else {
 611                 dm_dig_max = DM_DIG_MAX_NIC;
 612                 dm_dig_min = DM_DIG_MIN_NIC;
 613                 DIG_MaxOfMin = DM_DIG_MAX_AP;
 614         }
 615
 616         if (pDM_Odm->bLinked) {
 617               /* 2 8723A Series, offset need to be 10 */
 618                 if (pDM_Odm->SupportICType == ODM_RTL8723A) {
 619                         /* 2 Upper Bound */
 620                         if ((pDM_Odm->RSSI_Min + 10) > DM_DIG_MAX_NIC)
 621                                 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
 622                         else if ((pDM_Odm->RSSI_Min + 10) < DM_DIG_MIN_NIC)
 623                                 pDM_DigTable->rx_gain_range_max = DM_DIG_MIN_NIC;
 624                         else
 625                                 pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 10;
 626
 627                         /* 2 If BT is Concurrent, need to set Lower Bound */
 628                         DIG_Dynamic_MIN = DM_DIG_MIN_NIC;
 629                 } else {
 630                         /* 2 Modify DIG upper bound */
 631                         if ((pDM_Odm->RSSI_Min + 20) > dm_dig_max)
 632                                 pDM_DigTable->rx_gain_range_max = dm_dig_max;
 633                         else if ((pDM_Odm->RSSI_Min + 20) < dm_dig_min)
 634                                 pDM_DigTable->rx_gain_range_max = dm_dig_min;
 635                         else
 636                                 pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 20;
 637
 638                         /* 2 Modify DIG lower bound */
 639                         if (pDM_Odm->bOneEntryOnly) {
 640                                 if (pDM_Odm->RSSI_Min < dm_dig_min)
 641                                         DIG_Dynamic_MIN = dm_dig_min;
 642                                 else if (pDM_Odm->RSSI_Min > DIG_MaxOfMin)
 643                                         DIG_Dynamic_MIN = DIG_MaxOfMin;
 644                                 else
 645                                         DIG_Dynamic_MIN = pDM_Odm->RSSI_Min;
 646                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
 647                                              ("odm_DIG23a() : bOneEntryOnly = true,  DIG_Dynamic_MIN = 0x%x\n",
 648                                              DIG_Dynamic_MIN));
 649                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
 650                                              ("odm_DIG23a() : pDM_Odm->RSSI_Min =%d\n",
 651                                              pDM_Odm->RSSI_Min));
 652                         } else {
 653                                 DIG_Dynamic_MIN = dm_dig_min;
 654                         }
 655                 }
 656         } else {
 657                 pDM_DigTable->rx_gain_range_max = dm_dig_max;
 658                 DIG_Dynamic_MIN = dm_dig_min;
 659                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a() : No Link\n"));
 660         }
 661
 662         /* 1 Modify DIG lower bound, deal with abnormally large false alarm */
 663         if (pFalseAlmCnt->Cnt_all > 10000) {
 664                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
 665                              ("dm_DIG(): Abnornally false alarm case. \n"));
 666
 667                 if (pDM_DigTable->LargeFAHit != 3)
 668                         pDM_DigTable->LargeFAHit++;
 669                 if (pDM_DigTable->ForbiddenIGI < CurrentIGI) {
 670                         pDM_DigTable->ForbiddenIGI = CurrentIGI;
 671                         pDM_DigTable->LargeFAHit = 1;
 672                 }
 673
 674                 if (pDM_DigTable->LargeFAHit >= 3) {
 675                         if ((pDM_DigTable->ForbiddenIGI+1) > pDM_DigTable->rx_gain_range_max)
 676                                 pDM_DigTable->rx_gain_range_min = pDM_DigTable->rx_gain_range_max;
 677                         else
 678                                 pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1);
 679                         pDM_DigTable->Recover_cnt = 3600; /* 3600 = 2hr */
 680                 }
 681         } else {
 682                 /* Recovery mechanism for IGI lower bound */
 683                 if (pDM_DigTable->Recover_cnt != 0) {
 684                         pDM_DigTable->Recover_cnt--;
 685                 } else {
 686                         if (pDM_DigTable->LargeFAHit < 3) {
 687                                 if ((pDM_DigTable->ForbiddenIGI - 1) < DIG_Dynamic_MIN) {
 688                                         pDM_DigTable->ForbiddenIGI = DIG_Dynamic_MIN; /* DM_DIG_MIN; */
 689                                         pDM_DigTable->rx_gain_range_min = DIG_Dynamic_MIN; /* DM_DIG_MIN; */
 690                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
 691                                                      ("odm_DIG23a(): Normal Case: At Lower Bound\n"));
 692                                 } else {
 693                                         pDM_DigTable->ForbiddenIGI--;
 694                                         pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1);
 695                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
 696                                                      ("odm_DIG23a(): Normal Case: Approach Lower Bound\n"));
 697                                 }
 698                         } else {
 699                                 pDM_DigTable->LargeFAHit = 0;
 700                         }
 701                 }
 702         }
 703         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): pDM_DigTable->LargeFAHit =%d\n", pDM_DigTable->LargeFAHit));
 704
 705         /* 1 Adjust initial gain by false alarm */
 706         if (pDM_Odm->bLinked) {
 707                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): DIG AfterLink\n"));
 708                 if (FirstConnect) {
 709                         CurrentIGI = pDM_Odm->RSSI_Min;
 710                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: First Connect\n"));
 711                 } else {
 712                         if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2)
 713                                 CurrentIGI = CurrentIGI + 4;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */
 714                         else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1)
 715                                 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */
 716                         else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0)
 717                                 CurrentIGI = CurrentIGI - 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue-1; */
 718                 }
 719         } else {
 720                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): DIG BeforeLink\n"));
 721                 if (FirstDisConnect) {
 722                         CurrentIGI = pDM_DigTable->rx_gain_range_min;
 723                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): First DisConnect \n"));
 724                 } else {
 725                         /* 2012.03.30 LukeLee: enable DIG before link but with very high thresholds */
 726                         if (pFalseAlmCnt->Cnt_all > 10000)
 727                                 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */
 728                         else if (pFalseAlmCnt->Cnt_all > 8000)
 729                                 CurrentIGI = CurrentIGI + 1;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */
 730                         else if (pFalseAlmCnt->Cnt_all < 500)
 731                                 CurrentIGI = CurrentIGI - 1;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue-1; */
 732                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): England DIG \n"));
 733                 }
 734         }
 735         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): DIG End Adjust IGI\n"));
 736         /* 1 Check initial gain by upper/lower bound */
 737         if (CurrentIGI > pDM_DigTable->rx_gain_range_max)
 738                 CurrentIGI = pDM_DigTable->rx_gain_range_max;
 739         if (CurrentIGI < pDM_DigTable->rx_gain_range_min)
 740                 CurrentIGI = pDM_DigTable->rx_gain_range_min;
 741
 742         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): rx_gain_range_max = 0x%x, rx_gain_range_min = 0x%x\n",
 743                 pDM_DigTable->rx_gain_range_max, pDM_DigTable->rx_gain_range_min));
 744         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): TotalFA =%d\n", pFalseAlmCnt->Cnt_all));
 745         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): CurIGValue = 0x%x\n", CurrentIGI));
 746
 747         /* 2 High power RSSI threshold */
 748
 749         ODM_Write_DIG23a(pDM_Odm, CurrentIGI);/* ODM_Write_DIG23a(pDM_Odm, pDM_DigTable->CurIGValue); */
 750         pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked;
 751         pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN;
 752 }
 753
 754 /* 3 ============================================================ */
 755 /* 3 FASLE ALARM CHECK */
 756 /* 3 ============================================================ */
 757
 758 void odm_FalseAlarmCounterStatistics23a(struct dm_odm_t *pDM_Odm)
 759 {
 760         u32 ret_value;
 761         struct false_alarm_stats *FalseAlmCnt = &pDM_Odm->FalseAlmCnt;
 762
 763         if (!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT))
 764                 return;
 765
 766         /* hold ofdm counter */
 767          /* hold page C counter */
 768         ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT(31), 1);
 769         /* hold page D counter */
 770         ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(31), 1);
 771         ret_value =
 772                 ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE1_11N, bMaskDWord);
 773         FalseAlmCnt->Cnt_Fast_Fsync = (ret_value&0xffff);
 774         FalseAlmCnt->Cnt_SB_Search_fail = ((ret_value&0xffff0000)>>16);
 775         ret_value =
 776                 ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE2_11N, bMaskDWord);
 777         FalseAlmCnt->Cnt_OFDM_CCA = (ret_value&0xffff);
 778         FalseAlmCnt->Cnt_Parity_Fail = ((ret_value&0xffff0000)>>16);
 779         ret_value =
 780                 ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE3_11N, bMaskDWord);
 781         FalseAlmCnt->Cnt_Rate_Illegal = (ret_value&0xffff);
 782         FalseAlmCnt->Cnt_Crc8_fail = ((ret_value&0xffff0000)>>16);
 783         ret_value =
 784                 ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE4_11N, bMaskDWord);
 785         FalseAlmCnt->Cnt_Mcs_fail = (ret_value&0xffff);
 786
 787         FalseAlmCnt->Cnt_Ofdm_fail = FalseAlmCnt->Cnt_Parity_Fail +
 788                 FalseAlmCnt->Cnt_Rate_Illegal +
 789                 FalseAlmCnt->Cnt_Crc8_fail +
 790                 FalseAlmCnt->Cnt_Mcs_fail +
 791                 FalseAlmCnt->Cnt_Fast_Fsync +
 792                 FalseAlmCnt->Cnt_SB_Search_fail;
 793         /* hold cck counter */
 794         ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT(12), 1);
 795         ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT(14), 1);
 796
 797         ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_LSB_11N, bMaskByte0);
 798         FalseAlmCnt->Cnt_Cck_fail = ret_value;
 799         ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_MSB_11N, bMaskByte3);
 800         FalseAlmCnt->Cnt_Cck_fail +=  (ret_value & 0xff) << 8;
 801
 802         ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_CCA_CNT_11N, bMaskDWord);
 803         FalseAlmCnt->Cnt_CCK_CCA =
 804                 ((ret_value&0xFF)<<8) | ((ret_value&0xFF00)>>8);
 805
 806         FalseAlmCnt->Cnt_all = (FalseAlmCnt->Cnt_Fast_Fsync +
 807                                 FalseAlmCnt->Cnt_SB_Search_fail +
 808                                 FalseAlmCnt->Cnt_Parity_Fail +
 809                                 FalseAlmCnt->Cnt_Rate_Illegal +
 810                                 FalseAlmCnt->Cnt_Crc8_fail +
 811                                 FalseAlmCnt->Cnt_Mcs_fail +
 812                                 FalseAlmCnt->Cnt_Cck_fail);
 813
 814         FalseAlmCnt->Cnt_CCA_all =
 815                 FalseAlmCnt->Cnt_OFDM_CCA + FalseAlmCnt->Cnt_CCK_CCA;
 816
 817         if (pDM_Odm->SupportICType >= ODM_RTL8723A) {
 818                 /* reset false alarm counter registers */
 819                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT(31), 1);
 820                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT(31), 0);
 821                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(27), 1);
 822                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(27), 0);
 823                 /* update ofdm counter */
 824                  /* update page C counter */
 825                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT(31), 0);
 826                  /* update page D counter */
 827                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(31), 0);
 828
 829                 /* reset CCK CCA counter */
 830                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N,
 831                              BIT(13) | BIT(12), 0);
 832                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N,
 833                              BIT(13) | BIT(12), 2);
 834                 /* reset CCK FA counter */
 835                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N,
 836                              BIT(15) | BIT(14), 0);
 837                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N,
 838                              BIT(15) | BIT(14), 2);
 839         }
 840
 841         ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD,
 842                      ("Enter odm_FalseAlarmCounterStatistics23a\n"));
 843         ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD,
 844                      ("Cnt_Fast_Fsync =%d, Cnt_SB_Search_fail =%d\n",
 845                       FalseAlmCnt->Cnt_Fast_Fsync,
 846                       FalseAlmCnt->Cnt_SB_Search_fail));
 847         ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD,
 848                      ("Cnt_Parity_Fail =%d, Cnt_Rate_Illegal =%d\n",
 849                       FalseAlmCnt->Cnt_Parity_Fail,
 850                       FalseAlmCnt->Cnt_Rate_Illegal));
 851         ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD,
 852                      ("Cnt_Crc8_fail =%d, Cnt_Mcs_fail =%d\n",
 853                       FalseAlmCnt->Cnt_Crc8_fail, FalseAlmCnt->Cnt_Mcs_fail));
 854
 855         ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Cck_fail =%d\n", FalseAlmCnt->Cnt_Cck_fail));
 856         ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Ofdm_fail =%d\n", FalseAlmCnt->Cnt_Ofdm_fail));
 857         ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Total False Alarm =%d\n", FalseAlmCnt->Cnt_all));
 858 }
 859
 860 /* 3 ============================================================ */
 861 /* 3 CCK Packet Detect Threshold */
 862 /* 3 ============================================================ */
 863
 864 void odm_CCKPacketDetectionThresh23a(struct dm_odm_t *pDM_Odm)
 865 {
 866         struct false_alarm_stats *FalseAlmCnt = &pDM_Odm->FalseAlmCnt;
 867         u8 CurCCK_CCAThres;
 868
 869         if (!(pDM_Odm->SupportAbility & (ODM_BB_CCK_PD|ODM_BB_FA_CNT)))
 870                 return;
 871
 872         if (pDM_Odm->ExtLNA)
 873                 return;
 874
 875         if (pDM_Odm->bLinked) {
 876                 if (pDM_Odm->RSSI_Min > 25) {
 877                         CurCCK_CCAThres = 0xcd;
 878                 } else if ((pDM_Odm->RSSI_Min <= 25) && (pDM_Odm->RSSI_Min > 10)) {
 879                         CurCCK_CCAThres = 0x83;
 880                 } else {
 881                         if (FalseAlmCnt->Cnt_Cck_fail > 1000)
 882                                 CurCCK_CCAThres = 0x83;
 883                         else
 884                                 CurCCK_CCAThres = 0x40;
 885                 }
 886         } else {
 887                 if (FalseAlmCnt->Cnt_Cck_fail > 1000)
 888                         CurCCK_CCAThres = 0x83;
 889                 else
 890                         CurCCK_CCAThres = 0x40;
 891         }
 892
 893         ODM_Write_CCK_CCA_Thres23a(pDM_Odm, CurCCK_CCAThres);
 894 }
 895
 896 void ODM_Write_CCK_CCA_Thres23a(struct dm_odm_t *pDM_Odm, u8 CurCCK_CCAThres)
 897 {
 898         struct dig_t *pDM_DigTable = &pDM_Odm->DM_DigTable;
 899
 900         if (pDM_DigTable->CurCCK_CCAThres != CurCCK_CCAThres)
 901                 ODM_Write1Byte(pDM_Odm, ODM_REG(CCK_CCA, pDM_Odm), CurCCK_CCAThres);
 902         pDM_DigTable->PreCCK_CCAThres = pDM_DigTable->CurCCK_CCAThres;
 903         pDM_DigTable->CurCCK_CCAThres = CurCCK_CCAThres;
 904
 905 }
 906
 907 /* 3 ============================================================ */
 908 /* 3 BB Power Save */
 909 /* 3 ============================================================ */
 910 void odm23a_DynBBPSInit(struct dm_odm_t *pDM_Odm)
 911 {
 912         struct dynamic_pwr_sav *pDM_PSTable = &pDM_Odm->DM_PSTable;
 913
 914         pDM_PSTable->PreCCAState = CCA_MAX;
 915         pDM_PSTable->CurCCAState = CCA_MAX;
 916         pDM_PSTable->PreRFState = RF_MAX;
 917         pDM_PSTable->CurRFState = RF_MAX;
 918         pDM_PSTable->Rssi_val_min = 0;
 919         pDM_PSTable->initialize = 0;
 920 }
 921
 922 void odm_DynamicBBPowerSaving23a(struct dm_odm_t *pDM_Odm)
 923 {
 924         return;
 925 }
 926
 927 void ODM_RF_Saving23a(struct dm_odm_t *pDM_Odm, u8 bForceInNormal)
 928 {
 929         struct dynamic_pwr_sav *pDM_PSTable = &pDM_Odm->DM_PSTable;
 930         u8 Rssi_Up_bound = 30;
 931         u8 Rssi_Low_bound = 25;
 932         if (pDM_Odm->PatchID == 40) { /* RT_CID_819x_FUNAI_TV */
 933                 Rssi_Up_bound = 50;
 934                 Rssi_Low_bound = 45;
 935         }
 936         if (pDM_PSTable->initialize == 0) {
 937
 938                 pDM_PSTable->Reg874 = (ODM_GetBBReg(pDM_Odm, 0x874, bMaskDWord)&0x1CC000)>>14;
 939                 pDM_PSTable->RegC70 =
 940                         (ODM_GetBBReg(pDM_Odm, 0xc70, bMaskDWord) & BIT(3)) >>3;
 941                 pDM_PSTable->Reg85C = (ODM_GetBBReg(pDM_Odm, 0x85c, bMaskDWord)&0xFF000000)>>24;
 942                 pDM_PSTable->RegA74 = (ODM_GetBBReg(pDM_Odm, 0xa74, bMaskDWord)&0xF000)>>12;
 943                 /* Reg818 = PHY_QueryBBReg(pAdapter, 0x818, bMaskDWord); */
 944                 pDM_PSTable->initialize = 1;
 945         }
 946
 947         if (!bForceInNormal) {
 948                 if (pDM_Odm->RSSI_Min != 0xFF) {
 949                         if (pDM_PSTable->PreRFState == RF_Normal) {
 950                                 if (pDM_Odm->RSSI_Min >= Rssi_Up_bound)
 951                                         pDM_PSTable->CurRFState = RF_Save;
 952                                 else
 953                                         pDM_PSTable->CurRFState = RF_Normal;
 954                         } else {
 955                                 if (pDM_Odm->RSSI_Min <= Rssi_Low_bound)
 956                                         pDM_PSTable->CurRFState = RF_Normal;
 957                                 else
 958                                         pDM_PSTable->CurRFState = RF_Save;
 959                         }
 960                 } else {
 961                         pDM_PSTable->CurRFState = RF_MAX;
 962                 }
 963         } else {
 964                 pDM_PSTable->CurRFState = RF_Normal;
 965         }
 966
 967         if (pDM_PSTable->PreRFState != pDM_PSTable->CurRFState) {
 968                 if (pDM_PSTable->CurRFState == RF_Save) {
 969                         /*  <tynli_note> 8723 RSSI report will be wrong. Set 0x874[5]= 1 when enter BB power saving mode. */
 970                         /*  Suggested by SD3 Yu-Nan. 2011.01.20. */
 971                         if (pDM_Odm->SupportICType == ODM_RTL8723A)
 972                                 ODM_SetBBReg(pDM_Odm, 0x874, BIT(5), 0x1); /* Reg874[5]= 1b'1 */
 973                         ODM_SetBBReg(pDM_Odm, 0x874, 0x1C0000, 0x2); /* Reg874[20:18]= 3'b010 */
 974                         ODM_SetBBReg(pDM_Odm, 0xc70, BIT(3), 0); /* RegC70[3]= 1'b0 */
 975                         ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, 0x63); /* Reg85C[31:24]= 0x63 */
 976                         ODM_SetBBReg(pDM_Odm, 0x874, 0xC000, 0x2); /* Reg874[15:14]= 2'b10 */
 977                         ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, 0x3); /* RegA75[7:4]= 0x3 */
 978                         ODM_SetBBReg(pDM_Odm, 0x818, BIT(28), 0x0); /* Reg818[28]= 1'b0 */
 979                         ODM_SetBBReg(pDM_Odm, 0x818, BIT(28), 0x1); /* Reg818[28]= 1'b1 */
 980                 } else {
 981                         ODM_SetBBReg(pDM_Odm, 0x874, 0x1CC000, pDM_PSTable->Reg874);
 982                         ODM_SetBBReg(pDM_Odm, 0xc70, BIT(3), pDM_PSTable->RegC70);
 983                         ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, pDM_PSTable->Reg85C);
 984                         ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, pDM_PSTable->RegA74);
 985                         ODM_SetBBReg(pDM_Odm, 0x818, BIT(28), 0x0);
 986
 987                         if (pDM_Odm->SupportICType == ODM_RTL8723A)
 988                                 ODM_SetBBReg(pDM_Odm, 0x874, BIT(5), 0x0); /* Reg874[5]= 1b'0 */
 989                 }
 990                 pDM_PSTable->PreRFState = pDM_PSTable->CurRFState;
 991         }
 992 }
 993
 994 /* 3 ============================================================ */
 995 /* 3 RATR MASK */
 996 /* 3 ============================================================ */
 997 /* 3 ============================================================ */
 998 /* 3 Rate Adaptive */
 999 /* 3 ============================================================ */
1000
1001 void odm_RateAdaptiveMaskInit23a(struct dm_odm_t *pDM_Odm)
1002 {
1003         struct odm_rate_adapt *pOdmRA = &pDM_Odm->RateAdaptive;
1004
1005         pOdmRA->Type = DM_Type_ByDriver;
1006
1007         pOdmRA->RATRState = DM_RATR_STA_INIT;
1008         pOdmRA->HighRSSIThresh = 50;
1009         pOdmRA->LowRSSIThresh = 20;
1010 }
1011
1012 u32 ODM_Get_Rate_Bitmap23a(struct hal_data_8723a *pHalData, u32 macid,
1013                            u32 ra_mask, u8 rssi_level)
1014 {
1015         struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
1016         struct sta_info *pEntry;
1017         u32 rate_bitmap = 0x0fffffff;
1018         u8 WirelessMode;
1019
1020         pEntry = pDM_Odm->pODM_StaInfo[macid];
1021         if (!pEntry)
1022                 return ra_mask;
1023
1024         WirelessMode = pEntry->wireless_mode;
1025
1026         switch (WirelessMode) {
1027         case ODM_WM_B:
1028                 if (ra_mask & 0x0000000c)               /* 11M or 5.5M enable */
1029                         rate_bitmap = 0x0000000d;
1030                 else
1031                         rate_bitmap = 0x0000000f;
1032                 break;
1033         case (ODM_WM_A|ODM_WM_G):
1034                 if (rssi_level == DM_RATR_STA_HIGH)
1035                         rate_bitmap = 0x00000f00;
1036                 else
1037                         rate_bitmap = 0x00000ff0;
1038                 break;
1039         case (ODM_WM_B|ODM_WM_G):
1040                 if (rssi_level == DM_RATR_STA_HIGH)
1041                         rate_bitmap = 0x00000f00;
1042                 else if (rssi_level == DM_RATR_STA_MIDDLE)
1043                         rate_bitmap = 0x00000ff0;
1044                 else
1045                         rate_bitmap = 0x00000ff5;
1046                 break;
1047         case (ODM_WM_B|ODM_WM_G|ODM_WM_N24G):
1048         case (ODM_WM_A|ODM_WM_B|ODM_WM_G|ODM_WM_N24G):
1049                 if (pHalData->rf_type == RF_1T2R ||
1050                     pHalData->rf_type == RF_1T1R) {
1051                         if (rssi_level == DM_RATR_STA_HIGH) {
1052                                 rate_bitmap = 0x000f0000;
1053                         } else if (rssi_level == DM_RATR_STA_MIDDLE) {
1054                                 rate_bitmap = 0x000ff000;
1055                         } else {
1056                                 if (pHalData->CurrentChannelBW ==
1057                                     HT_CHANNEL_WIDTH_40)
1058                                         rate_bitmap = 0x000ff015;
1059                                 else
1060                                         rate_bitmap = 0x000ff005;
1061                         }
1062                 } else {
1063                         if (rssi_level == DM_RATR_STA_HIGH) {
1064                                 rate_bitmap = 0x0f8f0000;
1065                         } else if (rssi_level == DM_RATR_STA_MIDDLE) {
1066                                 rate_bitmap = 0x0f8ff000;
1067                         } else {
1068                                 if (pHalData->CurrentChannelBW ==
1069                                     HT_CHANNEL_WIDTH_40)
1070                                         rate_bitmap = 0x0f8ff015;
1071                                 else
1072                                         rate_bitmap = 0x0f8ff005;
1073                         }
1074                 }
1075                 break;
1076         default:
1077                 /* case WIRELESS_11_24N: */
1078                 /* case WIRELESS_11_5N: */
1079                 if (pHalData->rf_type == RF_1T2R)
1080                         rate_bitmap = 0x000fffff;
1081                 else
1082                         rate_bitmap = 0x0fffffff;
1083                 break;
1084         }
1085
1086         /* printk("%s ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x \n", __func__, rssi_level, WirelessMode, rate_bitmap); */
1087         ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, (" ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x \n", rssi_level, WirelessMode, rate_bitmap));
1088
1089         return rate_bitmap;
1090
1091 }
1092
1093 /*-----------------------------------------------------------------------------
1094  * Function:    odm_RefreshRateAdaptiveMask23a()
1095  *
1096  * Overview:    Update rate table mask according to rssi
1097  *
1098  * Input:               NONE
1099  *
1100  * Output:              NONE
1101  *
1102  * Return:              NONE
1103  *
1104  * Revised History:
1105  *When          Who             Remark
1106  *05/27/2009    hpfan   Create Version 0.
1107  *
1108  *---------------------------------------------------------------------------*/
1109 void odm_RefreshRateAdaptiveMask23a(struct dm_odm_t *pDM_Odm)
1110 {
1111         if (!(pDM_Odm->SupportAbility & ODM_BB_RA_MASK))
1112                 return;
1113         /*  */
1114         /*  2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1115         /*  at the same time. In the stage2/3, we need to prive universal interface and merge all */
1116         /*  HW dynamic mechanism. */
1117         /*  */
1118         odm_RefreshRateAdaptiveMask23aCE23a(pDM_Odm);
1119 }
1120
1121 void odm_RefreshRateAdaptiveMask23aCE23a(struct dm_odm_t *pDM_Odm)
1122 {
1123         u8 i;
1124         struct rtw_adapter *pAdapter     =  pDM_Odm->Adapter;
1125
1126         if (pAdapter->bDriverStopped) {
1127                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE,
1128                              ("<---- odm_RefreshRateAdaptiveMask23a(): driver is going to unload\n"));
1129                 return;
1130         }
1131
1132         for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
1133                 struct sta_info *pstat = pDM_Odm->pODM_StaInfo[i];
1134                 if (pstat) {
1135                         if (ODM_RAStateCheck23a(pDM_Odm, pstat->rssi_stat.UndecoratedSmoothedPWDB, false, &pstat->rssi_level)) {
1136                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD,
1137                                              ("RSSI:%d, RSSI_LEVEL:%d\n",
1138                                              pstat->rssi_stat.UndecoratedSmoothedPWDB,
1139                                              pstat->rssi_level));
1140                                 rtw_hal_update_ra_mask23a(pstat, pstat->rssi_level);
1141                         }
1142
1143                 }
1144         }
1145
1146 }
1147
1148 /*  Return Value: bool */
1149 /*  - true: RATRState is changed. */
1150 bool ODM_RAStateCheck23a(struct dm_odm_t *pDM_Odm, s32 RSSI, bool bForceUpdate,
1151                          u8 *pRATRState)
1152 {
1153         struct odm_rate_adapt *pRA = &pDM_Odm->RateAdaptive;
1154         const u8 GoUpGap = 5;
1155         u8 HighRSSIThreshForRA = pRA->HighRSSIThresh;
1156         u8 LowRSSIThreshForRA = pRA->LowRSSIThresh;
1157         u8 RATRState;
1158
1159         /*  Threshold Adjustment: */
1160         /*  when RSSI state trends to go up one or two levels, make sure RSSI is high enough. */
1161         /*  Here GoUpGap is added to solve the boundary's level alternation issue. */
1162         switch (*pRATRState) {
1163         case DM_RATR_STA_INIT:
1164         case DM_RATR_STA_HIGH:
1165                 break;
1166         case DM_RATR_STA_MIDDLE:
1167                 HighRSSIThreshForRA += GoUpGap;
1168                 break;
1169         case DM_RATR_STA_LOW:
1170                 HighRSSIThreshForRA += GoUpGap;
1171                 LowRSSIThreshForRA += GoUpGap;
1172                 break;
1173         default:
1174                 ODM_RT_ASSERT(pDM_Odm, false, ("wrong rssi level setting %d !", *pRATRState));
1175                 break;
1176         }
1177
1178         /*  Decide RATRState by RSSI. */
1179         if (RSSI > HighRSSIThreshForRA)
1180                 RATRState = DM_RATR_STA_HIGH;
1181         else if (RSSI > LowRSSIThreshForRA)
1182                 RATRState = DM_RATR_STA_MIDDLE;
1183         else
1184                 RATRState = DM_RATR_STA_LOW;
1185
1186         if (*pRATRState != RATRState || bForceUpdate) {
1187                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD,
1188                              ("RSSI Level %d -> %d\n", *pRATRState, RATRState));
1189                 *pRATRState = RATRState;
1190                 return true;
1191         }
1192         return false;
1193 }
1194
1195 /* 3 ============================================================ */
1196 /* 3 Dynamic Tx Power */
1197 /* 3 ============================================================ */
1198
1199 void odm_DynamicTxPower23aInit(struct dm_odm_t *pDM_Odm)
1200 {
1201         struct rtw_adapter *Adapter = pDM_Odm->Adapter;
1202         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1203         struct dm_priv *pdmpriv = &pHalData->dmpriv;
1204
1205         /*
1206          * This is never changed, so we should be able to clean up the
1207          * code checking for different values in rtl8723a_rf6052.c
1208          */
1209         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
1210 }
1211
1212 void odm_RSSIMonitorCheck23a(struct dm_odm_t *pDM_Odm)
1213 {
1214         /*  For AP/ADSL use struct rtl8723a_priv * */
1215         /*  For CE/NIC use struct rtw_adapter * */
1216
1217         if (!(pDM_Odm->SupportAbility & ODM_BB_RSSI_MONITOR))
1218                 return;
1219
1220         /*  2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1221         /*  at the same time. In the stage2/3, we need to prive universal interface and merge all */
1222         /*  HW dynamic mechanism. */
1223         odm_RSSIMonitorCheck23aCE(pDM_Odm);
1224 }       /*  odm_RSSIMonitorCheck23a */
1225
1226 static void
1227 FindMinimumRSSI(
1228         struct rtw_adapter *pAdapter
1229         )
1230 {
1231         struct hal_data_8723a *pHalData = GET_HAL_DATA(pAdapter);
1232         struct dm_priv *pdmpriv = &pHalData->dmpriv;
1233         struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
1234
1235         /* 1 1.Determine the minimum RSSI */
1236
1237         if ((!pDM_Odm->bLinked) &&
1238             (pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0))
1239                 pdmpriv->MinUndecoratedPWDBForDM = 0;
1240         else
1241                 pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
1242 }
1243
1244 void odm_RSSIMonitorCheck23aCE(struct dm_odm_t *pDM_Odm)
1245 {
1246         struct rtw_adapter *Adapter = pDM_Odm->Adapter;
1247         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1248         struct dm_priv *pdmpriv = &pHalData->dmpriv;
1249         int     i;
1250         int     tmpEntryMaxPWDB = 0, tmpEntryMinPWDB = 0xff;
1251         u8 sta_cnt = 0;
1252         u32 PWDB_rssi[NUM_STA] = {0};/* 0~15]:MACID, [16~31]:PWDB_rssi */
1253         struct sta_info *psta;
1254
1255         if (!pDM_Odm->bLinked)
1256                 return;
1257
1258         for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
1259                 psta = pDM_Odm->pODM_StaInfo[i];
1260                 if (psta) {
1261                         if (psta->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB)
1262                                 tmpEntryMinPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
1263
1264                         if (psta->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB)
1265                                 tmpEntryMaxPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
1266
1267                         if (psta->rssi_stat.UndecoratedSmoothedPWDB != (-1))
1268                                 PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16));
1269                 }
1270         }
1271
1272         for (i = 0; i < sta_cnt; i++) {
1273                 if (PWDB_rssi[i] != (0)) {
1274                         rtl8723a_set_rssi_cmd(Adapter, (u8 *)&PWDB_rssi[i]);
1275                 }
1276         }
1277
1278         if (tmpEntryMaxPWDB != 0)       /*  If associated entry is found */
1279                 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = tmpEntryMaxPWDB;
1280         else
1281                 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = 0;
1282
1283         if (tmpEntryMinPWDB != 0xff) /*  If associated entry is found */
1284                 pdmpriv->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB;
1285         else
1286                 pdmpriv->EntryMinUndecoratedSmoothedPWDB = 0;
1287
1288         FindMinimumRSSI(Adapter);/* get pdmpriv->MinUndecoratedPWDBForDM */
1289
1290         ODM_CmnInfoUpdate23a(&pHalData->odmpriv, ODM_CMNINFO_RSSI_MIN, pdmpriv->MinUndecoratedPWDBForDM);
1291 }
1292
1293 /* endif */
1294 /* 3 ============================================================ */
1295 /* 3 Tx Power Tracking */
1296 /* 3 ============================================================ */
1297
1298 void odm_TXPowerTrackingInit23a(struct dm_odm_t *pDM_Odm)
1299 {
1300         odm_TXPowerTrackingThermalMeterInit23a(pDM_Odm);
1301 }
1302
1303 void odm_TXPowerTrackingThermalMeterInit23a(struct dm_odm_t *pDM_Odm)
1304 {
1305         struct rtw_adapter *Adapter = pDM_Odm->Adapter;
1306         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1307         struct dm_priv *pdmpriv = &pHalData->dmpriv;
1308
1309         pdmpriv->bTXPowerTracking = true;
1310         pdmpriv->TXPowercount = 0;
1311         pdmpriv->bTXPowerTrackingInit = false;
1312         pdmpriv->TxPowerTrackControl = true;
1313         MSG_8723A("pdmpriv->TxPowerTrackControl = %d\n", pdmpriv->TxPowerTrackControl);
1314
1315         pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = true;
1316 }
1317
1318 void ODM_TXPowerTrackingCheck23a(struct dm_odm_t *pDM_Odm)
1319 {
1320         /*  For AP/ADSL use struct rtl8723a_priv * */
1321         /*  For CE/NIC use struct rtw_adapter * */
1322
1323         /*  2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1324         /*  at the same time. In the stage2/3, we need to prive universal interface and merge all */
1325         /*  HW dynamic mechanism. */
1326         odm_TXPowerTrackingCheckCE23a(pDM_Odm);
1327 }
1328
1329 void odm_TXPowerTrackingCheckCE23a(struct dm_odm_t *pDM_Odm)
1330 {
1331 }
1332
1333 /* EDCA Turbo */
1334 static void ODM_EdcaTurboInit23a(struct dm_odm_t *pDM_Odm)
1335 {
1336
1337         struct rtw_adapter *Adapter = pDM_Odm->Adapter;
1338
1339         pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false;
1340         pDM_Odm->DM_EDCA_Table.bIsCurRDLState = false;
1341         Adapter->recvpriv.bIsAnyNonBEPkts = false;
1342
1343         ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VO PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_VO_PARAM)));
1344         ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VI PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_VI_PARAM)));
1345         ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BE PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_BE_PARAM)));
1346         ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BK PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_BK_PARAM)));
1347
1348 }       /*  ODM_InitEdcaTurbo */
1349
1350 static void odm_EdcaTurboCheck23a(struct dm_odm_t *pDM_Odm)
1351 {
1352         struct rtw_adapter *Adapter = pDM_Odm->Adapter;
1353         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1354         struct xmit_priv *pxmitpriv = &Adapter->xmitpriv;
1355         struct recv_priv *precvpriv = &Adapter->recvpriv;
1356         struct registry_priv *pregpriv = &Adapter->registrypriv;
1357         struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
1358         struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
1359         u32 trafficIndex;
1360         u32 edca_param;
1361         u64 cur_tx_bytes;
1362         u64 cur_rx_bytes;
1363
1364         /*  For AP/ADSL use struct rtl8723a_priv * */
1365         /*  For CE/NIC use struct rtw_adapter * */
1366
1367         /*  2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1368         /*  at the same time. In the stage2/3, we need to prive universal interface and merge all */
1369         /*  HW dynamic mechanism. */
1370
1371         if (!(pDM_Odm->SupportAbility & ODM_MAC_EDCA_TURBO))
1372                 return;
1373
1374         if ((pregpriv->wifi_spec == 1))/*  (pmlmeinfo->HT_enable == 0)) */
1375                 goto dm_CheckEdcaTurbo_EXIT;
1376
1377         if (pmlmeinfo->assoc_AP_vendor >=  HT_IOT_PEER_MAX)
1378                 goto dm_CheckEdcaTurbo_EXIT;
1379
1380         if (rtl8723a_BT_disable_EDCA_turbo(Adapter))
1381                 goto dm_CheckEdcaTurbo_EXIT;
1382
1383         /*  Check if the status needs to be changed. */
1384         if (!precvpriv->bIsAnyNonBEPkts) {
1385                 cur_tx_bytes = pxmitpriv->tx_bytes - pxmitpriv->last_tx_bytes;
1386                 cur_rx_bytes = precvpriv->rx_bytes - precvpriv->last_rx_bytes;
1387
1388                 /* traffic, TX or RX */
1389                 if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_RALINK) ||
1390                     (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_ATHEROS)) {
1391                         if (cur_tx_bytes > (cur_rx_bytes << 2)) {
1392                                 /*  Uplink TP is present. */
1393                                 trafficIndex = UP_LINK;
1394                         } else { /*  Balance TP is present. */
1395                                 trafficIndex = DOWN_LINK;
1396                         }
1397                 } else {
1398                         if (cur_rx_bytes > (cur_tx_bytes << 2)) {
1399                                 /*  Downlink TP is present. */
1400                                 trafficIndex = DOWN_LINK;
1401                         } else { /*  Balance TP is present. */
1402                                 trafficIndex = UP_LINK;
1403                         }
1404                 }
1405
1406                 if ((pDM_Odm->DM_EDCA_Table.prv_traffic_idx != trafficIndex) ||
1407                     (!pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA)) {
1408                         if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_CISCO) &&
1409                             (pmlmeext->cur_wireless_mode & WIRELESS_11_24N))
1410                                 edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex];
1411                         else
1412                                 edca_param = EDCAParam[HT_IOT_PEER_UNKNOWN][trafficIndex];
1413                         rtl8723au_write32(Adapter, REG_EDCA_BE_PARAM,
1414                                           edca_param);
1415
1416                         pDM_Odm->DM_EDCA_Table.prv_traffic_idx = trafficIndex;
1417                 }
1418
1419                 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = true;
1420         } else {
1421                 /*  Turn Off EDCA turbo here. */
1422                 /*  Restore original EDCA according to the declaration of AP. */
1423                 if (pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA) {
1424                         rtl8723au_write32(Adapter, REG_EDCA_BE_PARAM,
1425                                           pHalData->AcParam_BE);
1426                         pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false;
1427                 }
1428         }
1429
1430 dm_CheckEdcaTurbo_EXIT:
1431         /*  Set variables for next time. */
1432         precvpriv->bIsAnyNonBEPkts = false;
1433         pxmitpriv->last_tx_bytes = pxmitpriv->tx_bytes;
1434         precvpriv->last_rx_bytes = precvpriv->rx_bytes;
1435 }
1436
1437 u32 GetPSDData(struct dm_odm_t *pDM_Odm, unsigned int point, u8 initial_gain_psd)
1438 {
1439         u32 psd_report;
1440
1441         /* Set DCO frequency index, offset = (40MHz/SamplePts)*point */
1442         ODM_SetBBReg(pDM_Odm, 0x808, 0x3FF, point);
1443
1444         /* Start PSD calculation, Reg808[22]= 0->1 */
1445         ODM_SetBBReg(pDM_Odm, 0x808, BIT(22), 1);
1446         /* Need to wait for HW PSD report */
1447         udelay(30);
1448         ODM_SetBBReg(pDM_Odm, 0x808, BIT(22), 0);
1449         /* Read PSD report, Reg8B4[15:0] */
1450         psd_report = ODM_GetBBReg(pDM_Odm, 0x8B4, bMaskDWord) & 0x0000FFFF;
1451
1452         psd_report = (u32)(ConvertTo_dB23a(psd_report))+(u32)(initial_gain_psd-0x1c);
1453
1454         return psd_report;
1455 }
1456
1457 u32
1458 ConvertTo_dB23a(
1459         u32 Value)
1460 {
1461         u8 i;
1462         u8 j;
1463         u32 dB;
1464
1465         Value = Value & 0xFFFF;
1466
1467         for (i = 0; i < 8; i++) {
1468                 if (Value <= dB_Invert_Table[i][11])
1469                         break;
1470         }
1471
1472         if (i >= 8)
1473                 return 96;      /*  maximum 96 dB */
1474
1475         for (j = 0; j < 12; j++) {
1476                 if (Value <= dB_Invert_Table[i][j])
1477                         break;
1478         }
1479
1480         dB = i*12 + j + 1;
1481
1482         return dB;
1483 }
1484
1485 /*  */
1486 /*  Description: */
1487 /*Set Single/Dual Antenna default setting for products that do not do detection in advance. */
1488 /*  */
1489 /*  Added by Joseph, 2012.03.22 */
1490 /*  */
1491 void ODM_SingleDualAntennaDefaultSetting(struct dm_odm_t *pDM_Odm)
1492 {
1493         struct sw_ant_sw *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
1494
1495         pDM_SWAT_Table->ANTA_ON = true;
1496         pDM_SWAT_Table->ANTB_ON = true;
1497 }
1498
1499 /* 2 8723A ANT DETECT */
1500
1501 static void odm_PHY_SaveAFERegisters(
1502         struct dm_odm_t *pDM_Odm,
1503         u32 *AFEReg,
1504         u32 *AFEBackup,
1505         u32 RegisterNum
1506         )
1507 {
1508         u32 i;
1509
1510         /* RTPRINT(FINIT, INIT_IQK, ("Save ADDA parameters.\n")); */
1511         for (i = 0 ; i < RegisterNum ; i++)
1512                 AFEBackup[i] = ODM_GetBBReg(pDM_Odm, AFEReg[i], bMaskDWord);
1513 }
1514
1515 static void odm_PHY_ReloadAFERegisters(struct dm_odm_t *pDM_Odm, u32 *AFEReg,
1516                                        u32 *AFEBackup, u32 RegiesterNum)
1517 {
1518         u32 i;
1519
1520         for (i = 0 ; i < RegiesterNum; i++)
1521                 ODM_SetBBReg(pDM_Odm, AFEReg[i], bMaskDWord, AFEBackup[i]);
1522 }
1523
1524 /* 2 8723A ANT DETECT */
1525 /*  Description: */
1526 /* Implement IQK single tone for RF DPK loopback and BB PSD scanning. */
1527 /* This function is cooperated with BB team Neil. */
1528 bool ODM_SingleDualAntennaDetection(struct dm_odm_t *pDM_Odm, u8 mode)
1529 {
1530         struct sw_ant_sw *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
1531         u32 CurrentChannel, RfLoopReg;
1532         u8 n;
1533         u32 Reg88c, Regc08, Reg874, Regc50;
1534         u8 initial_gain = 0x5a;
1535         u32 PSD_report_tmp;
1536         u32 AntA_report = 0x0, AntB_report = 0x0, AntO_report = 0x0;
1537         bool bResult = true;
1538         u32 AFE_Backup[16];
1539         u32 AFE_REG_8723A[16] = {
1540                 rRx_Wait_CCA, rTx_CCK_RFON,
1541                 rTx_CCK_BBON, rTx_OFDM_RFON,
1542                 rTx_OFDM_BBON, rTx_To_Rx,
1543                 rTx_To_Tx, rRx_CCK,
1544                 rRx_OFDM, rRx_Wait_RIFS,
1545                 rRx_TO_Rx, rStandby,
1546                 rSleep, rPMPD_ANAEN,
1547                 rFPGA0_XCD_SwitchControl, rBlue_Tooth};
1548
1549         if (!(pDM_Odm->SupportICType & ODM_RTL8723A))
1550                 return bResult;
1551
1552         if (!(pDM_Odm->SupportAbility&ODM_BB_ANT_DIV))
1553                 return bResult;
1554         /* 1 Backup Current RF/BB Settings */
1555
1556         CurrentChannel = ODM_GetRFReg(pDM_Odm, RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask);
1557         RfLoopReg = ODM_GetRFReg(pDM_Odm, RF_PATH_A, 0x00, bRFRegOffsetMask);
1558         ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, ODM_DPDT, Antenna_A);  /*  change to Antenna A */
1559         /*  Step 1: USE IQK to transmitter single tone */
1560
1561         udelay(10);
1562
1563         /* Store A Path Register 88c, c08, 874, c50 */
1564         Reg88c = ODM_GetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord);
1565         Regc08 = ODM_GetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord);
1566         Reg874 = ODM_GetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord);
1567         Regc50 = ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord);
1568
1569         /*  Store AFE Registers */
1570         odm_PHY_SaveAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16);
1571
1572         /* Set PSD 128 pts */
1573         ODM_SetBBReg(pDM_Odm, rFPGA0_PSDFunction, BIT(14) | BIT(15), 0x0);
1574
1575         /*  To SET CH1 to do */
1576         ODM_SetRFReg(pDM_Odm, RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask, 0x01);     /* Channel 1 */
1577
1578         /*  AFE all on step */
1579         ODM_SetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord, 0x6FDB25A4);
1580         ODM_SetBBReg(pDM_Odm, rTx_CCK_RFON, bMaskDWord, 0x6FDB25A4);
1581         ODM_SetBBReg(pDM_Odm, rTx_CCK_BBON, bMaskDWord, 0x6FDB25A4);
1582         ODM_SetBBReg(pDM_Odm, rTx_OFDM_RFON, bMaskDWord, 0x6FDB25A4);
1583         ODM_SetBBReg(pDM_Odm, rTx_OFDM_BBON, bMaskDWord, 0x6FDB25A4);
1584         ODM_SetBBReg(pDM_Odm, rTx_To_Rx, bMaskDWord, 0x6FDB25A4);
1585         ODM_SetBBReg(pDM_Odm, rTx_To_Tx, bMaskDWord, 0x6FDB25A4);
1586         ODM_SetBBReg(pDM_Odm, rRx_CCK, bMaskDWord, 0x6FDB25A4);
1587         ODM_SetBBReg(pDM_Odm, rRx_OFDM, bMaskDWord, 0x6FDB25A4);
1588         ODM_SetBBReg(pDM_Odm, rRx_Wait_RIFS, bMaskDWord, 0x6FDB25A4);
1589         ODM_SetBBReg(pDM_Odm, rRx_TO_Rx, bMaskDWord, 0x6FDB25A4);
1590         ODM_SetBBReg(pDM_Odm, rStandby, bMaskDWord, 0x6FDB25A4);
1591         ODM_SetBBReg(pDM_Odm, rSleep, bMaskDWord, 0x6FDB25A4);
1592         ODM_SetBBReg(pDM_Odm, rPMPD_ANAEN, bMaskDWord, 0x6FDB25A4);
1593         ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_SwitchControl, bMaskDWord, 0x6FDB25A4);
1594         ODM_SetBBReg(pDM_Odm, rBlue_Tooth, bMaskDWord, 0x6FDB25A4);
1595
1596         /*  3 wire Disable */
1597         ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, 0xCCF000C0);
1598
1599         /* BB IQK Setting */
1600         ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800E4);
1601         ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22208000);
1602
1603         /* IQK setting tone@ 4.34Mhz */
1604         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008C1C);
1605         ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00);
1606
1607         /* Page B init */
1608         ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00080000);
1609         ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000);
1610         ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800);
1611         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1f);
1612         ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82150008);
1613         ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28150008);
1614         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x001028d0);
1615
1616         /* RF loop Setting */
1617         ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x0, 0xFFFFF, 0x50008);
1618
1619         /* IQK Single tone start */
1620         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80800000);
1621         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
1622         udelay(1000);
1623         PSD_report_tmp = 0x0;
1624
1625         for (n = 0; n < 2; n++) {
1626                 PSD_report_tmp =  GetPSDData(pDM_Odm, 14, initial_gain);
1627                 if (PSD_report_tmp > AntA_report)
1628                         AntA_report = PSD_report_tmp;
1629         }
1630
1631         PSD_report_tmp = 0x0;
1632
1633         ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_B);  /*  change to Antenna B */
1634         udelay(10);
1635
1636         for (n = 0; n < 2; n++) {
1637                 PSD_report_tmp =  GetPSDData(pDM_Odm, 14, initial_gain);
1638                 if (PSD_report_tmp > AntB_report)
1639                         AntB_report = PSD_report_tmp;
1640         }
1641
1642         /*  change to open case */
1643         ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, 0);  /*  change to Ant A and B all open case */
1644         udelay(10);
1645
1646         for (n = 0; n < 2; n++) {
1647                 PSD_report_tmp =  GetPSDData(pDM_Odm, 14, initial_gain);
1648                 if (PSD_report_tmp > AntO_report)
1649                         AntO_report = PSD_report_tmp;
1650         }
1651
1652         /* Close IQK Single Tone function */
1653         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
1654         PSD_report_tmp = 0x0;
1655
1656         /* 1 Return to antanna A */
1657         ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_A);
1658         ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, Reg88c);
1659         ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, Regc08);
1660         ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, Reg874);
1661         ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, 0x7F, 0x40);
1662         ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord, Regc50);
1663         ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, CurrentChannel);
1664         ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x00, bRFRegOffsetMask, RfLoopReg);
1665
1666         /* Reload AFE Registers */
1667         odm_PHY_ReloadAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16);
1668
1669         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_A[%d]= %d \n", 2416, AntA_report));
1670         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_B[%d]= %d \n", 2416, AntB_report));
1671         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_O[%d]= %d \n", 2416, AntO_report));
1672
1673         /* 2 Test Ant B based on Ant A is ON */
1674         if (mode == ANTTESTB) {
1675                 if (AntA_report >= 100) {
1676                         if (AntB_report > (AntA_report+1)) {
1677                                 pDM_SWAT_Table->ANTB_ON = false;
1678                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Single Antenna A\n"));
1679                         } else {
1680                                 pDM_SWAT_Table->ANTB_ON = true;
1681                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Dual Antenna is A and B\n"));
1682                         }
1683                 } else {
1684                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n"));
1685                         pDM_SWAT_Table->ANTB_ON = false; /*  Set Antenna B off as default */
1686                         bResult = false;
1687                 }
1688         } else if (mode == ANTTESTALL) {
1689                 /* 2 Test Ant A and B based on DPDT Open */
1690                 if ((AntO_report >= 100) & (AntO_report < 118)) {
1691                         if (AntA_report > (AntO_report+1)) {
1692                                 pDM_SWAT_Table->ANTA_ON = false;
1693                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant A is OFF"));
1694                         } else {
1695                                 pDM_SWAT_Table->ANTA_ON = true;
1696                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant A is ON"));
1697                         }
1698
1699                         if (AntB_report > (AntO_report+2)) {
1700                                 pDM_SWAT_Table->ANTB_ON = false;
1701                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant B is OFF"));
1702                         } else {
1703                                 pDM_SWAT_Table->ANTB_ON = true;
1704                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant B is ON"));
1705                         }
1706                 }
1707         } else {
1708                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n"));
1709                 pDM_SWAT_Table->ANTA_ON = true; /*  Set Antenna A on as default */
1710                 pDM_SWAT_Table->ANTB_ON = false; /*  Set Antenna B off as default */
1711                 bResult = false;
1712         }
1713         return bResult;
1714 }
1715
1716 /* Justin: According to the current RRSI to adjust Response Frame TX power, 2012/11/05 */
1717 void odm_dtc(struct dm_odm_t *pDM_Odm)
1718 {
1719 }