drivers/staging/rtl8723au/hal/odm.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  ******************************************************************************/
  15
  16 #include "odm_precomp.h"
  17 #include "usb_ops_linux.h"
  18
  19 static const u16 dB_Invert_Table[8][12] = {
  20         {1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4},
  21         {4, 5, 6, 6, 7, 8, 9, 10, 11, 13, 14, 16},
  22         {18, 20, 22, 25, 28, 32, 35, 40, 45, 50, 56, 63},
  23         {71, 79, 89, 100, 112, 126, 141, 158, 178, 200, 224, 251},
  24         {282, 316, 355, 398, 447, 501, 562, 631, 708, 794, 891, 1000},
  25         {1122, 1259, 1413, 1585, 1778, 1995, 2239, 2512, 2818, 3162, 3548, 3981},
  26         {4467, 5012, 5623, 6310, 7079, 7943, 8913, 10000, 11220, 12589, 14125, 15849},
  27         {17783, 19953, 22387, 25119, 28184, 31623, 35481, 39811, 44668, 50119, 56234, 65535}
  28 };
  29
  30 static u32 EDCAParam[HT_IOT_PEER_MAX][3] = {          /*  UL                    DL */
  31         {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 0:unknown AP */
  32         {0xa44f, 0x5ea44f, 0x5e431c}, /*  1:realtek AP */
  33         {0x5ea42b, 0x5ea42b, 0x5ea42b}, /*  2:unknown AP => realtek_92SE */
  34         {0x5ea32b, 0x5ea42b, 0x5e4322}, /*  3:broadcom AP */
  35         {0x5ea422, 0x00a44f, 0x00a44f}, /*  4:ralink AP */
  36         {0x5ea322, 0x00a630, 0x00a44f}, /*  5:atheros AP */
  37         {0x5e4322, 0x5e4322, 0x5e4322},/*  6:cisco AP */
  38         {0x5ea44f, 0x00a44f, 0x5ea42b}, /*  8:marvell AP */
  39         {0x5ea42b, 0x5ea42b, 0x5ea42b}, /*  10:unknown AP => 92U AP */
  40         {0x5ea42b, 0xa630, 0x5e431c}, /*  11:airgocap AP */
  41 };
  42
  43 /*  EDCA Paramter for AP/ADSL   by Mingzhi 2011-11-22 */
  44
  45 /*  Global var */
  46 u32 OFDMSwingTable23A[OFDM_TABLE_SIZE_92D] = {
  47         0x7f8001fe, /*  0, +6.0dB */
  48         0x788001e2, /*  1, +5.5dB */
  49         0x71c001c7, /*  2, +5.0dB */
  50         0x6b8001ae, /*  3, +4.5dB */
  51         0x65400195, /*  4, +4.0dB */
  52         0x5fc0017f, /*  5, +3.5dB */
  53         0x5a400169, /*  6, +3.0dB */
  54         0x55400155, /*  7, +2.5dB */
  55         0x50800142, /*  8, +2.0dB */
  56         0x4c000130, /*  9, +1.5dB */
  57         0x47c0011f, /*  10, +1.0dB */
  58         0x43c0010f, /*  11, +0.5dB */
  59         0x40000100, /*  12, +0dB */
  60         0x3c8000f2, /*  13, -0.5dB */
  61         0x390000e4, /*  14, -1.0dB */
  62         0x35c000d7, /*  15, -1.5dB */
  63         0x32c000cb, /*  16, -2.0dB */
  64         0x300000c0, /*  17, -2.5dB */
  65         0x2d4000b5, /*  18, -3.0dB */
  66         0x2ac000ab, /*  19, -3.5dB */
  67         0x288000a2, /*  20, -4.0dB */
  68         0x26000098, /*  21, -4.5dB */
  69         0x24000090, /*  22, -5.0dB */
  70         0x22000088, /*  23, -5.5dB */
  71         0x20000080, /*  24, -6.0dB */
  72         0x1e400079, /*  25, -6.5dB */
  73         0x1c800072, /*  26, -7.0dB */
  74         0x1b00006c, /*  27. -7.5dB */
  75         0x19800066, /*  28, -8.0dB */
  76         0x18000060, /*  29, -8.5dB */
  77         0x16c0005b, /*  30, -9.0dB */
  78         0x15800056, /*  31, -9.5dB */
  79         0x14400051, /*  32, -10.0dB */
  80         0x1300004c, /*  33, -10.5dB */
  81         0x12000048, /*  34, -11.0dB */
  82         0x11000044, /*  35, -11.5dB */
  83         0x10000040, /*  36, -12.0dB */
  84         0x0f00003c,/*  37, -12.5dB */
  85         0x0e400039,/*  38, -13.0dB */
  86         0x0d800036,/*  39, -13.5dB */
  87         0x0cc00033,/*  40, -14.0dB */
  88         0x0c000030,/*  41, -14.5dB */
  89         0x0b40002d,/*  42, -15.0dB */
  90 };
  91
  92 u8 CCKSwingTable_Ch1_Ch1323A[CCK_TABLE_SIZE][8] = {
  93         {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /*  0, +0dB */
  94         {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /*  1, -0.5dB */
  95         {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /*  2, -1.0dB */
  96         {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /*  3, -1.5dB */
  97         {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /*  4, -2.0dB */
  98         {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /*  5, -2.5dB */
  99         {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /*  6, -3.0dB */
 100         {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /*  7, -3.5dB */
 101         {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /*  8, -4.0dB */
 102         {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /*  9, -4.5dB */
 103         {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /*  10, -5.0dB */
 104         {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /*  11, -5.5dB */
 105         {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /*  12, -6.0dB */
 106         {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /*  13, -6.5dB */
 107         {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /*  14, -7.0dB */
 108         {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /*  15, -7.5dB */
 109         {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /*  16, -8.0dB */
 110         {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /*  17, -8.5dB */
 111         {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /*  18, -9.0dB */
 112         {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /*  19, -9.5dB */
 113         {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /*  20, -10.0dB */
 114         {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /*  21, -10.5dB */
 115         {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /*  22, -11.0dB */
 116         {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /*  23, -11.5dB */
 117         {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /*  24, -12.0dB */
 118         {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /*  25, -12.5dB */
 119         {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /*  26, -13.0dB */
 120         {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /*  27, -13.5dB */
 121         {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /*  28, -14.0dB */
 122         {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /*  29, -14.5dB */
 123         {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /*  30, -15.0dB */
 124         {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /*  31, -15.5dB */
 125         {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}        /*  32, -16.0dB */
 126 };
 127
 128 u8 CCKSwingTable_Ch1423A[CCK_TABLE_SIZE][8] = {
 129         {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /*  0, +0dB */
 130         {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /*  1, -0.5dB */
 131         {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /*  2, -1.0dB */
 132         {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /*  3, -1.5dB */
 133         {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /*  4, -2.0dB */
 134         {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /*  5, -2.5dB */
 135         {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /*  6, -3.0dB */
 136         {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /*  7, -3.5dB */
 137         {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /*  8, -4.0dB */
 138         {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /*  9, -4.5dB */
 139         {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /*  10, -5.0dB */
 140         {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /*  11, -5.5dB */
 141         {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /*  12, -6.0dB */
 142         {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /*  13, -6.5dB */
 143         {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /*  14, -7.0dB */
 144         {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /*  15, -7.5dB */
 145         {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /*  16, -8.0dB */
 146         {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /*  17, -8.5dB */
 147         {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /*  18, -9.0dB */
 148         {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /*  19, -9.5dB */
 149         {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /*  20, -10.0dB */
 150         {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /*  21, -10.5dB */
 151         {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /*  22, -11.0dB */
 152         {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /*  23, -11.5dB */
 153         {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /*  24, -12.0dB */
 154         {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /*  25, -12.5dB */
 155         {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /*  26, -13.0dB */
 156         {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /*  27, -13.5dB */
 157         {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /*  28, -14.0dB */
 158         {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /*  29, -14.5dB */
 159         {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /*  30, -15.0dB */
 160         {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /*  31, -15.5dB */
 161         {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}        /*  32, -16.0dB */
 162 };
 163
 164 /*  Local Function predefine. */
 165
 166 /* START------------COMMON INFO RELATED--------------- */
 167 void odm_CommonInfoSelfInit23a(struct dm_odm_t *pDM_Odm);
 168
 169 static void odm_CommonInfoSelfUpdate(struct hal_data_8723a *pHalData);
 170
 171 void odm_CmnInfoInit_Debug23a(struct dm_odm_t *pDM_Odm);
 172
 173 void odm_CmnInfoUpdate_Debug23a(struct dm_odm_t *pDM_Odm);
 174
 175 /* START---------------DIG--------------------------- */
 176 void odm_FalseAlarmCounterStatistics23a(struct dm_odm_t *pDM_Odm);
 177
 178 void odm_DIG23aInit(struct dm_odm_t *pDM_Odm);
 179
 180 void odm_DIG23a(struct rtw_adapter *adapter);
 181
 182 void odm_CCKPacketDetectionThresh23a(struct dm_odm_t *pDM_Odm);
 183 /* END---------------DIG--------------------------- */
 184
 185 /* START-------BB POWER SAVE----------------------- */
 186 void odm23a_DynBBPSInit(struct dm_odm_t *pDM_Odm);
 187
 188 void odm_DynamicBBPowerSaving23a(struct dm_odm_t *pDM_Odm);
 189
 190 /* END---------BB POWER SAVE----------------------- */
 191
 192 void odm_DynamicTxPower23aInit(struct dm_odm_t *pDM_Odm);
 193
 194 void odm_RSSIMonitorCheck23a(struct dm_odm_t *pDM_Odm);
 195 void odm_DynamicTxPower23a(struct dm_odm_t *pDM_Odm);
 196
 197 void odm_RefreshRateAdaptiveMask23a(struct dm_odm_t *pDM_Odm);
 198
 199 void ODM_TXPowerTrackingCheck23a(struct dm_odm_t *pDM_Odm);
 200
 201 void odm_RateAdaptiveMaskInit23a(struct dm_odm_t *pDM_Odm);
 202
 203 void odm_TXPowerTrackingThermalMeterInit23a(struct dm_odm_t *pDM_Odm);
 204
 205 void odm_TXPowerTrackingInit23a(struct dm_odm_t *pDM_Odm);
 206
 207 void odm_TXPowerTrackingCheckCE23a(struct dm_odm_t *pDM_Odm);
 208
 209 static void odm_EdcaTurboCheck23a(struct dm_odm_t *pDM_Odm);
 210 static void ODM_EdcaTurboInit23a(struct dm_odm_t *pDM_Odm);
 211
 212 #define         RxDefaultAnt1           0x65a9
 213 #define RxDefaultAnt2           0x569a
 214
 215 bool odm_StaDefAntSel(struct dm_odm_t *pDM_Odm,
 216         u32 OFDM_Ant1_Cnt,
 217         u32 OFDM_Ant2_Cnt,
 218         u32 CCK_Ant1_Cnt,
 219         u32 CCK_Ant2_Cnt,
 220         u8 *pDefAnt
 221         );
 222
 223 void odm_SetRxIdleAnt(struct dm_odm_t *pDM_Odm,
 224         u8 Ant,
 225         bool   bDualPath
 226 );
 227
 228 /* 3 Export Interface */
 229
 230 /*  2011/09/21 MH Add to describe different team necessary resource allocate?? */
 231 void ODM23a_DMInit(struct dm_odm_t *pDM_Odm)
 232 {
 233         /* For all IC series */
 234         odm_CommonInfoSelfInit23a(pDM_Odm);
 235         odm_CmnInfoInit_Debug23a(pDM_Odm);
 236         odm_DIG23aInit(pDM_Odm);
 237         odm_RateAdaptiveMaskInit23a(pDM_Odm);
 238
 239         odm23a_DynBBPSInit(pDM_Odm);
 240         odm_DynamicTxPower23aInit(pDM_Odm);
 241         odm_TXPowerTrackingInit23a(pDM_Odm);
 242         ODM_EdcaTurboInit23a(pDM_Odm);
 243 }
 244
 245 /*  2011/09/20 MH This is the entry pointer for all team to execute HW out source DM. */
 246 /*  You can not add any dummy function here, be care, you can only use DM structure */
 247 /*  to perform any new ODM_DM. */
 248 void ODM_DMWatchdog23a(struct rtw_adapter *adapter)
 249 {
 250         struct hal_data_8723a *pHalData = GET_HAL_DATA(adapter);
 251         struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
 252         struct pwrctrl_priv *pwrctrlpriv = &adapter->pwrctrlpriv;
 253
 254         /* 2012.05.03 Luke: For all IC series */
 255         odm_CmnInfoUpdate_Debug23a(pDM_Odm);
 256         odm_CommonInfoSelfUpdate(pHalData);
 257         odm_FalseAlarmCounterStatistics23a(pDM_Odm);
 258         odm_RSSIMonitorCheck23a(pDM_Odm);
 259
 260         /* 8723A or 8189ES platform */
 261         /* NeilChen--2012--08--24-- */
 262         /* Fix Leave LPS issue */
 263         if ((pDM_Odm->Adapter->pwrctrlpriv.pwr_mode != PS_MODE_ACTIVE) &&/*  in LPS mode */
 264             (pDM_Odm->SupportICType & ODM_RTL8723A)) {
 265                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("----Step1: odm_DIG23a is in LPS mode\n"));
 266                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("---Step2: 8723AS is in LPS mode\n"));
 267                         odm_DIG23abyRSSI_LPS(pDM_Odm);
 268         } else {
 269                 odm_DIG23a(adapter);
 270         }
 271
 272         odm_CCKPacketDetectionThresh23a(pDM_Odm);
 273
 274         if (pwrctrlpriv->bpower_saving)
 275                 return;
 276
 277         odm_RefreshRateAdaptiveMask23a(pDM_Odm);
 278
 279         odm_DynamicBBPowerSaving23a(pDM_Odm);
 280
 281         ODM_TXPowerTrackingCheck23a(pDM_Odm);
 282         odm_EdcaTurboCheck23a(pDM_Odm);
 283 }
 284
 285 /*  */
 286 /*  Init /.. Fixed HW value. Only init time. */
 287 /*  */
 288 void ODM_CmnInfoInit23a(struct dm_odm_t *pDM_Odm,
 289                 enum odm_cmninfo CmnInfo,
 290                 u32 Value
 291         )
 292 {
 293         /* ODM_RT_TRACE(pDM_Odm,); */
 294
 295         /*  */
 296         /*  This section is used for init value */
 297         /*  */
 298         switch  (CmnInfo) {
 299         /*  Fixed ODM value. */
 300         case    ODM_CMNINFO_INTERFACE:
 301                 pDM_Odm->SupportInterface = (u8)Value;
 302                 break;
 303         case    ODM_CMNINFO_MP_TEST_CHIP:
 304                 pDM_Odm->bIsMPChip = (u8)Value;
 305                 break;
 306         case    ODM_CMNINFO_IC_TYPE:
 307                 pDM_Odm->SupportICType = Value;
 308                 break;
 309         case    ODM_CMNINFO_CUT_VER:
 310                 pDM_Odm->CutVersion = (u8)Value;
 311                 break;
 312         case    ODM_CMNINFO_FAB_VER:
 313                 pDM_Odm->FabVersion = (u8)Value;
 314                 break;
 315         case    ODM_CMNINFO_BOARD_TYPE:
 316                 pDM_Odm->BoardType = (u8)Value;
 317                 break;
 318         case    ODM_CMNINFO_EXT_LNA:
 319                 pDM_Odm->ExtLNA = (u8)Value;
 320                 break;
 321         case    ODM_CMNINFO_EXT_PA:
 322                 pDM_Odm->ExtPA = (u8)Value;
 323                 break;
 324         case    ODM_CMNINFO_EXT_TRSW:
 325                 pDM_Odm->ExtTRSW = (u8)Value;
 326                 break;
 327         case    ODM_CMNINFO_PATCH_ID:
 328                 pDM_Odm->PatchID = (u8)Value;
 329                 break;
 330         case    ODM_CMNINFO_BINHCT_TEST:
 331                 pDM_Odm->bInHctTest = (bool)Value;
 332                 break;
 333         case    ODM_CMNINFO_BWIFI_TEST:
 334                 pDM_Odm->bWIFITest = (bool)Value;
 335                 break;
 336         case    ODM_CMNINFO_SMART_CONCURRENT:
 337                 pDM_Odm->bDualMacSmartConcurrent = (bool)Value;
 338                 break;
 339         /* To remove the compiler warning, must add an empty default statement to handle the other values. */
 340         default:
 341                 /* do nothing */
 342                 break;
 343         }
 344
 345         /*  */
 346         /*  Tx power tracking BB swing table. */
 347         /*  The base index = 12. +((12-n)/2)dB 13~?? = decrease tx pwr by -((n-12)/2)dB */
 348         /*  */
 349         pDM_Odm->BbSwingIdxOfdm                 = 12; /*  Set defalut value as index 12. */
 350         pDM_Odm->BbSwingIdxOfdmCurrent  = 12;
 351         pDM_Odm->BbSwingFlagOfdm                = false;
 352
 353 }
 354
 355 void ODM_CmnInfoPtrArrayHook23a(struct dm_odm_t *pDM_Odm, enum odm_cmninfo CmnInfo,
 356                                 u16 Index, void *pValue)
 357 {
 358         /*  Hook call by reference pointer. */
 359         switch  (CmnInfo) {
 360         /*  Dynamic call by reference pointer. */
 361         case    ODM_CMNINFO_STA_STATUS:
 362                 pDM_Odm->pODM_StaInfo[Index] = (struct sta_info *)pValue;
 363                 break;
 364         /* To remove the compiler warning, must add an empty default statement to handle the other values. */
 365         default:
 366                 /* do nothing */
 367                 break;
 368         }
 369 }
 370
 371 /*  Update Band/CHannel/.. The values are dynamic but non-per-packet. */
 372 void ODM_CmnInfoUpdate23a(struct dm_odm_t *pDM_Odm, u32 CmnInfo, u64 Value)
 373 {
 374         /*  This init variable may be changed in run time. */
 375         switch  (CmnInfo) {
 376         case    ODM_CMNINFO_WIFI_DIRECT:
 377                 pDM_Odm->bWIFI_Direct = (bool)Value;
 378                 break;
 379         case    ODM_CMNINFO_WIFI_DISPLAY:
 380                 pDM_Odm->bWIFI_Display = (bool)Value;
 381                 break;
 382         case    ODM_CMNINFO_LINK:
 383                 pDM_Odm->bLinked = (bool)Value;
 384                 break;
 385         case    ODM_CMNINFO_RSSI_MIN:
 386                 pDM_Odm->RSSI_Min = (u8)Value;
 387                 break;
 388         case    ODM_CMNINFO_DBG_COMP:
 389                 pDM_Odm->DebugComponents = Value;
 390                 break;
 391         case    ODM_CMNINFO_DBG_LEVEL:
 392                 pDM_Odm->DebugLevel = (u32)Value;
 393                 break;
 394         case    ODM_CMNINFO_RA_THRESHOLD_HIGH:
 395                 pDM_Odm->RateAdaptive.HighRSSIThresh = (u8)Value;
 396                 break;
 397         case    ODM_CMNINFO_RA_THRESHOLD_LOW:
 398                 pDM_Odm->RateAdaptive.LowRSSIThresh = (u8)Value;
 399                 break;
 400         }
 401
 402 }
 403
 404 void odm_CommonInfoSelfInit23a(struct dm_odm_t *pDM_Odm
 405         )
 406 {
 407         pDM_Odm->bCckHighPower =
 408                 (bool) ODM_GetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter2, BIT(9));
 409         pDM_Odm->RFPathRxEnable =
 410                 (u8) ODM_GetBBReg(pDM_Odm, rOFDM0_TRxPathEnable, 0x0F);
 411
 412         ODM_InitDebugSetting23a(pDM_Odm);
 413 }
 414
 415 static void odm_CommonInfoSelfUpdate(struct hal_data_8723a *pHalData)
 416 {
 417         struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
 418         struct sta_info *pEntry;
 419         u8 EntryCnt = 0;
 420         u8 i;
 421
 422         if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40) {
 423                 if (pHalData->nCur40MhzPrimeSC == 1)
 424                         pDM_Odm->ControlChannel = pHalData->CurrentChannel - 2;
 425                 else if (pHalData->nCur40MhzPrimeSC == 2)
 426                         pDM_Odm->ControlChannel = pHalData->CurrentChannel + 2;
 427         } else {
 428                 pDM_Odm->ControlChannel = pHalData->CurrentChannel;
 429         }
 430
 431         for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
 432                 pEntry = pDM_Odm->pODM_StaInfo[i];
 433                 if (pEntry)
 434                         EntryCnt++;
 435         }
 436         if (EntryCnt == 1)
 437                 pDM_Odm->bOneEntryOnly = true;
 438         else
 439                 pDM_Odm->bOneEntryOnly = false;
 440 }
 441
 442 void odm_CmnInfoInit_Debug23a(struct dm_odm_t *pDM_Odm)
 443 {
 444         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoInit_Debug23a ==>\n"));
 445         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportAbility = 0x%x\n", pDM_Odm->SupportAbility));
 446         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportInterface =%d\n", pDM_Odm->SupportInterface));
 447         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportICType = 0x%x\n", pDM_Odm->SupportICType));
 448         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("CutVersion =%d\n", pDM_Odm->CutVersion));
 449         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("FabVersion =%d\n", pDM_Odm->FabVersion));
 450         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("BoardType =%d\n", pDM_Odm->BoardType));
 451         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtLNA =%d\n", pDM_Odm->ExtLNA));
 452         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtPA =%d\n", pDM_Odm->ExtPA));
 453         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtTRSW =%d\n", pDM_Odm->ExtTRSW));
 454         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("PatchID =%d\n", pDM_Odm->PatchID));
 455         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bInHctTest =%d\n", pDM_Odm->bInHctTest));
 456         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFITest =%d\n", pDM_Odm->bWIFITest));
 457         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bDualMacSmartConcurrent =%d\n", pDM_Odm->bDualMacSmartConcurrent));
 458
 459 }
 460
 461 void odm_CmnInfoUpdate_Debug23a(struct dm_odm_t *pDM_Odm)
 462 {
 463         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoUpdate_Debug23a ==>\n"));
 464         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Direct =%d\n", pDM_Odm->bWIFI_Direct));
 465         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Display =%d\n", pDM_Odm->bWIFI_Display));
 466         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bLinked =%d\n", pDM_Odm->bLinked));
 467         ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RSSI_Min =%d\n", pDM_Odm->RSSI_Min));
 468 }
 469
 470 void ODM_Write_DIG23a(struct dm_odm_t *pDM_Odm,
 471         u8 CurrentIGI
 472         )
 473 {
 474         struct dig_t *pDM_DigTable = &pDM_Odm->DM_DigTable;
 475
 476         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("ODM_REG(IGI_A, pDM_Odm) = 0x%x, ODM_BIT(IGI, pDM_Odm) = 0x%x \n",
 477                 ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm)));
 478
 479         if (pDM_DigTable->CurIGValue != CurrentIGI) {
 480                 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI);
 481                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("CurrentIGI(0x%02x). \n", CurrentIGI));
 482                 pDM_DigTable->CurIGValue = CurrentIGI;
 483         }
 484         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
 485                      ("ODM_Write_DIG23a():CurrentIGI = 0x%x \n", CurrentIGI));
 486 }
 487
 488 /* Need LPS mode for CE platform --2012--08--24--- */
 489 /* 8723AS/8189ES */
 490 void odm_DIG23abyRSSI_LPS(struct dm_odm_t *pDM_Odm)
 491 {
 492         struct rtw_adapter *pAdapter = pDM_Odm->Adapter;
 493         struct false_alarm_stats *pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
 494         u8 RSSI_Lower = DM_DIG_MIN_NIC;   /* 0x1E or 0x1C */
 495         u8 bFwCurrentInPSMode = false;
 496         u8 CurrentIGI = pDM_Odm->RSSI_Min;
 497
 498         if (!(pDM_Odm->SupportICType & ODM_RTL8723A))
 499                 return;
 500
 501         CurrentIGI = CurrentIGI+RSSI_OFFSET_DIG;
 502         bFwCurrentInPSMode = pAdapter->pwrctrlpriv.bFwCurrentInPSMode;
 503
 504         /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG_LPS, ODM_DBG_LOUD, ("odm_DIG23a() ==>\n")); */
 505
 506         /*  Using FW PS mode to make IGI */
 507         if (bFwCurrentInPSMode) {
 508                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("---Neil---odm_DIG23a is in LPS mode\n"));
 509                 /* Adjust by  FA in LPS MODE */
 510                 if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2_LPS)
 511                         CurrentIGI = CurrentIGI+2;
 512                 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1_LPS)
 513                         CurrentIGI = CurrentIGI+1;
 514                 else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0_LPS)
 515                         CurrentIGI = CurrentIGI-1;
 516         } else {
 517                 CurrentIGI = RSSI_Lower;
 518         }
 519
 520         /* Lower bound checking */
 521
 522         /* RSSI Lower bound check */
 523         if ((pDM_Odm->RSSI_Min-10) > DM_DIG_MIN_NIC)
 524                 RSSI_Lower = (pDM_Odm->RSSI_Min-10);
 525         else
 526                 RSSI_Lower = DM_DIG_MIN_NIC;
 527
 528         /* Upper and Lower Bound checking */
 529          if (CurrentIGI > DM_DIG_MAX_NIC)
 530                 CurrentIGI = DM_DIG_MAX_NIC;
 531          else if (CurrentIGI < RSSI_Lower)
 532                 CurrentIGI = RSSI_Lower;
 533
 534         ODM_Write_DIG23a(pDM_Odm, CurrentIGI);/* ODM_Write_DIG23a(pDM_Odm, pDM_DigTable->CurIGValue); */
 535
 536 }
 537
 538 void odm_DIG23aInit(struct dm_odm_t *pDM_Odm)
 539 {
 540         struct dig_t *pDM_DigTable = &pDM_Odm->DM_DigTable;
 541
 542         pDM_DigTable->CurIGValue = (u8) ODM_GetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm));
 543         pDM_DigTable->RssiLowThresh     = DM_DIG_THRESH_LOW;
 544         pDM_DigTable->RssiHighThresh    = DM_DIG_THRESH_HIGH;
 545         pDM_DigTable->FALowThresh       = DM_FALSEALARM_THRESH_LOW;
 546         pDM_DigTable->FAHighThresh      = DM_FALSEALARM_THRESH_HIGH;
 547         if (pDM_Odm->BoardType == ODM_BOARD_HIGHPWR) {
 548                 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
 549                 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC;
 550         } else {
 551                 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
 552                 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC;
 553         }
 554         pDM_DigTable->BackoffVal = DM_DIG_BACKOFF_DEFAULT;
 555         pDM_DigTable->BackoffVal_range_max = DM_DIG_BACKOFF_MAX;
 556         pDM_DigTable->BackoffVal_range_min = DM_DIG_BACKOFF_MIN;
 557         pDM_DigTable->PreCCK_CCAThres = 0xFF;
 558         pDM_DigTable->CurCCK_CCAThres = 0x83;
 559         pDM_DigTable->ForbiddenIGI = DM_DIG_MIN_NIC;
 560         pDM_DigTable->LargeFAHit = 0;
 561         pDM_DigTable->Recover_cnt = 0;
 562         pDM_DigTable->DIG_Dynamic_MIN_0 = DM_DIG_MIN_NIC;
 563         pDM_DigTable->DIG_Dynamic_MIN_1 = DM_DIG_MIN_NIC;
 564         pDM_DigTable->bMediaConnect_0 = false;
 565         pDM_DigTable->bMediaConnect_1 = false;
 566 }
 567
 568 void odm_DIG23a(struct rtw_adapter *adapter)
 569 {
 570         struct hal_data_8723a *pHalData = GET_HAL_DATA(adapter);
 571         struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
 572         struct dig_t *pDM_DigTable = &pDM_Odm->DM_DigTable;
 573         struct false_alarm_stats *pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
 574         u8 DIG_Dynamic_MIN;
 575         u8 DIG_MaxOfMin;
 576         bool FirstConnect, FirstDisConnect;
 577         u8 dm_dig_max, dm_dig_min;
 578         u8 CurrentIGI = pDM_DigTable->CurIGValue;
 579
 580         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a() ==>\n"));
 581         if (adapter->mlmepriv.bScanInProcess) {
 582                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a() Return: In Scan Progress \n"));
 583                 return;
 584         }
 585
 586         DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0;
 587         FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_0);
 588         FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0);
 589
 590         /* 1 Boundary Decision */
 591         if ((pDM_Odm->SupportICType & ODM_RTL8723A) &&
 592             ((pDM_Odm->BoardType == ODM_BOARD_HIGHPWR) || pDM_Odm->ExtLNA)) {
 593                 dm_dig_max = DM_DIG_MAX_NIC_HP;
 594                 dm_dig_min = DM_DIG_MIN_NIC_HP;
 595                 DIG_MaxOfMin = DM_DIG_MAX_AP_HP;
 596         } else {
 597                 dm_dig_max = DM_DIG_MAX_NIC;
 598                 dm_dig_min = DM_DIG_MIN_NIC;
 599                 DIG_MaxOfMin = DM_DIG_MAX_AP;
 600         }
 601
 602         if (pDM_Odm->bLinked) {
 603               /* 2 8723A Series, offset need to be 10 */
 604                 if (pDM_Odm->SupportICType == ODM_RTL8723A) {
 605                         /* 2 Upper Bound */
 606                         if ((pDM_Odm->RSSI_Min + 10) > DM_DIG_MAX_NIC)
 607                                 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
 608                         else if ((pDM_Odm->RSSI_Min + 10) < DM_DIG_MIN_NIC)
 609                                 pDM_DigTable->rx_gain_range_max = DM_DIG_MIN_NIC;
 610                         else
 611                                 pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 10;
 612
 613                         /* 2 If BT is Concurrent, need to set Lower Bound */
 614                         DIG_Dynamic_MIN = DM_DIG_MIN_NIC;
 615                 } else {
 616                         /* 2 Modify DIG upper bound */
 617                         if ((pDM_Odm->RSSI_Min + 20) > dm_dig_max)
 618                                 pDM_DigTable->rx_gain_range_max = dm_dig_max;
 619                         else if ((pDM_Odm->RSSI_Min + 20) < dm_dig_min)
 620                                 pDM_DigTable->rx_gain_range_max = dm_dig_min;
 621                         else
 622                                 pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 20;
 623
 624                         /* 2 Modify DIG lower bound */
 625                         if (pDM_Odm->bOneEntryOnly) {
 626                                 if (pDM_Odm->RSSI_Min < dm_dig_min)
 627                                         DIG_Dynamic_MIN = dm_dig_min;
 628                                 else if (pDM_Odm->RSSI_Min > DIG_MaxOfMin)
 629                                         DIG_Dynamic_MIN = DIG_MaxOfMin;
 630                                 else
 631                                         DIG_Dynamic_MIN = pDM_Odm->RSSI_Min;
 632                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
 633                                              ("odm_DIG23a() : bOneEntryOnly = true,  DIG_Dynamic_MIN = 0x%x\n",
 634                                              DIG_Dynamic_MIN));
 635                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
 636                                              ("odm_DIG23a() : pDM_Odm->RSSI_Min =%d\n",
 637                                              pDM_Odm->RSSI_Min));
 638                         } else {
 639                                 DIG_Dynamic_MIN = dm_dig_min;
 640                         }
 641                 }
 642         } else {
 643                 pDM_DigTable->rx_gain_range_max = dm_dig_max;
 644                 DIG_Dynamic_MIN = dm_dig_min;
 645                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a() : No Link\n"));
 646         }
 647
 648         /* 1 Modify DIG lower bound, deal with abnormally large false alarm */
 649         if (pFalseAlmCnt->Cnt_all > 10000) {
 650                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
 651                              ("dm_DIG(): Abnornally false alarm case. \n"));
 652
 653                 if (pDM_DigTable->LargeFAHit != 3)
 654                         pDM_DigTable->LargeFAHit++;
 655                 if (pDM_DigTable->ForbiddenIGI < CurrentIGI) {
 656                         pDM_DigTable->ForbiddenIGI = CurrentIGI;
 657                         pDM_DigTable->LargeFAHit = 1;
 658                 }
 659
 660                 if (pDM_DigTable->LargeFAHit >= 3) {
 661                         if ((pDM_DigTable->ForbiddenIGI+1) > pDM_DigTable->rx_gain_range_max)
 662                                 pDM_DigTable->rx_gain_range_min = pDM_DigTable->rx_gain_range_max;
 663                         else
 664                                 pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1);
 665                         pDM_DigTable->Recover_cnt = 3600; /* 3600 = 2hr */
 666                 }
 667         } else {
 668                 /* Recovery mechanism for IGI lower bound */
 669                 if (pDM_DigTable->Recover_cnt != 0) {
 670                         pDM_DigTable->Recover_cnt--;
 671                 } else {
 672                         if (pDM_DigTable->LargeFAHit < 3) {
 673                                 if ((pDM_DigTable->ForbiddenIGI - 1) < DIG_Dynamic_MIN) {
 674                                         pDM_DigTable->ForbiddenIGI = DIG_Dynamic_MIN; /* DM_DIG_MIN; */
 675                                         pDM_DigTable->rx_gain_range_min = DIG_Dynamic_MIN; /* DM_DIG_MIN; */
 676                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
 677                                                      ("odm_DIG23a(): Normal Case: At Lower Bound\n"));
 678                                 } else {
 679                                         pDM_DigTable->ForbiddenIGI--;
 680                                         pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1);
 681                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
 682                                                      ("odm_DIG23a(): Normal Case: Approach Lower Bound\n"));
 683                                 }
 684                         } else {
 685                                 pDM_DigTable->LargeFAHit = 0;
 686                         }
 687                 }
 688         }
 689         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): pDM_DigTable->LargeFAHit =%d\n", pDM_DigTable->LargeFAHit));
 690
 691         /* 1 Adjust initial gain by false alarm */
 692         if (pDM_Odm->bLinked) {
 693                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): DIG AfterLink\n"));
 694                 if (FirstConnect) {
 695                         CurrentIGI = pDM_Odm->RSSI_Min;
 696                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: First Connect\n"));
 697                 } else {
 698                         if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2)
 699                                 CurrentIGI = CurrentIGI + 4;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */
 700                         else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1)
 701                                 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */
 702                         else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0)
 703                                 CurrentIGI = CurrentIGI - 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue-1; */
 704                 }
 705         } else {
 706                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): DIG BeforeLink\n"));
 707                 if (FirstDisConnect) {
 708                         CurrentIGI = pDM_DigTable->rx_gain_range_min;
 709                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): First DisConnect \n"));
 710                 } else {
 711                         /* 2012.03.30 LukeLee: enable DIG before link but with very high thresholds */
 712                         if (pFalseAlmCnt->Cnt_all > 10000)
 713                                 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */
 714                         else if (pFalseAlmCnt->Cnt_all > 8000)
 715                                 CurrentIGI = CurrentIGI + 1;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */
 716                         else if (pFalseAlmCnt->Cnt_all < 500)
 717                                 CurrentIGI = CurrentIGI - 1;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue-1; */
 718                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): England DIG \n"));
 719                 }
 720         }
 721         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): DIG End Adjust IGI\n"));
 722         /* 1 Check initial gain by upper/lower bound */
 723         if (CurrentIGI > pDM_DigTable->rx_gain_range_max)
 724                 CurrentIGI = pDM_DigTable->rx_gain_range_max;
 725         if (CurrentIGI < pDM_DigTable->rx_gain_range_min)
 726                 CurrentIGI = pDM_DigTable->rx_gain_range_min;
 727
 728         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): rx_gain_range_max = 0x%x, rx_gain_range_min = 0x%x\n",
 729                 pDM_DigTable->rx_gain_range_max, pDM_DigTable->rx_gain_range_min));
 730         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): TotalFA =%d\n", pFalseAlmCnt->Cnt_all));
 731         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): CurIGValue = 0x%x\n", CurrentIGI));
 732
 733         /* 2 High power RSSI threshold */
 734
 735         ODM_Write_DIG23a(pDM_Odm, CurrentIGI);/* ODM_Write_DIG23a(pDM_Odm, pDM_DigTable->CurIGValue); */
 736         pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked;
 737         pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN;
 738 }
 739
 740 /* 3 ============================================================ */
 741 /* 3 FASLE ALARM CHECK */
 742 /* 3 ============================================================ */
 743
 744 void odm_FalseAlarmCounterStatistics23a(struct dm_odm_t *pDM_Odm)
 745 {
 746         u32 ret_value;
 747         struct false_alarm_stats *FalseAlmCnt = &pDM_Odm->FalseAlmCnt;
 748
 749         /* hold ofdm counter */
 750          /* hold page C counter */
 751         ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT(31), 1);
 752         /* hold page D counter */
 753         ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(31), 1);
 754         ret_value =
 755                 ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE1_11N, bMaskDWord);
 756         FalseAlmCnt->Cnt_Fast_Fsync = (ret_value&0xffff);
 757         FalseAlmCnt->Cnt_SB_Search_fail = ((ret_value&0xffff0000)>>16);
 758         ret_value =
 759                 ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE2_11N, bMaskDWord);
 760         FalseAlmCnt->Cnt_OFDM_CCA = (ret_value&0xffff);
 761         FalseAlmCnt->Cnt_Parity_Fail = ((ret_value&0xffff0000)>>16);
 762         ret_value =
 763                 ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE3_11N, bMaskDWord);
 764         FalseAlmCnt->Cnt_Rate_Illegal = (ret_value&0xffff);
 765         FalseAlmCnt->Cnt_Crc8_fail = ((ret_value&0xffff0000)>>16);
 766         ret_value =
 767                 ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE4_11N, bMaskDWord);
 768         FalseAlmCnt->Cnt_Mcs_fail = (ret_value&0xffff);
 769
 770         FalseAlmCnt->Cnt_Ofdm_fail = FalseAlmCnt->Cnt_Parity_Fail +
 771                 FalseAlmCnt->Cnt_Rate_Illegal +
 772                 FalseAlmCnt->Cnt_Crc8_fail +
 773                 FalseAlmCnt->Cnt_Mcs_fail +
 774                 FalseAlmCnt->Cnt_Fast_Fsync +
 775                 FalseAlmCnt->Cnt_SB_Search_fail;
 776         /* hold cck counter */
 777         ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT(12), 1);
 778         ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT(14), 1);
 779
 780         ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_LSB_11N, bMaskByte0);
 781         FalseAlmCnt->Cnt_Cck_fail = ret_value;
 782         ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_MSB_11N, bMaskByte3);
 783         FalseAlmCnt->Cnt_Cck_fail +=  (ret_value & 0xff) << 8;
 784
 785         ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_CCA_CNT_11N, bMaskDWord);
 786         FalseAlmCnt->Cnt_CCK_CCA =
 787                 ((ret_value&0xFF)<<8) | ((ret_value&0xFF00)>>8);
 788
 789         FalseAlmCnt->Cnt_all = (FalseAlmCnt->Cnt_Fast_Fsync +
 790                                 FalseAlmCnt->Cnt_SB_Search_fail +
 791                                 FalseAlmCnt->Cnt_Parity_Fail +
 792                                 FalseAlmCnt->Cnt_Rate_Illegal +
 793                                 FalseAlmCnt->Cnt_Crc8_fail +
 794                                 FalseAlmCnt->Cnt_Mcs_fail +
 795                                 FalseAlmCnt->Cnt_Cck_fail);
 796
 797         FalseAlmCnt->Cnt_CCA_all =
 798                 FalseAlmCnt->Cnt_OFDM_CCA + FalseAlmCnt->Cnt_CCK_CCA;
 799
 800         if (pDM_Odm->SupportICType >= ODM_RTL8723A) {
 801                 /* reset false alarm counter registers */
 802                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT(31), 1);
 803                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT(31), 0);
 804                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(27), 1);
 805                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(27), 0);
 806                 /* update ofdm counter */
 807                  /* update page C counter */
 808                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT(31), 0);
 809                  /* update page D counter */
 810                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(31), 0);
 811
 812                 /* reset CCK CCA counter */
 813                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N,
 814                              BIT(13) | BIT(12), 0);
 815                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N,
 816                              BIT(13) | BIT(12), 2);
 817                 /* reset CCK FA counter */
 818                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N,
 819                              BIT(15) | BIT(14), 0);
 820                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N,
 821                              BIT(15) | BIT(14), 2);
 822         }
 823
 824         ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD,
 825                      ("Enter odm_FalseAlarmCounterStatistics23a\n"));
 826         ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD,
 827                      ("Cnt_Fast_Fsync =%d, Cnt_SB_Search_fail =%d\n",
 828                       FalseAlmCnt->Cnt_Fast_Fsync,
 829                       FalseAlmCnt->Cnt_SB_Search_fail));
 830         ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD,
 831                      ("Cnt_Parity_Fail =%d, Cnt_Rate_Illegal =%d\n",
 832                       FalseAlmCnt->Cnt_Parity_Fail,
 833                       FalseAlmCnt->Cnt_Rate_Illegal));
 834         ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD,
 835                      ("Cnt_Crc8_fail =%d, Cnt_Mcs_fail =%d\n",
 836                       FalseAlmCnt->Cnt_Crc8_fail, FalseAlmCnt->Cnt_Mcs_fail));
 837
 838         ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Cck_fail =%d\n", FalseAlmCnt->Cnt_Cck_fail));
 839         ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Ofdm_fail =%d\n", FalseAlmCnt->Cnt_Ofdm_fail));
 840         ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Total False Alarm =%d\n", FalseAlmCnt->Cnt_all));
 841 }
 842
 843 /* 3 ============================================================ */
 844 /* 3 CCK Packet Detect Threshold */
 845 /* 3 ============================================================ */
 846
 847 void odm_CCKPacketDetectionThresh23a(struct dm_odm_t *pDM_Odm)
 848 {
 849         struct false_alarm_stats *FalseAlmCnt = &pDM_Odm->FalseAlmCnt;
 850         u8 CurCCK_CCAThres;
 851
 852         if (pDM_Odm->ExtLNA)
 853                 return;
 854
 855         if (pDM_Odm->bLinked) {
 856                 if (pDM_Odm->RSSI_Min > 25) {
 857                         CurCCK_CCAThres = 0xcd;
 858                 } else if ((pDM_Odm->RSSI_Min <= 25) && (pDM_Odm->RSSI_Min > 10)) {
 859                         CurCCK_CCAThres = 0x83;
 860                 } else {
 861                         if (FalseAlmCnt->Cnt_Cck_fail > 1000)
 862                                 CurCCK_CCAThres = 0x83;
 863                         else
 864                                 CurCCK_CCAThres = 0x40;
 865                 }
 866         } else {
 867                 if (FalseAlmCnt->Cnt_Cck_fail > 1000)
 868                         CurCCK_CCAThres = 0x83;
 869                 else
 870                         CurCCK_CCAThres = 0x40;
 871         }
 872
 873         ODM_Write_CCK_CCA_Thres23a(pDM_Odm, CurCCK_CCAThres);
 874 }
 875
 876 void ODM_Write_CCK_CCA_Thres23a(struct dm_odm_t *pDM_Odm, u8 CurCCK_CCAThres)
 877 {
 878         struct dig_t *pDM_DigTable = &pDM_Odm->DM_DigTable;
 879
 880         if (pDM_DigTable->CurCCK_CCAThres != CurCCK_CCAThres)
 881                 ODM_Write1Byte(pDM_Odm, ODM_REG(CCK_CCA, pDM_Odm), CurCCK_CCAThres);
 882         pDM_DigTable->PreCCK_CCAThres = pDM_DigTable->CurCCK_CCAThres;
 883         pDM_DigTable->CurCCK_CCAThres = CurCCK_CCAThres;
 884
 885 }
 886
 887 /* 3 ============================================================ */
 888 /* 3 BB Power Save */
 889 /* 3 ============================================================ */
 890 void odm23a_DynBBPSInit(struct dm_odm_t *pDM_Odm)
 891 {
 892         struct dynamic_pwr_sav *pDM_PSTable = &pDM_Odm->DM_PSTable;
 893
 894         pDM_PSTable->PreCCAState = CCA_MAX;
 895         pDM_PSTable->CurCCAState = CCA_MAX;
 896         pDM_PSTable->PreRFState = RF_MAX;
 897         pDM_PSTable->CurRFState = RF_MAX;
 898         pDM_PSTable->Rssi_val_min = 0;
 899         pDM_PSTable->initialize = 0;
 900 }
 901
 902 void odm_DynamicBBPowerSaving23a(struct dm_odm_t *pDM_Odm)
 903 {
 904         return;
 905 }
 906
 907 void ODM_RF_Saving23a(struct dm_odm_t *pDM_Odm, u8 bForceInNormal)
 908 {
 909         struct dynamic_pwr_sav *pDM_PSTable = &pDM_Odm->DM_PSTable;
 910         u8 Rssi_Up_bound = 30;
 911         u8 Rssi_Low_bound = 25;
 912         if (pDM_Odm->PatchID == 40) { /* RT_CID_819x_FUNAI_TV */
 913                 Rssi_Up_bound = 50;
 914                 Rssi_Low_bound = 45;
 915         }
 916         if (pDM_PSTable->initialize == 0) {
 917
 918                 pDM_PSTable->Reg874 = (ODM_GetBBReg(pDM_Odm, 0x874, bMaskDWord)&0x1CC000)>>14;
 919                 pDM_PSTable->RegC70 =
 920                         (ODM_GetBBReg(pDM_Odm, 0xc70, bMaskDWord) & BIT(3)) >>3;
 921                 pDM_PSTable->Reg85C = (ODM_GetBBReg(pDM_Odm, 0x85c, bMaskDWord)&0xFF000000)>>24;
 922                 pDM_PSTable->RegA74 = (ODM_GetBBReg(pDM_Odm, 0xa74, bMaskDWord)&0xF000)>>12;
 923                 /* Reg818 = PHY_QueryBBReg(pAdapter, 0x818, bMaskDWord); */
 924                 pDM_PSTable->initialize = 1;
 925         }
 926
 927         if (!bForceInNormal) {
 928                 if (pDM_Odm->RSSI_Min != 0xFF) {
 929                         if (pDM_PSTable->PreRFState == RF_Normal) {
 930                                 if (pDM_Odm->RSSI_Min >= Rssi_Up_bound)
 931                                         pDM_PSTable->CurRFState = RF_Save;
 932                                 else
 933                                         pDM_PSTable->CurRFState = RF_Normal;
 934                         } else {
 935                                 if (pDM_Odm->RSSI_Min <= Rssi_Low_bound)
 936                                         pDM_PSTable->CurRFState = RF_Normal;
 937                                 else
 938                                         pDM_PSTable->CurRFState = RF_Save;
 939                         }
 940                 } else {
 941                         pDM_PSTable->CurRFState = RF_MAX;
 942                 }
 943         } else {
 944                 pDM_PSTable->CurRFState = RF_Normal;
 945         }
 946
 947         if (pDM_PSTable->PreRFState != pDM_PSTable->CurRFState) {
 948                 if (pDM_PSTable->CurRFState == RF_Save) {
 949                         /*  <tynli_note> 8723 RSSI report will be wrong. Set 0x874[5]= 1 when enter BB power saving mode. */
 950                         /*  Suggested by SD3 Yu-Nan. 2011.01.20. */
 951                         if (pDM_Odm->SupportICType == ODM_RTL8723A)
 952                                 ODM_SetBBReg(pDM_Odm, 0x874, BIT(5), 0x1); /* Reg874[5]= 1b'1 */
 953                         ODM_SetBBReg(pDM_Odm, 0x874, 0x1C0000, 0x2); /* Reg874[20:18]= 3'b010 */
 954                         ODM_SetBBReg(pDM_Odm, 0xc70, BIT(3), 0); /* RegC70[3]= 1'b0 */
 955                         ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, 0x63); /* Reg85C[31:24]= 0x63 */
 956                         ODM_SetBBReg(pDM_Odm, 0x874, 0xC000, 0x2); /* Reg874[15:14]= 2'b10 */
 957                         ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, 0x3); /* RegA75[7:4]= 0x3 */
 958                         ODM_SetBBReg(pDM_Odm, 0x818, BIT(28), 0x0); /* Reg818[28]= 1'b0 */
 959                         ODM_SetBBReg(pDM_Odm, 0x818, BIT(28), 0x1); /* Reg818[28]= 1'b1 */
 960                 } else {
 961                         ODM_SetBBReg(pDM_Odm, 0x874, 0x1CC000, pDM_PSTable->Reg874);
 962                         ODM_SetBBReg(pDM_Odm, 0xc70, BIT(3), pDM_PSTable->RegC70);
 963                         ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, pDM_PSTable->Reg85C);
 964                         ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, pDM_PSTable->RegA74);
 965                         ODM_SetBBReg(pDM_Odm, 0x818, BIT(28), 0x0);
 966
 967                         if (pDM_Odm->SupportICType == ODM_RTL8723A)
 968                                 ODM_SetBBReg(pDM_Odm, 0x874, BIT(5), 0x0); /* Reg874[5]= 1b'0 */
 969                 }
 970                 pDM_PSTable->PreRFState = pDM_PSTable->CurRFState;
 971         }
 972 }
 973
 974 /* 3 ============================================================ */
 975 /* 3 RATR MASK */
 976 /* 3 ============================================================ */
 977 /* 3 ============================================================ */
 978 /* 3 Rate Adaptive */
 979 /* 3 ============================================================ */
 980
 981 void odm_RateAdaptiveMaskInit23a(struct dm_odm_t *pDM_Odm)
 982 {
 983         struct odm_rate_adapt *pOdmRA = &pDM_Odm->RateAdaptive;
 984
 985         pOdmRA->Type = DM_Type_ByDriver;
 986
 987         pOdmRA->RATRState = DM_RATR_STA_INIT;
 988         pOdmRA->HighRSSIThresh = 50;
 989         pOdmRA->LowRSSIThresh = 20;
 990 }
 991
 992 u32 ODM_Get_Rate_Bitmap23a(struct hal_data_8723a *pHalData, u32 macid,
 993                            u32 ra_mask, u8 rssi_level)
 994 {
 995         struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
 996         struct sta_info *pEntry;
 997         u32 rate_bitmap = 0x0fffffff;
 998         u8 WirelessMode;
 999
1000         pEntry = pDM_Odm->pODM_StaInfo[macid];
1001         if (!pEntry)
1002                 return ra_mask;
1003
1004         WirelessMode = pEntry->wireless_mode;
1005
1006         switch (WirelessMode) {
1007         case ODM_WM_B:
1008                 if (ra_mask & 0x0000000c)               /* 11M or 5.5M enable */
1009                         rate_bitmap = 0x0000000d;
1010                 else
1011                         rate_bitmap = 0x0000000f;
1012                 break;
1013         case (ODM_WM_A|ODM_WM_G):
1014                 if (rssi_level == DM_RATR_STA_HIGH)
1015                         rate_bitmap = 0x00000f00;
1016                 else
1017                         rate_bitmap = 0x00000ff0;
1018                 break;
1019         case (ODM_WM_B|ODM_WM_G):
1020                 if (rssi_level == DM_RATR_STA_HIGH)
1021                         rate_bitmap = 0x00000f00;
1022                 else if (rssi_level == DM_RATR_STA_MIDDLE)
1023                         rate_bitmap = 0x00000ff0;
1024                 else
1025                         rate_bitmap = 0x00000ff5;
1026                 break;
1027         case (ODM_WM_B|ODM_WM_G|ODM_WM_N24G):
1028         case (ODM_WM_A|ODM_WM_B|ODM_WM_G|ODM_WM_N24G):
1029                 if (pHalData->rf_type == RF_1T2R ||
1030                     pHalData->rf_type == RF_1T1R) {
1031                         if (rssi_level == DM_RATR_STA_HIGH) {
1032                                 rate_bitmap = 0x000f0000;
1033                         } else if (rssi_level == DM_RATR_STA_MIDDLE) {
1034                                 rate_bitmap = 0x000ff000;
1035                         } else {
1036                                 if (pHalData->CurrentChannelBW ==
1037                                     HT_CHANNEL_WIDTH_40)
1038                                         rate_bitmap = 0x000ff015;
1039                                 else
1040                                         rate_bitmap = 0x000ff005;
1041                         }
1042                 } else {
1043                         if (rssi_level == DM_RATR_STA_HIGH) {
1044                                 rate_bitmap = 0x0f8f0000;
1045                         } else if (rssi_level == DM_RATR_STA_MIDDLE) {
1046                                 rate_bitmap = 0x0f8ff000;
1047                         } else {
1048                                 if (pHalData->CurrentChannelBW ==
1049                                     HT_CHANNEL_WIDTH_40)
1050                                         rate_bitmap = 0x0f8ff015;
1051                                 else
1052                                         rate_bitmap = 0x0f8ff005;
1053                         }
1054                 }
1055                 break;
1056         default:
1057                 /* case WIRELESS_11_24N: */
1058                 /* case WIRELESS_11_5N: */
1059                 if (pHalData->rf_type == RF_1T2R)
1060                         rate_bitmap = 0x000fffff;
1061                 else
1062                         rate_bitmap = 0x0fffffff;
1063                 break;
1064         }
1065
1066         /* printk("%s ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x \n", __func__, rssi_level, WirelessMode, rate_bitmap); */
1067         ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, (" ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x \n", rssi_level, WirelessMode, rate_bitmap));
1068
1069         return rate_bitmap;
1070
1071 }
1072
1073 /*-----------------------------------------------------------------------------
1074  * Function:    odm_RefreshRateAdaptiveMask23a()
1075  *
1076  * Overview:    Update rate table mask according to rssi
1077  *
1078  * Input:               NONE
1079  *
1080  * Output:              NONE
1081  *
1082  * Return:              NONE
1083  *
1084  * Revised History:
1085  *When          Who             Remark
1086  *05/27/2009    hpfan   Create Version 0.
1087  *
1088  *---------------------------------------------------------------------------*/
1089 void odm_RefreshRateAdaptiveMask23a(struct dm_odm_t *pDM_Odm)
1090 {
1091         u8 i;
1092         struct rtw_adapter *pAdapter     =  pDM_Odm->Adapter;
1093
1094         if (pAdapter->bDriverStopped) {
1095                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE,
1096                              ("<---- %s: driver is going to unload\n",
1097                               __func__));
1098                 return;
1099         }
1100
1101         for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
1102                 struct sta_info *pstat = pDM_Odm->pODM_StaInfo[i];
1103                 if (pstat) {
1104                         if (ODM_RAStateCheck23a(pDM_Odm, pstat->rssi_stat.UndecoratedSmoothedPWDB, false, &pstat->rssi_level)) {
1105                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD,
1106                                              ("RSSI:%d, RSSI_LEVEL:%d\n",
1107                                              pstat->rssi_stat.UndecoratedSmoothedPWDB,
1108                                              pstat->rssi_level));
1109                                 rtw_hal_update_ra_mask23a(pstat, pstat->rssi_level);
1110                         }
1111
1112                 }
1113         }
1114
1115 }
1116
1117 /*  Return Value: bool */
1118 /*  - true: RATRState is changed. */
1119 bool ODM_RAStateCheck23a(struct dm_odm_t *pDM_Odm, s32 RSSI, bool bForceUpdate,
1120                          u8 *pRATRState)
1121 {
1122         struct odm_rate_adapt *pRA = &pDM_Odm->RateAdaptive;
1123         const u8 GoUpGap = 5;
1124         u8 HighRSSIThreshForRA = pRA->HighRSSIThresh;
1125         u8 LowRSSIThreshForRA = pRA->LowRSSIThresh;
1126         u8 RATRState;
1127
1128         /*  Threshold Adjustment: */
1129         /*  when RSSI state trends to go up one or two levels, make sure RSSI is high enough. */
1130         /*  Here GoUpGap is added to solve the boundary's level alternation issue. */
1131         switch (*pRATRState) {
1132         case DM_RATR_STA_INIT:
1133         case DM_RATR_STA_HIGH:
1134                 break;
1135         case DM_RATR_STA_MIDDLE:
1136                 HighRSSIThreshForRA += GoUpGap;
1137                 break;
1138         case DM_RATR_STA_LOW:
1139                 HighRSSIThreshForRA += GoUpGap;
1140                 LowRSSIThreshForRA += GoUpGap;
1141                 break;
1142         default:
1143                 ODM_RT_ASSERT(pDM_Odm, false, ("wrong rssi level setting %d !", *pRATRState));
1144                 break;
1145         }
1146
1147         /*  Decide RATRState by RSSI. */
1148         if (RSSI > HighRSSIThreshForRA)
1149                 RATRState = DM_RATR_STA_HIGH;
1150         else if (RSSI > LowRSSIThreshForRA)
1151                 RATRState = DM_RATR_STA_MIDDLE;
1152         else
1153                 RATRState = DM_RATR_STA_LOW;
1154
1155         if (*pRATRState != RATRState || bForceUpdate) {
1156                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD,
1157                              ("RSSI Level %d -> %d\n", *pRATRState, RATRState));
1158                 *pRATRState = RATRState;
1159                 return true;
1160         }
1161         return false;
1162 }
1163
1164 /* 3 ============================================================ */
1165 /* 3 Dynamic Tx Power */
1166 /* 3 ============================================================ */
1167
1168 void odm_DynamicTxPower23aInit(struct dm_odm_t *pDM_Odm)
1169 {
1170         struct rtw_adapter *Adapter = pDM_Odm->Adapter;
1171         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1172         struct dm_priv *pdmpriv = &pHalData->dmpriv;
1173
1174         /*
1175          * This is never changed, so we should be able to clean up the
1176          * code checking for different values in rtl8723a_rf6052.c
1177          */
1178         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
1179 }
1180
1181 static void
1182 FindMinimumRSSI(
1183         struct rtw_adapter *pAdapter
1184         )
1185 {
1186         struct hal_data_8723a *pHalData = GET_HAL_DATA(pAdapter);
1187         struct dm_priv *pdmpriv = &pHalData->dmpriv;
1188         struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
1189
1190         /* 1 1.Determine the minimum RSSI */
1191
1192         if ((!pDM_Odm->bLinked) &&
1193             (pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0))
1194                 pdmpriv->MinUndecoratedPWDBForDM = 0;
1195         else
1196                 pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
1197 }
1198
1199 void odm_RSSIMonitorCheck23a(struct dm_odm_t *pDM_Odm)
1200 {
1201         struct rtw_adapter *Adapter = pDM_Odm->Adapter;
1202         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1203         struct dm_priv *pdmpriv = &pHalData->dmpriv;
1204         int     i;
1205         int     tmpEntryMaxPWDB = 0, tmpEntryMinPWDB = 0xff;
1206         u8 sta_cnt = 0;
1207         u32 PWDB_rssi[NUM_STA] = {0};/* 0~15]:MACID, [16~31]:PWDB_rssi */
1208         struct sta_info *psta;
1209
1210         if (!pDM_Odm->bLinked)
1211                 return;
1212
1213         for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
1214                 psta = pDM_Odm->pODM_StaInfo[i];
1215                 if (psta) {
1216                         if (psta->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB)
1217                                 tmpEntryMinPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
1218
1219                         if (psta->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB)
1220                                 tmpEntryMaxPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
1221
1222                         if (psta->rssi_stat.UndecoratedSmoothedPWDB != (-1))
1223                                 PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16));
1224                 }
1225         }
1226
1227         for (i = 0; i < sta_cnt; i++) {
1228                 if (PWDB_rssi[i] != (0)) {
1229                         rtl8723a_set_rssi_cmd(Adapter, (u8 *)&PWDB_rssi[i]);
1230                 }
1231         }
1232
1233         if (tmpEntryMaxPWDB != 0)       /*  If associated entry is found */
1234                 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = tmpEntryMaxPWDB;
1235         else
1236                 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = 0;
1237
1238         if (tmpEntryMinPWDB != 0xff) /*  If associated entry is found */
1239                 pdmpriv->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB;
1240         else
1241                 pdmpriv->EntryMinUndecoratedSmoothedPWDB = 0;
1242
1243         FindMinimumRSSI(Adapter);/* get pdmpriv->MinUndecoratedPWDBForDM */
1244
1245         ODM_CmnInfoUpdate23a(&pHalData->odmpriv, ODM_CMNINFO_RSSI_MIN, pdmpriv->MinUndecoratedPWDBForDM);
1246 }
1247
1248 /* endif */
1249 /* 3 ============================================================ */
1250 /* 3 Tx Power Tracking */
1251 /* 3 ============================================================ */
1252
1253 void odm_TXPowerTrackingInit23a(struct dm_odm_t *pDM_Odm)
1254 {
1255         odm_TXPowerTrackingThermalMeterInit23a(pDM_Odm);
1256 }
1257
1258 void odm_TXPowerTrackingThermalMeterInit23a(struct dm_odm_t *pDM_Odm)
1259 {
1260         struct rtw_adapter *Adapter = pDM_Odm->Adapter;
1261         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1262         struct dm_priv *pdmpriv = &pHalData->dmpriv;
1263
1264         pdmpriv->bTXPowerTracking = true;
1265         pdmpriv->TXPowercount = 0;
1266         pdmpriv->bTXPowerTrackingInit = false;
1267         pdmpriv->TxPowerTrackControl = true;
1268         MSG_8723A("pdmpriv->TxPowerTrackControl = %d\n", pdmpriv->TxPowerTrackControl);
1269
1270         pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = true;
1271 }
1272
1273 void ODM_TXPowerTrackingCheck23a(struct dm_odm_t *pDM_Odm)
1274 {
1275         /*  For AP/ADSL use struct rtl8723a_priv * */
1276         /*  For CE/NIC use struct rtw_adapter * */
1277
1278         /*  2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1279         /*  at the same time. In the stage2/3, we need to prive universal interface and merge all */
1280         /*  HW dynamic mechanism. */
1281         odm_TXPowerTrackingCheckCE23a(pDM_Odm);
1282 }
1283
1284 void odm_TXPowerTrackingCheckCE23a(struct dm_odm_t *pDM_Odm)
1285 {
1286 }
1287
1288 /* EDCA Turbo */
1289 static void ODM_EdcaTurboInit23a(struct dm_odm_t *pDM_Odm)
1290 {
1291
1292         struct rtw_adapter *Adapter = pDM_Odm->Adapter;
1293
1294         pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false;
1295         pDM_Odm->DM_EDCA_Table.bIsCurRDLState = false;
1296         Adapter->recvpriv.bIsAnyNonBEPkts = false;
1297
1298         ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VO PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_VO_PARAM)));
1299         ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VI PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_VI_PARAM)));
1300         ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BE PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_BE_PARAM)));
1301         ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BK PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_BK_PARAM)));
1302
1303 }       /*  ODM_InitEdcaTurbo */
1304
1305 static void odm_EdcaTurboCheck23a(struct dm_odm_t *pDM_Odm)
1306 {
1307         struct rtw_adapter *Adapter = pDM_Odm->Adapter;
1308         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1309         struct xmit_priv *pxmitpriv = &Adapter->xmitpriv;
1310         struct recv_priv *precvpriv = &Adapter->recvpriv;
1311         struct registry_priv *pregpriv = &Adapter->registrypriv;
1312         struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
1313         struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
1314         u32 trafficIndex;
1315         u32 edca_param;
1316         u64 cur_tx_bytes;
1317         u64 cur_rx_bytes;
1318
1319         /*  For AP/ADSL use struct rtl8723a_priv * */
1320         /*  For CE/NIC use struct rtw_adapter * */
1321
1322         /*  2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1323         /*  at the same time. In the stage2/3, we need to prive universal interface and merge all */
1324         /*  HW dynamic mechanism. */
1325
1326         if ((pregpriv->wifi_spec == 1))/*  (pmlmeinfo->HT_enable == 0)) */
1327                 goto dm_CheckEdcaTurbo_EXIT;
1328
1329         if (pmlmeinfo->assoc_AP_vendor >=  HT_IOT_PEER_MAX)
1330                 goto dm_CheckEdcaTurbo_EXIT;
1331
1332         if (rtl8723a_BT_disable_EDCA_turbo(Adapter))
1333                 goto dm_CheckEdcaTurbo_EXIT;
1334
1335         /*  Check if the status needs to be changed. */
1336         if (!precvpriv->bIsAnyNonBEPkts) {
1337                 cur_tx_bytes = pxmitpriv->tx_bytes - pxmitpriv->last_tx_bytes;
1338                 cur_rx_bytes = precvpriv->rx_bytes - precvpriv->last_rx_bytes;
1339
1340                 /* traffic, TX or RX */
1341                 if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_RALINK) ||
1342                     (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_ATHEROS)) {
1343                         if (cur_tx_bytes > (cur_rx_bytes << 2)) {
1344                                 /*  Uplink TP is present. */
1345                                 trafficIndex = UP_LINK;
1346                         } else { /*  Balance TP is present. */
1347                                 trafficIndex = DOWN_LINK;
1348                         }
1349                 } else {
1350                         if (cur_rx_bytes > (cur_tx_bytes << 2)) {
1351                                 /*  Downlink TP is present. */
1352                                 trafficIndex = DOWN_LINK;
1353                         } else { /*  Balance TP is present. */
1354                                 trafficIndex = UP_LINK;
1355                         }
1356                 }
1357
1358                 if ((pDM_Odm->DM_EDCA_Table.prv_traffic_idx != trafficIndex) ||
1359                     (!pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA)) {
1360                         if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_CISCO) &&
1361                             (pmlmeext->cur_wireless_mode & WIRELESS_11_24N))
1362                                 edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex];
1363                         else
1364                                 edca_param = EDCAParam[HT_IOT_PEER_UNKNOWN][trafficIndex];
1365                         rtl8723au_write32(Adapter, REG_EDCA_BE_PARAM,
1366                                           edca_param);
1367
1368                         pDM_Odm->DM_EDCA_Table.prv_traffic_idx = trafficIndex;
1369                 }
1370
1371                 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = true;
1372         } else {
1373                 /*  Turn Off EDCA turbo here. */
1374                 /*  Restore original EDCA according to the declaration of AP. */
1375                 if (pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA) {
1376                         rtl8723au_write32(Adapter, REG_EDCA_BE_PARAM,
1377                                           pHalData->AcParam_BE);
1378                         pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false;
1379                 }
1380         }
1381
1382 dm_CheckEdcaTurbo_EXIT:
1383         /*  Set variables for next time. */
1384         precvpriv->bIsAnyNonBEPkts = false;
1385         pxmitpriv->last_tx_bytes = pxmitpriv->tx_bytes;
1386         precvpriv->last_rx_bytes = precvpriv->rx_bytes;
1387 }
1388
1389 u32 GetPSDData(struct dm_odm_t *pDM_Odm, unsigned int point, u8 initial_gain_psd)
1390 {
1391         u32 psd_report;
1392
1393         /* Set DCO frequency index, offset = (40MHz/SamplePts)*point */
1394         ODM_SetBBReg(pDM_Odm, 0x808, 0x3FF, point);
1395
1396         /* Start PSD calculation, Reg808[22]= 0->1 */
1397         ODM_SetBBReg(pDM_Odm, 0x808, BIT(22), 1);
1398         /* Need to wait for HW PSD report */
1399         udelay(30);
1400         ODM_SetBBReg(pDM_Odm, 0x808, BIT(22), 0);
1401         /* Read PSD report, Reg8B4[15:0] */
1402         psd_report = ODM_GetBBReg(pDM_Odm, 0x8B4, bMaskDWord) & 0x0000FFFF;
1403
1404         psd_report = (u32)(ConvertTo_dB23a(psd_report))+(u32)(initial_gain_psd-0x1c);
1405
1406         return psd_report;
1407 }
1408
1409 u32
1410 ConvertTo_dB23a(
1411         u32 Value)
1412 {
1413         u8 i;
1414         u8 j;
1415         u32 dB;
1416
1417         Value = Value & 0xFFFF;
1418
1419         for (i = 0; i < 8; i++) {
1420                 if (Value <= dB_Invert_Table[i][11])
1421                         break;
1422         }
1423
1424         if (i >= 8)
1425                 return 96;      /*  maximum 96 dB */
1426
1427         for (j = 0; j < 12; j++) {
1428                 if (Value <= dB_Invert_Table[i][j])
1429                         break;
1430         }
1431
1432         dB = i*12 + j + 1;
1433
1434         return dB;
1435 }
1436
1437 /*  */
1438 /*  Description: */
1439 /*Set Single/Dual Antenna default setting for products that do not do detection in advance. */
1440 /*  */
1441 /*  Added by Joseph, 2012.03.22 */
1442 /*  */
1443 void ODM_SingleDualAntennaDefaultSetting(struct dm_odm_t *pDM_Odm)
1444 {
1445         struct sw_ant_sw *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
1446
1447         pDM_SWAT_Table->ANTA_ON = true;
1448         pDM_SWAT_Table->ANTB_ON = true;
1449 }
1450
1451 /* 2 8723A ANT DETECT */
1452
1453 static void odm_PHY_SaveAFERegisters(struct dm_odm_t *pDM_Odm, u32 *AFEReg,
1454                                      u32 *AFEBackup, u32 RegisterNum)
1455 {
1456         u32 i;
1457
1458         for (i = 0 ; i < RegisterNum ; i++)
1459                 AFEBackup[i] = ODM_GetBBReg(pDM_Odm, AFEReg[i], bMaskDWord);
1460 }
1461
1462 static void odm_PHY_ReloadAFERegisters(struct dm_odm_t *pDM_Odm, u32 *AFEReg,
1463                                        u32 *AFEBackup, u32 RegiesterNum)
1464 {
1465         u32 i;
1466
1467         for (i = 0 ; i < RegiesterNum; i++)
1468                 ODM_SetBBReg(pDM_Odm, AFEReg[i], bMaskDWord, AFEBackup[i]);
1469 }
1470
1471 /* 2 8723A ANT DETECT */
1472 /*  Description: */
1473 /* Implement IQK single tone for RF DPK loopback and BB PSD scanning. */
1474 /* This function is cooperated with BB team Neil. */
1475 bool ODM_SingleDualAntennaDetection(struct dm_odm_t *pDM_Odm, u8 mode)
1476 {
1477         struct sw_ant_sw *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
1478         u32 CurrentChannel, RfLoopReg;
1479         u8 n;
1480         u32 Reg88c, Regc08, Reg874, Regc50;
1481         u8 initial_gain = 0x5a;
1482         u32 PSD_report_tmp;
1483         u32 AntA_report = 0x0, AntB_report = 0x0, AntO_report = 0x0;
1484         bool bResult = true;
1485         u32 AFE_Backup[16];
1486         u32 AFE_REG_8723A[16] = {
1487                 rRx_Wait_CCA, rTx_CCK_RFON,
1488                 rTx_CCK_BBON, rTx_OFDM_RFON,
1489                 rTx_OFDM_BBON, rTx_To_Rx,
1490                 rTx_To_Tx, rRx_CCK,
1491                 rRx_OFDM, rRx_Wait_RIFS,
1492                 rRx_TO_Rx, rStandby,
1493                 rSleep, rPMPD_ANAEN,
1494                 rFPGA0_XCD_SwitchControl, rBlue_Tooth};
1495
1496         if (!(pDM_Odm->SupportICType & ODM_RTL8723A))
1497                 return bResult;
1498
1499         if (!(pDM_Odm->SupportAbility&ODM_BB_ANT_DIV))
1500                 return bResult;
1501         /* 1 Backup Current RF/BB Settings */
1502
1503         CurrentChannel = ODM_GetRFReg(pDM_Odm, RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask);
1504         RfLoopReg = ODM_GetRFReg(pDM_Odm, RF_PATH_A, 0x00, bRFRegOffsetMask);
1505         ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, ODM_DPDT, Antenna_A);  /*  change to Antenna A */
1506         /*  Step 1: USE IQK to transmitter single tone */
1507
1508         udelay(10);
1509
1510         /* Store A Path Register 88c, c08, 874, c50 */
1511         Reg88c = ODM_GetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord);
1512         Regc08 = ODM_GetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord);
1513         Reg874 = ODM_GetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord);
1514         Regc50 = ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord);
1515
1516         /*  Store AFE Registers */
1517         odm_PHY_SaveAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16);
1518
1519         /* Set PSD 128 pts */
1520         ODM_SetBBReg(pDM_Odm, rFPGA0_PSDFunction, BIT(14) | BIT(15), 0x0);
1521
1522         /*  To SET CH1 to do */
1523         ODM_SetRFReg(pDM_Odm, RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask, 0x01);     /* Channel 1 */
1524
1525         /*  AFE all on step */
1526         ODM_SetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord, 0x6FDB25A4);
1527         ODM_SetBBReg(pDM_Odm, rTx_CCK_RFON, bMaskDWord, 0x6FDB25A4);
1528         ODM_SetBBReg(pDM_Odm, rTx_CCK_BBON, bMaskDWord, 0x6FDB25A4);
1529         ODM_SetBBReg(pDM_Odm, rTx_OFDM_RFON, bMaskDWord, 0x6FDB25A4);
1530         ODM_SetBBReg(pDM_Odm, rTx_OFDM_BBON, bMaskDWord, 0x6FDB25A4);
1531         ODM_SetBBReg(pDM_Odm, rTx_To_Rx, bMaskDWord, 0x6FDB25A4);
1532         ODM_SetBBReg(pDM_Odm, rTx_To_Tx, bMaskDWord, 0x6FDB25A4);
1533         ODM_SetBBReg(pDM_Odm, rRx_CCK, bMaskDWord, 0x6FDB25A4);
1534         ODM_SetBBReg(pDM_Odm, rRx_OFDM, bMaskDWord, 0x6FDB25A4);
1535         ODM_SetBBReg(pDM_Odm, rRx_Wait_RIFS, bMaskDWord, 0x6FDB25A4);
1536         ODM_SetBBReg(pDM_Odm, rRx_TO_Rx, bMaskDWord, 0x6FDB25A4);
1537         ODM_SetBBReg(pDM_Odm, rStandby, bMaskDWord, 0x6FDB25A4);
1538         ODM_SetBBReg(pDM_Odm, rSleep, bMaskDWord, 0x6FDB25A4);
1539         ODM_SetBBReg(pDM_Odm, rPMPD_ANAEN, bMaskDWord, 0x6FDB25A4);
1540         ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_SwitchControl, bMaskDWord, 0x6FDB25A4);
1541         ODM_SetBBReg(pDM_Odm, rBlue_Tooth, bMaskDWord, 0x6FDB25A4);
1542
1543         /*  3 wire Disable */
1544         ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, 0xCCF000C0);
1545
1546         /* BB IQK Setting */
1547         ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800E4);
1548         ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22208000);
1549
1550         /* IQK setting tone@ 4.34Mhz */
1551         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008C1C);
1552         ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00);
1553
1554         /* Page B init */
1555         ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00080000);
1556         ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000);
1557         ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800);
1558         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1f);
1559         ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82150008);
1560         ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28150008);
1561         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x001028d0);
1562
1563         /* RF loop Setting */
1564         ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x0, 0xFFFFF, 0x50008);
1565
1566         /* IQK Single tone start */
1567         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80800000);
1568         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
1569         udelay(1000);
1570         PSD_report_tmp = 0x0;
1571
1572         for (n = 0; n < 2; n++) {
1573                 PSD_report_tmp =  GetPSDData(pDM_Odm, 14, initial_gain);
1574                 if (PSD_report_tmp > AntA_report)
1575                         AntA_report = PSD_report_tmp;
1576         }
1577
1578         PSD_report_tmp = 0x0;
1579
1580         ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_B);  /*  change to Antenna B */
1581         udelay(10);
1582
1583         for (n = 0; n < 2; n++) {
1584                 PSD_report_tmp =  GetPSDData(pDM_Odm, 14, initial_gain);
1585                 if (PSD_report_tmp > AntB_report)
1586                         AntB_report = PSD_report_tmp;
1587         }
1588
1589         /*  change to open case */
1590         ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, 0);  /*  change to Ant A and B all open case */
1591         udelay(10);
1592
1593         for (n = 0; n < 2; n++) {
1594                 PSD_report_tmp =  GetPSDData(pDM_Odm, 14, initial_gain);
1595                 if (PSD_report_tmp > AntO_report)
1596                         AntO_report = PSD_report_tmp;
1597         }
1598
1599         /* Close IQK Single Tone function */
1600         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
1601         PSD_report_tmp = 0x0;
1602
1603         /* 1 Return to antanna A */
1604         ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_A);
1605         ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, Reg88c);
1606         ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, Regc08);
1607         ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, Reg874);
1608         ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, 0x7F, 0x40);
1609         ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord, Regc50);
1610         ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, CurrentChannel);
1611         ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x00, bRFRegOffsetMask, RfLoopReg);
1612
1613         /* Reload AFE Registers */
1614         odm_PHY_ReloadAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16);
1615
1616         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_A[%d]= %d \n", 2416, AntA_report));
1617         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_B[%d]= %d \n", 2416, AntB_report));
1618         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_O[%d]= %d \n", 2416, AntO_report));
1619
1620         /* 2 Test Ant B based on Ant A is ON */
1621         if (mode == ANTTESTB) {
1622                 if (AntA_report >= 100) {
1623                         if (AntB_report > (AntA_report+1)) {
1624                                 pDM_SWAT_Table->ANTB_ON = false;
1625                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Single Antenna A\n"));
1626                         } else {
1627                                 pDM_SWAT_Table->ANTB_ON = true;
1628                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Dual Antenna is A and B\n"));
1629                         }
1630                 } else {
1631                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n"));
1632                         pDM_SWAT_Table->ANTB_ON = false; /*  Set Antenna B off as default */
1633                         bResult = false;
1634                 }
1635         } else if (mode == ANTTESTALL) {
1636                 /* 2 Test Ant A and B based on DPDT Open */
1637                 if ((AntO_report >= 100) & (AntO_report < 118)) {
1638                         if (AntA_report > (AntO_report+1)) {
1639                                 pDM_SWAT_Table->ANTA_ON = false;
1640                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant A is OFF"));
1641                         } else {
1642                                 pDM_SWAT_Table->ANTA_ON = true;
1643                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant A is ON"));
1644                         }
1645
1646                         if (AntB_report > (AntO_report+2)) {
1647                                 pDM_SWAT_Table->ANTB_ON = false;
1648                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant B is OFF"));
1649                         } else {
1650                                 pDM_SWAT_Table->ANTB_ON = true;
1651                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant B is ON"));
1652                         }
1653                 }
1654         } else {
1655                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n"));
1656                 pDM_SWAT_Table->ANTA_ON = true; /*  Set Antenna A on as default */
1657                 pDM_SWAT_Table->ANTB_ON = false; /*  Set Antenna B off as default */
1658                 bResult = false;
1659         }
1660         return bResult;
1661 }