drivers/staging/rtl8723au/hal/usb_halinit.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  ******************************************************************************/
  15 #define _HCI_HAL_INIT_C_
  16
  17 #include <osdep_service.h>
  18 #include <drv_types.h>
  19 #include <rtw_efuse.h>
  20
  21 #include <HalPwrSeqCmd.h>
  22 #include <Hal8723PwrSeq.h>
  23 #include <rtl8723a_hal.h>
  24 #include <linux/ieee80211.h>
  25
  26 #include <usb_ops.h>
  27
  28 static void
  29 _ConfigChipOutEP(struct rtw_adapter *pAdapter, u8 NumOutPipe)
  30 {
  31         u8 value8;
  32         struct hal_data_8723a *pHalData = GET_HAL_DATA(pAdapter);
  33
  34         pHalData->OutEpQueueSel = 0;
  35         pHalData->OutEpNumber = 0;
  36
  37         /*  Normal and High queue */
  38         value8 = rtl8723au_read8(pAdapter, (REG_NORMAL_SIE_EP + 1));
  39
  40         if (value8 & USB_NORMAL_SIE_EP_MASK) {
  41                 pHalData->OutEpQueueSel |= TX_SELE_HQ;
  42                 pHalData->OutEpNumber++;
  43         }
  44
  45         if ((value8 >> USB_NORMAL_SIE_EP_SHIFT) & USB_NORMAL_SIE_EP_MASK) {
  46                 pHalData->OutEpQueueSel |= TX_SELE_NQ;
  47                 pHalData->OutEpNumber++;
  48         }
  49
  50         /*  Low queue */
  51         value8 = rtl8723au_read8(pAdapter, (REG_NORMAL_SIE_EP + 2));
  52         if (value8 & USB_NORMAL_SIE_EP_MASK) {
  53                 pHalData->OutEpQueueSel |= TX_SELE_LQ;
  54                 pHalData->OutEpNumber++;
  55         }
  56
  57         /*  TODO: Error recovery for this case */
  58         /* RT_ASSERT((NumOutPipe == pHalData->OutEpNumber),
  59            ("Out EP number isn't match! %d(Descriptor) != %d (SIE reg)\n",
  60            (u32)NumOutPipe, (u32)pHalData->OutEpNumber)); */
  61 }
  62
  63 bool rtl8723au_chip_configure(struct rtw_adapter *padapter)
  64 {
  65         struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
  66         struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
  67         u8 NumInPipe = pdvobjpriv->RtNumInPipes;
  68         u8 NumOutPipe = pdvobjpriv->RtNumOutPipes;
  69
  70         _ConfigChipOutEP(padapter, NumOutPipe);
  71
  72         /*  Normal chip with one IN and one OUT doesn't have interrupt IN EP. */
  73         if (pHalData->OutEpNumber == 1) {
  74                 if (NumInPipe != 1)
  75                         return false;
  76         }
  77
  78         return Hal_MappingOutPipe23a(padapter, NumOutPipe);
  79 }
  80
  81 static int _InitPowerOn(struct rtw_adapter *padapter)
  82 {
  83         u16 value16;
  84         u8 value8;
  85
  86         /*  RSV_CTRL 0x1C[7:0] = 0x00
  87             unlock ISO/CLK/Power control register */
  88         rtl8723au_write8(padapter, REG_RSV_CTRL, 0x0);
  89
  90         /*  HW Power on sequence */
  91         if (!HalPwrSeqCmdParsing23a(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
  92                                  PWR_INTF_USB_MSK, rtl8723AU_card_enable_flow))
  93                 return _FAIL;
  94
  95         /*  0x04[19] = 1, suggest by Jackie 2011.05.09, reset 8051 */
  96         value8 = rtl8723au_read8(padapter, REG_APS_FSMCO+2);
  97         rtl8723au_write8(padapter, REG_APS_FSMCO + 2, value8 | BIT(3));
  98
  99         /*  Enable MAC DMA/WMAC/SCHEDULE/SEC block */
 100         /*  Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy.
 101             Added by tynli. 2011.08.31. */
 102         value16 = rtl8723au_read16(padapter, REG_CR);
 103         value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN |
 104                     PROTOCOL_EN | SCHEDULE_EN | MACTXEN | MACRXEN |
 105                     ENSEC | CALTMR_EN);
 106         rtl8723au_write16(padapter, REG_CR, value16);
 107
 108         /* for Efuse PG, suggest by Jackie 2011.11.23 */
 109         PHY_SetBBReg(padapter, REG_EFUSE_CTRL, BIT(28)|BIT(29)|BIT(30), 0x06);
 110
 111         return _SUCCESS;
 112 }
 113
 114 /*  Shall USB interface init this? */
 115 static void _InitInterrupt(struct rtw_adapter *Adapter)
 116 {
 117         u32 value32;
 118
 119         /*  HISR - turn all on */
 120         value32 = 0xFFFFFFFF;
 121         rtl8723au_write32(Adapter, REG_HISR, value32);
 122
 123         /*  HIMR - turn all on */
 124         rtl8723au_write32(Adapter, REG_HIMR, value32);
 125 }
 126
 127 static void _InitQueueReservedPage(struct rtw_adapter *Adapter)
 128 {
 129         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
 130         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 131         u32 numHQ = 0;
 132         u32 numLQ = 0;
 133         u32 numNQ = 0;
 134         u32 numPubQ;
 135         u32 value32;
 136         u8 value8;
 137         bool bWiFiConfig = pregistrypriv->wifi_spec;
 138
 139         /* RT_ASSERT((outEPNum>= 2), ("for WMM , number of out-ep "
 140            "must more than or equal to 2!\n")); */
 141
 142         numPubQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_PUBQ : NORMAL_PAGE_NUM_PUBQ;
 143
 144         if (pHalData->OutEpQueueSel & TX_SELE_HQ) {
 145                 numHQ = bWiFiConfig ?
 146                         WMM_NORMAL_PAGE_NUM_HPQ : NORMAL_PAGE_NUM_HPQ;
 147         }
 148
 149         if (pHalData->OutEpQueueSel & TX_SELE_LQ) {
 150                 numLQ = bWiFiConfig ?
 151                         WMM_NORMAL_PAGE_NUM_LPQ : NORMAL_PAGE_NUM_LPQ;
 152         }
 153         /*  NOTE: This step shall be proceed before
 154             writting REG_RQPN. */
 155         if (pHalData->OutEpQueueSel & TX_SELE_NQ) {
 156                 numNQ = bWiFiConfig ?
 157                         WMM_NORMAL_PAGE_NUM_NPQ : NORMAL_PAGE_NUM_NPQ;
 158         }
 159         value8 = (u8)_NPQ(numNQ);
 160         rtl8723au_write8(Adapter, REG_RQPN_NPQ, value8);
 161
 162         /*  TX DMA */
 163         value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
 164         rtl8723au_write32(Adapter, REG_RQPN, value32);
 165 }
 166
 167 static void _InitTxBufferBoundary(struct rtw_adapter *Adapter)
 168 {
 169         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 170
 171         u8 txpktbuf_bndy;
 172
 173         if (!pregistrypriv->wifi_spec)
 174                 txpktbuf_bndy = TX_PAGE_BOUNDARY;
 175         else /* for WMM */
 176                 txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY;
 177
 178         rtl8723au_write8(Adapter, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 179         rtl8723au_write8(Adapter, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 180         rtl8723au_write8(Adapter, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy);
 181         rtl8723au_write8(Adapter, REG_TRXFF_BNDY, txpktbuf_bndy);
 182         rtl8723au_write8(Adapter, REG_TDECTRL+1, txpktbuf_bndy);
 183 }
 184
 185 static void _InitPageBoundary(struct rtw_adapter *Adapter)
 186 {
 187         /*  RX Page Boundary */
 188         /* srand(static_cast<unsigned int>(time(NULL))); */
 189         u16 rxff_bndy = 0x27FF;/* rand() % 1) ? 0x27FF : 0x23FF; */
 190
 191         rtl8723au_write16(Adapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
 192
 193         /*  TODO: ?? shall we set tx boundary? */
 194 }
 195
 196 static void
 197 _InitNormalChipRegPriority(struct rtw_adapter *Adapter, u16 beQ, u16 bkQ,
 198                            u16 viQ, u16 voQ, u16 mgtQ, u16 hiQ)
 199 {
 200         u16 value16 = rtl8723au_read16(Adapter, REG_TRXDMA_CTRL) & 0x7;
 201
 202         value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) |
 203                 _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) |
 204                 _TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ);
 205
 206         rtl8723au_write16(Adapter, REG_TRXDMA_CTRL, value16);
 207 }
 208
 209 static void _InitNormalChipOneOutEpPriority(struct rtw_adapter *Adapter)
 210 {
 211         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
 212         u16 value = 0;
 213
 214         switch (pHalData->OutEpQueueSel) {
 215         case TX_SELE_HQ:
 216                 value = QUEUE_HIGH;
 217                 break;
 218         case TX_SELE_LQ:
 219                 value = QUEUE_LOW;
 220                 break;
 221         case TX_SELE_NQ:
 222                 value = QUEUE_NORMAL;
 223                 break;
 224         default:
 225                 /* RT_ASSERT(false, ("Shall not reach here!\n")); */
 226                 break;
 227         }
 228
 229         _InitNormalChipRegPriority(Adapter, value, value, value,
 230                                    value, value, value);
 231 }
 232
 233 static void _InitNormalChipTwoOutEpPriority(struct rtw_adapter *Adapter)
 234 {
 235         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
 236         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 237         u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
 238         u16 valueHi = 0;
 239         u16 valueLow = 0;
 240
 241         switch (pHalData->OutEpQueueSel) {
 242         case (TX_SELE_HQ | TX_SELE_LQ):
 243                 valueHi = QUEUE_HIGH;
 244                 valueLow = QUEUE_LOW;
 245                 break;
 246         case (TX_SELE_NQ | TX_SELE_LQ):
 247                 valueHi = QUEUE_NORMAL;
 248                 valueLow = QUEUE_LOW;
 249                 break;
 250         case (TX_SELE_HQ | TX_SELE_NQ):
 251                 valueHi = QUEUE_HIGH;
 252                 valueLow = QUEUE_NORMAL;
 253                 break;
 254         default:
 255                 /* RT_ASSERT(false, ("Shall not reach here!\n")); */
 256                 break;
 257         }
 258
 259         if (!pregistrypriv->wifi_spec) {
 260                 beQ = valueLow;
 261                 bkQ = valueLow;
 262                 viQ = valueHi;
 263                 voQ = valueHi;
 264                 mgtQ = valueHi;
 265                 hiQ = valueHi;
 266         } else {/* for WMM , CONFIG_OUT_EP_WIFI_MODE */
 267                 beQ = valueLow;
 268                 bkQ = valueHi;
 269                 viQ = valueHi;
 270                 voQ = valueLow;
 271                 mgtQ = valueHi;
 272                 hiQ = valueHi;
 273         }
 274
 275         _InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
 276 }
 277
 278 static void _InitNormalChipThreeOutEpPriority(struct rtw_adapter *Adapter)
 279 {
 280         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 281         u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
 282
 283         if (!pregistrypriv->wifi_spec) {/*  typical setting */
 284                 beQ = QUEUE_LOW;
 285                 bkQ = QUEUE_LOW;
 286                 viQ = QUEUE_NORMAL;
 287                 voQ = QUEUE_HIGH;
 288                 mgtQ = QUEUE_HIGH;
 289                 hiQ = QUEUE_HIGH;
 290         } else {/*  for WMM */
 291                 beQ = QUEUE_LOW;
 292                 bkQ = QUEUE_NORMAL;
 293                 viQ = QUEUE_NORMAL;
 294                 voQ = QUEUE_HIGH;
 295                 mgtQ = QUEUE_HIGH;
 296                 hiQ = QUEUE_HIGH;
 297         }
 298         _InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
 299 }
 300
 301 static void _InitNormalChipQueuePriority(struct rtw_adapter *Adapter)
 302 {
 303         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
 304
 305         switch (pHalData->OutEpNumber) {
 306         case 1:
 307                 _InitNormalChipOneOutEpPriority(Adapter);
 308                 break;
 309         case 2:
 310                 _InitNormalChipTwoOutEpPriority(Adapter);
 311                 break;
 312         case 3:
 313                 _InitNormalChipThreeOutEpPriority(Adapter);
 314                 break;
 315         default:
 316                 /* RT_ASSERT(false, ("Shall not reach here!\n")); */
 317                 break;
 318         }
 319 }
 320
 321 static void _InitQueuePriority(struct rtw_adapter *Adapter)
 322 {
 323         _InitNormalChipQueuePriority(Adapter);
 324 }
 325
 326 static void _InitTransferPageSize(struct rtw_adapter *Adapter)
 327 {
 328         /*  Tx page size is always 128. */
 329
 330         u8 value8;
 331         value8 = _PSRX(PBP_128) | _PSTX(PBP_128);
 332         rtl8723au_write8(Adapter, REG_PBP, value8);
 333 }
 334
 335 static void _InitDriverInfoSize(struct rtw_adapter *Adapter, u8 drvInfoSize)
 336 {
 337         rtl8723au_write8(Adapter, REG_RX_DRVINFO_SZ, drvInfoSize);
 338 }
 339
 340 static void _InitWMACSetting(struct rtw_adapter *Adapter)
 341 {
 342         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
 343
 344         /*  don't turn on AAP, it will allow all packets to driver */
 345         pHalData->ReceiveConfig = RCR_APM | RCR_AM | RCR_AB | RCR_CBSSID_DATA |
 346                                   RCR_CBSSID_BCN | RCR_APP_ICV | RCR_AMF |
 347                                   RCR_HTC_LOC_CTRL | RCR_APP_MIC |
 348                                   RCR_APP_PHYSTS;
 349
 350         /*  some REG_RCR will be modified later by
 351             phy_ConfigMACWithHeaderFile() */
 352         rtl8723au_write32(Adapter, REG_RCR, pHalData->ReceiveConfig);
 353
 354         /*  Accept all multicast address */
 355         rtl8723au_write32(Adapter, REG_MAR, 0xFFFFFFFF);
 356         rtl8723au_write32(Adapter, REG_MAR + 4, 0xFFFFFFFF);
 357
 358         /*  Accept all data frames */
 359         /* value16 = 0xFFFF; */
 360         /* rtl8723au_write16(Adapter, REG_RXFLTMAP2, value16); */
 361
 362         /*  2010.09.08 hpfan */
 363         /*  Since ADF is removed from RCR, ps-poll will not be indicate
 364             to driver, */
 365         /*  RxFilterMap should mask ps-poll to gurantee AP mode can
 366             rx ps-poll. */
 367         /* value16 = 0x400; */
 368         /* rtl8723au_write16(Adapter, REG_RXFLTMAP1, value16); */
 369
 370         /*  Accept all management frames */
 371         /* value16 = 0xFFFF; */
 372         /* rtl8723au_write16(Adapter, REG_RXFLTMAP0, value16); */
 373
 374         /* enable RX_SHIFT bits */
 375         /* rtl8723au_write8(Adapter, REG_TRXDMA_CTRL, rtl8723au_read8(Adapter,
 376            REG_TRXDMA_CTRL)|BIT(1)); */
 377 }
 378
 379 static void _InitAdaptiveCtrl(struct rtw_adapter *Adapter)
 380 {
 381         u16 value16;
 382         u32 value32;
 383
 384         /*  Response Rate Set */
 385         value32 = rtl8723au_read32(Adapter, REG_RRSR);
 386         value32 &= ~RATE_BITMAP_ALL;
 387         value32 |= RATE_RRSR_CCK_ONLY_1M;
 388         rtl8723au_write32(Adapter, REG_RRSR, value32);
 389
 390         /*  CF-END Threshold */
 391         /* m_spIoBase->rtl8723au_write8(REG_CFEND_TH, 0x1); */
 392
 393         /*  SIFS (used in NAV) */
 394         value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
 395         rtl8723au_write16(Adapter, REG_SPEC_SIFS, value16);
 396
 397         /*  Retry Limit */
 398         value16 = _LRL(0x30) | _SRL(0x30);
 399         rtl8723au_write16(Adapter, REG_RL, value16);
 400 }
 401
 402 static void _InitRateFallback(struct rtw_adapter *Adapter)
 403 {
 404         /*  Set Data Auto Rate Fallback Retry Count register. */
 405         rtl8723au_write32(Adapter, REG_DARFRC, 0x00000000);
 406         rtl8723au_write32(Adapter, REG_DARFRC+4, 0x10080404);
 407         rtl8723au_write32(Adapter, REG_RARFRC, 0x04030201);
 408         rtl8723au_write32(Adapter, REG_RARFRC+4, 0x08070605);
 409 }
 410
 411 static void _InitEDCA(struct rtw_adapter *Adapter)
 412 {
 413         /*  Set Spec SIFS (used in NAV) */
 414         rtl8723au_write16(Adapter, REG_SPEC_SIFS, 0x100a);
 415         rtl8723au_write16(Adapter, REG_MAC_SPEC_SIFS, 0x100a);
 416
 417         /*  Set SIFS for CCK */
 418         rtl8723au_write16(Adapter, REG_SIFS_CTX, 0x100a);
 419
 420         /*  Set SIFS for OFDM */
 421         rtl8723au_write16(Adapter, REG_SIFS_TRX, 0x100a);
 422
 423         /*  TXOP */
 424         rtl8723au_write32(Adapter, REG_EDCA_BE_PARAM, 0x005EA42B);
 425         rtl8723au_write32(Adapter, REG_EDCA_BK_PARAM, 0x0000A44F);
 426         rtl8723au_write32(Adapter, REG_EDCA_VI_PARAM, 0x005EA324);
 427         rtl8723au_write32(Adapter, REG_EDCA_VO_PARAM, 0x002FA226);
 428 }
 429
 430 static void _InitHWLed(struct rtw_adapter *Adapter)
 431 {
 432 }
 433
 434 static void _InitRDGSetting(struct rtw_adapter *Adapter)
 435 {
 436         rtl8723au_write8(Adapter, REG_RD_CTRL, 0xFF);
 437         rtl8723au_write16(Adapter, REG_RD_NAV_NXT, 0x200);
 438         rtl8723au_write8(Adapter, REG_RD_RESP_PKT_TH, 0x05);
 439 }
 440
 441 static void _InitRetryFunction(struct rtw_adapter *Adapter)
 442 {
 443         u8 value8;
 444
 445         value8 = rtl8723au_read8(Adapter, REG_FWHW_TXQ_CTRL);
 446         value8 |= EN_AMPDU_RTY_NEW;
 447         rtl8723au_write8(Adapter, REG_FWHW_TXQ_CTRL, value8);
 448
 449         /*  Set ACK timeout */
 450         rtl8723au_write8(Adapter, REG_ACKTO, 0x40);
 451 }
 452
 453 static void _InitRFType(struct rtw_adapter *Adapter)
 454 {
 455         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
 456         bool is92CU = IS_92C_SERIAL(pHalData->VersionID);
 457
 458         pHalData->rf_chip = RF_6052;
 459
 460         if (!is92CU) {
 461                 pHalData->rf_type = RF_1T1R;
 462                 DBG_8723A("Set RF Chip ID to RF_6052 and RF type to 1T1R.\n");
 463                 return;
 464         }
 465
 466         /*  TODO: Consider that EEPROM set 92CU to 1T1R later. */
 467         /*  Force to overwrite setting according to chip version. Ignore
 468             EEPROM setting. */
 469         /* pHalData->RF_Type = is92CU ? RF_2T2R : RF_1T1R; */
 470         MSG_8723A("Set RF Chip ID to RF_6052 and RF type to %d.\n",
 471                   pHalData->rf_type);
 472 }
 473
 474 /*  Set CCK and OFDM Block "ON" */
 475 static void _BBTurnOnBlock(struct rtw_adapter *Adapter)
 476 {
 477         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bCCKEn, 0x1);
 478         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
 479 }
 480
 481 #define MgntActSet_RF_State(...)
 482 static void _RfPowerSave(struct rtw_adapter *padapter)
 483 {
 484 }
 485
 486 enum {
 487         Antenna_Lfet = 1,
 488         Antenna_Right = 2,
 489 };
 490
 491 enum rt_rf_power_state RfOnOffDetect23a(struct rtw_adapter *pAdapter)
 492 {
 493         /* struct hal_data_8723a *pHalData = GET_HAL_DATA(pAdapter); */
 494         u8 val8;
 495         enum rt_rf_power_state rfpowerstate = rf_off;
 496
 497         rtl8723au_write8(pAdapter, REG_MAC_PINMUX_CFG,
 498                          rtl8723au_read8(pAdapter,
 499                                          REG_MAC_PINMUX_CFG) & ~BIT(3));
 500         val8 = rtl8723au_read8(pAdapter, REG_GPIO_IO_SEL);
 501         DBG_8723A("GPIO_IN =%02x\n", val8);
 502         rfpowerstate = (val8 & BIT(3)) ? rf_on : rf_off;
 503
 504         return rfpowerstate;
 505 }
 506
 507 void _ps_open_RF23a(struct rtw_adapter *padapter);
 508
 509 int rtl8723au_hal_init(struct rtw_adapter *Adapter)
 510 {
 511         u8 val8 = 0;
 512         u32 boundary;
 513         int status = _SUCCESS;
 514         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
 515         struct pwrctrl_priv *pwrctrlpriv = &Adapter->pwrctrlpriv;
 516         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 517
 518         unsigned long init_start_time = jiffies;
 519
 520         Adapter->hw_init_completed = false;
 521
 522         if (Adapter->pwrctrlpriv.bkeepfwalive) {
 523                 _ps_open_RF23a(Adapter);
 524
 525                 if (pHalData->bIQKInitialized) {
 526                         rtl8723a_phy_iq_calibrate(Adapter, true);
 527                 } else {
 528                         rtl8723a_phy_iq_calibrate(Adapter, false);
 529                         pHalData->bIQKInitialized = true;
 530                 }
 531                 rtl8723a_odm_check_tx_power_tracking(Adapter);
 532                 rtl8723a_phy_lc_calibrate(Adapter);
 533
 534                 goto exit;
 535         }
 536
 537         /*  Check if MAC has already power on. by tynli. 2011.05.27. */
 538         val8 = rtl8723au_read8(Adapter, REG_CR);
 539         RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
 540                  ("%s: REG_CR 0x100 = 0x%02x\n", __func__, val8));
 541         /* Fix 92DU-VC S3 hang with the reason is that secondary mac is not
 542            initialized. */
 543         /* 0x100 value of first mac is 0xEA while 0x100 value of secondary
 544            is 0x00 */
 545         if (val8 == 0xEA) {
 546                 pHalData->bMACFuncEnable = false;
 547         } else {
 548                 pHalData->bMACFuncEnable = true;
 549                 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
 550                          ("%s: MAC has already power on\n", __func__));
 551         }
 552
 553         status = _InitPowerOn(Adapter);
 554         if (status == _FAIL) {
 555                 RT_TRACE(_module_hci_hal_init_c_, _drv_err_,
 556                          ("Failed to init power on!\n"));
 557                 goto exit;
 558         }
 559
 560         if (!pregistrypriv->wifi_spec) {
 561                 boundary = TX_PAGE_BOUNDARY;
 562         } else {
 563                 /*  for WMM */
 564                 boundary = WMM_NORMAL_TX_PAGE_BOUNDARY;
 565         }
 566
 567         if (!pHalData->bMACFuncEnable) {
 568                 status =  InitLLTTable23a(Adapter, boundary);
 569                 if (status == _FAIL) {
 570                         RT_TRACE(_module_hci_hal_init_c_, _drv_err_,
 571                                  ("Failed to init LLT table\n"));
 572                         goto exit;
 573                 }
 574         }
 575
 576         if (pHalData->bRDGEnable)
 577                 _InitRDGSetting(Adapter);
 578
 579         status = rtl8723a_FirmwareDownload(Adapter);
 580         if (status != _SUCCESS) {
 581                 Adapter->bFWReady = false;
 582                 pHalData->fw_ractrl = false;
 583                 DBG_8723A("fw download fail!\n");
 584                 goto exit;
 585         } else {
 586                 Adapter->bFWReady = true;
 587                 pHalData->fw_ractrl = true;
 588                 DBG_8723A("fw download ok!\n");
 589         }
 590
 591         rtl8723a_InitializeFirmwareVars(Adapter);
 592
 593         if (pwrctrlpriv->reg_rfoff == true) {
 594                 pwrctrlpriv->rf_pwrstate = rf_off;
 595         }
 596
 597         /*  2010/08/09 MH We need to check if we need to turnon or off RF after detecting */
 598         /*  HW GPIO pin. Before PHY_RFConfig8192C. */
 599         /* HalDetectPwrDownMode(Adapter); */
 600         /*  2010/08/26 MH If Efuse does not support sective suspend then disable the function. */
 601         /* HalDetectSelectiveSuspendMode(Adapter); */
 602
 603         /*  Set RF type for BB/RF configuration */
 604         _InitRFType(Adapter);/* _ReadRFType() */
 605
 606         /*  Save target channel */
 607         /*  <Roger_Notes> Current Channel will be updated again later. */
 608         pHalData->CurrentChannel = 6;/* default set to 6 */
 609
 610         status = PHY_MACConfig8723A(Adapter);
 611         if (status == _FAIL) {
 612                 DBG_8723A("PHY_MACConfig8723A fault !!\n");
 613                 goto exit;
 614         }
 615
 616         /*  */
 617         /* d. Initialize BB related configurations. */
 618         /*  */
 619         status = PHY_BBConfig8723A(Adapter);
 620         if (status == _FAIL) {
 621                 DBG_8723A("PHY_BBConfig8723A fault !!\n");
 622                 goto exit;
 623         }
 624
 625         /*  Add for tx power by rate fine tune. We need to call the function after BB config. */
 626         /*  Because the tx power by rate table is inited in BB config. */
 627
 628         status = PHY_RF6052_Config8723A(Adapter);
 629         if (status == _FAIL) {
 630                 DBG_8723A("PHY_RF6052_Config8723A failed!!\n");
 631                 goto exit;
 632         }
 633
 634         /* reducing 80M spur */
 635         PHY_SetBBReg(Adapter, RF_T_METER, bMaskDWord, 0x0381808d);
 636         PHY_SetBBReg(Adapter, RF_SYN_G4, bMaskDWord, 0xf2ffff83);
 637         PHY_SetBBReg(Adapter, RF_SYN_G4, bMaskDWord, 0xf2ffff82);
 638         PHY_SetBBReg(Adapter, RF_SYN_G4, bMaskDWord, 0xf2ffff83);
 639
 640         /* RFSW Control */
 641         PHY_SetBBReg(Adapter, rFPGA0_TxInfo, bMaskDWord, 0x00000003);   /* 0x804[14]= 0 */
 642         PHY_SetBBReg(Adapter, rFPGA0_XAB_RFInterfaceSW, bMaskDWord, 0x07000760);        /* 0x870[6:5]= b'11 */
 643         PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, bMaskDWord, 0x66F60210); /* 0x860[6:5]= b'00 */
 644
 645         RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("%s: 0x870 = value 0x%x\n", __func__, PHY_QueryBBReg(Adapter, 0x870, bMaskDWord)));
 646
 647         /*  */
 648         /*  Joseph Note: Keep RfRegChnlVal for later use. */
 649         /*  */
 650         pHalData->RfRegChnlVal[0] = PHY_QueryRFReg(Adapter, (enum RF_RADIO_PATH)0, RF_CHNLBW, bRFRegOffsetMask);
 651         pHalData->RfRegChnlVal[1] = PHY_QueryRFReg(Adapter, (enum RF_RADIO_PATH)1, RF_CHNLBW, bRFRegOffsetMask);
 652
 653         if (!pHalData->bMACFuncEnable) {
 654                 _InitQueueReservedPage(Adapter);
 655                 _InitTxBufferBoundary(Adapter);
 656         }
 657         _InitQueuePriority(Adapter);
 658         _InitPageBoundary(Adapter);
 659         _InitTransferPageSize(Adapter);
 660
 661         /*  Get Rx PHY status in order to report RSSI and others. */
 662         _InitDriverInfoSize(Adapter, DRVINFO_SZ);
 663
 664         _InitInterrupt(Adapter);
 665         hw_var_set_macaddr(Adapter, Adapter->eeprompriv.mac_addr);
 666         rtl8723a_set_media_status(Adapter, MSR_INFRA);
 667         _InitWMACSetting(Adapter);
 668         _InitAdaptiveCtrl(Adapter);
 669         _InitEDCA(Adapter);
 670         _InitRateFallback(Adapter);
 671         _InitRetryFunction(Adapter);
 672         rtl8723a_InitBeaconParameters(Adapter);
 673
 674         _InitHWLed(Adapter);
 675
 676         _BBTurnOnBlock(Adapter);
 677         /* NicIFSetMacAddress(padapter, padapter->PermanentAddress); */
 678
 679         rtl8723a_cam_invalidate_all(Adapter);
 680
 681         /*  2010/12/17 MH We need to set TX power according to EFUSE content at first. */
 682         PHY_SetTxPowerLevel8723A(Adapter, pHalData->CurrentChannel);
 683
 684         rtl8723a_InitAntenna_Selection(Adapter);
 685
 686         /*  HW SEQ CTRL */
 687         /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */
 688         rtl8723au_write8(Adapter, REG_HWSEQ_CTRL, 0xFF);
 689
 690         /*  */
 691         /*  Disable BAR, suggested by Scott */
 692         /*  2010.04.09 add by hpfan */
 693         /*  */
 694         rtl8723au_write32(Adapter, REG_BAR_MODE_CTRL, 0x0201ffff);
 695
 696         if (pregistrypriv->wifi_spec)
 697                 rtl8723au_write16(Adapter, REG_FAST_EDCA_CTRL, 0);
 698
 699         /*  Move by Neo for USB SS from above setp */
 700         _RfPowerSave(Adapter);
 701
 702         /*  2010/08/26 MH Merge from 8192CE. */
 703         /* sherry masked that it has been done in _RfPowerSave */
 704         /* 20110927 */
 705         /* recovery for 8192cu and 9723Au 20111017 */
 706         if (pwrctrlpriv->rf_pwrstate == rf_on) {
 707                 if (pHalData->bIQKInitialized) {
 708                         rtl8723a_phy_iq_calibrate(Adapter, true);
 709                 } else {
 710                         rtl8723a_phy_iq_calibrate(Adapter, false);
 711                         pHalData->bIQKInitialized = true;
 712                 }
 713
 714                 rtl8723a_odm_check_tx_power_tracking(Adapter);
 715
 716                 rtl8723a_phy_lc_calibrate(Adapter);
 717
 718                 rtl8723a_dual_antenna_detection(Adapter);
 719         }
 720
 721         /* fixed USB interface interference issue */
 722         rtl8723au_write8(Adapter, 0xfe40, 0xe0);
 723         rtl8723au_write8(Adapter, 0xfe41, 0x8d);
 724         rtl8723au_write8(Adapter, 0xfe42, 0x80);
 725         rtl8723au_write32(Adapter, 0x20c, 0xfd0320);
 726         /* Solve too many protocol error on USB bus */
 727         if (!IS_81xxC_VENDOR_UMC_A_CUT(pHalData->VersionID)) {
 728                 /*  0xE6 = 0x94 */
 729                 rtl8723au_write8(Adapter, 0xFE40, 0xE6);
 730                 rtl8723au_write8(Adapter, 0xFE41, 0x94);
 731                 rtl8723au_write8(Adapter, 0xFE42, 0x80);
 732
 733                 /*  0xE0 = 0x19 */
 734                 rtl8723au_write8(Adapter, 0xFE40, 0xE0);
 735                 rtl8723au_write8(Adapter, 0xFE41, 0x19);
 736                 rtl8723au_write8(Adapter, 0xFE42, 0x80);
 737
 738                 /*  0xE5 = 0x91 */
 739                 rtl8723au_write8(Adapter, 0xFE40, 0xE5);
 740                 rtl8723au_write8(Adapter, 0xFE41, 0x91);
 741                 rtl8723au_write8(Adapter, 0xFE42, 0x80);
 742
 743                 /*  0xE2 = 0x81 */
 744                 rtl8723au_write8(Adapter, 0xFE40, 0xE2);
 745                 rtl8723au_write8(Adapter, 0xFE41, 0x81);
 746                 rtl8723au_write8(Adapter, 0xFE42, 0x80);
 747
 748         }
 749
 750 /*      _InitPABias(Adapter); */
 751
 752         /*  Init BT hw config. */
 753         rtl8723a_BT_init_hwconfig(Adapter);
 754
 755         rtl8723a_InitHalDm(Adapter);
 756
 757         val8 = ((WiFiNavUpperUs + HAL_8723A_NAV_UPPER_UNIT - 1) /
 758                 HAL_8723A_NAV_UPPER_UNIT);
 759         rtl8723au_write8(Adapter, REG_NAV_UPPER, val8);
 760
 761         /*  2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test, but we need to fin root cause. */
 762         if (((rtl8723au_read32(Adapter, rFPGA0_RFMOD) & 0xFF000000) !=
 763              0x83000000)) {
 764                 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT(24), 1);
 765                 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("%s: IQK fail recorver\n", __func__));
 766         }
 767
 768         /* ack for xmit mgmt frames. */
 769         rtl8723au_write32(Adapter, REG_FWHW_TXQ_CTRL,
 770                           rtl8723au_read32(Adapter, REG_FWHW_TXQ_CTRL)|BIT(12));
 771
 772 exit:
 773         if (status == _SUCCESS) {
 774                 Adapter->hw_init_completed = true;
 775
 776                 if (Adapter->registrypriv.notch_filter == 1)
 777                         rtl8723a_notch_filter(Adapter, 1);
 778         }
 779
 780         DBG_8723A("%s in %dms\n", __func__,
 781                   jiffies_to_msecs(jiffies - init_start_time));
 782         return status;
 783 }
 784
 785 static void phy_SsPwrSwitch92CU(struct rtw_adapter *Adapter,
 786                                 enum rt_rf_power_state eRFPowerState,
 787                                 int bRegSSPwrLvl)
 788 {
 789         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
 790         u8 value8;
 791         u8 bytetmp;
 792
 793         switch (eRFPowerState) {
 794         case rf_on:
 795                 if (bRegSSPwrLvl == 1) {
 796                         /*  1. Enable MAC Clock. Can not be enabled now. */
 797                         /* WriteXBYTE(REG_SYS_CLKR+1,
 798                            ReadXBYTE(REG_SYS_CLKR+1) | BIT(3)); */
 799
 800                         /*  2. Force PWM, Enable SPS18_LDO_Marco_Block */
 801                         rtl8723au_write8(Adapter, REG_SPS0_CTRL,
 802                                          rtl8723au_read8(Adapter, REG_SPS0_CTRL) |
 803                                          BIT(0) | BIT(3));
 804
 805                         /*  3. restore BB, AFE control register. */
 806                         /* RF */
 807                         if (pHalData->rf_type ==  RF_2T2R)
 808                                 PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter,
 809                                              0x380038, 1);
 810                         else
 811                                 PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter,
 812                                              0x38, 1);
 813                         PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 1);
 814                         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT(1), 0);
 815
 816                         /* AFE */
 817                         if (pHalData->rf_type ==  RF_2T2R)
 818                                 PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord,
 819                                              0x63DB25A0);
 820                         else if (pHalData->rf_type ==  RF_1T1R)
 821                                 PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord,
 822                                              0x631B25A0);
 823
 824                         /*  4. issue 3-wire command that RF set to Rx idle
 825                             mode. This is used to re-write the RX idle mode. */
 826                         /*  We can only prvide a usual value instead and then
 827                             HW will modify the value by itself. */
 828                         PHY_SetRFReg(Adapter, RF_PATH_A, 0,
 829                                      bRFRegOffsetMask, 0x32D95);
 830                         if (pHalData->rf_type ==  RF_2T2R) {
 831                                 PHY_SetRFReg(Adapter, RF_PATH_B, 0,
 832                                              bRFRegOffsetMask, 0x32D95);
 833                         }
 834                 } else {                /*  Level 2 or others. */
 835                         /* h.   AFE_PLL_CTRL 0x28[7:0] = 0x80
 836                            disable AFE PLL */
 837                         rtl8723au_write8(Adapter, REG_AFE_PLL_CTRL, 0x81);
 838
 839                         /*  i.  AFE_XTAL_CTRL 0x24[15:0] = 0x880F
 840                             gated AFE DIG_CLOCK */
 841                         rtl8723au_write16(Adapter, REG_AFE_XTAL_CTRL, 0x800F);
 842                         mdelay(1);
 843
 844                         /*  2. Force PWM, Enable SPS18_LDO_Marco_Block */
 845                         rtl8723au_write8(Adapter, REG_SPS0_CTRL,
 846                                          rtl8723au_read8(Adapter, REG_SPS0_CTRL) |
 847                                          BIT(0) | BIT(3));
 848
 849                         /*  3. restore BB, AFE control register. */
 850                         /* RF */
 851                         if (pHalData->rf_type ==  RF_2T2R)
 852                                 PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter,
 853                                              0x380038, 1);
 854                         else
 855                                 PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter,
 856                                              0x38, 1);
 857                         PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 1);
 858                         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT(1), 0);
 859
 860                         /* AFE */
 861                         if (pHalData->rf_type ==  RF_2T2R)
 862                                 PHY_SetBBReg(Adapter, rRx_Wait_CCA,
 863                                              bMaskDWord, 0x63DB25A0);
 864                         else if (pHalData->rf_type ==  RF_1T1R)
 865                                 PHY_SetBBReg(Adapter, rRx_Wait_CCA,
 866                                              bMaskDWord, 0x631B25A0);
 867
 868                         /*  4. issue 3-wire command that RF set to Rx idle
 869                             mode. This is used to re-write the RX idle mode. */
 870                         /*  We can only prvide a usual value instead and
 871                             then HW will modify the value by itself. */
 872                         PHY_SetRFReg(Adapter, RF_PATH_A, 0,
 873                                      bRFRegOffsetMask, 0x32D95);
 874                         if (pHalData->rf_type ==  RF_2T2R) {
 875                                 PHY_SetRFReg(Adapter, RF_PATH_B, 0,
 876                                              bRFRegOffsetMask, 0x32D95);
 877                         }
 878
 879                         /*  5. gated MAC Clock */
 880                         bytetmp = rtl8723au_read8(Adapter, REG_APSD_CTRL);
 881                         rtl8723au_write8(Adapter, REG_APSD_CTRL,
 882                                          bytetmp & ~BIT(6));
 883
 884                         mdelay(10);
 885
 886                         /*  Set BB reset at first */
 887                         /* 0x16 */
 888                         rtl8723au_write8(Adapter, REG_SYS_FUNC_EN, 0x17);
 889
 890                         /*  Enable TX */
 891                         rtl8723au_write8(Adapter, REG_TXPAUSE, 0x0);
 892                 }
 893                 break;
 894         case rf_sleep:
 895         case rf_off:
 896                 value8 = rtl8723au_read8(Adapter, REG_SPS0_CTRL);
 897                 if (IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID))
 898                         value8 &= ~BIT(0);
 899                 else
 900                         value8 &= ~(BIT(0) | BIT(3));
 901                 if (bRegSSPwrLvl == 1) {
 902                         RT_TRACE(_module_hal_init_c_, _drv_err_, ("SS LVL1\n"));
 903                         /*  Disable RF and BB only for SelectSuspend. */
 904
 905                         /*  1. Set BB/RF to shutdown. */
 906                         /*      (1) Reg878[5:3]= 0       RF rx_code for
 907                                                         preamble power saving */
 908                         /*      (2)Reg878[21:19]= 0     Turn off RF-B */
 909                         /*      (3) RegC04[7:4]= 0      Turn off all paths
 910                                                         for packet detection */
 911                         /*      (4) Reg800[1] = 1       enable preamble power
 912                                                         saving */
 913                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF0] =
 914                                 PHY_QueryBBReg(Adapter, rFPGA0_XAB_RFParameter,
 915                                                bMaskDWord);
 916                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF1] =
 917                                 PHY_QueryBBReg(Adapter, rOFDM0_TRxPathEnable,
 918                                                bMaskDWord);
 919                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF2] =
 920                                 PHY_QueryBBReg(Adapter, rFPGA0_RFMOD,
 921                                                bMaskDWord);
 922                         if (pHalData->rf_type ==  RF_2T2R) {
 923                                 PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter,
 924                                              0x380038, 0);
 925                         } else if (pHalData->rf_type ==  RF_1T1R) {
 926                                 PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter,
 927                                              0x38, 0);
 928                         }
 929                         PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 0);
 930                         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT(1), 1);
 931
 932                         /*  2 .AFE control register to power down. bit[30:22] */
 933                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_AFE0] =
 934                                 PHY_QueryBBReg(Adapter, rRx_Wait_CCA,
 935                                                bMaskDWord);
 936                         if (pHalData->rf_type ==  RF_2T2R)
 937                                 PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord,
 938                                              0x00DB25A0);
 939                         else if (pHalData->rf_type ==  RF_1T1R)
 940                                 PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord,
 941                                              0x001B25A0);
 942
 943                         /*  3. issue 3-wire command that RF set to power down.*/
 944                         PHY_SetRFReg(Adapter, RF_PATH_A, 0, bRFRegOffsetMask, 0);
 945                         if (pHalData->rf_type ==  RF_2T2R)
 946                                 PHY_SetRFReg(Adapter, RF_PATH_B, 0,
 947                                              bRFRegOffsetMask, 0);
 948
 949                         /*  4. Force PFM , disable SPS18_LDO_Marco_Block */
 950                         rtl8723au_write8(Adapter, REG_SPS0_CTRL, value8);
 951                 } else {        /*  Level 2 or others. */
 952                         RT_TRACE(_module_hal_init_c_, _drv_err_, ("SS LVL2\n"));
 953                         {
 954                                 u8 eRFPath = RF_PATH_A, value8 = 0;
 955                                 rtl8723au_write8(Adapter, REG_TXPAUSE, 0xFF);
 956                                 PHY_SetRFReg(Adapter,
 957                                              (enum RF_RADIO_PATH)eRFPath,
 958                                              0x0, bMaskByte0, 0x0);
 959                                 value8 |= APSDOFF;
 960                                 /* 0x40 */
 961                                 rtl8723au_write8(Adapter, REG_APSD_CTRL,
 962                                                  value8);
 963
 964                                 /*  After switch APSD, we need to delay
 965                                     for stability */
 966                                 mdelay(10);
 967
 968                                 /*  Set BB reset at first */
 969                                 value8 = 0;
 970                                 value8 |= (FEN_USBD | FEN_USBA |
 971                                            FEN_BB_GLB_RSTn);
 972                                 /* 0x16 */
 973                                 rtl8723au_write8(Adapter, REG_SYS_FUNC_EN,
 974                                                  value8);
 975                         }
 976
 977                         /*  Disable RF and BB only for SelectSuspend. */
 978
 979                         /*  1. Set BB/RF to shutdown. */
 980                         /*      (1) Reg878[5:3]= 0      RF rx_code for
 981                                                         preamble power saving */
 982                         /*      (2)Reg878[21:19]= 0     Turn off RF-B */
 983                         /*      (3) RegC04[7:4]= 0      Turn off all paths for
 984                                                         packet detection */
 985                         /*      (4) Reg800[1] = 1       enable preamble power
 986                                                         saving */
 987                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF0] =
 988                                 PHY_QueryBBReg(Adapter, rFPGA0_XAB_RFParameter,
 989                                                bMaskDWord);
 990                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF1] =
 991                                 PHY_QueryBBReg(Adapter, rOFDM0_TRxPathEnable,
 992                                                bMaskDWord);
 993                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF2] =
 994                                 PHY_QueryBBReg(Adapter, rFPGA0_RFMOD,
 995                                                bMaskDWord);
 996                         if (pHalData->rf_type ==  RF_2T2R)
 997                                 PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter,
 998                                              0x380038, 0);
 999                         else if (pHalData->rf_type ==  RF_1T1R)
1000                                 PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter,
1001                                              0x38, 0);
1002                         PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 0);
1003                         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT(1), 1);
1004
1005                         /*  2 .AFE control register to power down. bit[30:22] */
1006                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_AFE0] =
1007                                 PHY_QueryBBReg(Adapter, rRx_Wait_CCA,
1008                                                bMaskDWord);
1009                         if (pHalData->rf_type ==  RF_2T2R)
1010                                 PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord,
1011                                              0x00DB25A0);
1012                         else if (pHalData->rf_type ==  RF_1T1R)
1013                                 PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord,
1014                                              0x001B25A0);
1015
1016                         /* 3. issue 3-wire command that RF set to power down. */
1017                         PHY_SetRFReg(Adapter, RF_PATH_A, 0, bRFRegOffsetMask, 0);
1018                         if (pHalData->rf_type ==  RF_2T2R)
1019                                 PHY_SetRFReg(Adapter, RF_PATH_B, 0,
1020                                              bRFRegOffsetMask, 0);
1021
1022                         /*  4. Force PFM , disable SPS18_LDO_Marco_Block */
1023                         rtl8723au_write8(Adapter, REG_SPS0_CTRL, value8);
1024
1025                         /*  2010/10/13 MH/Isaachsu exchange sequence. */
1026                         /* h.   AFE_PLL_CTRL 0x28[7:0] = 0x80
1027                                 disable AFE PLL */
1028                         rtl8723au_write8(Adapter, REG_AFE_PLL_CTRL, 0x80);
1029                         mdelay(1);
1030
1031                         /*  i.  AFE_XTAL_CTRL 0x24[15:0] = 0x880F
1032                                 gated AFE DIG_CLOCK */
1033                         rtl8723au_write16(Adapter, REG_AFE_XTAL_CTRL, 0xA80F);
1034                 }
1035                 break;
1036         default:
1037                 break;
1038         }
1039
1040 }       /*  phy_PowerSwitch92CU */
1041
1042 void _ps_open_RF23a(struct rtw_adapter *padapter)
1043 {
1044         /* here call with bRegSSPwrLvl 1, bRegSSPwrLvl 2 needs to be verified */
1045         phy_SsPwrSwitch92CU(padapter, rf_on, 1);
1046 }
1047
1048 static void CardDisableRTL8723U(struct rtw_adapter *Adapter)
1049 {
1050         u8              u1bTmp;
1051
1052         DBG_8723A("CardDisableRTL8723U\n");
1053         /*  USB-MF Card Disable Flow */
1054         /*  1. Run LPS WL RFOFF flow */
1055         HalPwrSeqCmdParsing23a(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1056                             PWR_INTF_USB_MSK, rtl8723AU_enter_lps_flow);
1057
1058         /*  2. 0x1F[7:0] = 0            turn off RF */
1059         rtl8723au_write8(Adapter, REG_RF_CTRL, 0x00);
1060
1061         /*      ==== Reset digital sequence   ====== */
1062         if ((rtl8723au_read8(Adapter, REG_MCUFWDL) & BIT(7)) &&
1063             Adapter->bFWReady) /* 8051 RAM code */
1064                 rtl8723a_FirmwareSelfReset(Adapter);
1065
1066         /*  Reset MCU. Suggested by Filen. 2011.01.26. by tynli. */
1067         u1bTmp = rtl8723au_read8(Adapter, REG_SYS_FUNC_EN+1);
1068         rtl8723au_write8(Adapter, REG_SYS_FUNC_EN+1, u1bTmp & ~BIT(2));
1069
1070         /*  g.  MCUFWDL 0x80[1:0]= 0            reset MCU ready status */
1071         rtl8723au_write8(Adapter, REG_MCUFWDL, 0x00);
1072
1073         /*      ==== Reset digital sequence end ====== */
1074         /*  Card disable power action flow */
1075         HalPwrSeqCmdParsing23a(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1076                                PWR_INTF_USB_MSK,
1077                                rtl8723AU_card_disable_flow);
1078
1079         /*  Reset MCU IO Wrapper, added by Roger, 2011.08.30. */
1080         u1bTmp = rtl8723au_read8(Adapter, REG_RSV_CTRL + 1);
1081         rtl8723au_write8(Adapter, REG_RSV_CTRL+1, u1bTmp & ~BIT(0));
1082         u1bTmp = rtl8723au_read8(Adapter, REG_RSV_CTRL + 1);
1083         rtl8723au_write8(Adapter, REG_RSV_CTRL+1, u1bTmp | BIT(0));
1084
1085         /*  7. RSV_CTRL 0x1C[7:0] = 0x0E  lock ISO/CLK/Power control register */
1086         rtl8723au_write8(Adapter, REG_RSV_CTRL, 0x0e);
1087 }
1088
1089 int rtl8723au_hal_deinit(struct rtw_adapter *padapter)
1090 {
1091         DBG_8723A("==> %s\n", __func__);
1092
1093 #ifdef CONFIG_8723AU_BT_COEXIST
1094         BT_HaltProcess(padapter);
1095 #endif
1096         /*  2011/02/18 To Fix RU LNA  power leakage problem. We need to
1097             execute below below in Adapter init and halt sequence.
1098             According to EEchou's opinion, we can enable the ability for all */
1099         /*  IC. Accord to johnny's opinion, only RU need the support. */
1100         CardDisableRTL8723U(padapter);
1101
1102         padapter->hw_init_completed = false;
1103
1104         return _SUCCESS;
1105 }
1106
1107 int rtl8723au_inirp_init(struct rtw_adapter *Adapter)
1108 {
1109         u8 i;
1110         struct recv_buf *precvbuf;
1111         int status;
1112         struct recv_priv *precvpriv = &Adapter->recvpriv;
1113         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1114
1115         status = _SUCCESS;
1116
1117         RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("===> usb_inirp_init\n"));
1118
1119         /* issue Rx irp to receive data */
1120         precvbuf = (struct recv_buf *)precvpriv->precv_buf;
1121         for (i = 0; i < NR_RECVBUFF; i++) {
1122                 if (rtl8723au_read_port(Adapter, RECV_BULK_IN_ADDR, 0,
1123                                         precvbuf) == _FAIL) {
1124                         RT_TRACE(_module_hci_hal_init_c_, _drv_err_,
1125                                  ("usb_rx_init: usb_read_port error\n"));
1126                         status = _FAIL;
1127                         goto exit;
1128                 }
1129                 precvbuf++;
1130         }
1131         if (rtl8723au_read_interrupt(Adapter, RECV_INT_IN_ADDR) == _FAIL) {
1132                 RT_TRACE(_module_hci_hal_init_c_, _drv_err_,
1133                          ("usb_rx_init: usb_read_interrupt error\n"));
1134                 status = _FAIL;
1135         }
1136         pHalData->IntrMask[0] = rtl8723au_read32(Adapter, REG_USB_HIMR);
1137         MSG_8723A("pHalData->IntrMask = 0x%04x\n", pHalData->IntrMask[0]);
1138         pHalData->IntrMask[0] |= UHIMR_C2HCMD|UHIMR_CPWM;
1139         rtl8723au_write32(Adapter, REG_USB_HIMR, pHalData->IntrMask[0]);
1140 exit:
1141         RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1142                  ("<=== usb_inirp_init\n"));
1143         return status;
1144 }
1145
1146 int rtl8723au_inirp_deinit(struct rtw_adapter *Adapter)
1147 {
1148         struct hal_data_8723a   *pHalData = GET_HAL_DATA(Adapter);
1149
1150         RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1151                  ("\n ===> usb_rx_deinit\n"));
1152         rtl8723au_read_port_cancel(Adapter);
1153         pHalData->IntrMask[0] = rtl8723au_read32(Adapter, REG_USB_HIMR);
1154         MSG_8723A("%s pHalData->IntrMask = 0x%04x\n", __func__,
1155                   pHalData->IntrMask[0]);
1156         pHalData->IntrMask[0] = 0x0;
1157         rtl8723au_write32(Adapter, REG_USB_HIMR, pHalData->IntrMask[0]);
1158         RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1159                  ("\n <=== usb_rx_deinit\n"));
1160         return _SUCCESS;
1161 }
1162
1163 static void _ReadBoardType(struct rtw_adapter *Adapter, u8 *PROMContent,
1164                            bool AutoloadFail)
1165 {
1166         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1167         u8 boardType = BOARD_USB_DONGLE;
1168
1169         if (AutoloadFail) {
1170                 if (IS_8723_SERIES(pHalData->VersionID))
1171                         pHalData->rf_type = RF_1T1R;
1172                 else
1173                         pHalData->rf_type = RF_2T2R;
1174                 pHalData->BoardType = boardType;
1175                 return;
1176         }
1177
1178         boardType = PROMContent[EEPROM_NORMAL_BoardType];
1179         boardType &= BOARD_TYPE_NORMAL_MASK;/* bit[7:5] */
1180         boardType >>= 5;
1181
1182         pHalData->BoardType = boardType;
1183         MSG_8723A("_ReadBoardType(%x)\n", pHalData->BoardType);
1184
1185         if (boardType == BOARD_USB_High_PA)
1186                 pHalData->ExternalPA = 1;
1187 }
1188
1189 static void Hal_EfuseParseMACAddr_8723AU(struct rtw_adapter *padapter,
1190                                          u8 *hwinfo, bool AutoLoadFail)
1191 {
1192         u16 i;
1193         u8 sMacAddr[ETH_ALEN] = {0x00, 0xE0, 0x4C, 0x87, 0x23, 0x00};
1194         struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1195
1196         if (AutoLoadFail) {
1197                 for (i = 0; i < 6; i++)
1198                         pEEPROM->mac_addr[i] = sMacAddr[i];
1199         } else {
1200                 /* Read Permanent MAC address */
1201                 memcpy(pEEPROM->mac_addr, &hwinfo[EEPROM_MAC_ADDR_8723AU],
1202                        ETH_ALEN);
1203         }
1204
1205         RT_TRACE(_module_hci_hal_init_c_, _drv_notice_,
1206                  ("Hal_EfuseParseMACAddr_8723AU: Permanent Address =%02x:%02x:"
1207                   "%02x:%02x:%02x:%02x\n",
1208                   pEEPROM->mac_addr[0], pEEPROM->mac_addr[1],
1209                   pEEPROM->mac_addr[2], pEEPROM->mac_addr[3],
1210                   pEEPROM->mac_addr[4], pEEPROM->mac_addr[5]));
1211 }
1212
1213 static void readAdapterInfo(struct rtw_adapter *padapter)
1214 {
1215         struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1216         /* struct hal_data_8723a * pHalData = GET_HAL_DATA(padapter); */
1217         u8 hwinfo[HWSET_MAX_SIZE];
1218
1219         Hal_InitPGData(padapter, hwinfo);
1220         Hal_EfuseParseIDCode(padapter, hwinfo);
1221         Hal_EfuseParseEEPROMVer(padapter, hwinfo,
1222                                 pEEPROM->bautoload_fail_flag);
1223         Hal_EfuseParseMACAddr_8723AU(padapter, hwinfo,
1224                                      pEEPROM->bautoload_fail_flag);
1225         Hal_EfuseParsetxpowerinfo_8723A(padapter, hwinfo,
1226                                         pEEPROM->bautoload_fail_flag);
1227         _ReadBoardType(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1228         Hal_EfuseParseBTCoexistInfo_8723A(padapter, hwinfo,
1229                                           pEEPROM->bautoload_fail_flag);
1230
1231         rtl8723a_EfuseParseChnlPlan(padapter, hwinfo,
1232                                     pEEPROM->bautoload_fail_flag);
1233         Hal_EfuseParseThermalMeter_8723A(padapter, hwinfo,
1234                                          pEEPROM->bautoload_fail_flag);
1235 /*      _ReadRFSetting(Adapter, PROMContent, pEEPROM->bautoload_fail_flag); */
1236 /*      _ReadPSSetting(Adapter, PROMContent, pEEPROM->bautoload_fail_flag); */
1237         Hal_EfuseParseAntennaDiversity(padapter, hwinfo,
1238                                        pEEPROM->bautoload_fail_flag);
1239
1240         Hal_EfuseParseEEPROMVer(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1241         Hal_EfuseParseCustomerID(padapter, hwinfo,
1242                                  pEEPROM->bautoload_fail_flag);
1243         Hal_EfuseParseRateIndicationOption(padapter, hwinfo,
1244                                            pEEPROM->bautoload_fail_flag);
1245         Hal_EfuseParseXtal_8723A(padapter, hwinfo,
1246                                  pEEPROM->bautoload_fail_flag);
1247
1248         /* hal_CustomizedBehavior_8723U(Adapter); */
1249
1250 /*      Adapter->bDongle = (PROMContent[EEPROM_EASY_REPLACEMENT] == 1)? 0: 1; */
1251         DBG_8723A("%s(): REPLACEMENT = %x\n", __func__, padapter->bDongle);
1252 }
1253
1254 static void _ReadPROMContent(struct rtw_adapter *Adapter)
1255 {
1256         struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter);
1257         u8 eeValue;
1258
1259         eeValue = rtl8723au_read8(Adapter, REG_9346CR);
1260         /*  To check system boot selection. */
1261         pEEPROM->EepromOrEfuse = (eeValue & BOOT_FROM_EEPROM) ? true : false;
1262         pEEPROM->bautoload_fail_flag = (eeValue & EEPROM_EN) ? false : true;
1263
1264         DBG_8723A("Boot from %s, Autoload %s !\n",
1265                   (pEEPROM->EepromOrEfuse ? "EEPROM" : "EFUSE"),
1266                   (pEEPROM->bautoload_fail_flag ? "Fail" : "OK"));
1267
1268         readAdapterInfo(Adapter);
1269 }
1270
1271 static void _ReadRFType(struct rtw_adapter *Adapter)
1272 {
1273         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1274
1275         pHalData->rf_chip = RF_6052;
1276 }
1277
1278 static void _ReadSilmComboMode(struct rtw_adapter *Adapter)
1279 {
1280         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1281
1282         pHalData->SlimComboDbg = false; /*  Default is not debug mode. */
1283 }
1284
1285 /*  */
1286 /*      Description: */
1287 /*              We should set Efuse cell selection to WiFi cell in default. */
1288 /*  */
1289 /*      Assumption: */
1290 /*              PASSIVE_LEVEL */
1291 /*  */
1292 /*      Added by Roger, 2010.11.23. */
1293 /*  */
1294 static void hal_EfuseCellSel(struct rtw_adapter *Adapter)
1295 {
1296         u32 value32;
1297
1298         value32 = rtl8723au_read32(Adapter, EFUSE_TEST);
1299         value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
1300         rtl8723au_write32(Adapter, EFUSE_TEST, value32);
1301 }
1302
1303 void rtl8723a_read_adapter_info(struct rtw_adapter *Adapter)
1304 {
1305         unsigned long start = jiffies;
1306
1307         /*  Read EEPROM size before call any EEPROM function */
1308         Adapter->EepromAddressSize = GetEEPROMSize8723A(Adapter);
1309
1310         MSG_8723A("====> _ReadAdapterInfo8723AU\n");
1311
1312         hal_EfuseCellSel(Adapter);
1313
1314         _ReadRFType(Adapter);/* rf_chip -> _InitRFType() */
1315         _ReadPROMContent(Adapter);
1316
1317         /*  2010/10/25 MH THe function must be called after
1318             borad_type & IC-Version recognize. */
1319         _ReadSilmComboMode(Adapter);
1320
1321         /* MSG_8723A("%s()(done), rf_chip = 0x%x, rf_type = 0x%x\n",
1322            __func__, pHalData->rf_chip, pHalData->rf_type); */
1323
1324         MSG_8723A("<==== _ReadAdapterInfo8723AU in %d ms\n",
1325                   jiffies_to_msecs(jiffies - start));
1326 }
1327
1328 /*  */
1329 /*      Description: */
1330 /*              Query setting of specified variable. */
1331 /*  */
1332 int GetHalDefVar8192CUsb(struct rtw_adapter *Adapter,
1333                          enum hal_def_variable eVariable, void *pValue)
1334 {
1335         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1336         int bResult = _SUCCESS;
1337
1338         switch (eVariable) {
1339         case HAL_DEF_UNDERCORATEDSMOOTHEDPWDB:
1340                 *((int *)pValue) = pHalData->dmpriv.UndecoratedSmoothedPWDB;
1341                 break;
1342         case HAL_DEF_IS_SUPPORT_ANT_DIV:
1343                 break;
1344         case HAL_DEF_CURRENT_ANTENNA:
1345                 break;
1346         case HAL_DEF_DRVINFO_SZ:
1347                 *((u32 *)pValue) = DRVINFO_SZ;
1348                 break;
1349         case HAL_DEF_MAX_RECVBUF_SZ:
1350                 *((u32 *)pValue) = MAX_RECVBUF_SZ;
1351                 break;
1352         case HAL_DEF_RX_PACKET_OFFSET:
1353                 *((u32 *)pValue) = RXDESC_SIZE + DRVINFO_SZ;
1354                 break;
1355         case HAL_DEF_DBG_DUMP_RXPKT:
1356                 *((u8 *)pValue) = pHalData->bDumpRxPkt;
1357                 break;
1358         case HAL_DEF_DBG_DM_FUNC:
1359                 *((u32 *)pValue) = pHalData->odmpriv.SupportAbility;
1360                 break;
1361         case HW_VAR_MAX_RX_AMPDU_FACTOR:
1362                 *((u32 *)pValue) = IEEE80211_HT_MAX_AMPDU_64K;
1363                 break;
1364         case HW_DEF_ODM_DBG_FLAG:
1365         {
1366                 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
1367                 printk("pDM_Odm->DebugComponents = 0x%llx\n",
1368                        pDM_Odm->DebugComponents);
1369         }
1370                 break;
1371         default:
1372                 /* RT_TRACE(COMP_INIT, DBG_WARNING, ("GetHalDefVar8192CUsb(): "
1373                    "Unkown variable: %d!\n", eVariable)); */
1374                 bResult = _FAIL;
1375                 break;
1376         }
1377
1378         return bResult;
1379 }
1380
1381 void rtl8723a_update_ramask(struct rtw_adapter *padapter,
1382                             u32 mac_id, u8 rssi_level)
1383 {
1384         u8      init_rate = 0;
1385         u8      networkType, raid;
1386         u32     mask, rate_bitmap;
1387         u8      shortGIrate = false;
1388         int     supportRateNum = 0;
1389         struct sta_info *psta;
1390         struct hal_data_8723a   *pHalData = GET_HAL_DATA(padapter);
1391         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
1392         struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
1393         struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
1394         struct wlan_bssid_ex *cur_network = &pmlmeinfo->network;
1395
1396         if (mac_id >= NUM_STA) /* CAM_SIZE */
1397                 return;
1398
1399         psta = pmlmeinfo->FW_sta_info[mac_id].psta;
1400         if (psta == NULL)
1401                 return;
1402
1403         switch (mac_id) {
1404         case 0:/*  for infra mode */
1405                 supportRateNum =
1406                         rtw_get_rateset_len23a(cur_network->SupportedRates);
1407                 networkType = judge_network_type23a(padapter,
1408                                                  cur_network->SupportedRates,
1409                                                  supportRateNum) & 0xf;
1410                 /* pmlmeext->cur_wireless_mode = networkType; */
1411                 raid = networktype_to_raid23a(networkType);
1412
1413                 mask = update_supported_rate23a(cur_network->SupportedRates,
1414                                              supportRateNum);
1415                 mask |= (pmlmeinfo->HT_enable) ?
1416                         update_MSC_rate23a(&pmlmeinfo->ht_cap) : 0;
1417
1418                 if (support_short_GI23a(padapter, &pmlmeinfo->ht_cap))
1419                         shortGIrate = true;
1420                 break;
1421
1422         case 1:/* for broadcast/multicast */
1423                 supportRateNum = rtw_get_rateset_len23a(
1424                         pmlmeinfo->FW_sta_info[mac_id].SupportedRates);
1425                 if (pmlmeext->cur_wireless_mode & WIRELESS_11B)
1426                         networkType = WIRELESS_11B;
1427                 else
1428                         networkType = WIRELESS_11G;
1429                 raid = networktype_to_raid23a(networkType);
1430
1431                 mask = update_basic_rate23a(cur_network->SupportedRates,
1432                                          supportRateNum);
1433                 break;
1434
1435         default: /* for each sta in IBSS */
1436                 supportRateNum = rtw_get_rateset_len23a(
1437                         pmlmeinfo->FW_sta_info[mac_id].SupportedRates);
1438                 networkType = judge_network_type23a(padapter,
1439                                                  pmlmeinfo->FW_sta_info[mac_id].SupportedRates,
1440                                                  supportRateNum) & 0xf;
1441                 /* pmlmeext->cur_wireless_mode = networkType; */
1442                 raid = networktype_to_raid23a(networkType);
1443
1444                 mask = update_supported_rate23a(cur_network->SupportedRates,
1445                                              supportRateNum);
1446
1447                 /* todo: support HT in IBSS */
1448                 break;
1449         }
1450
1451         /* mask &= 0x0fffffff; */
1452         rate_bitmap = ODM_Get_Rate_Bitmap23a(pHalData, mac_id, mask,
1453                                              rssi_level);
1454         DBG_8723A("%s => mac_id:%d, networkType:0x%02x, "
1455                   "mask:0x%08x\n\t ==> rssi_level:%d, rate_bitmap:0x%08x\n",
1456                   __func__, mac_id, networkType, mask, rssi_level, rate_bitmap);
1457
1458         mask &= rate_bitmap;
1459         mask |= ((raid<<28)&0xf0000000);
1460
1461         init_rate = get_highest_rate_idx23a(mask)&0x3f;
1462
1463         if (pHalData->fw_ractrl == true) {
1464                 u8 arg = 0;
1465
1466                 /* arg = (cam_idx-4)&0x1f;MACID */
1467                 arg = mac_id&0x1f;/* MACID */
1468
1469                 arg |= BIT(7);
1470
1471                 if (shortGIrate == true)
1472                         arg |= BIT(5);
1473
1474                 DBG_8723A("update raid entry, mask = 0x%x, arg = 0x%x\n",
1475                           mask, arg);
1476
1477                 rtl8723a_set_raid_cmd(padapter, mask, arg);
1478         } else {
1479                 if (shortGIrate == true)
1480                         init_rate |= BIT(6);
1481
1482                 rtl8723au_write8(padapter, (REG_INIDATA_RATE_SEL+mac_id),
1483                                  init_rate);
1484         }
1485
1486         /* set ra_id */
1487         psta->raid = raid;
1488         psta->init_rate = init_rate;
1489
1490         /* set correct initial date rate for each mac_id */
1491         pdmpriv->INIDATA_RATE[mac_id] = init_rate;
1492 }