drivers/staging/rtl8723au/hal/usb_halinit.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  ******************************************************************************/
  15 #define _HCI_HAL_INIT_C_
  16
  17 #include <osdep_service.h>
  18 #include <drv_types.h>
  19 #include <rtw_efuse.h>
  20
  21 #include <HalPwrSeqCmd.h>
  22 #include <Hal8723PwrSeq.h>
  23 #include <rtl8723a_hal.h>
  24 #include <linux/ieee80211.h>
  25
  26 #include <usb_ops.h>
  27
  28 static void phy_SsPwrSwitch92CU(struct rtw_adapter *Adapter,
  29                                 enum rt_rf_power_state eRFPowerState);
  30
  31 static void
  32 _ConfigChipOutEP(struct rtw_adapter *pAdapter, u8 NumOutPipe)
  33 {
  34         u8 value8;
  35         struct hal_data_8723a *pHalData = GET_HAL_DATA(pAdapter);
  36
  37         pHalData->OutEpQueueSel = 0;
  38         pHalData->OutEpNumber = 0;
  39
  40         /*  Normal and High queue */
  41         value8 = rtl8723au_read8(pAdapter, (REG_NORMAL_SIE_EP + 1));
  42
  43         if (value8 & USB_NORMAL_SIE_EP_MASK) {
  44                 pHalData->OutEpQueueSel |= TX_SELE_HQ;
  45                 pHalData->OutEpNumber++;
  46         }
  47
  48         if ((value8 >> USB_NORMAL_SIE_EP_SHIFT) & USB_NORMAL_SIE_EP_MASK) {
  49                 pHalData->OutEpQueueSel |= TX_SELE_NQ;
  50                 pHalData->OutEpNumber++;
  51         }
  52
  53         /*  Low queue */
  54         value8 = rtl8723au_read8(pAdapter, (REG_NORMAL_SIE_EP + 2));
  55         if (value8 & USB_NORMAL_SIE_EP_MASK) {
  56                 pHalData->OutEpQueueSel |= TX_SELE_LQ;
  57                 pHalData->OutEpNumber++;
  58         }
  59
  60         /*  TODO: Error recovery for this case */
  61         /* RT_ASSERT((NumOutPipe == pHalData->OutEpNumber),
  62            ("Out EP number isn't match! %d(Descriptor) != %d (SIE reg)\n",
  63            (u32)NumOutPipe, (u32)pHalData->OutEpNumber)); */
  64 }
  65
  66 bool rtl8723au_chip_configure(struct rtw_adapter *padapter)
  67 {
  68         struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
  69         struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
  70         u8 NumInPipe = pdvobjpriv->RtNumInPipes;
  71         u8 NumOutPipe = pdvobjpriv->RtNumOutPipes;
  72
  73         _ConfigChipOutEP(padapter, NumOutPipe);
  74
  75         /*  Normal chip with one IN and one OUT doesn't have interrupt IN EP. */
  76         if (pHalData->OutEpNumber == 1) {
  77                 if (NumInPipe != 1)
  78                         return false;
  79         }
  80
  81         return Hal_MappingOutPipe23a(padapter, NumOutPipe);
  82 }
  83
  84 static int _InitPowerOn(struct rtw_adapter *padapter)
  85 {
  86         u16 value16;
  87         u8 value8;
  88
  89         /*  RSV_CTRL 0x1C[7:0] = 0x00
  90             unlock ISO/CLK/Power control register */
  91         rtl8723au_write8(padapter, REG_RSV_CTRL, 0x0);
  92
  93         /*  HW Power on sequence */
  94         if (!HalPwrSeqCmdParsing23a(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
  95                                  PWR_INTF_USB_MSK, rtl8723AU_card_enable_flow))
  96                 return _FAIL;
  97
  98         /*  0x04[19] = 1, suggest by Jackie 2011.05.09, reset 8051 */
  99         value8 = rtl8723au_read8(padapter, REG_APS_FSMCO+2);
 100         rtl8723au_write8(padapter, REG_APS_FSMCO + 2, value8 | BIT(3));
 101
 102         /*  Enable MAC DMA/WMAC/SCHEDULE/SEC block */
 103         /*  Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy.
 104             Added by tynli. 2011.08.31. */
 105         value16 = rtl8723au_read16(padapter, REG_CR);
 106         value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN |
 107                     PROTOCOL_EN | SCHEDULE_EN | MACTXEN | MACRXEN |
 108                     ENSEC | CALTMR_EN);
 109         rtl8723au_write16(padapter, REG_CR, value16);
 110
 111         /* for Efuse PG, suggest by Jackie 2011.11.23 */
 112         PHY_SetBBReg(padapter, REG_EFUSE_CTRL, BIT(28)|BIT(29)|BIT(30), 0x06);
 113
 114         return _SUCCESS;
 115 }
 116
 117 /*  Shall USB interface init this? */
 118 static void _InitInterrupt(struct rtw_adapter *Adapter)
 119 {
 120         u32 value32;
 121
 122         /*  HISR - turn all on */
 123         value32 = 0xFFFFFFFF;
 124         rtl8723au_write32(Adapter, REG_HISR, value32);
 125
 126         /*  HIMR - turn all on */
 127         rtl8723au_write32(Adapter, REG_HIMR, value32);
 128 }
 129
 130 static void _InitQueueReservedPage(struct rtw_adapter *Adapter)
 131 {
 132         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
 133         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 134         u32 numHQ = 0;
 135         u32 numLQ = 0;
 136         u32 numNQ = 0;
 137         u32 numPubQ;
 138         u32 value32;
 139         u8 value8;
 140         bool bWiFiConfig = pregistrypriv->wifi_spec;
 141
 142         /* RT_ASSERT((outEPNum>= 2), ("for WMM , number of out-ep "
 143            "must more than or equal to 2!\n")); */
 144
 145         numPubQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_PUBQ : NORMAL_PAGE_NUM_PUBQ;
 146
 147         if (pHalData->OutEpQueueSel & TX_SELE_HQ) {
 148                 numHQ = bWiFiConfig ?
 149                         WMM_NORMAL_PAGE_NUM_HPQ : NORMAL_PAGE_NUM_HPQ;
 150         }
 151
 152         if (pHalData->OutEpQueueSel & TX_SELE_LQ) {
 153                 numLQ = bWiFiConfig ?
 154                         WMM_NORMAL_PAGE_NUM_LPQ : NORMAL_PAGE_NUM_LPQ;
 155         }
 156         /*  NOTE: This step shall be proceed before
 157             writting REG_RQPN. */
 158         if (pHalData->OutEpQueueSel & TX_SELE_NQ) {
 159                 numNQ = bWiFiConfig ?
 160                         WMM_NORMAL_PAGE_NUM_NPQ : NORMAL_PAGE_NUM_NPQ;
 161         }
 162         value8 = (u8)_NPQ(numNQ);
 163         rtl8723au_write8(Adapter, REG_RQPN_NPQ, value8);
 164
 165         /*  TX DMA */
 166         value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
 167         rtl8723au_write32(Adapter, REG_RQPN, value32);
 168 }
 169
 170 static void _InitTxBufferBoundary(struct rtw_adapter *Adapter)
 171 {
 172         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 173
 174         u8 txpktbuf_bndy;
 175
 176         if (!pregistrypriv->wifi_spec)
 177                 txpktbuf_bndy = TX_PAGE_BOUNDARY;
 178         else /* for WMM */
 179                 txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY;
 180
 181         rtl8723au_write8(Adapter, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 182         rtl8723au_write8(Adapter, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 183         rtl8723au_write8(Adapter, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy);
 184         rtl8723au_write8(Adapter, REG_TRXFF_BNDY, txpktbuf_bndy);
 185         rtl8723au_write8(Adapter, REG_TDECTRL+1, txpktbuf_bndy);
 186 }
 187
 188 static void _InitPageBoundary(struct rtw_adapter *Adapter)
 189 {
 190         /*  RX Page Boundary */
 191         /* srand(static_cast<unsigned int>(time(NULL))); */
 192         u16 rxff_bndy = 0x27FF;/* rand() % 1) ? 0x27FF : 0x23FF; */
 193
 194         rtl8723au_write16(Adapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
 195
 196         /*  TODO: ?? shall we set tx boundary? */
 197 }
 198
 199 static void
 200 _InitNormalChipRegPriority(struct rtw_adapter *Adapter, u16 beQ, u16 bkQ,
 201                            u16 viQ, u16 voQ, u16 mgtQ, u16 hiQ)
 202 {
 203         u16 value16 = rtl8723au_read16(Adapter, REG_TRXDMA_CTRL) & 0x7;
 204
 205         value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) |
 206                 _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) |
 207                 _TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ);
 208
 209         rtl8723au_write16(Adapter, REG_TRXDMA_CTRL, value16);
 210 }
 211
 212 static void _InitNormalChipOneOutEpPriority(struct rtw_adapter *Adapter)
 213 {
 214         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
 215         u16 value = 0;
 216
 217         switch (pHalData->OutEpQueueSel) {
 218         case TX_SELE_HQ:
 219                 value = QUEUE_HIGH;
 220                 break;
 221         case TX_SELE_LQ:
 222                 value = QUEUE_LOW;
 223                 break;
 224         case TX_SELE_NQ:
 225                 value = QUEUE_NORMAL;
 226                 break;
 227         default:
 228                 /* RT_ASSERT(false, ("Shall not reach here!\n")); */
 229                 break;
 230         }
 231
 232         _InitNormalChipRegPriority(Adapter, value, value, value,
 233                                    value, value, value);
 234 }
 235
 236 static void _InitNormalChipTwoOutEpPriority(struct rtw_adapter *Adapter)
 237 {
 238         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
 239         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 240         u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
 241         u16 valueHi = 0;
 242         u16 valueLow = 0;
 243
 244         switch (pHalData->OutEpQueueSel) {
 245         case (TX_SELE_HQ | TX_SELE_LQ):
 246                 valueHi = QUEUE_HIGH;
 247                 valueLow = QUEUE_LOW;
 248                 break;
 249         case (TX_SELE_NQ | TX_SELE_LQ):
 250                 valueHi = QUEUE_NORMAL;
 251                 valueLow = QUEUE_LOW;
 252                 break;
 253         case (TX_SELE_HQ | TX_SELE_NQ):
 254                 valueHi = QUEUE_HIGH;
 255                 valueLow = QUEUE_NORMAL;
 256                 break;
 257         default:
 258                 /* RT_ASSERT(false, ("Shall not reach here!\n")); */
 259                 break;
 260         }
 261
 262         if (!pregistrypriv->wifi_spec) {
 263                 beQ = valueLow;
 264                 bkQ = valueLow;
 265                 viQ = valueHi;
 266                 voQ = valueHi;
 267                 mgtQ = valueHi;
 268                 hiQ = valueHi;
 269         } else {/* for WMM , CONFIG_OUT_EP_WIFI_MODE */
 270                 beQ = valueLow;
 271                 bkQ = valueHi;
 272                 viQ = valueHi;
 273                 voQ = valueLow;
 274                 mgtQ = valueHi;
 275                 hiQ = valueHi;
 276         }
 277
 278         _InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
 279 }
 280
 281 static void _InitNormalChipThreeOutEpPriority(struct rtw_adapter *Adapter)
 282 {
 283         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 284         u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
 285
 286         if (!pregistrypriv->wifi_spec) {/*  typical setting */
 287                 beQ = QUEUE_LOW;
 288                 bkQ = QUEUE_LOW;
 289                 viQ = QUEUE_NORMAL;
 290                 voQ = QUEUE_HIGH;
 291                 mgtQ = QUEUE_HIGH;
 292                 hiQ = QUEUE_HIGH;
 293         } else {/*  for WMM */
 294                 beQ = QUEUE_LOW;
 295                 bkQ = QUEUE_NORMAL;
 296                 viQ = QUEUE_NORMAL;
 297                 voQ = QUEUE_HIGH;
 298                 mgtQ = QUEUE_HIGH;
 299                 hiQ = QUEUE_HIGH;
 300         }
 301         _InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
 302 }
 303
 304 static void _InitQueuePriority(struct rtw_adapter *Adapter)
 305 {
 306         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
 307
 308         switch (pHalData->OutEpNumber) {
 309         case 1:
 310                 _InitNormalChipOneOutEpPriority(Adapter);
 311                 break;
 312         case 2:
 313                 _InitNormalChipTwoOutEpPriority(Adapter);
 314                 break;
 315         case 3:
 316                 _InitNormalChipThreeOutEpPriority(Adapter);
 317                 break;
 318         default:
 319                 /* RT_ASSERT(false, ("Shall not reach here!\n")); */
 320                 break;
 321         }
 322 }
 323
 324 static void _InitTransferPageSize(struct rtw_adapter *Adapter)
 325 {
 326         /*  Tx page size is always 128. */
 327
 328         u8 value8;
 329         value8 = _PSRX(PBP_128) | _PSTX(PBP_128);
 330         rtl8723au_write8(Adapter, REG_PBP, value8);
 331 }
 332
 333 static void _InitDriverInfoSize(struct rtw_adapter *Adapter, u8 drvInfoSize)
 334 {
 335         rtl8723au_write8(Adapter, REG_RX_DRVINFO_SZ, drvInfoSize);
 336 }
 337
 338 static void _InitWMACSetting(struct rtw_adapter *Adapter)
 339 {
 340         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
 341
 342         /*  don't turn on AAP, it will allow all packets to driver */
 343         pHalData->ReceiveConfig = RCR_APM | RCR_AM | RCR_AB | RCR_CBSSID_DATA |
 344                                   RCR_CBSSID_BCN | RCR_APP_ICV | RCR_AMF |
 345                                   RCR_HTC_LOC_CTRL | RCR_APP_MIC |
 346                                   RCR_APP_PHYSTS;
 347
 348         /*  some REG_RCR will be modified later by
 349             phy_ConfigMACWithHeaderFile() */
 350         rtl8723au_write32(Adapter, REG_RCR, pHalData->ReceiveConfig);
 351
 352         /*  Accept all multicast address */
 353         rtl8723au_write32(Adapter, REG_MAR, 0xFFFFFFFF);
 354         rtl8723au_write32(Adapter, REG_MAR + 4, 0xFFFFFFFF);
 355
 356         /*  Accept all data frames */
 357         /* value16 = 0xFFFF; */
 358         /* rtl8723au_write16(Adapter, REG_RXFLTMAP2, value16); */
 359
 360         /*  2010.09.08 hpfan */
 361         /*  Since ADF is removed from RCR, ps-poll will not be indicate
 362             to driver, */
 363         /*  RxFilterMap should mask ps-poll to gurantee AP mode can
 364             rx ps-poll. */
 365         /* value16 = 0x400; */
 366         /* rtl8723au_write16(Adapter, REG_RXFLTMAP1, value16); */
 367
 368         /*  Accept all management frames */
 369         /* value16 = 0xFFFF; */
 370         /* rtl8723au_write16(Adapter, REG_RXFLTMAP0, value16); */
 371
 372         /* enable RX_SHIFT bits */
 373         /* rtl8723au_write8(Adapter, REG_TRXDMA_CTRL, rtl8723au_read8(Adapter,
 374            REG_TRXDMA_CTRL)|BIT(1)); */
 375 }
 376
 377 static void _InitAdaptiveCtrl(struct rtw_adapter *Adapter)
 378 {
 379         u16 value16;
 380         u32 value32;
 381
 382         /*  Response Rate Set */
 383         value32 = rtl8723au_read32(Adapter, REG_RRSR);
 384         value32 &= ~RATE_BITMAP_ALL;
 385         value32 |= RATE_RRSR_CCK_ONLY_1M;
 386         rtl8723au_write32(Adapter, REG_RRSR, value32);
 387
 388         /*  CF-END Threshold */
 389         /* m_spIoBase->rtl8723au_write8(REG_CFEND_TH, 0x1); */
 390
 391         /*  SIFS (used in NAV) */
 392         value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
 393         rtl8723au_write16(Adapter, REG_SPEC_SIFS, value16);
 394
 395         /*  Retry Limit */
 396         value16 = _LRL(0x30) | _SRL(0x30);
 397         rtl8723au_write16(Adapter, REG_RL, value16);
 398 }
 399
 400 static void _InitRateFallback(struct rtw_adapter *Adapter)
 401 {
 402         /*  Set Data Auto Rate Fallback Retry Count register. */
 403         rtl8723au_write32(Adapter, REG_DARFRC, 0x00000000);
 404         rtl8723au_write32(Adapter, REG_DARFRC+4, 0x10080404);
 405         rtl8723au_write32(Adapter, REG_RARFRC, 0x04030201);
 406         rtl8723au_write32(Adapter, REG_RARFRC+4, 0x08070605);
 407 }
 408
 409 static void _InitEDCA(struct rtw_adapter *Adapter)
 410 {
 411         /*  Set Spec SIFS (used in NAV) */
 412         rtl8723au_write16(Adapter, REG_SPEC_SIFS, 0x100a);
 413         rtl8723au_write16(Adapter, REG_MAC_SPEC_SIFS, 0x100a);
 414
 415         /*  Set SIFS for CCK */
 416         rtl8723au_write16(Adapter, REG_SIFS_CTX, 0x100a);
 417
 418         /*  Set SIFS for OFDM */
 419         rtl8723au_write16(Adapter, REG_SIFS_TRX, 0x100a);
 420
 421         /*  TXOP */
 422         rtl8723au_write32(Adapter, REG_EDCA_BE_PARAM, 0x005EA42B);
 423         rtl8723au_write32(Adapter, REG_EDCA_BK_PARAM, 0x0000A44F);
 424         rtl8723au_write32(Adapter, REG_EDCA_VI_PARAM, 0x005EA324);
 425         rtl8723au_write32(Adapter, REG_EDCA_VO_PARAM, 0x002FA226);
 426 }
 427
 428 static void _InitRDGSetting(struct rtw_adapter *Adapter)
 429 {
 430         rtl8723au_write8(Adapter, REG_RD_CTRL, 0xFF);
 431         rtl8723au_write16(Adapter, REG_RD_NAV_NXT, 0x200);
 432         rtl8723au_write8(Adapter, REG_RD_RESP_PKT_TH, 0x05);
 433 }
 434
 435 static void _InitRetryFunction(struct rtw_adapter *Adapter)
 436 {
 437         u8 value8;
 438
 439         value8 = rtl8723au_read8(Adapter, REG_FWHW_TXQ_CTRL);
 440         value8 |= EN_AMPDU_RTY_NEW;
 441         rtl8723au_write8(Adapter, REG_FWHW_TXQ_CTRL, value8);
 442
 443         /*  Set ACK timeout */
 444         rtl8723au_write8(Adapter, REG_ACKTO, 0x40);
 445 }
 446
 447 static void _InitRFType(struct rtw_adapter *Adapter)
 448 {
 449         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
 450         bool is92CU = IS_92C_SERIAL(pHalData->VersionID);
 451
 452         pHalData->rf_chip = RF_6052;
 453
 454         if (!is92CU) {
 455                 pHalData->rf_type = RF_1T1R;
 456                 DBG_8723A("Set RF Chip ID to RF_6052 and RF type to 1T1R.\n");
 457                 return;
 458         }
 459
 460         /*  TODO: Consider that EEPROM set 92CU to 1T1R later. */
 461         /*  Force to overwrite setting according to chip version. Ignore
 462             EEPROM setting. */
 463         /* pHalData->RF_Type = is92CU ? RF_2T2R : RF_1T1R; */
 464         MSG_8723A("Set RF Chip ID to RF_6052 and RF type to %d.\n",
 465                   pHalData->rf_type);
 466 }
 467
 468 /*  Set CCK and OFDM Block "ON" */
 469 static void _BBTurnOnBlock(struct rtw_adapter *Adapter)
 470 {
 471         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bCCKEn, 0x1);
 472         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
 473 }
 474
 475 #define MgntActSet_RF_State(...)
 476 static void _RfPowerSave(struct rtw_adapter *padapter)
 477 {
 478 }
 479
 480 enum {
 481         Antenna_Lfet = 1,
 482         Antenna_Right = 2,
 483 };
 484
 485 enum rt_rf_power_state RfOnOffDetect23a(struct rtw_adapter *pAdapter)
 486 {
 487         /* struct hal_data_8723a *pHalData = GET_HAL_DATA(pAdapter); */
 488         u8 val8;
 489         enum rt_rf_power_state rfpowerstate = rf_off;
 490
 491         rtl8723au_write8(pAdapter, REG_MAC_PINMUX_CFG,
 492                          rtl8723au_read8(pAdapter,
 493                                          REG_MAC_PINMUX_CFG) & ~BIT(3));
 494         val8 = rtl8723au_read8(pAdapter, REG_GPIO_IO_SEL);
 495         DBG_8723A("GPIO_IN =%02x\n", val8);
 496         rfpowerstate = (val8 & BIT(3)) ? rf_on : rf_off;
 497
 498         return rfpowerstate;
 499 }
 500
 501 int rtl8723au_hal_init(struct rtw_adapter *Adapter)
 502 {
 503         u8 val8 = 0;
 504         u32 boundary;
 505         int status = _SUCCESS;
 506         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
 507         struct pwrctrl_priv *pwrctrlpriv = &Adapter->pwrctrlpriv;
 508         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 509
 510         unsigned long init_start_time = jiffies;
 511
 512         Adapter->hw_init_completed = false;
 513
 514         if (Adapter->pwrctrlpriv.bkeepfwalive) {
 515                 phy_SsPwrSwitch92CU(Adapter, rf_on);
 516
 517                 if (pHalData->bIQKInitialized) {
 518                         rtl8723a_phy_iq_calibrate(Adapter, true);
 519                 } else {
 520                         rtl8723a_phy_iq_calibrate(Adapter, false);
 521                         pHalData->bIQKInitialized = true;
 522                 }
 523                 rtl8723a_odm_check_tx_power_tracking(Adapter);
 524                 rtl8723a_phy_lc_calibrate(Adapter);
 525
 526                 goto exit;
 527         }
 528
 529         /*  Check if MAC has already power on. by tynli. 2011.05.27. */
 530         val8 = rtl8723au_read8(Adapter, REG_CR);
 531         RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
 532                  ("%s: REG_CR 0x100 = 0x%02x\n", __func__, val8));
 533         /* Fix 92DU-VC S3 hang with the reason is that secondary mac is not
 534            initialized. */
 535         /* 0x100 value of first mac is 0xEA while 0x100 value of secondary
 536            is 0x00 */
 537         if (val8 == 0xEA) {
 538                 pHalData->bMACFuncEnable = false;
 539         } else {
 540                 pHalData->bMACFuncEnable = true;
 541                 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
 542                          ("%s: MAC has already power on\n", __func__));
 543         }
 544
 545         status = _InitPowerOn(Adapter);
 546         if (status == _FAIL) {
 547                 RT_TRACE(_module_hci_hal_init_c_, _drv_err_,
 548                          ("Failed to init power on!\n"));
 549                 goto exit;
 550         }
 551
 552         if (!pregistrypriv->wifi_spec) {
 553                 boundary = TX_PAGE_BOUNDARY;
 554         } else {
 555                 /*  for WMM */
 556                 boundary = WMM_NORMAL_TX_PAGE_BOUNDARY;
 557         }
 558
 559         if (!pHalData->bMACFuncEnable) {
 560                 status =  InitLLTTable23a(Adapter, boundary);
 561                 if (status == _FAIL) {
 562                         RT_TRACE(_module_hci_hal_init_c_, _drv_err_,
 563                                  ("Failed to init LLT table\n"));
 564                         goto exit;
 565                 }
 566         }
 567
 568         if (pHalData->bRDGEnable)
 569                 _InitRDGSetting(Adapter);
 570
 571         status = rtl8723a_FirmwareDownload(Adapter);
 572         if (status != _SUCCESS) {
 573                 Adapter->bFWReady = false;
 574                 pHalData->fw_ractrl = false;
 575                 DBG_8723A("fw download fail!\n");
 576                 goto exit;
 577         } else {
 578                 Adapter->bFWReady = true;
 579                 pHalData->fw_ractrl = true;
 580                 DBG_8723A("fw download ok!\n");
 581         }
 582
 583         rtl8723a_InitializeFirmwareVars(Adapter);
 584
 585         if (pwrctrlpriv->reg_rfoff == true) {
 586                 pwrctrlpriv->rf_pwrstate = rf_off;
 587         }
 588
 589         /*  2010/08/09 MH We need to check if we need to turnon or off RF after detecting */
 590         /*  HW GPIO pin. Before PHY_RFConfig8192C. */
 591         /* HalDetectPwrDownMode(Adapter); */
 592         /*  2010/08/26 MH If Efuse does not support sective suspend then disable the function. */
 593         /* HalDetectSelectiveSuspendMode(Adapter); */
 594
 595         /*  Set RF type for BB/RF configuration */
 596         _InitRFType(Adapter);/* _ReadRFType() */
 597
 598         /*  Save target channel */
 599         /*  <Roger_Notes> Current Channel will be updated again later. */
 600         pHalData->CurrentChannel = 6;/* default set to 6 */
 601
 602         status = PHY_MACConfig8723A(Adapter);
 603         if (status == _FAIL) {
 604                 DBG_8723A("PHY_MACConfig8723A fault !!\n");
 605                 goto exit;
 606         }
 607
 608         /*  */
 609         /* d. Initialize BB related configurations. */
 610         /*  */
 611         status = PHY_BBConfig8723A(Adapter);
 612         if (status == _FAIL) {
 613                 DBG_8723A("PHY_BBConfig8723A fault !!\n");
 614                 goto exit;
 615         }
 616
 617         /*  Add for tx power by rate fine tune. We need to call the function after BB config. */
 618         /*  Because the tx power by rate table is inited in BB config. */
 619
 620         status = PHY_RF6052_Config8723A(Adapter);
 621         if (status == _FAIL) {
 622                 DBG_8723A("PHY_RF6052_Config8723A failed!!\n");
 623                 goto exit;
 624         }
 625
 626         /* reducing 80M spur */
 627         PHY_SetBBReg(Adapter, RF_T_METER, bMaskDWord, 0x0381808d);
 628         PHY_SetBBReg(Adapter, RF_SYN_G4, bMaskDWord, 0xf2ffff83);
 629         PHY_SetBBReg(Adapter, RF_SYN_G4, bMaskDWord, 0xf2ffff82);
 630         PHY_SetBBReg(Adapter, RF_SYN_G4, bMaskDWord, 0xf2ffff83);
 631
 632         /* RFSW Control */
 633         PHY_SetBBReg(Adapter, rFPGA0_TxInfo, bMaskDWord, 0x00000003);   /* 0x804[14]= 0 */
 634         PHY_SetBBReg(Adapter, rFPGA0_XAB_RFInterfaceSW, bMaskDWord, 0x07000760);        /* 0x870[6:5]= b'11 */
 635         PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, bMaskDWord, 0x66F60210); /* 0x860[6:5]= b'00 */
 636
 637         RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("%s: 0x870 = value 0x%x\n", __func__, PHY_QueryBBReg(Adapter, 0x870, bMaskDWord)));
 638
 639         /*  */
 640         /*  Joseph Note: Keep RfRegChnlVal for later use. */
 641         /*  */
 642         pHalData->RfRegChnlVal[0] = PHY_QueryRFReg(Adapter, (enum RF_RADIO_PATH)0, RF_CHNLBW, bRFRegOffsetMask);
 643         pHalData->RfRegChnlVal[1] = PHY_QueryRFReg(Adapter, (enum RF_RADIO_PATH)1, RF_CHNLBW, bRFRegOffsetMask);
 644
 645         if (!pHalData->bMACFuncEnable) {
 646                 _InitQueueReservedPage(Adapter);
 647                 _InitTxBufferBoundary(Adapter);
 648         }
 649         _InitQueuePriority(Adapter);
 650         _InitPageBoundary(Adapter);
 651         _InitTransferPageSize(Adapter);
 652
 653         /*  Get Rx PHY status in order to report RSSI and others. */
 654         _InitDriverInfoSize(Adapter, DRVINFO_SZ);
 655
 656         _InitInterrupt(Adapter);
 657         hw_var_set_macaddr(Adapter, Adapter->eeprompriv.mac_addr);
 658         rtl8723a_set_media_status(Adapter, MSR_INFRA);
 659         _InitWMACSetting(Adapter);
 660         _InitAdaptiveCtrl(Adapter);
 661         _InitEDCA(Adapter);
 662         _InitRateFallback(Adapter);
 663         _InitRetryFunction(Adapter);
 664         rtl8723a_InitBeaconParameters(Adapter);
 665
 666         _BBTurnOnBlock(Adapter);
 667         /* NicIFSetMacAddress(padapter, padapter->PermanentAddress); */
 668
 669         rtl8723a_cam_invalidate_all(Adapter);
 670
 671         /*  2010/12/17 MH We need to set TX power according to EFUSE content at first. */
 672         PHY_SetTxPowerLevel8723A(Adapter, pHalData->CurrentChannel);
 673
 674         rtl8723a_InitAntenna_Selection(Adapter);
 675
 676         /*  HW SEQ CTRL */
 677         /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */
 678         rtl8723au_write8(Adapter, REG_HWSEQ_CTRL, 0xFF);
 679
 680         /*  */
 681         /*  Disable BAR, suggested by Scott */
 682         /*  2010.04.09 add by hpfan */
 683         /*  */
 684         rtl8723au_write32(Adapter, REG_BAR_MODE_CTRL, 0x0201ffff);
 685
 686         if (pregistrypriv->wifi_spec)
 687                 rtl8723au_write16(Adapter, REG_FAST_EDCA_CTRL, 0);
 688
 689         /*  Move by Neo for USB SS from above setp */
 690         _RfPowerSave(Adapter);
 691
 692         /*  2010/08/26 MH Merge from 8192CE. */
 693         /* sherry masked that it has been done in _RfPowerSave */
 694         /* 20110927 */
 695         /* recovery for 8192cu and 9723Au 20111017 */
 696         if (pwrctrlpriv->rf_pwrstate == rf_on) {
 697                 if (pHalData->bIQKInitialized) {
 698                         rtl8723a_phy_iq_calibrate(Adapter, true);
 699                 } else {
 700                         rtl8723a_phy_iq_calibrate(Adapter, false);
 701                         pHalData->bIQKInitialized = true;
 702                 }
 703
 704                 rtl8723a_odm_check_tx_power_tracking(Adapter);
 705
 706                 rtl8723a_phy_lc_calibrate(Adapter);
 707
 708                 rtl8723a_dual_antenna_detection(Adapter);
 709         }
 710
 711         /* fixed USB interface interference issue */
 712         rtl8723au_write8(Adapter, 0xfe40, 0xe0);
 713         rtl8723au_write8(Adapter, 0xfe41, 0x8d);
 714         rtl8723au_write8(Adapter, 0xfe42, 0x80);
 715         rtl8723au_write32(Adapter, 0x20c, 0xfd0320);
 716         /* Solve too many protocol error on USB bus */
 717         if (!IS_81xxC_VENDOR_UMC_A_CUT(pHalData->VersionID)) {
 718                 /*  0xE6 = 0x94 */
 719                 rtl8723au_write8(Adapter, 0xFE40, 0xE6);
 720                 rtl8723au_write8(Adapter, 0xFE41, 0x94);
 721                 rtl8723au_write8(Adapter, 0xFE42, 0x80);
 722
 723                 /*  0xE0 = 0x19 */
 724                 rtl8723au_write8(Adapter, 0xFE40, 0xE0);
 725                 rtl8723au_write8(Adapter, 0xFE41, 0x19);
 726                 rtl8723au_write8(Adapter, 0xFE42, 0x80);
 727
 728                 /*  0xE5 = 0x91 */
 729                 rtl8723au_write8(Adapter, 0xFE40, 0xE5);
 730                 rtl8723au_write8(Adapter, 0xFE41, 0x91);
 731                 rtl8723au_write8(Adapter, 0xFE42, 0x80);
 732
 733                 /*  0xE2 = 0x81 */
 734                 rtl8723au_write8(Adapter, 0xFE40, 0xE2);
 735                 rtl8723au_write8(Adapter, 0xFE41, 0x81);
 736                 rtl8723au_write8(Adapter, 0xFE42, 0x80);
 737
 738         }
 739
 740 /*      _InitPABias(Adapter); */
 741
 742         /*  Init BT hw config. */
 743         rtl8723a_BT_init_hwconfig(Adapter);
 744
 745         rtl8723a_InitHalDm(Adapter);
 746
 747         val8 = ((WiFiNavUpperUs + HAL_8723A_NAV_UPPER_UNIT - 1) /
 748                 HAL_8723A_NAV_UPPER_UNIT);
 749         rtl8723au_write8(Adapter, REG_NAV_UPPER, val8);
 750
 751         /*  2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test, but we need to fin root cause. */
 752         if (((rtl8723au_read32(Adapter, rFPGA0_RFMOD) & 0xFF000000) !=
 753              0x83000000)) {
 754                 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT(24), 1);
 755                 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("%s: IQK fail recorver\n", __func__));
 756         }
 757
 758         /* ack for xmit mgmt frames. */
 759         rtl8723au_write32(Adapter, REG_FWHW_TXQ_CTRL,
 760                           rtl8723au_read32(Adapter, REG_FWHW_TXQ_CTRL)|BIT(12));
 761
 762 exit:
 763         if (status == _SUCCESS) {
 764                 Adapter->hw_init_completed = true;
 765
 766                 if (Adapter->registrypriv.notch_filter == 1)
 767                         rtl8723a_notch_filter(Adapter, 1);
 768         }
 769
 770         DBG_8723A("%s in %dms\n", __func__,
 771                   jiffies_to_msecs(jiffies - init_start_time));
 772         return status;
 773 }
 774
 775 static void phy_SsPwrSwitch92CU(struct rtw_adapter *Adapter,
 776                                 enum rt_rf_power_state eRFPowerState)
 777 {
 778         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
 779         u8 sps0;
 780
 781         sps0 = rtl8723au_read8(Adapter, REG_SPS0_CTRL);
 782
 783         switch (eRFPowerState) {
 784         case rf_on:
 785                 /*  1. Enable MAC Clock. Can not be enabled now. */
 786                 /* WriteXBYTE(REG_SYS_CLKR+1,
 787                    ReadXBYTE(REG_SYS_CLKR+1) | BIT(3)); */
 788
 789                 /*  2. Force PWM, Enable SPS18_LDO_Marco_Block */
 790                 rtl8723au_write8(Adapter, REG_SPS0_CTRL,
 791                                  sps0 | BIT(0) | BIT(3));
 792
 793                 /*  3. restore BB, AFE control register. */
 794                 /* RF */
 795                 if (pHalData->rf_type ==  RF_2T2R)
 796                         PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter,
 797                                      0x380038, 1);
 798                 else
 799                         PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter,
 800                                      0x38, 1);
 801                 PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 1);
 802                 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT(1), 0);
 803
 804                 /* AFE */
 805                 if (pHalData->rf_type ==  RF_2T2R)
 806                         PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord,
 807                                      0x63DB25A0);
 808                 else if (pHalData->rf_type ==  RF_1T1R)
 809                         PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord,
 810                                      0x631B25A0);
 811
 812                 /*  4. issue 3-wire command that RF set to Rx idle
 813                     mode. This is used to re-write the RX idle mode. */
 814                 /*  We can only prvide a usual value instead and then
 815                     HW will modify the value by itself. */
 816                 PHY_SetRFReg(Adapter, RF_PATH_A, 0, bRFRegOffsetMask, 0x32D95);
 817                 if (pHalData->rf_type ==  RF_2T2R) {
 818                         PHY_SetRFReg(Adapter, RF_PATH_B, 0,
 819                                      bRFRegOffsetMask, 0x32D95);
 820                 }
 821                 break;
 822         case rf_sleep:
 823         case rf_off:
 824                 if (IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID))
 825                         sps0 &= ~BIT(0);
 826                 else
 827                         sps0 &= ~(BIT(0) | BIT(3));
 828
 829                 RT_TRACE(_module_hal_init_c_, _drv_err_, ("SS LVL1\n"));
 830                 /*  Disable RF and BB only for SelectSuspend. */
 831
 832                 /*  1. Set BB/RF to shutdown. */
 833                 /*      (1) Reg878[5:3]= 0      RF rx_code for
 834                                                 preamble power saving */
 835                 /*      (2)Reg878[21:19]= 0     Turn off RF-B */
 836                 /*      (3) RegC04[7:4]= 0      Turn off all paths
 837                                                 for packet detection */
 838                 /*      (4) Reg800[1] = 1       enable preamble power saving */
 839                 Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF0] =
 840                         PHY_QueryBBReg(Adapter, rFPGA0_XAB_RFParameter,
 841                                        bMaskDWord);
 842                 Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF1] =
 843                         PHY_QueryBBReg(Adapter, rOFDM0_TRxPathEnable,
 844                                        bMaskDWord);
 845                 Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF2] =
 846                         PHY_QueryBBReg(Adapter, rFPGA0_RFMOD, bMaskDWord);
 847                 if (pHalData->rf_type ==  RF_2T2R) {
 848                         PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter,
 849                                      0x380038, 0);
 850                 } else if (pHalData->rf_type ==  RF_1T1R) {
 851                         PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x38, 0);
 852                 }
 853                 PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 0);
 854                 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT(1), 1);
 855
 856                 /*  2 .AFE control register to power down. bit[30:22] */
 857                 Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_AFE0] =
 858                         PHY_QueryBBReg(Adapter, rRx_Wait_CCA, bMaskDWord);
 859                 if (pHalData->rf_type ==  RF_2T2R)
 860                         PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord,
 861                                      0x00DB25A0);
 862                 else if (pHalData->rf_type ==  RF_1T1R)
 863                         PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord,
 864                                      0x001B25A0);
 865
 866                 /*  3. issue 3-wire command that RF set to power down.*/
 867                 PHY_SetRFReg(Adapter, RF_PATH_A, 0, bRFRegOffsetMask, 0);
 868                 if (pHalData->rf_type ==  RF_2T2R)
 869                         PHY_SetRFReg(Adapter, RF_PATH_B, 0,
 870                                      bRFRegOffsetMask, 0);
 871
 872                 /*  4. Force PFM , disable SPS18_LDO_Marco_Block */
 873                 rtl8723au_write8(Adapter, REG_SPS0_CTRL, sps0);
 874                 break;
 875         default:
 876                 break;
 877         }
 878 }
 879
 880 static void CardDisableRTL8723U(struct rtw_adapter *Adapter)
 881 {
 882         u8              u1bTmp;
 883
 884         DBG_8723A("CardDisableRTL8723U\n");
 885         /*  USB-MF Card Disable Flow */
 886         /*  1. Run LPS WL RFOFF flow */
 887         HalPwrSeqCmdParsing23a(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
 888                             PWR_INTF_USB_MSK, rtl8723AU_enter_lps_flow);
 889
 890         /*  2. 0x1F[7:0] = 0            turn off RF */
 891         rtl8723au_write8(Adapter, REG_RF_CTRL, 0x00);
 892
 893         /*      ==== Reset digital sequence   ====== */
 894         if ((rtl8723au_read8(Adapter, REG_MCUFWDL) & BIT(7)) &&
 895             Adapter->bFWReady) /* 8051 RAM code */
 896                 rtl8723a_FirmwareSelfReset(Adapter);
 897
 898         /*  Reset MCU. Suggested by Filen. 2011.01.26. by tynli. */
 899         u1bTmp = rtl8723au_read8(Adapter, REG_SYS_FUNC_EN+1);
 900         rtl8723au_write8(Adapter, REG_SYS_FUNC_EN+1, u1bTmp & ~BIT(2));
 901
 902         /*  g.  MCUFWDL 0x80[1:0]= 0            reset MCU ready status */
 903         rtl8723au_write8(Adapter, REG_MCUFWDL, 0x00);
 904
 905         /*      ==== Reset digital sequence end ====== */
 906         /*  Card disable power action flow */
 907         HalPwrSeqCmdParsing23a(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
 908                                PWR_INTF_USB_MSK,
 909                                rtl8723AU_card_disable_flow);
 910
 911         /*  Reset MCU IO Wrapper, added by Roger, 2011.08.30. */
 912         u1bTmp = rtl8723au_read8(Adapter, REG_RSV_CTRL + 1);
 913         rtl8723au_write8(Adapter, REG_RSV_CTRL+1, u1bTmp & ~BIT(0));
 914         u1bTmp = rtl8723au_read8(Adapter, REG_RSV_CTRL + 1);
 915         rtl8723au_write8(Adapter, REG_RSV_CTRL+1, u1bTmp | BIT(0));
 916
 917         /*  7. RSV_CTRL 0x1C[7:0] = 0x0E  lock ISO/CLK/Power control register */
 918         rtl8723au_write8(Adapter, REG_RSV_CTRL, 0x0e);
 919 }
 920
 921 int rtl8723au_hal_deinit(struct rtw_adapter *padapter)
 922 {
 923         DBG_8723A("==> %s\n", __func__);
 924
 925 #ifdef CONFIG_8723AU_BT_COEXIST
 926         BT_HaltProcess(padapter);
 927 #endif
 928         /*  2011/02/18 To Fix RU LNA  power leakage problem. We need to
 929             execute below below in Adapter init and halt sequence.
 930             According to EEchou's opinion, we can enable the ability for all */
 931         /*  IC. Accord to johnny's opinion, only RU need the support. */
 932         CardDisableRTL8723U(padapter);
 933
 934         padapter->hw_init_completed = false;
 935
 936         return _SUCCESS;
 937 }
 938
 939 int rtl8723au_inirp_init(struct rtw_adapter *Adapter)
 940 {
 941         u8 i;
 942         struct recv_buf *precvbuf;
 943         int status;
 944         struct recv_priv *precvpriv = &Adapter->recvpriv;
 945         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
 946
 947         status = _SUCCESS;
 948
 949         RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("===> usb_inirp_init\n"));
 950
 951         /* issue Rx irp to receive data */
 952         precvbuf = (struct recv_buf *)precvpriv->precv_buf;
 953         for (i = 0; i < NR_RECVBUFF; i++) {
 954                 if (rtl8723au_read_port(Adapter, RECV_BULK_IN_ADDR, 0,
 955                                         precvbuf) == _FAIL) {
 956                         RT_TRACE(_module_hci_hal_init_c_, _drv_err_,
 957                                  ("usb_rx_init: usb_read_port error\n"));
 958                         status = _FAIL;
 959                         goto exit;
 960                 }
 961                 precvbuf++;
 962         }
 963         if (rtl8723au_read_interrupt(Adapter, RECV_INT_IN_ADDR) == _FAIL) {
 964                 RT_TRACE(_module_hci_hal_init_c_, _drv_err_,
 965                          ("usb_rx_init: usb_read_interrupt error\n"));
 966                 status = _FAIL;
 967         }
 968         pHalData->IntrMask[0] = rtl8723au_read32(Adapter, REG_USB_HIMR);
 969         MSG_8723A("pHalData->IntrMask = 0x%04x\n", pHalData->IntrMask[0]);
 970         pHalData->IntrMask[0] |= UHIMR_C2HCMD|UHIMR_CPWM;
 971         rtl8723au_write32(Adapter, REG_USB_HIMR, pHalData->IntrMask[0]);
 972 exit:
 973         RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
 974                  ("<=== usb_inirp_init\n"));
 975         return status;
 976 }
 977
 978 int rtl8723au_inirp_deinit(struct rtw_adapter *Adapter)
 979 {
 980         struct hal_data_8723a   *pHalData = GET_HAL_DATA(Adapter);
 981
 982         RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
 983                  ("\n ===> usb_rx_deinit\n"));
 984         rtl8723au_read_port_cancel(Adapter);
 985         pHalData->IntrMask[0] = rtl8723au_read32(Adapter, REG_USB_HIMR);
 986         MSG_8723A("%s pHalData->IntrMask = 0x%04x\n", __func__,
 987                   pHalData->IntrMask[0]);
 988         pHalData->IntrMask[0] = 0x0;
 989         rtl8723au_write32(Adapter, REG_USB_HIMR, pHalData->IntrMask[0]);
 990         RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
 991                  ("\n <=== usb_rx_deinit\n"));
 992         return _SUCCESS;
 993 }
 994
 995 static void _ReadBoardType(struct rtw_adapter *Adapter, u8 *PROMContent,
 996                            bool AutoloadFail)
 997 {
 998         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
 999         u8 boardType = BOARD_USB_DONGLE;
1000
1001         if (AutoloadFail) {
1002                 if (IS_8723_SERIES(pHalData->VersionID))
1003                         pHalData->rf_type = RF_1T1R;
1004                 else
1005                         pHalData->rf_type = RF_2T2R;
1006                 pHalData->BoardType = boardType;
1007                 return;
1008         }
1009
1010         boardType = PROMContent[EEPROM_NORMAL_BoardType];
1011         boardType &= BOARD_TYPE_NORMAL_MASK;/* bit[7:5] */
1012         boardType >>= 5;
1013
1014         pHalData->BoardType = boardType;
1015         MSG_8723A("_ReadBoardType(%x)\n", pHalData->BoardType);
1016
1017         if (boardType == BOARD_USB_High_PA)
1018                 pHalData->ExternalPA = 1;
1019 }
1020
1021 static void Hal_EfuseParseMACAddr_8723AU(struct rtw_adapter *padapter,
1022                                          u8 *hwinfo, bool AutoLoadFail)
1023 {
1024         u16 i;
1025         u8 sMacAddr[ETH_ALEN] = {0x00, 0xE0, 0x4C, 0x87, 0x23, 0x00};
1026         struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1027
1028         if (AutoLoadFail) {
1029                 for (i = 0; i < 6; i++)
1030                         pEEPROM->mac_addr[i] = sMacAddr[i];
1031         } else {
1032                 /* Read Permanent MAC address */
1033                 memcpy(pEEPROM->mac_addr, &hwinfo[EEPROM_MAC_ADDR_8723AU],
1034                        ETH_ALEN);
1035         }
1036
1037         RT_TRACE(_module_hci_hal_init_c_, _drv_notice_,
1038                  ("Hal_EfuseParseMACAddr_8723AU: Permanent Address =%02x:%02x:"
1039                   "%02x:%02x:%02x:%02x\n",
1040                   pEEPROM->mac_addr[0], pEEPROM->mac_addr[1],
1041                   pEEPROM->mac_addr[2], pEEPROM->mac_addr[3],
1042                   pEEPROM->mac_addr[4], pEEPROM->mac_addr[5]));
1043 }
1044
1045 static void readAdapterInfo(struct rtw_adapter *padapter)
1046 {
1047         struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1048         /* struct hal_data_8723a * pHalData = GET_HAL_DATA(padapter); */
1049         u8 hwinfo[HWSET_MAX_SIZE];
1050
1051         Hal_InitPGData(padapter, hwinfo);
1052         Hal_EfuseParseIDCode(padapter, hwinfo);
1053         Hal_EfuseParseEEPROMVer(padapter, hwinfo,
1054                                 pEEPROM->bautoload_fail_flag);
1055         Hal_EfuseParseMACAddr_8723AU(padapter, hwinfo,
1056                                      pEEPROM->bautoload_fail_flag);
1057         Hal_EfuseParsetxpowerinfo_8723A(padapter, hwinfo,
1058                                         pEEPROM->bautoload_fail_flag);
1059         _ReadBoardType(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1060         Hal_EfuseParseBTCoexistInfo_8723A(padapter, hwinfo,
1061                                           pEEPROM->bautoload_fail_flag);
1062
1063         rtl8723a_EfuseParseChnlPlan(padapter, hwinfo,
1064                                     pEEPROM->bautoload_fail_flag);
1065         Hal_EfuseParseThermalMeter_8723A(padapter, hwinfo,
1066                                          pEEPROM->bautoload_fail_flag);
1067 /*      _ReadRFSetting(Adapter, PROMContent, pEEPROM->bautoload_fail_flag); */
1068 /*      _ReadPSSetting(Adapter, PROMContent, pEEPROM->bautoload_fail_flag); */
1069         Hal_EfuseParseAntennaDiversity(padapter, hwinfo,
1070                                        pEEPROM->bautoload_fail_flag);
1071
1072         Hal_EfuseParseEEPROMVer(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1073         Hal_EfuseParseCustomerID(padapter, hwinfo,
1074                                  pEEPROM->bautoload_fail_flag);
1075         Hal_EfuseParseRateIndicationOption(padapter, hwinfo,
1076                                            pEEPROM->bautoload_fail_flag);
1077         Hal_EfuseParseXtal_8723A(padapter, hwinfo,
1078                                  pEEPROM->bautoload_fail_flag);
1079
1080         /* hal_CustomizedBehavior_8723U(Adapter); */
1081
1082 /*      Adapter->bDongle = (PROMContent[EEPROM_EASY_REPLACEMENT] == 1)? 0: 1; */
1083         DBG_8723A("%s(): REPLACEMENT = %x\n", __func__, padapter->bDongle);
1084 }
1085
1086 static void _ReadPROMContent(struct rtw_adapter *Adapter)
1087 {
1088         struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter);
1089         u8 eeValue;
1090
1091         eeValue = rtl8723au_read8(Adapter, REG_9346CR);
1092         /*  To check system boot selection. */
1093         pEEPROM->EepromOrEfuse = (eeValue & BOOT_FROM_EEPROM) ? true : false;
1094         pEEPROM->bautoload_fail_flag = (eeValue & EEPROM_EN) ? false : true;
1095
1096         DBG_8723A("Boot from %s, Autoload %s !\n",
1097                   (pEEPROM->EepromOrEfuse ? "EEPROM" : "EFUSE"),
1098                   (pEEPROM->bautoload_fail_flag ? "Fail" : "OK"));
1099
1100         readAdapterInfo(Adapter);
1101 }
1102
1103 static void _ReadRFType(struct rtw_adapter *Adapter)
1104 {
1105         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1106
1107         pHalData->rf_chip = RF_6052;
1108 }
1109
1110 static void _ReadSilmComboMode(struct rtw_adapter *Adapter)
1111 {
1112         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1113
1114         pHalData->SlimComboDbg = false; /*  Default is not debug mode. */
1115 }
1116
1117 /*  */
1118 /*      Description: */
1119 /*              We should set Efuse cell selection to WiFi cell in default. */
1120 /*  */
1121 /*      Assumption: */
1122 /*              PASSIVE_LEVEL */
1123 /*  */
1124 /*      Added by Roger, 2010.11.23. */
1125 /*  */
1126 static void hal_EfuseCellSel(struct rtw_adapter *Adapter)
1127 {
1128         u32 value32;
1129
1130         value32 = rtl8723au_read32(Adapter, EFUSE_TEST);
1131         value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
1132         rtl8723au_write32(Adapter, EFUSE_TEST, value32);
1133 }
1134
1135 void rtl8723a_read_adapter_info(struct rtw_adapter *Adapter)
1136 {
1137         unsigned long start = jiffies;
1138
1139         /*  Read EEPROM size before call any EEPROM function */
1140         Adapter->EepromAddressSize = GetEEPROMSize8723A(Adapter);
1141
1142         MSG_8723A("====> _ReadAdapterInfo8723AU\n");
1143
1144         hal_EfuseCellSel(Adapter);
1145
1146         _ReadRFType(Adapter);/* rf_chip -> _InitRFType() */
1147         _ReadPROMContent(Adapter);
1148
1149         /*  2010/10/25 MH THe function must be called after
1150             borad_type & IC-Version recognize. */
1151         _ReadSilmComboMode(Adapter);
1152
1153         /* MSG_8723A("%s()(done), rf_chip = 0x%x, rf_type = 0x%x\n",
1154            __func__, pHalData->rf_chip, pHalData->rf_type); */
1155
1156         MSG_8723A("<==== _ReadAdapterInfo8723AU in %d ms\n",
1157                   jiffies_to_msecs(jiffies - start));
1158 }
1159
1160 /*  */
1161 /*      Description: */
1162 /*              Query setting of specified variable. */
1163 /*  */
1164 int GetHalDefVar8192CUsb(struct rtw_adapter *Adapter,
1165                          enum hal_def_variable eVariable, void *pValue)
1166 {
1167         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1168         int bResult = _SUCCESS;
1169
1170         switch (eVariable) {
1171         case HAL_DEF_UNDERCORATEDSMOOTHEDPWDB:
1172                 *((int *)pValue) = pHalData->dmpriv.UndecoratedSmoothedPWDB;
1173                 break;
1174         case HAL_DEF_IS_SUPPORT_ANT_DIV:
1175                 break;
1176         case HAL_DEF_CURRENT_ANTENNA:
1177                 break;
1178         case HAL_DEF_DRVINFO_SZ:
1179                 *((u32 *)pValue) = DRVINFO_SZ;
1180                 break;
1181         case HAL_DEF_MAX_RECVBUF_SZ:
1182                 *((u32 *)pValue) = MAX_RECVBUF_SZ;
1183                 break;
1184         case HAL_DEF_RX_PACKET_OFFSET:
1185                 *((u32 *)pValue) = RXDESC_SIZE + DRVINFO_SZ;
1186                 break;
1187         case HAL_DEF_DBG_DUMP_RXPKT:
1188                 *((u8 *)pValue) = pHalData->bDumpRxPkt;
1189                 break;
1190         case HAL_DEF_DBG_DM_FUNC:
1191                 *((u32 *)pValue) = pHalData->odmpriv.SupportAbility;
1192                 break;
1193         case HW_VAR_MAX_RX_AMPDU_FACTOR:
1194                 *((u32 *)pValue) = IEEE80211_HT_MAX_AMPDU_64K;
1195                 break;
1196         case HW_DEF_ODM_DBG_FLAG:
1197         {
1198                 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
1199                 printk("pDM_Odm->DebugComponents = 0x%llx\n",
1200                        pDM_Odm->DebugComponents);
1201         }
1202                 break;
1203         default:
1204                 /* RT_TRACE(COMP_INIT, DBG_WARNING, ("GetHalDefVar8192CUsb(): "
1205                    "Unkown variable: %d!\n", eVariable)); */
1206                 bResult = _FAIL;
1207                 break;
1208         }
1209
1210         return bResult;
1211 }
1212
1213 void rtl8723a_update_ramask(struct rtw_adapter *padapter,
1214                             u32 mac_id, u8 rssi_level)
1215 {
1216         u8      init_rate = 0;
1217         u8      networkType, raid;
1218         u32     mask, rate_bitmap;
1219         u8      shortGIrate = false;
1220         int     supportRateNum = 0;
1221         struct sta_info *psta;
1222         struct hal_data_8723a   *pHalData = GET_HAL_DATA(padapter);
1223         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
1224         struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
1225         struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
1226         struct wlan_bssid_ex *cur_network = &pmlmeinfo->network;
1227
1228         if (mac_id >= NUM_STA) /* CAM_SIZE */
1229                 return;
1230
1231         psta = pmlmeinfo->FW_sta_info[mac_id].psta;
1232         if (psta == NULL)
1233                 return;
1234
1235         switch (mac_id) {
1236         case 0:/*  for infra mode */
1237                 supportRateNum =
1238                         rtw_get_rateset_len23a(cur_network->SupportedRates);
1239                 networkType = judge_network_type23a(padapter,
1240                                                  cur_network->SupportedRates,
1241                                                  supportRateNum) & 0xf;
1242                 /* pmlmeext->cur_wireless_mode = networkType; */
1243                 raid = networktype_to_raid23a(networkType);
1244
1245                 mask = update_supported_rate23a(cur_network->SupportedRates,
1246                                              supportRateNum);
1247                 mask |= (pmlmeinfo->HT_enable) ?
1248                         update_MSC_rate23a(&pmlmeinfo->ht_cap) : 0;
1249
1250                 if (support_short_GI23a(padapter, &pmlmeinfo->ht_cap))
1251                         shortGIrate = true;
1252                 break;
1253
1254         case 1:/* for broadcast/multicast */
1255                 supportRateNum = rtw_get_rateset_len23a(
1256                         pmlmeinfo->FW_sta_info[mac_id].SupportedRates);
1257                 if (pmlmeext->cur_wireless_mode & WIRELESS_11B)
1258                         networkType = WIRELESS_11B;
1259                 else
1260                         networkType = WIRELESS_11G;
1261                 raid = networktype_to_raid23a(networkType);
1262
1263                 mask = update_basic_rate23a(cur_network->SupportedRates,
1264                                          supportRateNum);
1265                 break;
1266
1267         default: /* for each sta in IBSS */
1268                 supportRateNum = rtw_get_rateset_len23a(
1269                         pmlmeinfo->FW_sta_info[mac_id].SupportedRates);
1270                 networkType = judge_network_type23a(padapter,
1271                                                  pmlmeinfo->FW_sta_info[mac_id].SupportedRates,
1272                                                  supportRateNum) & 0xf;
1273                 /* pmlmeext->cur_wireless_mode = networkType; */
1274                 raid = networktype_to_raid23a(networkType);
1275
1276                 mask = update_supported_rate23a(cur_network->SupportedRates,
1277                                              supportRateNum);
1278
1279                 /* todo: support HT in IBSS */
1280                 break;
1281         }
1282
1283         /* mask &= 0x0fffffff; */
1284         rate_bitmap = ODM_Get_Rate_Bitmap23a(pHalData, mac_id, mask,
1285                                              rssi_level);
1286         DBG_8723A("%s => mac_id:%d, networkType:0x%02x, "
1287                   "mask:0x%08x\n\t ==> rssi_level:%d, rate_bitmap:0x%08x\n",
1288                   __func__, mac_id, networkType, mask, rssi_level, rate_bitmap);
1289
1290         mask &= rate_bitmap;
1291         mask |= ((raid<<28)&0xf0000000);
1292
1293         init_rate = get_highest_rate_idx23a(mask)&0x3f;
1294
1295         if (pHalData->fw_ractrl == true) {
1296                 u8 arg = 0;
1297
1298                 /* arg = (cam_idx-4)&0x1f;MACID */
1299                 arg = mac_id&0x1f;/* MACID */
1300
1301                 arg |= BIT(7);
1302
1303                 if (shortGIrate == true)
1304                         arg |= BIT(5);
1305
1306                 DBG_8723A("update raid entry, mask = 0x%x, arg = 0x%x\n",
1307                           mask, arg);
1308
1309                 rtl8723a_set_raid_cmd(padapter, mask, arg);
1310         } else {
1311                 if (shortGIrate == true)
1312                         init_rate |= BIT(6);
1313
1314                 rtl8723au_write8(padapter, (REG_INIDATA_RATE_SEL+mac_id),
1315                                  init_rate);
1316         }
1317
1318         /* set ra_id */
1319         psta->raid = raid;
1320         psta->init_rate = init_rate;
1321
1322         /* set correct initial date rate for each mac_id */
1323         pdmpriv->INIDATA_RATE[mac_id] = init_rate;
1324 }