drivers/staging/rtl8723au/hal/usb_halinit.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  ******************************************************************************/
  15 #define _HCI_HAL_INIT_C_
  16
  17 #include <osdep_service.h>
  18 #include <drv_types.h>
  19 #include <rtw_efuse.h>
  20
  21 #include <HalPwrSeqCmd.h>
  22 #include <Hal8723PwrSeq.h>
  23 #include <rtl8723a_hal.h>
  24 #include <rtl8723a_led.h>
  25 #include <linux/ieee80211.h>
  26
  27 #include <usb_ops.h>
  28 #include <usb_hal.h>
  29 #include <usb_osintf.h>
  30
  31 static void
  32 _ConfigChipOutEP(struct rtw_adapter *pAdapter, u8 NumOutPipe)
  33 {
  34         u8 value8;
  35         struct hal_data_8723a *pHalData = GET_HAL_DATA(pAdapter);
  36
  37         pHalData->OutEpQueueSel = 0;
  38         pHalData->OutEpNumber = 0;
  39
  40         /*  Normal and High queue */
  41         value8 = rtw_read8(pAdapter, (REG_NORMAL_SIE_EP + 1));
  42
  43         if (value8 & USB_NORMAL_SIE_EP_MASK) {
  44                 pHalData->OutEpQueueSel |= TX_SELE_HQ;
  45                 pHalData->OutEpNumber++;
  46         }
  47
  48         if ((value8 >> USB_NORMAL_SIE_EP_SHIFT) & USB_NORMAL_SIE_EP_MASK) {
  49                 pHalData->OutEpQueueSel |= TX_SELE_NQ;
  50                 pHalData->OutEpNumber++;
  51         }
  52
  53         /*  Low queue */
  54         value8 = rtw_read8(pAdapter, (REG_NORMAL_SIE_EP + 2));
  55         if (value8 & USB_NORMAL_SIE_EP_MASK) {
  56                 pHalData->OutEpQueueSel |= TX_SELE_LQ;
  57                 pHalData->OutEpNumber++;
  58         }
  59
  60         /*  TODO: Error recovery for this case */
  61         /* RT_ASSERT((NumOutPipe == pHalData->OutEpNumber),
  62            ("Out EP number isn't match! %d(Descriptor) != %d (SIE reg)\n",
  63            (u32)NumOutPipe, (u32)pHalData->OutEpNumber)); */
  64 }
  65
  66 static bool rtl8723au_set_queue_pipe_mapping(struct rtw_adapter *pAdapter,
  67                                              u8 NumInPipe, u8 NumOutPipe)
  68 {
  69         struct hal_data_8723a *pHalData = GET_HAL_DATA(pAdapter);
  70         bool result = false;
  71
  72         _ConfigChipOutEP(pAdapter, NumOutPipe);
  73
  74         /*  Normal chip with one IN and one OUT doesn't have interrupt IN EP. */
  75         if (pHalData->OutEpNumber == 1) {
  76                 if (NumInPipe != 1)
  77                         return result;
  78         }
  79
  80         result = Hal_MappingOutPipe23a(pAdapter, NumOutPipe);
  81
  82         return result;
  83 }
  84
  85 static void rtl8723au_interface_configure(struct rtw_adapter *padapter)
  86 {
  87         struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
  88         struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
  89
  90         if (pdvobjpriv->ishighspeed == true) {
  91                 /* 512 bytes */
  92                 pHalData->UsbBulkOutSize = USB_HIGH_SPEED_BULK_SIZE;
  93         } else {
  94                 /* 64 bytes */
  95                 pHalData->UsbBulkOutSize = USB_FULL_SPEED_BULK_SIZE;
  96         }
  97
  98         pHalData->interfaceIndex = pdvobjpriv->InterfaceNumber;
  99
 100         rtl8723au_set_queue_pipe_mapping(padapter,
 101                                          pdvobjpriv->RtNumInPipes,
 102                                          pdvobjpriv->RtNumOutPipes);
 103 }
 104
 105 static u8 _InitPowerOn(struct rtw_adapter *padapter)
 106 {
 107         u8 status = _SUCCESS;
 108         u16 value16 = 0;
 109         u8 value8 = 0;
 110
 111         /*  RSV_CTRL 0x1C[7:0] = 0x00
 112             unlock ISO/CLK/Power control register */
 113         rtw_write8(padapter, REG_RSV_CTRL, 0x0);
 114
 115         /*  HW Power on sequence */
 116         if (!HalPwrSeqCmdParsing23a(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
 117                                  PWR_INTF_USB_MSK, rtl8723AU_card_enable_flow))
 118                 return _FAIL;
 119
 120         /*  0x04[19] = 1, suggest by Jackie 2011.05.09, reset 8051 */
 121         value8 = rtw_read8(padapter, REG_APS_FSMCO+2);
 122         rtw_write8(padapter, REG_APS_FSMCO + 2, (value8 | BIT3));
 123
 124         /*  Enable MAC DMA/WMAC/SCHEDULE/SEC block */
 125         /*  Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy.
 126             Added by tynli. 2011.08.31. */
 127         value16 = rtw_read16(padapter, REG_CR);
 128         value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN |
 129                     PROTOCOL_EN | SCHEDULE_EN | MACTXEN | MACRXEN |
 130                     ENSEC | CALTMR_EN);
 131         rtw_write16(padapter, REG_CR, value16);
 132
 133         /* for Efuse PG, suggest by Jackie 2011.11.23 */
 134         PHY_SetBBReg(padapter, REG_EFUSE_CTRL, BIT28|BIT29|BIT30, 0x06);
 135
 136         return status;
 137 }
 138
 139 /*  Shall USB interface init this? */
 140 static void _InitInterrupt(struct rtw_adapter *Adapter)
 141 {
 142         u32 value32;
 143
 144         /*  HISR - turn all on */
 145         value32 = 0xFFFFFFFF;
 146         rtw_write32(Adapter, REG_HISR, value32);
 147
 148         /*  HIMR - turn all on */
 149         rtw_write32(Adapter, REG_HIMR, value32);
 150 }
 151
 152 static void _InitQueueReservedPage(struct rtw_adapter *Adapter)
 153 {
 154         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
 155         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 156         u32 numHQ = 0;
 157         u32 numLQ = 0;
 158         u32 numNQ = 0;
 159         u32 numPubQ;
 160         u32 value32;
 161         u8 value8;
 162         bool bWiFiConfig = pregistrypriv->wifi_spec;
 163         /* u32                  txQPageNum, txQPageUnit, txQRemainPage; */
 164
 165         { /* for WMM */
 166                 /* RT_ASSERT((outEPNum>= 2), ("for WMM , number of out-ep "
 167                    "must more than or equal to 2!\n")); */
 168
 169                 numPubQ = bWiFiConfig ?
 170                         WMM_NORMAL_PAGE_NUM_PUBQ : NORMAL_PAGE_NUM_PUBQ;
 171
 172                 if (pHalData->OutEpQueueSel & TX_SELE_HQ) {
 173                         numHQ = bWiFiConfig ?
 174                                 WMM_NORMAL_PAGE_NUM_HPQ : NORMAL_PAGE_NUM_HPQ;
 175                 }
 176
 177                 if (pHalData->OutEpQueueSel & TX_SELE_LQ) {
 178                         numLQ = bWiFiConfig ?
 179                                 WMM_NORMAL_PAGE_NUM_LPQ : NORMAL_PAGE_NUM_LPQ;
 180                 }
 181                 /*  NOTE: This step shall be proceed before
 182                     writting REG_RQPN. */
 183                 if (pHalData->OutEpQueueSel & TX_SELE_NQ) {
 184                         numNQ = bWiFiConfig ?
 185                                 WMM_NORMAL_PAGE_NUM_NPQ : NORMAL_PAGE_NUM_NPQ;
 186                 }
 187                 value8 = (u8)_NPQ(numNQ);
 188                 rtw_write8(Adapter, REG_RQPN_NPQ, value8);
 189         }
 190
 191         /*  TX DMA */
 192         value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
 193         rtw_write32(Adapter, REG_RQPN, value32);
 194 }
 195
 196 static void _InitTxBufferBoundary(struct rtw_adapter *Adapter)
 197 {
 198         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 199
 200         u8 txpktbuf_bndy;
 201
 202         if (!pregistrypriv->wifi_spec)
 203                 txpktbuf_bndy = TX_PAGE_BOUNDARY;
 204         else /* for WMM */
 205                 txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY;
 206
 207         rtw_write8(Adapter, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 208         rtw_write8(Adapter, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 209         rtw_write8(Adapter, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy);
 210         rtw_write8(Adapter, REG_TRXFF_BNDY, txpktbuf_bndy);
 211         rtw_write8(Adapter, REG_TDECTRL+1, txpktbuf_bndy);
 212 }
 213
 214 static void _InitPageBoundary(struct rtw_adapter *Adapter)
 215 {
 216         /*  RX Page Boundary */
 217         /* srand(static_cast<unsigned int>(time(NULL))); */
 218         u16 rxff_bndy = 0x27FF;/* rand() % 1) ? 0x27FF : 0x23FF; */
 219
 220         rtw_write16(Adapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
 221
 222         /*  TODO: ?? shall we set tx boundary? */
 223 }
 224
 225 static void
 226 _InitNormalChipRegPriority(struct rtw_adapter *Adapter, u16 beQ, u16 bkQ,
 227                            u16 viQ, u16 voQ, u16 mgtQ, u16 hiQ)
 228 {
 229         u16 value16 = rtw_read16(Adapter, REG_TRXDMA_CTRL) & 0x7;
 230
 231         value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) |
 232                 _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) |
 233                 _TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ);
 234
 235         rtw_write16(Adapter, REG_TRXDMA_CTRL, value16);
 236 }
 237
 238 static void _InitNormalChipOneOutEpPriority(struct rtw_adapter *Adapter)
 239 {
 240         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
 241         u16 value = 0;
 242
 243         switch (pHalData->OutEpQueueSel) {
 244         case TX_SELE_HQ:
 245                 value = QUEUE_HIGH;
 246                 break;
 247         case TX_SELE_LQ:
 248                 value = QUEUE_LOW;
 249                 break;
 250         case TX_SELE_NQ:
 251                 value = QUEUE_NORMAL;
 252                 break;
 253         default:
 254                 /* RT_ASSERT(false, ("Shall not reach here!\n")); */
 255                 break;
 256         }
 257
 258         _InitNormalChipRegPriority(Adapter, value, value, value,
 259                                    value, value, value);
 260 }
 261
 262 static void _InitNormalChipTwoOutEpPriority(struct rtw_adapter *Adapter)
 263 {
 264         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
 265         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 266         u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
 267         u16 valueHi = 0;
 268         u16 valueLow = 0;
 269
 270         switch (pHalData->OutEpQueueSel) {
 271         case (TX_SELE_HQ | TX_SELE_LQ):
 272                 valueHi = QUEUE_HIGH;
 273                 valueLow = QUEUE_LOW;
 274                 break;
 275         case (TX_SELE_NQ | TX_SELE_LQ):
 276                 valueHi = QUEUE_NORMAL;
 277                 valueLow = QUEUE_LOW;
 278                 break;
 279         case (TX_SELE_HQ | TX_SELE_NQ):
 280                 valueHi = QUEUE_HIGH;
 281                 valueLow = QUEUE_NORMAL;
 282                 break;
 283         default:
 284                 /* RT_ASSERT(false, ("Shall not reach here!\n")); */
 285                 break;
 286         }
 287
 288         if (!pregistrypriv->wifi_spec) {
 289                 beQ = valueLow;
 290                 bkQ = valueLow;
 291                 viQ = valueHi;
 292                 voQ = valueHi;
 293                 mgtQ = valueHi;
 294                 hiQ = valueHi;
 295         } else {/* for WMM , CONFIG_OUT_EP_WIFI_MODE */
 296                 beQ = valueLow;
 297                 bkQ = valueHi;
 298                 viQ = valueHi;
 299                 voQ = valueLow;
 300                 mgtQ = valueHi;
 301                 hiQ = valueHi;
 302         }
 303
 304         _InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
 305 }
 306
 307 static void _InitNormalChipThreeOutEpPriority(struct rtw_adapter *Adapter)
 308 {
 309         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 310         u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
 311
 312         if (!pregistrypriv->wifi_spec) {/*  typical setting */
 313                 beQ = QUEUE_LOW;
 314                 bkQ = QUEUE_LOW;
 315                 viQ = QUEUE_NORMAL;
 316                 voQ = QUEUE_HIGH;
 317                 mgtQ = QUEUE_HIGH;
 318                 hiQ = QUEUE_HIGH;
 319         } else {/*  for WMM */
 320                 beQ = QUEUE_LOW;
 321                 bkQ = QUEUE_NORMAL;
 322                 viQ = QUEUE_NORMAL;
 323                 voQ = QUEUE_HIGH;
 324                 mgtQ = QUEUE_HIGH;
 325                 hiQ = QUEUE_HIGH;
 326         }
 327         _InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
 328 }
 329
 330 static void _InitNormalChipQueuePriority(struct rtw_adapter *Adapter)
 331 {
 332         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
 333
 334         switch (pHalData->OutEpNumber) {
 335         case 1:
 336                 _InitNormalChipOneOutEpPriority(Adapter);
 337                 break;
 338         case 2:
 339                 _InitNormalChipTwoOutEpPriority(Adapter);
 340                 break;
 341         case 3:
 342                 _InitNormalChipThreeOutEpPriority(Adapter);
 343                 break;
 344         default:
 345                 /* RT_ASSERT(false, ("Shall not reach here!\n")); */
 346                 break;
 347         }
 348 }
 349
 350 static void _InitQueuePriority(struct rtw_adapter *Adapter)
 351 {
 352         _InitNormalChipQueuePriority(Adapter);
 353 }
 354
 355 static void _InitNetworkType(struct rtw_adapter *Adapter)
 356 {
 357         u32 value32;
 358
 359         value32 = rtw_read32(Adapter, REG_CR);
 360
 361         /*  TODO: use the other function to set network type */
 362         value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP);
 363         rtw_write32(Adapter, REG_CR, value32);
 364 }
 365
 366 static void _InitTransferPageSize(struct rtw_adapter *Adapter)
 367 {
 368         /*  Tx page size is always 128. */
 369
 370         u8 value8;
 371         value8 = _PSRX(PBP_128) | _PSTX(PBP_128);
 372         rtw_write8(Adapter, REG_PBP, value8);
 373 }
 374
 375 static void _InitDriverInfoSize(struct rtw_adapter *Adapter, u8 drvInfoSize)
 376 {
 377         rtw_write8(Adapter, REG_RX_DRVINFO_SZ, drvInfoSize);
 378 }
 379
 380 static void _InitWMACSetting(struct rtw_adapter *Adapter)
 381 {
 382         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
 383
 384         /*  don't turn on AAP, it will allow all packets to driver */
 385         pHalData->ReceiveConfig = RCR_APM | RCR_AM | RCR_AB | RCR_CBSSID_DATA |
 386                                   RCR_CBSSID_BCN | RCR_APP_ICV | RCR_AMF |
 387                                   RCR_HTC_LOC_CTRL | RCR_APP_MIC |
 388                                   RCR_APP_PHYSTS;
 389
 390         /*  some REG_RCR will be modified later by
 391             phy_ConfigMACWithHeaderFile() */
 392         rtw_write32(Adapter, REG_RCR, pHalData->ReceiveConfig);
 393
 394         /*  Accept all multicast address */
 395         rtw_write32(Adapter, REG_MAR, 0xFFFFFFFF);
 396         rtw_write32(Adapter, REG_MAR + 4, 0xFFFFFFFF);
 397
 398         /*  Accept all data frames */
 399         /* value16 = 0xFFFF; */
 400         /* rtw_write16(Adapter, REG_RXFLTMAP2, value16); */
 401
 402         /*  2010.09.08 hpfan */
 403         /*  Since ADF is removed from RCR, ps-poll will not be indicate
 404             to driver, */
 405         /*  RxFilterMap should mask ps-poll to gurantee AP mode can
 406             rx ps-poll. */
 407         /* value16 = 0x400; */
 408         /* rtw_write16(Adapter, REG_RXFLTMAP1, value16); */
 409
 410         /*  Accept all management frames */
 411         /* value16 = 0xFFFF; */
 412         /* rtw_write16(Adapter, REG_RXFLTMAP0, value16); */
 413
 414         /* enable RX_SHIFT bits */
 415         /* rtw_write8(Adapter, REG_TRXDMA_CTRL, rtw_read8(Adapter,
 416            REG_TRXDMA_CTRL)|BIT(1)); */
 417 }
 418
 419 static void _InitAdaptiveCtrl(struct rtw_adapter *Adapter)
 420 {
 421         u16 value16;
 422         u32 value32;
 423
 424         /*  Response Rate Set */
 425         value32 = rtw_read32(Adapter, REG_RRSR);
 426         value32 &= ~RATE_BITMAP_ALL;
 427         value32 |= RATE_RRSR_CCK_ONLY_1M;
 428         rtw_write32(Adapter, REG_RRSR, value32);
 429
 430         /*  CF-END Threshold */
 431         /* m_spIoBase->rtw_write8(REG_CFEND_TH, 0x1); */
 432
 433         /*  SIFS (used in NAV) */
 434         value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
 435         rtw_write16(Adapter, REG_SPEC_SIFS, value16);
 436
 437         /*  Retry Limit */
 438         value16 = _LRL(0x30) | _SRL(0x30);
 439         rtw_write16(Adapter, REG_RL, value16);
 440 }
 441
 442 static void _InitRateFallback(struct rtw_adapter *Adapter)
 443 {
 444         /*  Set Data Auto Rate Fallback Retry Count register. */
 445         rtw_write32(Adapter, REG_DARFRC, 0x00000000);
 446         rtw_write32(Adapter, REG_DARFRC+4, 0x10080404);
 447         rtw_write32(Adapter, REG_RARFRC, 0x04030201);
 448         rtw_write32(Adapter, REG_RARFRC+4, 0x08070605);
 449 }
 450
 451 static void _InitEDCA(struct rtw_adapter *Adapter)
 452 {
 453         /*  Set Spec SIFS (used in NAV) */
 454         rtw_write16(Adapter, REG_SPEC_SIFS, 0x100a);
 455         rtw_write16(Adapter, REG_MAC_SPEC_SIFS, 0x100a);
 456
 457         /*  Set SIFS for CCK */
 458         rtw_write16(Adapter, REG_SIFS_CTX, 0x100a);
 459
 460         /*  Set SIFS for OFDM */
 461         rtw_write16(Adapter, REG_SIFS_TRX, 0x100a);
 462
 463         /*  TXOP */
 464         rtw_write32(Adapter, REG_EDCA_BE_PARAM, 0x005EA42B);
 465         rtw_write32(Adapter, REG_EDCA_BK_PARAM, 0x0000A44F);
 466         rtw_write32(Adapter, REG_EDCA_VI_PARAM, 0x005EA324);
 467         rtw_write32(Adapter, REG_EDCA_VO_PARAM, 0x002FA226);
 468 }
 469
 470 static void _InitHWLed(struct rtw_adapter *Adapter)
 471 {
 472         struct led_priv *pledpriv = &Adapter->ledpriv;
 473
 474         if (pledpriv->LedStrategy != HW_LED)
 475                 return;
 476
 477 /*  HW led control */
 478 /*  to do .... */
 479 /* must consider cases of antenna diversity/ commbo card/solo card/mini card */
 480 }
 481
 482 static void _InitRDGSetting(struct rtw_adapter *Adapter)
 483 {
 484         rtw_write8(Adapter, REG_RD_CTRL, 0xFF);
 485         rtw_write16(Adapter, REG_RD_NAV_NXT, 0x200);
 486         rtw_write8(Adapter, REG_RD_RESP_PKT_TH, 0x05);
 487 }
 488
 489 static void _InitRetryFunction(struct rtw_adapter *Adapter)
 490 {
 491         u8 value8;
 492
 493         value8 = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL);
 494         value8 |= EN_AMPDU_RTY_NEW;
 495         rtw_write8(Adapter, REG_FWHW_TXQ_CTRL, value8);
 496
 497         /*  Set ACK timeout */
 498         rtw_write8(Adapter, REG_ACKTO, 0x40);
 499 }
 500
 501 /*-----------------------------------------------------------------------------
 502  * Function:    usb_AggSettingTxUpdate()
 503  *
 504  * Overview:    Seperate TX/RX parameters update independent for TP
 505  *              detection and dynamic TX/RX aggreagtion parameters update.
 506  *
 507  * Input:                       struct rtw_adapter *
 508  *
 509  * Output/Return:       NONE
 510  *
 511  * Revised History:
 512  *      When            Who             Remark
 513  *      12/10/2010      MHC             Seperate to smaller function.
 514  *
 515  *---------------------------------------------------------------------------*/
 516 static void usb_AggSettingTxUpdate(struct rtw_adapter *Adapter)
 517 {
 518 }       /*  usb_AggSettingTxUpdate */
 519
 520 /*-----------------------------------------------------------------------------
 521  * Function:    usb_AggSettingRxUpdate()
 522  *
 523  * Overview:    Seperate TX/RX parameters update independent for TP
 524  *              detection and dynamic TX/RX aggreagtion parameters update.
 525  *
 526  * Input:                       struct rtw_adapter *
 527  *
 528  * Output/Return:       NONE
 529  *
 530  * Revised History:
 531  *      When            Who             Remark
 532  *      12/10/2010      MHC             Seperate to smaller function.
 533  *
 534  *---------------------------------------------------------------------------*/
 535 static void usb_AggSettingRxUpdate(struct rtw_adapter *Adapter)
 536 {
 537 }       /*  usb_AggSettingRxUpdate */
 538
 539 static void InitUsbAggregationSetting(struct rtw_adapter *Adapter)
 540 {
 541         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
 542
 543         /*  Tx aggregation setting */
 544         usb_AggSettingTxUpdate(Adapter);
 545
 546         /*  Rx aggregation setting */
 547         usb_AggSettingRxUpdate(Adapter);
 548
 549         /*  201/12/10 MH Add for USB agg mode dynamic switch. */
 550         pHalData->UsbRxHighSpeedMode = false;
 551 }
 552
 553 static void _InitOperationMode(struct rtw_adapter *Adapter)
 554 {
 555 }
 556
 557 static void _InitRFType(struct rtw_adapter *Adapter)
 558 {
 559         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
 560         bool is92CU = IS_92C_SERIAL(pHalData->VersionID);
 561
 562         pHalData->rf_chip = RF_6052;
 563
 564         if (is92CU == false) {
 565                 pHalData->rf_type = RF_1T1R;
 566                 DBG_8723A("Set RF Chip ID to RF_6052 and RF type to 1T1R.\n");
 567                 return;
 568         }
 569
 570         /*  TODO: Consider that EEPROM set 92CU to 1T1R later. */
 571         /*  Force to overwrite setting according to chip version. Ignore
 572             EEPROM setting. */
 573         /* pHalData->RF_Type = is92CU ? RF_2T2R : RF_1T1R; */
 574         MSG_8723A("Set RF Chip ID to RF_6052 and RF type to %d.\n",
 575                   pHalData->rf_type);
 576 }
 577
 578 /*  Set CCK and OFDM Block "ON" */
 579 static void _BBTurnOnBlock(struct rtw_adapter *Adapter)
 580 {
 581         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bCCKEn, 0x1);
 582         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
 583 }
 584
 585 #define MgntActSet_RF_State(...)
 586 static void _RfPowerSave(struct rtw_adapter *padapter)
 587 {
 588 }
 589
 590 enum {
 591         Antenna_Lfet = 1,
 592         Antenna_Right = 2,
 593 };
 594
 595 enum rt_rf_power_state RfOnOffDetect23a(struct rtw_adapter *pAdapter)
 596 {
 597         /* struct hal_data_8723a *pHalData = GET_HAL_DATA(pAdapter); */
 598         u8 val8;
 599         enum rt_rf_power_state rfpowerstate = rf_off;
 600
 601         if (pAdapter->pwrctrlpriv.bHWPowerdown) {
 602                 val8 = rtw_read8(pAdapter, REG_HSISR);
 603                 DBG_8723A("pwrdown, 0x5c(BIT7) =%02x\n", val8);
 604                 rfpowerstate = (val8 & BIT7) ? rf_off : rf_on;
 605         } else { /*  rf on/off */
 606                 rtw_write8(pAdapter, REG_MAC_PINMUX_CFG,
 607                            rtw_read8(pAdapter, REG_MAC_PINMUX_CFG) & ~BIT3);
 608                 val8 = rtw_read8(pAdapter, REG_GPIO_IO_SEL);
 609                 DBG_8723A("GPIO_IN =%02x\n", val8);
 610                 rfpowerstate = (val8 & BIT3) ? rf_on : rf_off;
 611         }
 612         return rfpowerstate;
 613 }       /*  HalDetectPwrDownMode */
 614
 615 void _ps_open_RF23a(struct rtw_adapter *padapter);
 616
 617 static u32 rtl8723au_hal_init(struct rtw_adapter *Adapter)
 618 {
 619         u8      val8 = 0;
 620         u32     boundary, status = _SUCCESS;
 621         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
 622         struct pwrctrl_priv *pwrctrlpriv = &Adapter->pwrctrlpriv;
 623         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 624         u32 NavUpper = WiFiNavUpperUs;
 625
 626         unsigned long init_start_time = jiffies;
 627
 628 #define HAL_INIT_PROFILE_TAG(stage) do {} while (0)
 629
 630         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BEGIN);
 631         if (Adapter->pwrctrlpriv.bkeepfwalive) {
 632                 _ps_open_RF23a(Adapter);
 633
 634                 if (pHalData->bIQKInitialized) {
 635                         rtl8723a_phy_iq_calibrate(Adapter, true);
 636                 } else {
 637                         rtl8723a_phy_iq_calibrate(Adapter, false);
 638                         pHalData->bIQKInitialized = true;
 639                 }
 640                 rtl8723a_odm_check_tx_power_tracking(Adapter);
 641                 rtl8723a_phy_lc_calibrate(Adapter);
 642
 643                 goto exit;
 644         }
 645
 646         /*  Check if MAC has already power on. by tynli. 2011.05.27. */
 647         val8 = rtw_read8(Adapter, REG_CR);
 648         RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
 649                  ("%s: REG_CR 0x100 = 0x%02x\n", __func__, val8));
 650         /* Fix 92DU-VC S3 hang with the reason is that secondary mac is not
 651            initialized. */
 652         /* 0x100 value of first mac is 0xEA while 0x100 value of secondary
 653            is 0x00 */
 654         if (val8 == 0xEA) {
 655                 pHalData->bMACFuncEnable = false;
 656         } else {
 657                 pHalData->bMACFuncEnable = true;
 658                 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
 659                          ("%s: MAC has already power on\n", __func__));
 660         }
 661
 662         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PW_ON);
 663         status = _InitPowerOn(Adapter);
 664         if (status == _FAIL) {
 665                 RT_TRACE(_module_hci_hal_init_c_, _drv_err_,
 666                          ("Failed to init power on!\n"));
 667                 goto exit;
 668         }
 669
 670         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_LLTT);
 671         if (!pregistrypriv->wifi_spec) {
 672                 boundary = TX_PAGE_BOUNDARY;
 673         } else {
 674                 /*  for WMM */
 675                 boundary = WMM_NORMAL_TX_PAGE_BOUNDARY;
 676         }
 677
 678         if (!pHalData->bMACFuncEnable) {
 679                 status =  InitLLTTable23a(Adapter, boundary);
 680                 if (status == _FAIL) {
 681                         RT_TRACE(_module_hci_hal_init_c_, _drv_err_,
 682                                  ("Failed to init LLT table\n"));
 683                         goto exit;
 684                 }
 685         }
 686
 687         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC01);
 688         if (pHalData->bRDGEnable)
 689                 _InitRDGSetting(Adapter);
 690
 691         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_DOWNLOAD_FW);
 692         status = rtl8723a_FirmwareDownload(Adapter);
 693         if (status != _SUCCESS) {
 694                 Adapter->bFWReady = false;
 695                 pHalData->fw_ractrl = false;
 696                 DBG_8723A("fw download fail!\n");
 697                 goto exit;
 698         } else {
 699                 Adapter->bFWReady = true;
 700                 pHalData->fw_ractrl = true;
 701                 DBG_8723A("fw download ok!\n");
 702         }
 703
 704         rtl8723a_InitializeFirmwareVars(Adapter);
 705
 706         if (pwrctrlpriv->reg_rfoff == true) {
 707                 pwrctrlpriv->rf_pwrstate = rf_off;
 708         }
 709
 710         /*  2010/08/09 MH We need to check if we need to turnon or off RF after detecting */
 711         /*  HW GPIO pin. Before PHY_RFConfig8192C. */
 712         /* HalDetectPwrDownMode(Adapter); */
 713         /*  2010/08/26 MH If Efuse does not support sective suspend then disable the function. */
 714         /* HalDetectSelectiveSuspendMode(Adapter); */
 715
 716         /*  Set RF type for BB/RF configuration */
 717         _InitRFType(Adapter);/* _ReadRFType() */
 718
 719         /*  Save target channel */
 720         /*  <Roger_Notes> Current Channel will be updated again later. */
 721         pHalData->CurrentChannel = 6;/* default set to 6 */
 722
 723         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MAC);
 724         status = PHY_MACConfig8723A(Adapter);
 725         if (status == _FAIL) {
 726                 DBG_8723A("PHY_MACConfig8723A fault !!\n");
 727                 goto exit;
 728         }
 729
 730         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BB);
 731         /*  */
 732         /* d. Initialize BB related configurations. */
 733         /*  */
 734         status = PHY_BBConfig8723A(Adapter);
 735         if (status == _FAIL) {
 736                 DBG_8723A("PHY_BBConfig8723A fault !!\n");
 737                 goto exit;
 738         }
 739
 740         /*  Add for tx power by rate fine tune. We need to call the function after BB config. */
 741         /*  Because the tx power by rate table is inited in BB config. */
 742
 743         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_RF);
 744         status = PHY_RFConfig8723A(Adapter);
 745         if (status == _FAIL) {
 746                 DBG_8723A("PHY_RFConfig8723A fault !!\n");
 747                 goto exit;
 748         }
 749
 750         /* reducing 80M spur */
 751         PHY_SetBBReg(Adapter, RF_T_METER, bMaskDWord, 0x0381808d);
 752         PHY_SetBBReg(Adapter, RF_SYN_G4, bMaskDWord, 0xf2ffff83);
 753         PHY_SetBBReg(Adapter, RF_SYN_G4, bMaskDWord, 0xf2ffff82);
 754         PHY_SetBBReg(Adapter, RF_SYN_G4, bMaskDWord, 0xf2ffff83);
 755
 756         /* RFSW Control */
 757         PHY_SetBBReg(Adapter, rFPGA0_TxInfo, bMaskDWord, 0x00000003);   /* 0x804[14]= 0 */
 758         PHY_SetBBReg(Adapter, rFPGA0_XAB_RFInterfaceSW, bMaskDWord, 0x07000760);        /* 0x870[6:5]= b'11 */
 759         PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, bMaskDWord, 0x66F60210); /* 0x860[6:5]= b'00 */
 760
 761         RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("%s: 0x870 = value 0x%x\n", __func__, PHY_QueryBBReg(Adapter, 0x870, bMaskDWord)));
 762
 763         /*  */
 764         /*  Joseph Note: Keep RfRegChnlVal for later use. */
 765         /*  */
 766         pHalData->RfRegChnlVal[0] = PHY_QueryRFReg(Adapter, (enum RF_RADIO_PATH)0, RF_CHNLBW, bRFRegOffsetMask);
 767         pHalData->RfRegChnlVal[1] = PHY_QueryRFReg(Adapter, (enum RF_RADIO_PATH)1, RF_CHNLBW, bRFRegOffsetMask);
 768
 769         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC02);
 770         if (!pHalData->bMACFuncEnable) {
 771                 _InitQueueReservedPage(Adapter);
 772                 _InitTxBufferBoundary(Adapter);
 773         }
 774         _InitQueuePriority(Adapter);
 775         _InitPageBoundary(Adapter);
 776         _InitTransferPageSize(Adapter);
 777
 778         /*  Get Rx PHY status in order to report RSSI and others. */
 779         _InitDriverInfoSize(Adapter, DRVINFO_SZ);
 780
 781         _InitInterrupt(Adapter);
 782         hal_init_macaddr23a(Adapter);/* set mac_address */
 783         _InitNetworkType(Adapter);/* set msr */
 784         _InitWMACSetting(Adapter);
 785         _InitAdaptiveCtrl(Adapter);
 786         _InitEDCA(Adapter);
 787         _InitRateFallback(Adapter);
 788         _InitRetryFunction(Adapter);
 789         InitUsbAggregationSetting(Adapter);
 790         _InitOperationMode(Adapter);/* todo */
 791         rtl8723a_InitBeaconParameters(Adapter);
 792
 793         _InitHWLed(Adapter);
 794
 795         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_TURN_ON_BLOCK);
 796         _BBTurnOnBlock(Adapter);
 797         /* NicIFSetMacAddress(padapter, padapter->PermanentAddress); */
 798
 799         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_SECURITY);
 800         invalidate_cam_all23a(Adapter);
 801
 802         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC11);
 803         /*  2010/12/17 MH We need to set TX power according to EFUSE content at first. */
 804         PHY_SetTxPowerLevel8723A(Adapter, pHalData->CurrentChannel);
 805
 806         rtl8723a_InitAntenna_Selection(Adapter);
 807
 808         /*  HW SEQ CTRL */
 809         /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */
 810         rtw_write8(Adapter, REG_HWSEQ_CTRL, 0xFF);
 811
 812         /*  */
 813         /*  Disable BAR, suggested by Scott */
 814         /*  2010.04.09 add by hpfan */
 815         /*  */
 816         rtw_write32(Adapter, REG_BAR_MODE_CTRL, 0x0201ffff);
 817
 818         if (pregistrypriv->wifi_spec)
 819                 rtw_write16(Adapter, REG_FAST_EDCA_CTRL, 0);
 820
 821         /*  Move by Neo for USB SS from above setp */
 822         _RfPowerSave(Adapter);
 823
 824         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_IQK);
 825                 /*  2010/08/26 MH Merge from 8192CE. */
 826                 /* sherry masked that it has been done in _RfPowerSave */
 827                 /* 20110927 */
 828                 /* recovery for 8192cu and 9723Au 20111017 */
 829                 if (pwrctrlpriv->rf_pwrstate == rf_on) {
 830                         if (pHalData->bIQKInitialized) {
 831                                 rtl8723a_phy_iq_calibrate(Adapter, true);
 832                         } else {
 833                                 rtl8723a_phy_iq_calibrate(Adapter, false);
 834                                 pHalData->bIQKInitialized = true;
 835                         }
 836
 837         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_PW_TRACK);
 838                         rtl8723a_odm_check_tx_power_tracking(Adapter);
 839
 840         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_LCK);
 841                         rtl8723a_phy_lc_calibrate(Adapter);
 842
 843 #ifdef CONFIG_8723AU_BT_COEXIST
 844                         rtl8723a_SingleDualAntennaDetection(Adapter);
 845 #endif
 846                 }
 847
 848         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC21);
 849  /* fixed USB interface interference issue */
 850         rtw_write8(Adapter, 0xfe40, 0xe0);
 851         rtw_write8(Adapter, 0xfe41, 0x8d);
 852         rtw_write8(Adapter, 0xfe42, 0x80);
 853         rtw_write32(Adapter, 0x20c, 0xfd0320);
 854         /* Solve too many protocol error on USB bus */
 855         if (!IS_81xxC_VENDOR_UMC_A_CUT(pHalData->VersionID)) {
 856                 /*  0xE6 = 0x94 */
 857                 rtw_write8(Adapter, 0xFE40, 0xE6);
 858                 rtw_write8(Adapter, 0xFE41, 0x94);
 859                 rtw_write8(Adapter, 0xFE42, 0x80);
 860
 861                 /*  0xE0 = 0x19 */
 862                 rtw_write8(Adapter, 0xFE40, 0xE0);
 863                 rtw_write8(Adapter, 0xFE41, 0x19);
 864                 rtw_write8(Adapter, 0xFE42, 0x80);
 865
 866                 /*  0xE5 = 0x91 */
 867                 rtw_write8(Adapter, 0xFE40, 0xE5);
 868                 rtw_write8(Adapter, 0xFE41, 0x91);
 869                 rtw_write8(Adapter, 0xFE42, 0x80);
 870
 871                 /*  0xE2 = 0x81 */
 872                 rtw_write8(Adapter, 0xFE40, 0xE2);
 873                 rtw_write8(Adapter, 0xFE41, 0x81);
 874                 rtw_write8(Adapter, 0xFE42, 0x80);
 875
 876         }
 877
 878 /* HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PABIAS); */
 879 /*      _InitPABias(Adapter); */
 880
 881 #ifdef CONFIG_8723AU_BT_COEXIST
 882         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BT_COEXIST);
 883         /*  Init BT hw config. */
 884         BT_InitHwConfig(Adapter);
 885 #endif
 886
 887         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_HAL_DM);
 888         rtl8723a_InitHalDm(Adapter);
 889
 890         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC31);
 891         rtw_hal_set_hwreg23a(Adapter, HW_VAR_NAV_UPPER, (u8 *)&NavUpper);
 892
 893         /*  2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test, but we need to fin root cause. */
 894         if (((rtw_read32(Adapter, rFPGA0_RFMOD) & 0xFF000000) != 0x83000000)) {
 895                 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT(24), 1);
 896                 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("%s: IQK fail recorver\n", __func__));
 897         }
 898
 899         /* ack for xmit mgmt frames. */
 900         rtw_write32(Adapter, REG_FWHW_TXQ_CTRL, rtw_read32(Adapter, REG_FWHW_TXQ_CTRL)|BIT(12));
 901
 902 exit:
 903         HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_END);
 904
 905         DBG_8723A("%s in %dms\n", __func__,
 906                   jiffies_to_msecs(jiffies - init_start_time));
 907         return status;
 908 }
 909
 910 static void phy_SsPwrSwitch92CU(struct rtw_adapter *Adapter,
 911                                 enum rt_rf_power_state eRFPowerState,
 912                                 int bRegSSPwrLvl)
 913 {
 914         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
 915         u8 value8;
 916         u8 bytetmp;
 917
 918         switch (eRFPowerState) {
 919         case rf_on:
 920                 if (bRegSSPwrLvl == 1) {
 921                         /*  1. Enable MAC Clock. Can not be enabled now. */
 922                         /* WriteXBYTE(REG_SYS_CLKR+1,
 923                            ReadXBYTE(REG_SYS_CLKR+1) | BIT(3)); */
 924
 925                         /*  2. Force PWM, Enable SPS18_LDO_Marco_Block */
 926                         rtw_write8(Adapter, REG_SPS0_CTRL,
 927                                    rtw_read8(Adapter, REG_SPS0_CTRL) |
 928                                    (BIT0|BIT3));
 929
 930                         /*  3. restore BB, AFE control register. */
 931                         /* RF */
 932                         if (pHalData->rf_type ==  RF_2T2R)
 933                                 PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter,
 934                                              0x380038, 1);
 935                         else
 936                                 PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter,
 937                                              0x38, 1);
 938                         PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 1);
 939                         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT1, 0);
 940
 941                         /* AFE */
 942                         if (pHalData->rf_type ==  RF_2T2R)
 943                                 PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord,
 944                                              0x63DB25A0);
 945                         else if (pHalData->rf_type ==  RF_1T1R)
 946                                 PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord,
 947                                              0x631B25A0);
 948
 949                         /*  4. issue 3-wire command that RF set to Rx idle
 950                             mode. This is used to re-write the RX idle mode. */
 951                         /*  We can only prvide a usual value instead and then
 952                             HW will modify the value by itself. */
 953                         PHY_SetRFReg(Adapter, RF_PATH_A, 0,
 954                                      bRFRegOffsetMask, 0x32D95);
 955                         if (pHalData->rf_type ==  RF_2T2R) {
 956                                 PHY_SetRFReg(Adapter, RF_PATH_B, 0,
 957                                              bRFRegOffsetMask, 0x32D95);
 958                         }
 959                 } else {                /*  Level 2 or others. */
 960                         /* h.   AFE_PLL_CTRL 0x28[7:0] = 0x80
 961                            disable AFE PLL */
 962                         rtw_write8(Adapter, REG_AFE_PLL_CTRL, 0x81);
 963
 964                         /*  i.  AFE_XTAL_CTRL 0x24[15:0] = 0x880F
 965                             gated AFE DIG_CLOCK */
 966                         rtw_write16(Adapter, REG_AFE_XTAL_CTRL, 0x800F);
 967                         mdelay(1);
 968
 969                         /*  2. Force PWM, Enable SPS18_LDO_Marco_Block */
 970                         rtw_write8(Adapter, REG_SPS0_CTRL,
 971                                    rtw_read8(Adapter, REG_SPS0_CTRL) |
 972                                    (BIT0|BIT3));
 973
 974                         /*  3. restore BB, AFE control register. */
 975                         /* RF */
 976                         if (pHalData->rf_type ==  RF_2T2R)
 977                                 PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter,
 978                                              0x380038, 1);
 979                         else
 980                                 PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter,
 981                                              0x38, 1);
 982                         PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 1);
 983                         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT1, 0);
 984
 985                         /* AFE */
 986                         if (pHalData->rf_type ==  RF_2T2R)
 987                                 PHY_SetBBReg(Adapter, rRx_Wait_CCA,
 988                                              bMaskDWord, 0x63DB25A0);
 989                         else if (pHalData->rf_type ==  RF_1T1R)
 990                                 PHY_SetBBReg(Adapter, rRx_Wait_CCA,
 991                                              bMaskDWord, 0x631B25A0);
 992
 993                         /*  4. issue 3-wire command that RF set to Rx idle
 994                             mode. This is used to re-write the RX idle mode. */
 995                         /*  We can only prvide a usual value instead and
 996                             then HW will modify the value by itself. */
 997                         PHY_SetRFReg(Adapter, RF_PATH_A, 0,
 998                                      bRFRegOffsetMask, 0x32D95);
 999                         if (pHalData->rf_type ==  RF_2T2R) {
1000                                 PHY_SetRFReg(Adapter, RF_PATH_B, 0,
1001                                              bRFRegOffsetMask, 0x32D95);
1002                         }
1003
1004                         /*  5. gated MAC Clock */
1005                         bytetmp = rtw_read8(Adapter, REG_APSD_CTRL);
1006                         rtw_write8(Adapter, REG_APSD_CTRL, bytetmp & ~BIT6);
1007
1008                         mdelay(10);
1009
1010                         /*  Set BB reset at first */
1011                         rtw_write8(Adapter, REG_SYS_FUNC_EN, 0x17); /* 0x16 */
1012
1013                         /*  Enable TX */
1014                         rtw_write8(Adapter, REG_TXPAUSE, 0x0);
1015                 }
1016                 break;
1017         case rf_sleep:
1018         case rf_off:
1019                 value8 = rtw_read8(Adapter, REG_SPS0_CTRL) ;
1020                 if (IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID))
1021                         value8 &= ~(BIT0);
1022                 else
1023                         value8 &= ~(BIT0|BIT3);
1024                 if (bRegSSPwrLvl == 1) {
1025                         RT_TRACE(_module_hal_init_c_, _drv_err_, ("SS LVL1\n"));
1026                         /*  Disable RF and BB only for SelectSuspend. */
1027
1028                         /*  1. Set BB/RF to shutdown. */
1029                         /*      (1) Reg878[5:3]= 0       RF rx_code for
1030                                                         preamble power saving */
1031                         /*      (2)Reg878[21:19]= 0     Turn off RF-B */
1032                         /*      (3) RegC04[7:4]= 0      Turn off all paths
1033                                                         for packet detection */
1034                         /*      (4) Reg800[1] = 1       enable preamble power
1035                                                         saving */
1036                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF0] =
1037                                 PHY_QueryBBReg(Adapter, rFPGA0_XAB_RFParameter,
1038                                                bMaskDWord);
1039                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF1] =
1040                                 PHY_QueryBBReg(Adapter, rOFDM0_TRxPathEnable,
1041                                                bMaskDWord);
1042                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF2] =
1043                                 PHY_QueryBBReg(Adapter, rFPGA0_RFMOD,
1044                                                bMaskDWord);
1045                         if (pHalData->rf_type ==  RF_2T2R) {
1046                                 PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter,
1047                                              0x380038, 0);
1048                         } else if (pHalData->rf_type ==  RF_1T1R) {
1049                                 PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter,
1050                                              0x38, 0);
1051                         }
1052                         PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 0);
1053                         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT1, 1);
1054
1055                         /*  2 .AFE control register to power down. bit[30:22] */
1056                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_AFE0] =
1057                                 PHY_QueryBBReg(Adapter, rRx_Wait_CCA,
1058                                                bMaskDWord);
1059                         if (pHalData->rf_type ==  RF_2T2R)
1060                                 PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord,
1061                                              0x00DB25A0);
1062                         else if (pHalData->rf_type ==  RF_1T1R)
1063                                 PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord,
1064                                              0x001B25A0);
1065
1066                         /*  3. issue 3-wire command that RF set to power down.*/
1067                         PHY_SetRFReg(Adapter, RF_PATH_A, 0, bRFRegOffsetMask, 0);
1068                         if (pHalData->rf_type ==  RF_2T2R)
1069                                 PHY_SetRFReg(Adapter, RF_PATH_B, 0,
1070                                              bRFRegOffsetMask, 0);
1071
1072                         /*  4. Force PFM , disable SPS18_LDO_Marco_Block */
1073                         rtw_write8(Adapter, REG_SPS0_CTRL, value8);
1074                 } else {        /*  Level 2 or others. */
1075                         RT_TRACE(_module_hal_init_c_, _drv_err_, ("SS LVL2\n"));
1076                         {
1077                                 u8 eRFPath = RF_PATH_A, value8 = 0;
1078                                 rtw_write8(Adapter, REG_TXPAUSE, 0xFF);
1079                                 PHY_SetRFReg(Adapter,
1080                                              (enum RF_RADIO_PATH)eRFPath,
1081                                              0x0, bMaskByte0, 0x0);
1082                                 value8 |= APSDOFF;
1083                                 /* 0x40 */
1084                                 rtw_write8(Adapter, REG_APSD_CTRL, value8);
1085
1086                                 /*  After switch APSD, we need to delay
1087                                     for stability */
1088                                 mdelay(10);
1089
1090                                 /*  Set BB reset at first */
1091                                 value8 = 0 ;
1092                                 value8 |= (FEN_USBD | FEN_USBA |
1093                                            FEN_BB_GLB_RSTn);
1094                                 /* 0x16 */
1095                                 rtw_write8(Adapter, REG_SYS_FUNC_EN, value8);
1096                         }
1097
1098                         /*  Disable RF and BB only for SelectSuspend. */
1099
1100                         /*  1. Set BB/RF to shutdown. */
1101                         /*      (1) Reg878[5:3]= 0      RF rx_code for
1102                                                         preamble power saving */
1103                         /*      (2)Reg878[21:19]= 0     Turn off RF-B */
1104                         /*      (3) RegC04[7:4]= 0      Turn off all paths for
1105                                                         packet detection */
1106                         /*      (4) Reg800[1] = 1       enable preamble power
1107                                                         saving */
1108                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF0] =
1109                                 PHY_QueryBBReg(Adapter, rFPGA0_XAB_RFParameter,
1110                                                bMaskDWord);
1111                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF1] =
1112                                 PHY_QueryBBReg(Adapter, rOFDM0_TRxPathEnable,
1113                                                bMaskDWord);
1114                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF2] =
1115                                 PHY_QueryBBReg(Adapter, rFPGA0_RFMOD,
1116                                                bMaskDWord);
1117                         if (pHalData->rf_type ==  RF_2T2R)
1118                                 PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter,
1119                                              0x380038, 0);
1120                         else if (pHalData->rf_type ==  RF_1T1R)
1121                                 PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter,
1122                                              0x38, 0);
1123                         PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 0);
1124                         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT1, 1);
1125
1126                         /*  2 .AFE control register to power down. bit[30:22] */
1127                         Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_AFE0] =
1128                                 PHY_QueryBBReg(Adapter, rRx_Wait_CCA,
1129                                                bMaskDWord);
1130                         if (pHalData->rf_type ==  RF_2T2R)
1131                                 PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord,
1132                                              0x00DB25A0);
1133                         else if (pHalData->rf_type ==  RF_1T1R)
1134                                 PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord,
1135                                              0x001B25A0);
1136
1137                         /* 3. issue 3-wire command that RF set to power down. */
1138                         PHY_SetRFReg(Adapter, RF_PATH_A, 0, bRFRegOffsetMask, 0);
1139                         if (pHalData->rf_type ==  RF_2T2R)
1140                                 PHY_SetRFReg(Adapter, RF_PATH_B, 0,
1141                                              bRFRegOffsetMask, 0);
1142
1143                         /*  4. Force PFM , disable SPS18_LDO_Marco_Block */
1144                         rtw_write8(Adapter, REG_SPS0_CTRL, value8);
1145
1146                         /*  2010/10/13 MH/Isaachsu exchange sequence. */
1147                         /* h.   AFE_PLL_CTRL 0x28[7:0] = 0x80
1148                                 disable AFE PLL */
1149                         rtw_write8(Adapter, REG_AFE_PLL_CTRL, 0x80);
1150                         mdelay(1);
1151
1152                         /*  i.  AFE_XTAL_CTRL 0x24[15:0] = 0x880F
1153                                 gated AFE DIG_CLOCK */
1154                         rtw_write16(Adapter, REG_AFE_XTAL_CTRL, 0xA80F);
1155                 }
1156                 break;
1157         default:
1158                 break;
1159         }
1160
1161 }       /*  phy_PowerSwitch92CU */
1162
1163 void _ps_open_RF23a(struct rtw_adapter *padapter)
1164 {
1165         /* here call with bRegSSPwrLvl 1, bRegSSPwrLvl 2 needs to be verified */
1166         phy_SsPwrSwitch92CU(padapter, rf_on, 1);
1167 }
1168
1169 static void CardDisableRTL8723U(struct rtw_adapter *Adapter)
1170 {
1171         u8              u1bTmp;
1172
1173         DBG_8723A("CardDisableRTL8723U\n");
1174         /*  USB-MF Card Disable Flow */
1175         /*  1. Run LPS WL RFOFF flow */
1176         HalPwrSeqCmdParsing23a(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1177                             PWR_INTF_USB_MSK, rtl8723AU_enter_lps_flow);
1178
1179         /*  2. 0x1F[7:0] = 0            turn off RF */
1180         rtw_write8(Adapter, REG_RF_CTRL, 0x00);
1181
1182         /*      ==== Reset digital sequence   ====== */
1183         if ((rtw_read8(Adapter, REG_MCUFWDL)&BIT7) &&
1184             Adapter->bFWReady) /* 8051 RAM code */
1185                 rtl8723a_FirmwareSelfReset(Adapter);
1186
1187         /*  Reset MCU. Suggested by Filen. 2011.01.26. by tynli. */
1188         u1bTmp = rtw_read8(Adapter, REG_SYS_FUNC_EN+1);
1189         rtw_write8(Adapter, REG_SYS_FUNC_EN+1, (u1bTmp & (~BIT2)));
1190
1191         /*  g.  MCUFWDL 0x80[1:0]= 0            reset MCU ready status */
1192         rtw_write8(Adapter, REG_MCUFWDL, 0x00);
1193
1194         /*      ==== Reset digital sequence end ====== */
1195         /*  Card disable power action flow */
1196         HalPwrSeqCmdParsing23a(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1197                                PWR_INTF_USB_MSK,
1198                                rtl8723AU_card_disable_flow);
1199
1200         /*  Reset MCU IO Wrapper, added by Roger, 2011.08.30. */
1201         u1bTmp = rtw_read8(Adapter, REG_RSV_CTRL + 1);
1202         rtw_write8(Adapter, REG_RSV_CTRL+1, (u1bTmp & (~BIT0)));
1203         u1bTmp = rtw_read8(Adapter, REG_RSV_CTRL + 1);
1204         rtw_write8(Adapter, REG_RSV_CTRL+1, u1bTmp | BIT0);
1205
1206         /*  7. RSV_CTRL 0x1C[7:0] = 0x0E  lock ISO/CLK/Power control register */
1207         rtw_write8(Adapter, REG_RSV_CTRL, 0x0e);
1208 }
1209
1210 static u32 rtl8723au_hal_deinit(struct rtw_adapter *padapter)
1211 {
1212         DBG_8723A("==> %s\n", __func__);
1213
1214 #ifdef CONFIG_8723AU_BT_COEXIST
1215         BT_HaltProcess(padapter);
1216 #endif
1217         /*  2011/02/18 To Fix RU LNA  power leakage problem. We need to
1218             execute below below in Adapter init and halt sequence.
1219             According to EEchou's opinion, we can enable the ability for all */
1220         /*  IC. Accord to johnny's opinion, only RU need the support. */
1221         CardDisableRTL8723U(padapter);
1222
1223         return _SUCCESS;
1224 }
1225
1226 static unsigned int rtl8723au_inirp_init(struct rtw_adapter *Adapter)
1227 {
1228         u8 i;
1229         struct recv_buf *precvbuf;
1230         uint    status;
1231         struct intf_hdl *pintfhdl = &Adapter->iopriv.intf;
1232         struct recv_priv *precvpriv = &Adapter->recvpriv;
1233         u32 (*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt,
1234                           struct recv_buf *rbuf);
1235         u32 (*_read_interrupt)(struct intf_hdl *pintfhdl, u32 addr);
1236         struct hal_data_8723a   *pHalData = GET_HAL_DATA(Adapter);
1237
1238         _read_port = pintfhdl->io_ops._read_port;
1239
1240         status = _SUCCESS;
1241
1242         RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("===> usb_inirp_init\n"));
1243
1244         precvpriv->ff_hwaddr = RECV_BULK_IN_ADDR;
1245
1246         /* issue Rx irp to receive data */
1247         precvbuf = (struct recv_buf *)precvpriv->precv_buf;
1248         for (i = 0; i < NR_RECVBUFF; i++) {
1249                 if (_read_port(pintfhdl, precvpriv->ff_hwaddr, 0, precvbuf) ==
1250                     false) {
1251                         RT_TRACE(_module_hci_hal_init_c_, _drv_err_,
1252                                  ("usb_rx_init: usb_read_port error\n"));
1253                         status = _FAIL;
1254                         goto exit;
1255                 }
1256                 precvbuf++;
1257                 precvpriv->free_recv_buf_queue_cnt--;
1258         }
1259         _read_interrupt = pintfhdl->io_ops._read_interrupt;
1260         if (_read_interrupt(pintfhdl, RECV_INT_IN_ADDR) == false) {
1261                 RT_TRACE(_module_hci_hal_init_c_, _drv_err_,
1262                          ("usb_rx_init: usb_read_interrupt error\n"));
1263                 status = _FAIL;
1264         }
1265         pHalData->IntrMask[0] = rtw_read32(Adapter, REG_USB_HIMR);
1266         MSG_8723A("pHalData->IntrMask = 0x%04x\n", pHalData->IntrMask[0]);
1267         pHalData->IntrMask[0] |= UHIMR_C2HCMD|UHIMR_CPWM;
1268         rtw_write32(Adapter, REG_USB_HIMR, pHalData->IntrMask[0]);
1269 exit:
1270         RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1271                  ("<=== usb_inirp_init\n"));
1272         return status;
1273 }
1274
1275 static unsigned int rtl8723au_inirp_deinit(struct rtw_adapter *Adapter)
1276 {
1277         struct hal_data_8723a   *pHalData = GET_HAL_DATA(Adapter);
1278
1279         RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1280                  ("\n ===> usb_rx_deinit\n"));
1281         rtw_read_port_cancel(Adapter);
1282         pHalData->IntrMask[0] = rtw_read32(Adapter, REG_USB_HIMR);
1283         MSG_8723A("%s pHalData->IntrMask = 0x%04x\n", __func__,
1284                   pHalData->IntrMask[0]);
1285         pHalData->IntrMask[0] = 0x0;
1286         rtw_write32(Adapter, REG_USB_HIMR, pHalData->IntrMask[0]);
1287         RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1288                  ("\n <=== usb_rx_deinit\n"));
1289         return _SUCCESS;
1290 }
1291
1292 static void _ReadBoardType(struct rtw_adapter *Adapter, u8 *PROMContent,
1293                            bool AutoloadFail)
1294 {
1295         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1296         u8 boardType = BOARD_USB_DONGLE;
1297
1298         if (AutoloadFail) {
1299                 if (IS_8723_SERIES(pHalData->VersionID))
1300                         pHalData->rf_type = RF_1T1R;
1301                 else
1302                         pHalData->rf_type = RF_2T2R;
1303                 pHalData->BoardType = boardType;
1304                 return;
1305         }
1306
1307         boardType = PROMContent[EEPROM_NORMAL_BoardType];
1308         boardType &= BOARD_TYPE_NORMAL_MASK;/* bit[7:5] */
1309         boardType >>= 5;
1310
1311         pHalData->BoardType = boardType;
1312         MSG_8723A("_ReadBoardType(%x)\n", pHalData->BoardType);
1313
1314         if (boardType == BOARD_USB_High_PA)
1315                 pHalData->ExternalPA = 1;
1316 }
1317
1318 static void _ReadLEDSetting(struct rtw_adapter *Adapter, u8 *PROMContent,
1319                             bool AutoloadFail)
1320 {
1321         struct led_priv *pledpriv = &Adapter->ledpriv;
1322
1323         pledpriv->LedStrategy = HW_LED;
1324 }
1325
1326 static void Hal_EfuseParsePIDVID_8723AU(struct rtw_adapter *pAdapter,
1327                                         u8 *hwinfo, bool AutoLoadFail)
1328 {
1329         struct hal_data_8723a *pHalData = GET_HAL_DATA(pAdapter);
1330
1331         if (AutoLoadFail) {
1332                 pHalData->EEPROMVID = 0;
1333                 pHalData->EEPROMPID = 0;
1334         } else {
1335                 /*  VID, PID */
1336                 pHalData->EEPROMVID =
1337                         le16_to_cpu(*(u16 *)&hwinfo[EEPROM_VID_8723AU]);
1338                 pHalData->EEPROMPID =
1339                         le16_to_cpu(*(u16 *)&hwinfo[EEPROM_PID_8723AU]);
1340         }
1341
1342         MSG_8723A("EEPROM VID = 0x%4x\n", pHalData->EEPROMVID);
1343         MSG_8723A("EEPROM PID = 0x%4x\n", pHalData->EEPROMPID);
1344 }
1345
1346 static void Hal_EfuseParseMACAddr_8723AU(struct rtw_adapter *padapter,
1347                                          u8 *hwinfo, bool AutoLoadFail)
1348 {
1349         u16 i;
1350         u8 sMacAddr[ETH_ALEN] = {0x00, 0xE0, 0x4C, 0x87, 0x23, 0x00};
1351         struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1352
1353         if (AutoLoadFail) {
1354                 for (i = 0; i < 6; i++)
1355                         pEEPROM->mac_addr[i] = sMacAddr[i];
1356         } else {
1357                 /* Read Permanent MAC address */
1358                 memcpy(pEEPROM->mac_addr, &hwinfo[EEPROM_MAC_ADDR_8723AU],
1359                        ETH_ALEN);
1360         }
1361
1362         RT_TRACE(_module_hci_hal_init_c_, _drv_notice_,
1363                  ("Hal_EfuseParseMACAddr_8723AU: Permanent Address =%02x:%02x:"
1364                   "%02x:%02x:%02x:%02x\n",
1365                   pEEPROM->mac_addr[0], pEEPROM->mac_addr[1],
1366                   pEEPROM->mac_addr[2], pEEPROM->mac_addr[3],
1367                   pEEPROM->mac_addr[4], pEEPROM->mac_addr[5]));
1368 }
1369
1370 static void readAdapterInfo(struct rtw_adapter *padapter)
1371 {
1372         struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1373         /* struct hal_data_8723a * pHalData = GET_HAL_DATA(padapter); */
1374         u8 hwinfo[HWSET_MAX_SIZE];
1375
1376         Hal_InitPGData(padapter, hwinfo);
1377         Hal_EfuseParseIDCode(padapter, hwinfo);
1378         Hal_EfuseParsePIDVID_8723AU(padapter, hwinfo,
1379                                     pEEPROM->bautoload_fail_flag);
1380         Hal_EfuseParseEEPROMVer(padapter, hwinfo,
1381                                 pEEPROM->bautoload_fail_flag);
1382         Hal_EfuseParseMACAddr_8723AU(padapter, hwinfo,
1383                                      pEEPROM->bautoload_fail_flag);
1384         Hal_EfuseParsetxpowerinfo_8723A(padapter, hwinfo,
1385                                         pEEPROM->bautoload_fail_flag);
1386         _ReadBoardType(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1387         Hal_EfuseParseBTCoexistInfo_8723A(padapter, hwinfo,
1388                                           pEEPROM->bautoload_fail_flag);
1389
1390         rtl8723a_EfuseParseChnlPlan(padapter, hwinfo,
1391                                     pEEPROM->bautoload_fail_flag);
1392         Hal_EfuseParseThermalMeter_8723A(padapter, hwinfo,
1393                                          pEEPROM->bautoload_fail_flag);
1394         _ReadLEDSetting(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1395 /*      _ReadRFSetting(Adapter, PROMContent, pEEPROM->bautoload_fail_flag); */
1396 /*      _ReadPSSetting(Adapter, PROMContent, pEEPROM->bautoload_fail_flag); */
1397         Hal_EfuseParseAntennaDiversity(padapter, hwinfo,
1398                                        pEEPROM->bautoload_fail_flag);
1399
1400         Hal_EfuseParseEEPROMVer(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1401         Hal_EfuseParseCustomerID(padapter, hwinfo,
1402                                  pEEPROM->bautoload_fail_flag);
1403         Hal_EfuseParseRateIndicationOption(padapter, hwinfo,
1404                                            pEEPROM->bautoload_fail_flag);
1405         Hal_EfuseParseXtal_8723A(padapter, hwinfo,
1406                                  pEEPROM->bautoload_fail_flag);
1407         /*  */
1408         /*  The following part initialize some vars by PG info. */
1409         /*  */
1410         Hal_InitChannelPlan23a(padapter);
1411
1412         /* hal_CustomizedBehavior_8723U(Adapter); */
1413
1414 /*      Adapter->bDongle = (PROMContent[EEPROM_EASY_REPLACEMENT] == 1)? 0: 1; */
1415         DBG_8723A("%s(): REPLACEMENT = %x\n", __func__, padapter->bDongle);
1416 }
1417
1418 static void _ReadPROMContent(struct rtw_adapter *Adapter)
1419 {
1420         struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter);
1421         u8 eeValue;
1422
1423         eeValue = rtw_read8(Adapter, REG_9346CR);
1424         /*  To check system boot selection. */
1425         pEEPROM->EepromOrEfuse = (eeValue & BOOT_FROM_EEPROM) ? true : false;
1426         pEEPROM->bautoload_fail_flag = (eeValue & EEPROM_EN) ? false : true;
1427
1428         DBG_8723A("Boot from %s, Autoload %s !\n",
1429                   (pEEPROM->EepromOrEfuse ? "EEPROM" : "EFUSE"),
1430                   (pEEPROM->bautoload_fail_flag ? "Fail" : "OK"));
1431
1432         readAdapterInfo(Adapter);
1433 }
1434
1435 static void _ReadRFType(struct rtw_adapter *Adapter)
1436 {
1437         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1438
1439         pHalData->rf_chip = RF_6052;
1440 }
1441
1442 static void _ReadSilmComboMode(struct rtw_adapter *Adapter)
1443 {
1444         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1445
1446         pHalData->SlimComboDbg = false; /*  Default is not debug mode. */
1447 }
1448
1449 /*  */
1450 /*      Description: */
1451 /*              We should set Efuse cell selection to WiFi cell in default. */
1452 /*  */
1453 /*      Assumption: */
1454 /*              PASSIVE_LEVEL */
1455 /*  */
1456 /*      Added by Roger, 2010.11.23. */
1457 /*  */
1458 static void hal_EfuseCellSel(struct rtw_adapter *Adapter)
1459 {
1460         u32 value32;
1461
1462         value32 = rtw_read32(Adapter, EFUSE_TEST);
1463         value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
1464         rtw_write32(Adapter, EFUSE_TEST, value32);
1465 }
1466
1467 static int _ReadAdapterInfo8723AU(struct rtw_adapter *Adapter)
1468 {
1469         /* struct hal_data_8723a        *pHalData = GET_HAL_DATA(Adapter); */
1470         unsigned long start = jiffies;
1471
1472         MSG_8723A("====> _ReadAdapterInfo8723AU\n");
1473
1474         hal_EfuseCellSel(Adapter);
1475
1476         _ReadRFType(Adapter);/* rf_chip -> _InitRFType() */
1477         _ReadPROMContent(Adapter);
1478
1479         /*  2010/10/25 MH THe function must be called after
1480             borad_type & IC-Version recognize. */
1481         _ReadSilmComboMode(Adapter);
1482
1483         /* MSG_8723A("%s()(done), rf_chip = 0x%x, rf_type = 0x%x\n",
1484            __func__, pHalData->rf_chip, pHalData->rf_type); */
1485
1486         MSG_8723A("<==== _ReadAdapterInfo8723AU in %d ms\n",
1487                   jiffies_to_msecs(jiffies - start));
1488
1489         return _SUCCESS;
1490 }
1491
1492 static void ReadAdapterInfo8723AU(struct rtw_adapter *Adapter)
1493 {
1494         /*  Read EEPROM size before call any EEPROM function */
1495         Adapter->EepromAddressSize = GetEEPROMSize8723A(Adapter);
1496
1497         _ReadAdapterInfo8723AU(Adapter);
1498 }
1499
1500 #define GPIO_DEBUG_PORT_NUM 0
1501 static void rtl8723au_trigger_gpio_0(struct rtw_adapter *padapter)
1502 {
1503         u32 gpioctrl;
1504         DBG_8723A("==> trigger_gpio_0...\n");
1505         rtw_write16_async(padapter, REG_GPIO_PIN_CTRL, 0);
1506         rtw_write8_async(padapter, REG_GPIO_PIN_CTRL+2, 0xFF);
1507         gpioctrl = (BIT(GPIO_DEBUG_PORT_NUM) << 24)|
1508                 (BIT(GPIO_DEBUG_PORT_NUM) << 16);
1509         rtw_write32_async(padapter, REG_GPIO_PIN_CTRL, gpioctrl);
1510         gpioctrl |= (BIT(GPIO_DEBUG_PORT_NUM)<<8);
1511         rtw_write32_async(padapter, REG_GPIO_PIN_CTRL, gpioctrl);
1512         DBG_8723A("<=== trigger_gpio_0...\n");
1513 }
1514
1515 /*
1516  * If variable not handled here,
1517  * some variables will be processed in SetHwReg8723A()
1518  */
1519 static void SetHwReg8723AU(struct rtw_adapter *Adapter, u8 variable, u8 *val)
1520 {
1521         switch (variable) {
1522         case HW_VAR_RXDMA_AGG_PG_TH:
1523                 break;
1524         case HW_VAR_SET_RPWM:
1525                 rtl8723a_set_rpwm(Adapter, *val);
1526                 break;
1527         case HW_VAR_TRIGGER_GPIO_0:
1528                 rtl8723au_trigger_gpio_0(Adapter);
1529                 break;
1530         default:
1531                 SetHwReg8723A(Adapter, variable, val);
1532                 break;
1533         }
1534
1535 }
1536
1537 /*
1538  * If variable not handled here,
1539  * some variables will be processed in GetHwReg8723A()
1540  */
1541 static void GetHwReg8723AU(struct rtw_adapter *Adapter, u8 variable, u8 *val)
1542 {
1543         GetHwReg8723A(Adapter, variable, val);
1544 }
1545
1546 /*  */
1547 /*      Description: */
1548 /*              Query setting of specified variable. */
1549 /*  */
1550 static u8 GetHalDefVar8192CUsb(struct rtw_adapter *Adapter,
1551                                enum hal_def_variable eVariable, void *pValue)
1552 {
1553         struct hal_data_8723a   *pHalData = GET_HAL_DATA(Adapter);
1554         u8                      bResult = _SUCCESS;
1555
1556         switch (eVariable) {
1557         case HAL_DEF_UNDERCORATEDSMOOTHEDPWDB:
1558                 *((int *)pValue) = pHalData->dmpriv.UndecoratedSmoothedPWDB;
1559                 break;
1560         case HAL_DEF_IS_SUPPORT_ANT_DIV:
1561                 break;
1562         case HAL_DEF_CURRENT_ANTENNA:
1563                 break;
1564         case HAL_DEF_DRVINFO_SZ:
1565                 *((u32 *)pValue) = DRVINFO_SZ;
1566                 break;
1567         case HAL_DEF_MAX_RECVBUF_SZ:
1568                 *((u32 *)pValue) = MAX_RECVBUF_SZ;
1569                 break;
1570         case HAL_DEF_RX_PACKET_OFFSET:
1571                 *((u32 *)pValue) = RXDESC_SIZE + DRVINFO_SZ;
1572                 break;
1573         case HAL_DEF_DBG_DUMP_RXPKT:
1574                 *((u8 *)pValue) = pHalData->bDumpRxPkt;
1575                 break;
1576         case HAL_DEF_DBG_DM_FUNC:
1577                 *((u32 *)pValue) = pHalData->odmpriv.SupportAbility;
1578                 break;
1579         case HW_VAR_MAX_RX_AMPDU_FACTOR:
1580                 *((u32 *)pValue) = IEEE80211_HT_MAX_AMPDU_64K;
1581                 break;
1582         case HW_DEF_ODM_DBG_FLAG:
1583         {
1584                 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
1585                 printk("pDM_Odm->DebugComponents = 0x%llx\n",
1586                        pDM_Odm->DebugComponents);
1587         }
1588                 break;
1589         default:
1590                 /* RT_TRACE(COMP_INIT, DBG_WARNING, ("GetHalDefVar8192CUsb(): "
1591                    "Unkown variable: %d!\n", eVariable)); */
1592                 bResult = _FAIL;
1593                 break;
1594         }
1595
1596         return bResult;
1597 }
1598
1599 /*      Change default setting of specified variable. */
1600 static u8 SetHalDefVar8192CUsb(struct rtw_adapter *Adapter,
1601                                enum hal_def_variable eVariable, void *pValue)
1602 {
1603         struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1604         u8 bResult = _SUCCESS;
1605
1606         switch (eVariable) {
1607         case HAL_DEF_DBG_DUMP_RXPKT:
1608                 pHalData->bDumpRxPkt = *((u8 *)pValue);
1609                 break;
1610         case HAL_DEF_DBG_DM_FUNC:
1611         {
1612                 u8 dm_func = *((u8 *)pValue);
1613                 struct dm_priv  *pdmpriv = &pHalData->dmpriv;
1614                 struct dm_odm_t *podmpriv = &pHalData->odmpriv;
1615
1616                 if (dm_func == 0) { /* disable all dynamic func */
1617                         podmpriv->SupportAbility = DYNAMIC_FUNC_DISABLE;
1618                         DBG_8723A("==> Disable all dynamic function...\n");
1619                 } else if (dm_func == 1) {/* disable DIG */
1620                         podmpriv->SupportAbility &= (~DYNAMIC_BB_DIG);
1621                         DBG_8723A("==> Disable DIG...\n");
1622                 } else if (dm_func == 2) {/* disable High power */
1623                         podmpriv->SupportAbility &= (~DYNAMIC_BB_DYNAMIC_TXPWR);
1624                 } else if (dm_func == 3) {/* disable tx power tracking */
1625                         podmpriv->SupportAbility &= (~DYNAMIC_RF_CALIBRATION);
1626                         DBG_8723A("==> Disable tx power tracking...\n");
1627                 } else if (dm_func == 4) {/* disable BT coexistence */
1628                         pdmpriv->DMFlag &= (~DYNAMIC_FUNC_BT);
1629                 } else if (dm_func == 5) {/* disable antenna diversity */
1630                         podmpriv->SupportAbility &= (~DYNAMIC_BB_ANT_DIV);
1631                 } else if (dm_func == 6) {/* turn on all dynamic func */
1632                         if (!(podmpriv->SupportAbility & DYNAMIC_BB_DIG)) {
1633                                 struct dig_t *pDigTable =
1634                                         &podmpriv->DM_DigTable;
1635                                 pDigTable->CurIGValue = rtw_read8(Adapter, 0xc50);
1636                         }
1637                         pdmpriv->DMFlag |= DYNAMIC_FUNC_BT;
1638                         podmpriv->SupportAbility = DYNAMIC_ALL_FUNC_ENABLE;
1639                         DBG_8723A("==> Turn on all dynamic function...\n");
1640                 }
1641         }
1642                 break;
1643         case HW_DEF_FA_CNT_DUMP:
1644         {
1645                 u8 bRSSIDump = *((u8 *)pValue);
1646                 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
1647                 if (bRSSIDump)
1648                         pDM_Odm->DebugComponents = ODM_COMP_DIG|ODM_COMP_FA_CNT;
1649                 else
1650                         pDM_Odm->DebugComponents = 0;
1651         }
1652                 break;
1653         case HW_DEF_ODM_DBG_FLAG:
1654         {
1655                 u64 DebugComponents = *((u64 *)pValue);
1656                 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
1657                 pDM_Odm->DebugComponents = DebugComponents;
1658         }
1659                 break;
1660         default:
1661                 /* RT_TRACE(COMP_INIT, DBG_TRACE, ("SetHalDefVar819xUsb(): "
1662                    "Unkown variable: %d!\n", eVariable)); */
1663                 bResult = _FAIL;
1664                 break;
1665         }
1666
1667         return bResult;
1668 }
1669
1670 static void UpdateHalRAMask8192CUsb(struct rtw_adapter *padapter,
1671                                     u32 mac_id, u8 rssi_level)
1672 {
1673         u8      init_rate = 0;
1674         u8      networkType, raid;
1675         u32     mask, rate_bitmap;
1676         u8      shortGIrate = false;
1677         int     supportRateNum = 0;
1678         struct sta_info *psta;
1679         struct hal_data_8723a   *pHalData = GET_HAL_DATA(padapter);
1680         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
1681         struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
1682         struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
1683         struct wlan_bssid_ex *cur_network = &pmlmeinfo->network;
1684
1685         if (mac_id >= NUM_STA) /* CAM_SIZE */
1686                 return;
1687
1688         psta = pmlmeinfo->FW_sta_info[mac_id].psta;
1689         if (psta == NULL)
1690                 return;
1691
1692         switch (mac_id) {
1693         case 0:/*  for infra mode */
1694                 supportRateNum =
1695                         rtw_get_rateset_len23a(cur_network->SupportedRates);
1696                 networkType = judge_network_type23a(padapter,
1697                                                  cur_network->SupportedRates,
1698                                                  supportRateNum) & 0xf;
1699                 /* pmlmeext->cur_wireless_mode = networkType; */
1700                 raid = networktype_to_raid23a(networkType);
1701
1702                 mask = update_supported_rate23a(cur_network->SupportedRates,
1703                                              supportRateNum);
1704                 mask |= (pmlmeinfo->HT_enable) ?
1705                         update_MSC_rate23a(&pmlmeinfo->HT_caps) : 0;
1706
1707                 if (support_short_GI23a(padapter, &pmlmeinfo->HT_caps))
1708                         shortGIrate = true;
1709                 break;
1710
1711         case 1:/* for broadcast/multicast */
1712                 supportRateNum = rtw_get_rateset_len23a(
1713                         pmlmeinfo->FW_sta_info[mac_id].SupportedRates);
1714                 if (pmlmeext->cur_wireless_mode & WIRELESS_11B)
1715                         networkType = WIRELESS_11B;
1716                 else
1717                         networkType = WIRELESS_11G;
1718                 raid = networktype_to_raid23a(networkType);
1719
1720                 mask = update_basic_rate23a(cur_network->SupportedRates,
1721                                          supportRateNum);
1722                 break;
1723
1724         default: /* for each sta in IBSS */
1725                 supportRateNum = rtw_get_rateset_len23a(
1726                         pmlmeinfo->FW_sta_info[mac_id].SupportedRates);
1727                 networkType = judge_network_type23a(padapter,
1728                                                  pmlmeinfo->FW_sta_info[mac_id].SupportedRates,
1729                                                  supportRateNum) & 0xf;
1730                 /* pmlmeext->cur_wireless_mode = networkType; */
1731                 raid = networktype_to_raid23a(networkType);
1732
1733                 mask = update_supported_rate23a(cur_network->SupportedRates,
1734                                              supportRateNum);
1735
1736                 /* todo: support HT in IBSS */
1737                 break;
1738         }
1739
1740         /* mask &= 0x0fffffff; */
1741         rate_bitmap = 0x0fffffff;
1742         rate_bitmap = ODM_Get_Rate_Bitmap23a(&pHalData->odmpriv,
1743                                           mac_id, mask, rssi_level);
1744         printk(KERN_DEBUG "%s => mac_id:%d, networkType:0x%02x, "
1745                "mask:0x%08x\n\t ==> rssi_level:%d, rate_bitmap:0x%08x\n",
1746                __func__,
1747                mac_id, networkType, mask, rssi_level, rate_bitmap);
1748
1749         mask &= rate_bitmap;
1750         mask |= ((raid<<28)&0xf0000000);
1751
1752         init_rate = get_highest_rate_idx23a(mask)&0x3f;
1753
1754         if (pHalData->fw_ractrl == true) {
1755                 u8 arg = 0;
1756
1757                 /* arg = (cam_idx-4)&0x1f;MACID */
1758                 arg = mac_id&0x1f;/* MACID */
1759
1760                 arg |= BIT(7);
1761
1762                 if (shortGIrate == true)
1763                         arg |= BIT(5);
1764
1765                 DBG_8723A("update raid entry, mask = 0x%x, arg = 0x%x\n",
1766                           mask, arg);
1767
1768                 rtl8723a_set_raid_cmd(padapter, mask, arg);
1769         } else {
1770                 if (shortGIrate == true)
1771                         init_rate |= BIT(6);
1772
1773                 rtw_write8(padapter, (REG_INIDATA_RATE_SEL+mac_id), init_rate);
1774         }
1775
1776         /* set ra_id */
1777         psta->raid = raid;
1778         psta->init_rate = init_rate;
1779
1780         /* set correct initial date rate for each mac_id */
1781         pdmpriv->INIDATA_RATE[mac_id] = init_rate;
1782 }
1783
1784 static void rtl8723au_init_default_value(struct rtw_adapter *padapter)
1785 {
1786         rtl8723a_init_default_value(padapter);
1787 }
1788
1789 static u8 rtl8192cu_ps_func(struct rtw_adapter *Adapter,
1790                             enum hal_intf_ps_func efunc_id, u8 *val)
1791 {
1792         return true;
1793 }
1794
1795 int rtl8723au_set_hal_ops(struct rtw_adapter *padapter)
1796 {
1797         struct hal_ops  *pHalFunc = &padapter->HalFunc;
1798
1799         padapter->HalData = kzalloc(sizeof(struct hal_data_8723a), GFP_KERNEL);
1800         if (!padapter->HalData) {
1801                 DBG_8723A("cannot alloc memory for HAL DATA\n");
1802                 return -ENOMEM;
1803         }
1804         padapter->hal_data_sz = sizeof(struct hal_data_8723a);
1805
1806         pHalFunc->hal_init = &rtl8723au_hal_init;
1807         pHalFunc->hal_deinit = &rtl8723au_hal_deinit;
1808
1809         pHalFunc->inirp_init = &rtl8723au_inirp_init;
1810         pHalFunc->inirp_deinit = &rtl8723au_inirp_deinit;
1811
1812         pHalFunc->init_xmit_priv = &rtl8723au_init_xmit_priv;
1813         pHalFunc->free_xmit_priv = &rtl8723au_free_xmit_priv;
1814
1815         pHalFunc->init_recv_priv = &rtl8723au_init_recv_priv;
1816         pHalFunc->free_recv_priv = &rtl8723au_free_recv_priv;
1817         pHalFunc->InitSwLeds = NULL;
1818         pHalFunc->DeInitSwLeds = NULL;
1819
1820         pHalFunc->init_default_value = &rtl8723au_init_default_value;
1821         pHalFunc->intf_chip_configure = &rtl8723au_interface_configure;
1822         pHalFunc->read_adapter_info = &ReadAdapterInfo8723AU;
1823         pHalFunc->SetHwRegHandler = &SetHwReg8723AU;
1824         pHalFunc->GetHwRegHandler = &GetHwReg8723AU;
1825         pHalFunc->GetHalDefVarHandler = &GetHalDefVar8192CUsb;
1826         pHalFunc->SetHalDefVarHandler = &SetHalDefVar8192CUsb;
1827         pHalFunc->UpdateRAMaskHandler = &UpdateHalRAMask8192CUsb;
1828         pHalFunc->hal_xmit = &rtl8723au_hal_xmit;
1829         pHalFunc->mgnt_xmit = &rtl8723au_mgnt_xmit;
1830         pHalFunc->hal_xmitframe_enqueue = &rtl8723au_hal_xmitframe_enqueue;
1831         pHalFunc->interface_ps_func = &rtl8192cu_ps_func;
1832         rtl8723a_set_hal_ops(pHalFunc);
1833         return 0;
1834 }