drivers/staging/rtl8723au/include/Hal8723APhyCfg.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  *
  15  ******************************************************************************/
  16 #ifndef __INC_HAL8723PHYCFG_H__
  17 #define __INC_HAL8723PHYCFG_H__
  18
  19 /*--------------------------Define Parameters-------------------------------*/
  20 #define LOOP_LIMIT                              5
  21 #define MAX_STALL_TIME          50              /* us */
  22 #define AntennaDiversityValue   0x80
  23 #define MAX_TXPWR_IDX_NMODE_92S 63
  24 #define Reset_Cnt_Limit         3
  25
  26
  27 #define MAX_AGGR_NUM    0x0909
  28
  29 /*--------------------------Define Parameters-------------------------------*/
  30
  31
  32 /*------------------------------Define structure----------------------------*/
  33 enum swchnlcmdid {
  34         CmdID_End,
  35         CmdID_SetTxPowerLevel,
  36         CmdID_BBRegWrite10,
  37         CmdID_WritePortUlong,
  38         CmdID_WritePortUshort,
  39         CmdID_WritePortUchar,
  40         CmdID_RF_WriteReg,
  41 };
  42
  43
  44 /* 1. Switch channel related */
  45 struct swchnlcmd {
  46         enum swchnlcmdid        CmdID;
  47         u32                     Para1;
  48         u32                     Para2;
  49         u32                     msDelay;
  50 };
  51
  52 enum HW90_BLOCK {
  53         HW90_BLOCK_MAC = 0,
  54         HW90_BLOCK_PHY0 = 1,
  55         HW90_BLOCK_PHY1 = 2,
  56         HW90_BLOCK_RF = 3,
  57         HW90_BLOCK_MAXIMUM = 4, /*  Never use this */
  58 };
  59
  60 enum RF_RADIO_PATH {
  61         RF_PATH_A = 0,                  /* Radio Path A */
  62         RF_PATH_B = 1,                  /* Radio Path B */
  63         RF_PATH_MAX                     /* Max RF number 90 support */
  64 };
  65
  66 #define CHANNEL_MAX_NUMBER              14      /*  14 is the max channel number */
  67 #define CHANNEL_GROUP_MAX               3       /*  ch1~3, ch4~9, ch10~14 total three groups */
  68
  69 enum WIRELESS_MODE {
  70         WIRELESS_MODE_UNKNOWN   = 0x00,
  71         WIRELESS_MODE_A         = BIT(2),
  72         WIRELESS_MODE_B         = BIT(0),
  73         WIRELESS_MODE_G         = BIT(1),
  74         WIRELESS_MODE_AUTO      = BIT(5),
  75         WIRELESS_MODE_N_24G     = BIT(3),
  76         WIRELESS_MODE_N_5G      = BIT(4),
  77         WIRELESS_MODE_AC        = BIT(6)
  78 };
  79
  80 enum baseband_config_type {
  81         BaseBand_Config_PHY_REG = 0,                    /* Radio Path A */
  82         BaseBand_Config_AGC_TAB = 1,                    /* Radio Path B */
  83 };
  84
  85 enum ra_offset_area {
  86         RA_OFFSET_LEGACY_OFDM1,
  87         RA_OFFSET_LEGACY_OFDM2,
  88         RA_OFFSET_HT_OFDM1,
  89         RA_OFFSET_HT_OFDM2,
  90         RA_OFFSET_HT_OFDM3,
  91         RA_OFFSET_HT_OFDM4,
  92         RA_OFFSET_HT_CCK,
  93 };
  94
  95
  96 /* BB/RF related */
  97 enum rf_type_8190p {
  98         RF_TYPE_MIN,            /*  0 */
  99         RF_8225 = 1,            /*  1 11b/g RF for verification only */
 100         RF_8256 = 2,            /*  2 11b/g/n */
 101         RF_8258 = 3,            /*  3 11a/b/g/n RF */
 102         RF_6052 = 4,            /*  4 11b/g/n RF */
 103         RF_PSEUDO_11N = 5,      /*  5, It is a temporality RF. */
 104 };
 105
 106 struct bb_reg_define {
 107         u32 rfintfs;            /*  set software control: */
 108                                 /*              0x870~0x877[8 bytes] */
 109         u32 rfintfi;            /*  readback data: */
 110                                 /*              0x8e0~0x8e7[8 bytes] */
 111         u32 rfintfo;            /*  output data: */
 112                                 /*              0x860~0x86f [16 bytes] */
 113         u32 rfintfe;            /*  output enable: */
 114                                 /*              0x860~0x86f [16 bytes] */
 115         u32 rf3wireOffset;      /*  LSSI data: */
 116                                 /*              0x840~0x84f [16 bytes] */
 117         u32 rfLSSI_Select;      /*  BB Band Select: */
 118                                 /*              0x878~0x87f [8 bytes] */
 119         u32 rfTxGainStage;      /*  Tx gain stage: */
 120                                 /*              0x80c~0x80f [4 bytes] */
 121         u32 rfHSSIPara1;        /*  wire parameter control1 : */
 122                                 /*              0x820~0x823, 0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes] */
 123         u32 rfHSSIPara2;        /*  wire parameter control2 : */
 124                                 /*              0x824~0x827, 0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes] */
 125         u32 rfSwitchControl; /* Tx Rx antenna control : */
 126                                 /*              0x858~0x85f [16 bytes] */
 127         u32 rfAGCControl1;      /* AGC parameter control1 : */
 128                                 /*      0xc50~0xc53, 0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes] */
 129         u32 rfAGCControl2;      /* AGC parameter control2 : */
 130                                 /*              0xc54~0xc57, 0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes] */
 131         u32 rfRxIQImbalance; /* OFDM Rx IQ imbalance matrix : */
 132                                 /*              0xc14~0xc17, 0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes] */
 133         u32 rfRxAFE;            /* Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : */
 134                                 /*      0xc10~0xc13, 0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes] */
 135         u32 rfTxIQImbalance; /* OFDM Tx IQ imbalance matrix */
 136                                 /*      0xc80~0xc83, 0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes] */
 137         u32 rfTxAFE;            /* Tx IQ DC Offset and Tx DFIR type */
 138                                 /*      0xc84~0xc87, 0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes] */
 139         u32 rfLSSIReadBack;     /* LSSI RF readback data SI mode */
 140                                 /*      0x8a0~0x8af [16 bytes] */
 141         u32 rfLSSIReadBackPi;   /* LSSI RF readback data PI mode 0x8b8-8bc for Path A and B */
 142 };
 143
 144 struct r_antenna_sel_ofdm {
 145         u32                     r_tx_antenna:4;
 146         u32                     r_ant_l:4;
 147         u32                     r_ant_non_ht:4;
 148         u32                     r_ant_ht1:4;
 149         u32                     r_ant_ht2:4;
 150         u32                     r_ant_ht_s1:4;
 151         u32                     r_ant_non_ht_s1:4;
 152         u32                     OFDM_TXSC:2;
 153         u32                     Reserved:2;
 154 };
 155
 156 struct r_antenna_sel_cck {
 157         u8                      r_cckrx_enable_2:2;
 158         u8                      r_cckrx_enable:2;
 159         u8                      r_ccktx_enable:4;
 160 };
 161
 162 /*------------------------------Define structure----------------------------*/
 163
 164
 165 /*------------------------Export global variable----------------------------*/
 166 /*------------------------Export global variable----------------------------*/
 167
 168
 169 /*------------------------Export Macro Definition---------------------------*/
 170 /*------------------------Export Macro Definition---------------------------*/
 171
 172
 173 /*--------------------------Exported Function prototype---------------------*/
 174 /*  */
 175 /*  BB and RF register read/write */
 176 /*  */
 177 u32     PHY_QueryBBReg(struct rtw_adapter *Adapter, u32 RegAddr,
 178                        u32 BitMask);
 179 void    PHY_SetBBReg(struct rtw_adapter *Adapter, u32 RegAddr,
 180                      u32 BitMask, u32 Data);
 181 u32     PHY_QueryRFReg(struct rtw_adapter *Adapter,
 182                        enum RF_RADIO_PATH       eRFPath, u32 RegAddr,
 183                        u32 BitMask);
 184 void    PHY_SetRFReg(struct rtw_adapter *Adapter,
 185                      enum RF_RADIO_PATH eRFPath, u32 RegAddr,
 186                      u32 BitMask,  u32  Data);
 187
 188 /*  */
 189 /*  BB TX Power R/W */
 190 /*  */
 191 void PHY_SetTxPowerLevel8723A(struct rtw_adapter *Adapter, u8 channel);
 192
 193 /*  */
 194 /*  Switch bandwidth for 8723A */
 195 /*  */
 196 void    PHY_SetBWMode23a8723A(struct rtw_adapter *pAdapter,
 197                            enum ht_channel_width ChnlWidth,
 198                            unsigned char Offset);
 199
 200 /*  */
 201 /*  channel switch related funciton */
 202 /*  */
 203 void    PHY_SwChnl8723A(struct rtw_adapter *pAdapter, u8 channel);
 204                                 /*  Call after initialization */
 205 void ChkFwCmdIoDone(struct rtw_adapter *Adapter);
 206
 207 /*  */
 208 /*  Modify the value of the hw register when beacon interval be changed. */
 209 /*  */
 210 void
 211 rtl8192c_PHY_SetBeaconHwReg(struct rtw_adapter *Adapter, u16 BeaconInterval);
 212
 213
 214 void PHY_SwitchEphyParameter(struct rtw_adapter *Adapter);
 215
 216 void PHY_EnableHostClkReq(struct rtw_adapter *Adapter);
 217
 218 bool
 219 SetAntennaConfig92C(struct rtw_adapter *Adapter, u8 DefaultAnt);
 220
 221 /*--------------------------Exported Function prototype---------------------*/
 222
 223 #define PHY_SetMacReg   PHY_SetBBReg
 224
 225 /* MAC/BB/RF HAL config */
 226 int PHY_BBConfig8723A(struct rtw_adapter *Adapter);
 227 s32 PHY_MACConfig8723A(struct rtw_adapter *padapter);
 228
 229 #endif