drivers/staging/rts5139/xd.c

   1 /* Driver for Realtek RTS51xx USB card reader
   2  *
   3  * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2, or (at your option) any
   8  * later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * Author:
  19  *   wwang (wei_wang@realsil.com.cn)
  20  *   No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
  21  * Maintainer:
  22  *   Edwin Rong (edwin_rong@realsil.com.cn)
  23  *   No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
  24  */
  25
  26 #include <linux/blkdev.h>
  27 #include <linux/kthread.h>
  28 #include <linux/sched.h>
  29 #include <linux/vmalloc.h>
  30
  31 #include "debug.h"
  32 #include "trace.h"
  33 #include "rts51x.h"
  34 #include "rts51x_transport.h"
  35 #include "rts51x_scsi.h"
  36 #include "rts51x_card.h"
  37 #include "xd.h"
  38
  39 static int xd_build_l2p_tbl(struct rts51x_chip *chip, int zone_no);
  40 static int xd_init_page(struct rts51x_chip *chip, u32 phy_blk, u16 logoff,
  41                         u8 start_page, u8 end_page);
  42
  43 static inline void xd_set_err_code(struct rts51x_chip *chip, u8 err_code)
  44 {
  45         struct xd_info *xd_card = &(chip->xd_card);
  46
  47         xd_card->err_code = err_code;
  48 }
  49
  50 static int xd_set_init_para(struct rts51x_chip *chip)
  51 {
  52         struct xd_info *xd_card = &(chip->xd_card);
  53         int retval;
  54
  55         if (chip->asic_code)
  56                 xd_card->xd_clock = 47;
  57         else
  58                 xd_card->xd_clock = CLK_50;
  59
  60         retval = switch_clock(chip, xd_card->xd_clock);
  61         if (retval != STATUS_SUCCESS)
  62                 TRACE_RET(chip, retval);
  63
  64         return STATUS_SUCCESS;
  65 }
  66
  67 static int xd_switch_clock(struct rts51x_chip *chip)
  68 {
  69         struct xd_info *xd_card = &(chip->xd_card);
  70         int retval;
  71
  72         retval = rts51x_select_card(chip, XD_CARD);
  73         if (retval != STATUS_SUCCESS)
  74                 TRACE_RET(chip, retval);
  75
  76         retval = switch_clock(chip, xd_card->xd_clock);
  77         if (retval != STATUS_SUCCESS)
  78                 TRACE_RET(chip, retval);
  79
  80         return STATUS_SUCCESS;
  81 }
  82
  83 static int xd_read_id(struct rts51x_chip *chip, u8 id_cmd, u8 *id_buf,
  84                       u8 buf_len)
  85 {
  86         int retval, i;
  87
  88         rts51x_init_cmd(chip);
  89
  90         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_DAT, 0xFF, id_cmd);
  91         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
  92                        XD_TRANSFER_START | XD_READ_ID);
  93         rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END,
  94                        XD_TRANSFER_END);
  95
  96         for (i = 0; i < 4; i++) {
  97                 rts51x_add_cmd(chip, READ_REG_CMD, (u16) (XD_ADDRESS1 + i), 0,
  98                                0);
  99         }
 100
 101         retval = rts51x_send_cmd(chip, MODE_CR, 20);
 102         if (retval != STATUS_SUCCESS)
 103                 TRACE_RET(chip, retval);
 104
 105         retval = rts51x_get_rsp(chip, 5, 20);
 106
 107         if (retval != STATUS_SUCCESS) {
 108                 rts51x_clear_xd_error(chip);
 109                 TRACE_RET(chip, retval);
 110         }
 111
 112         if (id_buf && buf_len) {
 113                 if (buf_len > 4)
 114                         buf_len = 4;
 115                 rts51x_read_rsp_buf(chip, 1, id_buf, buf_len);
 116         }
 117
 118         return STATUS_SUCCESS;
 119 }
 120
 121 static void xd_assign_phy_addr(struct rts51x_chip *chip, u32 addr, u8 mode)
 122 {
 123         struct xd_info *xd_card = &(chip->xd_card);
 124
 125         switch (mode) {
 126         case XD_RW_ADDR:
 127                 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS0, 0xFF, 0);
 128                 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS1, 0xFF,
 129                                (u8) addr);
 130                 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS2, 0xFF,
 131                                (u8) (addr >> 8));
 132                 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS3, 0xFF,
 133                                (u8) (addr >> 16));
 134                 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CFG, 0xFF,
 135                                xd_card->addr_cycle | XD_CALC_ECC |
 136                                XD_BA_NO_TRANSFORM);
 137                 break;
 138
 139         case XD_ERASE_ADDR:
 140                 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS0, 0xFF,
 141                                (u8) addr);
 142                 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS1, 0xFF,
 143                                (u8) (addr >> 8));
 144                 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS2, 0xFF,
 145                                (u8) (addr >> 16));
 146                 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CFG, 0xFF,
 147                                (xd_card->addr_cycle - 1) |
 148                                XD_CALC_ECC | XD_BA_NO_TRANSFORM);
 149                 break;
 150
 151         default:
 152                 break;
 153         }
 154 }
 155
 156 static int xd_read_redundant(struct rts51x_chip *chip, u32 page_addr, u8 *buf,
 157                              int buf_len)
 158 {
 159         int retval, i;
 160
 161         rts51x_init_cmd(chip);
 162
 163         xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
 164
 165         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
 166                        XD_TRANSFER_START | XD_READ_REDUNDANT);
 167         rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END,
 168                        XD_TRANSFER_END);
 169
 170         for (i = 0; i < 6; i++) {
 171                 rts51x_add_cmd(chip, READ_REG_CMD, (u16) (XD_PAGE_STATUS + i),
 172                                0, 0);
 173         }
 174         for (i = 0; i < 4; i++) {
 175                 rts51x_add_cmd(chip, READ_REG_CMD, (u16) (XD_RESERVED0 + i), 0,
 176                                0);
 177         }
 178         rts51x_add_cmd(chip, READ_REG_CMD, XD_PARITY, 0, 0);
 179
 180         retval = rts51x_send_cmd(chip, MODE_CR, 100);
 181         if (retval != STATUS_SUCCESS)
 182                 TRACE_RET(chip, retval);
 183
 184         retval = rts51x_get_rsp(chip, 11, 500);
 185
 186         if (retval != STATUS_SUCCESS) {
 187                 rts51x_clear_xd_error(chip);
 188                 TRACE_RET(chip, retval);
 189         }
 190
 191         if (buf && buf_len) {
 192                 if (buf_len > 11)
 193                         buf_len = 11;
 194                 rts51x_read_rsp_buf(chip, 1, buf, buf_len);
 195         }
 196
 197         return STATUS_SUCCESS;
 198 }
 199
 200 static int xd_read_data_from_ppb(struct rts51x_chip *chip, int offset, u8 *buf,
 201                                  int buf_len)
 202 {
 203         int retval, i;
 204
 205         if (!buf || (buf_len <= 0))
 206                 TRACE_RET(chip, STATUS_FAIL);
 207
 208         rts51x_init_cmd(chip);
 209
 210         for (i = 0; i < buf_len; i++) {
 211                 rts51x_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + offset + i, 0,
 212                                0);
 213         }
 214
 215         retval = rts51x_send_cmd(chip, MODE_CR, 100);
 216         if (retval != STATUS_SUCCESS)
 217                 TRACE_RET(chip, retval);
 218
 219         retval = rts51x_get_rsp(chip, buf_len, 200);
 220         if (retval != STATUS_SUCCESS)
 221                 TRACE_RET(chip, retval);
 222
 223         rts51x_read_rsp_buf(chip, 0, buf, buf_len);
 224
 225         return STATUS_SUCCESS;
 226 }
 227
 228 static int xd_read_cis(struct rts51x_chip *chip, u32 page_addr, u8 *buf,
 229                        int buf_len)
 230 {
 231         int retval;
 232         u8 reg;
 233
 234         if (!buf || (buf_len < 10))
 235                 TRACE_RET(chip, STATUS_FAIL);
 236
 237         rts51x_init_cmd(chip);
 238
 239         xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
 240
 241         rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
 242                        PINGPONG_BUFFER);
 243         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1);
 244         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS,
 245                        XD_AUTO_CHK_DATA_STATUS, XD_AUTO_CHK_DATA_STATUS);
 246
 247         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
 248                        XD_TRANSFER_START | XD_READ_PAGES);
 249         rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
 250                        XD_TRANSFER_END | XD_PPB_EMPTY,
 251                        XD_TRANSFER_END | XD_PPB_EMPTY);
 252
 253         retval = rts51x_send_cmd(chip, MODE_CR, 100);
 254         if (retval != STATUS_SUCCESS)
 255                 TRACE_RET(chip, retval);
 256
 257         retval = rts51x_get_rsp(chip, 1, 500);
 258         if (retval == STATUS_TIMEDOUT) {
 259                 rts51x_clear_xd_error(chip);
 260                 TRACE_RET(chip, retval);
 261         }
 262
 263         RTS51X_READ_REG(chip, XD_PAGE_STATUS, &reg);
 264         if (reg != XD_GPG) {
 265                 rts51x_clear_xd_error(chip);
 266                 TRACE_RET(chip, STATUS_FAIL);
 267         }
 268
 269         RTS51X_READ_REG(chip, XD_CTL, &reg);
 270
 271         if (!(reg & XD_ECC1_ERROR) || !(reg & XD_ECC1_UNCORRECTABLE)) {
 272                 retval = xd_read_data_from_ppb(chip, 0, buf, buf_len);
 273                 if (retval != STATUS_SUCCESS)
 274                         TRACE_RET(chip, retval);
 275                 if (reg & XD_ECC1_ERROR) {      /* correctable error */
 276                         u8 ecc_bit, ecc_byte;
 277
 278                         RTS51X_READ_REG(chip, XD_ECC_BIT1, &ecc_bit);
 279                         RTS51X_READ_REG(chip, XD_ECC_BYTE1, &ecc_byte);
 280
 281                         RTS51X_DEBUGP("ECC_BIT1 = 0x%x, ECC_BYTE1 = 0x%x\n",
 282                                        ecc_bit, ecc_byte);
 283                         if (ecc_byte < buf_len) {
 284                                 RTS51X_DEBUGP("Before correct: 0x%x\n",
 285                                                buf[ecc_byte]);
 286                                 buf[ecc_byte] ^= (1 << ecc_bit);
 287                                 RTS51X_DEBUGP("After correct: 0x%x\n",
 288                                                buf[ecc_byte]);
 289                         }
 290                 }
 291         } else if (!(reg & XD_ECC2_ERROR) || !(reg & XD_ECC2_UNCORRECTABLE)) {
 292                 RTS51X_WRITE_REG(chip, CARD_STOP, XD_STOP | XD_CLR_ERR,
 293                                  XD_STOP | XD_CLR_ERR);
 294
 295                 retval = xd_read_data_from_ppb(chip, 256, buf, buf_len);
 296                 if (retval != STATUS_SUCCESS)
 297                         TRACE_RET(chip, retval);
 298                 if (reg & XD_ECC2_ERROR) {
 299                         u8 ecc_bit, ecc_byte;
 300
 301                         RTS51X_READ_REG(chip, XD_ECC_BIT2, &ecc_bit);
 302                         RTS51X_READ_REG(chip, XD_ECC_BYTE2, &ecc_byte);
 303
 304                         RTS51X_DEBUGP("ECC_BIT2 = 0x%x, ECC_BYTE2 = 0x%x\n",
 305                                        ecc_bit, ecc_byte);
 306                         if (ecc_byte < buf_len) {
 307                                 RTS51X_DEBUGP("Before correct: 0x%x\n",
 308                                                buf[ecc_byte]);
 309                                 buf[ecc_byte] ^= (1 << ecc_bit);
 310                                 RTS51X_DEBUGP("After correct: 0x%x\n",
 311                                                buf[ecc_byte]);
 312                         }
 313                 }
 314         } else {
 315                 rts51x_clear_xd_error(chip);
 316                 TRACE_RET(chip, STATUS_FAIL);
 317         }
 318
 319         return STATUS_SUCCESS;
 320 }
 321
 322 static void xd_pull_ctl_disable(struct rts51x_chip *chip)
 323 {
 324         if (CHECK_PKG(chip, LQFP48)) {
 325                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x55);
 326                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
 327                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);
 328                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
 329                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x55);
 330                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0xA5);
 331         } else {
 332                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x65);
 333                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
 334                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);
 335                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
 336                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x56);
 337                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0x59);
 338         }
 339 }
 340
 341 static void xd_pull_ctl_enable(struct rts51x_chip *chip)
 342 {
 343         if (CHECK_PKG(chip, LQFP48)) {
 344                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0xAA);
 345                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
 346                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);
 347                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
 348                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x55);
 349                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0xA5);
 350         } else {
 351                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0xA5);
 352                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x59);
 353                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);
 354                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
 355                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x55);
 356                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0x59);
 357         }
 358 }
 359
 360 static int reset_xd(struct rts51x_chip *chip)
 361 {
 362         struct xd_info *xd_card = &(chip->xd_card);
 363         int retval, i, j;
 364         u8 id_buf[4], redunt[11];
 365
 366         retval = rts51x_select_card(chip, XD_CARD);
 367         if (retval != STATUS_SUCCESS)
 368                 TRACE_RET(chip, STATUS_FAIL);
 369
 370         rts51x_init_cmd(chip);
 371
 372         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS, 0xFF,
 373                        XD_PGSTS_NOT_FF);
 374         if (chip->asic_code)
 375                 xd_pull_ctl_disable(chip);
 376         else
 377                 rts51x_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF,
 378                                (FPGA_XD_PULL_CTL_EN1 & FPGA_XD_PULL_CTL_EN3));
 379
 380         if (!chip->option.FT2_fast_mode) {
 381                 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_INIT, XD_NO_AUTO_PWR_OFF,
 382                                0);
 383                 if (CHECK_PKG(chip, LQFP48) ||
 384                                 chip->option.rts5129_D3318_off_enable) {
 385                         rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL,
 386                                        DV3318_AUTO_PWR_OFF,
 387                                        DV3318_AUTO_PWR_OFF);
 388                 }
 389         }
 390         rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN, 0);
 391         if (!chip->option.FT2_fast_mode) {
 392                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, POWER_MASK,
 393                                POWER_OFF);
 394         }
 395
 396         retval = rts51x_send_cmd(chip, MODE_C, 100);
 397         if (retval != STATUS_SUCCESS)
 398                 TRACE_RET(chip, retval);
 399         if (!chip->option.FT2_fast_mode) {
 400 #ifdef SD_XD_IO_FOLLOW_PWR
 401                 if (CHECK_PKG(chip, LQFP48)
 402                     || chip->option.rts5129_D3318_off_enable) {
 403                         rts51x_write_register(chip, CARD_PWR_CTL,
 404                                         LDO_OFF, LDO_OFF);
 405                 }
 406 #endif
 407
 408                 wait_timeout(250);
 409
 410 #ifdef SD_XD_IO_FOLLOW_PWR
 411                 if (CHECK_PKG(chip, LQFP48)
 412                     || chip->option.rts5129_D3318_off_enable) {
 413                         rts51x_init_cmd(chip);
 414                         if (chip->asic_code) {
 415                                 xd_pull_ctl_enable(chip);
 416                         } else {
 417                                 rts51x_add_cmd(chip, WRITE_REG_CMD,
 418                                         FPGA_PULL_CTL, 0xFF,
 419                                         (FPGA_XD_PULL_CTL_EN1 &
 420                                                 FPGA_XD_PULL_CTL_EN2));
 421                         }
 422                         retval = rts51x_send_cmd(chip, MODE_C, 100);
 423                         if (retval != STATUS_SUCCESS)
 424                                 TRACE_RET(chip, STATUS_FAIL);
 425                 }
 426 #endif
 427
 428                 retval = rts51x_card_power_on(chip, XD_CARD);
 429                 if (retval != STATUS_SUCCESS)
 430                         TRACE_RET(chip, retval);
 431 #ifdef SUPPORT_OCP
 432                 wait_timeout(50);
 433                 rts51x_get_card_status(chip, &(chip->card_status));
 434                 chip->ocp_stat = (chip->card_status >> 4) & 0x03;
 435
 436                 if (chip->ocp_stat & (MS_OCP_NOW | MS_OCP_EVER)) {
 437                         RTS51X_DEBUGP("Over current, OCPSTAT is 0x%x\n",
 438                                        chip->ocp_stat);
 439                         TRACE_RET(chip, STATUS_FAIL);
 440                 }
 441 #endif
 442         }
 443
 444         rts51x_init_cmd(chip);
 445
 446         if (chip->asic_code)
 447                 xd_pull_ctl_enable(chip);
 448         else
 449                 rts51x_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF,
 450                                (FPGA_XD_PULL_CTL_EN1 & FPGA_XD_PULL_CTL_EN2));
 451         rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN,
 452                        XD_OUTPUT_EN);
 453         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CTL, XD_CE_DISEN, XD_CE_DISEN);
 454
 455         retval = rts51x_send_cmd(chip, MODE_C, 100);
 456         if (retval != STATUS_SUCCESS)
 457                 TRACE_RET(chip, STATUS_FAIL);
 458
 459         if (!chip->option.FT2_fast_mode)
 460                 wait_timeout(200);
 461
 462         retval = xd_set_init_para(chip);
 463         if (retval != STATUS_SUCCESS)
 464                 TRACE_RET(chip, STATUS_FAIL);
 465         /* Read ID to check if the timing setting is right */
 466         for (i = 0; i < 4; i++) {
 467                 u8 xd_dat, xd_ctl;
 468
 469                 if (monitor_card_cd(chip, XD_CARD) == CD_NOT_EXIST)
 470                         TRACE_RET(chip, STATUS_FAIL);
 471
 472                 rts51x_init_cmd(chip);
 473                 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_DTCTL, 0xFF,
 474                         XD_TIME_SETUP_STEP * 3 + XD_TIME_RW_STEP *
 475                         (2 + i + chip->option.rts51x_xd_rw_step)
 476                         + XD_TIME_RWN_STEP *
 477                         (i + chip->option.rts51x_xd_rwn_step));
 478                 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CATCTL, 0xFF,
 479                         XD_TIME_SETUP_STEP * 3 + XD_TIME_RW_STEP * (4 +
 480                         i) + XD_TIME_RWN_STEP * (3 + i));
 481
 482                 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
 483                                XD_TRANSFER_START | XD_RESET);
 484                 rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
 485                                XD_TRANSFER_END, XD_TRANSFER_END);
 486
 487                 rts51x_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0);
 488                 rts51x_add_cmd(chip, READ_REG_CMD, XD_CTL, 0, 0);
 489
 490                 retval = rts51x_send_cmd(chip, MODE_CR, 100);
 491                 if (retval != STATUS_SUCCESS) {
 492                         rts51x_clear_xd_error(chip);
 493                         TRACE_RET(chip, retval);
 494                 }
 495
 496                 retval = rts51x_get_rsp(chip, 3, 100);
 497                 if (retval != STATUS_SUCCESS) {
 498                         rts51x_clear_xd_error(chip);
 499                         TRACE_RET(chip, retval);
 500                 }
 501
 502                 xd_dat = chip->rsp_buf[1];
 503                 xd_ctl = chip->rsp_buf[2];
 504                 RTS51X_DEBUGP("XD_DAT: 0x%x, XD_CTL: 0x%x\n", xd_dat, xd_ctl);
 505
 506                 if (((xd_dat & READY_FLAG) != READY_STATE)
 507                     || !(xd_ctl & XD_RDY))
 508                         continue;
 509
 510                 retval = xd_read_id(chip, READ_ID, id_buf, 4);
 511                 if (retval != STATUS_SUCCESS)
 512                         TRACE_RET(chip, retval);
 513
 514                 RTS51X_DEBUGP("READ_ID: 0x%x 0x%x 0x%x 0x%x\n",
 515                                id_buf[0], id_buf[1], id_buf[2], id_buf[3]);
 516
 517                 xd_card->device_code = id_buf[1];
 518
 519                 switch (xd_card->device_code) {
 520                 case XD_4M_X8_512_1:
 521                 case XD_4M_X8_512_2:
 522                         xd_card->block_shift = 4;       /* 16 pages per block */
 523                         xd_card->page_off = 0x0F;
 524                         xd_card->addr_cycle = 3;
 525                         xd_card->zone_cnt = 1;
 526                         xd_card->capacity = 8000;       /* 500 * 2 ^ 4 */
 527                         XD_SET_4MB(xd_card);
 528                         break;
 529                 case XD_8M_X8_512:
 530                         xd_card->block_shift = 4;
 531                         xd_card->page_off = 0x0F;
 532                         xd_card->addr_cycle = 3;
 533                         xd_card->zone_cnt = 1;
 534                         xd_card->capacity = 16000;      /* 1000 * 2 ^ 4 */
 535                         break;
 536                 case XD_16M_X8_512:
 537                         XD_PAGE_512(xd_card);   /* 32 pages per block */
 538                         xd_card->addr_cycle = 3;
 539                         xd_card->zone_cnt = 1;
 540                         xd_card->capacity = 32000;      /* 1000 * 2 ^ 5 */
 541                         break;
 542                 case XD_32M_X8_512:
 543                         XD_PAGE_512(xd_card);
 544                         xd_card->addr_cycle = 3;
 545                         xd_card->zone_cnt = 2;
 546                         xd_card->capacity = 64000;      /* 2000 * 2 ^ 5 */
 547                         break;
 548                 case XD_64M_X8_512:
 549                         XD_PAGE_512(xd_card);
 550                         xd_card->addr_cycle = 4;
 551                         xd_card->zone_cnt = 4;
 552                         xd_card->capacity = 128000;     /* 4000 * 2 ^ 5 */
 553                         break;
 554                 case XD_128M_X8_512:
 555                         XD_PAGE_512(xd_card);
 556                         xd_card->addr_cycle = 4;
 557                         xd_card->zone_cnt = 8;
 558                         xd_card->capacity = 256000;     /* 8000 * 2 ^ 5 */
 559                         break;
 560                 case XD_256M_X8_512:
 561                         XD_PAGE_512(xd_card);
 562                         xd_card->addr_cycle = 4;
 563                         xd_card->zone_cnt = 16;
 564                         xd_card->capacity = 512000;     /* 16000 * 2 ^ 5 */
 565                         break;
 566                 case XD_512M_X8:
 567                         XD_PAGE_512(xd_card);
 568                         xd_card->addr_cycle = 4;
 569                         xd_card->zone_cnt = 32;
 570                         xd_card->capacity = 1024000;    /* 32000 * 2 ^ 5 */
 571                         break;
 572                 case xD_1G_X8_512:
 573                         XD_PAGE_512(xd_card);
 574                         xd_card->addr_cycle = 4;
 575                         xd_card->zone_cnt = 64;
 576                         xd_card->capacity = 2048000;    /* 64000 * 2 ^ 5 */
 577                         break;
 578                 case xD_2G_X8_512:
 579                         XD_PAGE_512(xd_card);
 580                         xd_card->addr_cycle = 4;
 581                         xd_card->zone_cnt = 128;
 582                         xd_card->capacity = 4096000;    /* 128000 * 2 ^ 5 */
 583                         break;
 584                 default:
 585                         continue;
 586                 }
 587
 588                 /* Confirm timing setting */
 589                 for (j = 0; j < 10; j++) {
 590                         retval = xd_read_id(chip, READ_ID, id_buf, 4);
 591                         if (retval != STATUS_SUCCESS)
 592                                 TRACE_RET(chip, retval);
 593
 594                         if (id_buf[1] != xd_card->device_code)
 595                                 break;
 596                 }
 597
 598                 /* Current timing pass */
 599                 if (j == 10)
 600                         break;
 601         }
 602
 603         if (i == 4) {
 604                 xd_card->block_shift = 0;
 605                 xd_card->page_off = 0;
 606                 xd_card->addr_cycle = 0;
 607                 xd_card->capacity = 0;
 608
 609                 TRACE_RET(chip, STATUS_FAIL);
 610         }
 611
 612         retval = xd_read_id(chip, READ_xD_ID, id_buf, 4);
 613         if (retval != STATUS_SUCCESS)
 614                 TRACE_RET(chip, retval);
 615         RTS51X_DEBUGP("READ_xD_ID: 0x%x 0x%x 0x%x 0x%x\n",
 616                        id_buf[0], id_buf[1], id_buf[2], id_buf[3]);
 617         if (id_buf[2] != XD_ID_CODE)
 618                 TRACE_RET(chip, STATUS_FAIL);
 619
 620         /* Search CIS block */
 621         for (i = 0; i < 24; i++) {
 622                 u32 page_addr;
 623
 624                 if (monitor_card_cd(chip, XD_CARD) == CD_NOT_EXIST)
 625                         TRACE_RET(chip, STATUS_FAIL);
 626
 627                 page_addr = (u32) i << xd_card->block_shift;
 628
 629                 for (j = 0; j < 3; j++) {
 630                         retval = xd_read_redundant(chip, page_addr, redunt, 11);
 631                         if (retval == STATUS_SUCCESS)
 632                                 break;
 633                 }
 634                 if (j == 3)
 635                         continue;
 636
 637                 if (redunt[BLOCK_STATUS] != XD_GBLK)
 638                         continue;
 639
 640                 j = 0;
 641                 /* Check page status */
 642                 if (redunt[PAGE_STATUS] != XD_GPG) {
 643                         for (j = 1; j <= 8; j++) {
 644                                 retval =
 645                                     xd_read_redundant(chip, page_addr + j,
 646                                                       redunt, 11);
 647                                 if (retval == STATUS_SUCCESS) {
 648                                         if (redunt[PAGE_STATUS] == XD_GPG)
 649                                                 break;
 650                                 }
 651                         }
 652
 653                         if (j == 9)
 654                                 break;
 655                 }
 656
 657                 if ((redunt[BLOCK_STATUS] == XD_GBLK)
 658                     && (redunt[PARITY] & XD_BA1_ALL0)) {
 659                         u8 buf[10];
 660
 661                         page_addr += j;
 662
 663                         retval = xd_read_cis(chip, page_addr, buf, 10);
 664                         if (retval != STATUS_SUCCESS)
 665                                 TRACE_RET(chip, retval);
 666
 667                         if ((buf[0] == 0x01) && (buf[1] == 0x03)
 668                             && (buf[2] == 0xD9)
 669                             && (buf[3] == 0x01) && (buf[4] == 0xFF)
 670                             && (buf[5] == 0x18) && (buf[6] == 0x02)
 671                             && (buf[7] == 0xDF) && (buf[8] == 0x01)
 672                             && (buf[9] == 0x20)) {
 673                                 xd_card->cis_block = (u16) i;
 674                         }
 675                 }
 676
 677                 break;
 678         }
 679
 680         RTS51X_DEBUGP("CIS block: 0x%x\n", xd_card->cis_block);
 681         if (xd_card->cis_block == 0xFFFF)
 682                 TRACE_RET(chip, STATUS_FAIL);
 683
 684         chip->capacity[chip->card2lun[XD_CARD]] = xd_card->capacity;
 685
 686         return STATUS_SUCCESS;
 687 }
 688
 689 static int xd_check_data_blank(u8 *redunt)
 690 {
 691         int i;
 692
 693         for (i = 0; i < 6; i++) {
 694                 if (redunt[PAGE_STATUS + i] != 0xFF)
 695                         return 0;
 696         }
 697
 698         if ((redunt[PARITY] & (XD_ECC1_ALL1 | XD_ECC2_ALL1)) !=
 699             (XD_ECC1_ALL1 | XD_ECC2_ALL1))
 700                 return 0;
 701
 702         for (i = 0; i < 4; i++) {
 703                 if (redunt[RESERVED0 + i] != 0xFF)
 704                         return 0;
 705         }
 706
 707         return 1;
 708 }
 709
 710 static u16 xd_load_log_block_addr(u8 *redunt)
 711 {
 712         u16 addr = 0xFFFF;
 713
 714         if (redunt[PARITY] & XD_BA1_BA2_EQL)
 715                 addr =
 716                     ((u16) redunt[BLOCK_ADDR1_H] << 8) | redunt[BLOCK_ADDR1_L];
 717         else if (redunt[PARITY] & XD_BA1_VALID)
 718                 addr =
 719                     ((u16) redunt[BLOCK_ADDR1_H] << 8) | redunt[BLOCK_ADDR1_L];
 720         else if (redunt[PARITY] & XD_BA2_VALID)
 721                 addr =
 722                     ((u16) redunt[BLOCK_ADDR2_H] << 8) | redunt[BLOCK_ADDR2_L];
 723
 724         return addr;
 725 }
 726
 727 static int xd_init_l2p_tbl(struct rts51x_chip *chip)
 728 {
 729         struct xd_info *xd_card = &(chip->xd_card);
 730         int size, i;
 731
 732         RTS51X_DEBUGP("xd_init_l2p_tbl: zone_cnt = %d\n", xd_card->zone_cnt);
 733
 734         if (xd_card->zone_cnt < 1)
 735                 TRACE_RET(chip, STATUS_FAIL);
 736
 737         size = xd_card->zone_cnt * sizeof(struct zone_entry);
 738         RTS51X_DEBUGP("Buffer size for l2p table is %d\n", size);
 739
 740         xd_card->zone = vmalloc(size);
 741         if (!xd_card->zone)
 742                 TRACE_RET(chip, STATUS_NOMEM);
 743
 744         for (i = 0; i < xd_card->zone_cnt; i++) {
 745                 xd_card->zone[i].build_flag = 0;
 746                 xd_card->zone[i].l2p_table = NULL;
 747                 xd_card->zone[i].free_table = NULL;
 748                 xd_card->zone[i].get_index = 0;
 749                 xd_card->zone[i].set_index = 0;
 750                 xd_card->zone[i].unused_blk_cnt = 0;
 751         }
 752
 753         return STATUS_SUCCESS;
 754 }
 755
 756 static inline void free_zone(struct zone_entry *zone)
 757 {
 758         RTS51X_DEBUGP("free_zone\n");
 759         if (!zone)
 760                 return;
 761         zone->build_flag = 0;
 762         zone->set_index = 0;
 763         zone->get_index = 0;
 764         zone->unused_blk_cnt = 0;
 765         if (zone->l2p_table) {
 766                 vfree(zone->l2p_table);
 767                 zone->l2p_table = NULL;
 768         }
 769         if (zone->free_table) {
 770                 vfree(zone->free_table);
 771                 zone->free_table = NULL;
 772         }
 773 }
 774
 775 static void xd_set_unused_block(struct rts51x_chip *chip, u32 phy_blk)
 776 {
 777         struct xd_info *xd_card = &(chip->xd_card);
 778         struct zone_entry *zone;
 779         int zone_no;
 780
 781         zone_no = (int)phy_blk >> 10;
 782         if (zone_no >= xd_card->zone_cnt) {
 783                 RTS51X_DEBUGP("Set unused block to invalid zone"
 784                                         "(zone_no = %d, zone_cnt = %d)\n",
 785                                         zone_no, xd_card->zone_cnt);
 786                 return;
 787         }
 788         zone = &(xd_card->zone[zone_no]);
 789
 790         if (zone->free_table == NULL) {
 791                 if (xd_build_l2p_tbl(chip, zone_no) != STATUS_SUCCESS)
 792                         return;
 793         }
 794
 795         if ((zone->set_index >= XD_FREE_TABLE_CNT)
 796             || (zone->set_index < 0)) {
 797                 free_zone(zone);
 798                 RTS51X_DEBUGP("Set unused block fail, invalid set_index\n");
 799                 return;
 800         }
 801
 802         RTS51X_DEBUGP("Set unused block to index %d\n", zone->set_index);
 803
 804         zone->free_table[zone->set_index++] = (u16) (phy_blk & 0x3ff);
 805         if (zone->set_index >= XD_FREE_TABLE_CNT)
 806                 zone->set_index = 0;
 807         zone->unused_blk_cnt++;
 808 }
 809
 810 static u32 xd_get_unused_block(struct rts51x_chip *chip, int zone_no)
 811 {
 812         struct xd_info *xd_card = &(chip->xd_card);
 813         struct zone_entry *zone;
 814         u32 phy_blk;
 815
 816         if (zone_no >= xd_card->zone_cnt) {
 817                 RTS51X_DEBUGP("Get unused block from invalid zone"
 818                                         "(zone_no = %d, zone_cnt = %d)\n",
 819                                         zone_no, xd_card->zone_cnt);
 820                 TRACE_RET(chip, BLK_NOT_FOUND);
 821         }
 822         zone = &(xd_card->zone[zone_no]);
 823
 824         if ((zone->unused_blk_cnt == 0) ||
 825                         (zone->set_index == zone->get_index)) {
 826                 free_zone(zone);
 827                 RTS51X_DEBUGP("Get unused block fail,"
 828                                         "no unused block available\n");
 829                 TRACE_RET(chip, BLK_NOT_FOUND);
 830         }
 831         if ((zone->get_index >= XD_FREE_TABLE_CNT) || (zone->get_index < 0)) {
 832                 free_zone(zone);
 833                 RTS51X_DEBUGP("Get unused block fail, invalid get_index\n");
 834                 TRACE_RET(chip, BLK_NOT_FOUND);
 835         }
 836
 837         RTS51X_DEBUGP("Get unused block from index %d\n", zone->get_index);
 838
 839         phy_blk = zone->free_table[zone->get_index];
 840         zone->free_table[zone->get_index++] = 0xFFFF;
 841         if (zone->get_index >= XD_FREE_TABLE_CNT)
 842                 zone->get_index = 0;
 843         zone->unused_blk_cnt--;
 844
 845         phy_blk += ((u32) (zone_no) << 10);
 846         return phy_blk;
 847 }
 848
 849 static void xd_set_l2p_tbl(struct rts51x_chip *chip, int zone_no, u16 log_off,
 850                            u16 phy_off)
 851 {
 852         struct xd_info *xd_card = &(chip->xd_card);
 853         struct zone_entry *zone;
 854
 855         zone = &(xd_card->zone[zone_no]);
 856         zone->l2p_table[log_off] = phy_off;
 857 }
 858
 859 static int xd_delay_write(struct rts51x_chip *chip);
 860
 861 static u32 xd_get_l2p_tbl(struct rts51x_chip *chip, int zone_no, u16 log_off)
 862 {
 863         struct xd_info *xd_card = &(chip->xd_card);
 864         struct zone_entry *zone;
 865         int retval;
 866
 867         zone = &(xd_card->zone[zone_no]);
 868         if (zone->l2p_table[log_off] == 0xFFFF) {
 869                 u32 phy_blk = 0;
 870                 int i;
 871
 872                 retval = xd_delay_write(chip);
 873                 if (retval != STATUS_SUCCESS) {
 874                         RTS51X_DEBUGP("In xd_get_l2p_tbl,"
 875                                                 "delay write fail!\n");
 876                         TRACE_RET(chip, BLK_NOT_FOUND);
 877                 }
 878
 879                 if (zone->unused_blk_cnt <= 0) {
 880                         RTS51X_DEBUGP("No unused block!\n");
 881                         TRACE_RET(chip, BLK_NOT_FOUND);
 882                 }
 883
 884                 for (i = 0; i < zone->unused_blk_cnt; i++) {
 885                         phy_blk = xd_get_unused_block(chip, zone_no);
 886                         if (phy_blk == BLK_NOT_FOUND) {
 887                                 RTS51X_DEBUGP("No unused block available!\n");
 888                                 TRACE_RET(chip, BLK_NOT_FOUND);
 889                         }
 890
 891                         retval =
 892                             xd_init_page(chip, phy_blk, log_off, 0,
 893                                          xd_card->page_off + 1);
 894                         if (retval == STATUS_SUCCESS)
 895                                 break;
 896                 }
 897                 if (i >= zone->unused_blk_cnt) {
 898                         RTS51X_DEBUGP("No good unused block available!\n");
 899                         TRACE_RET(chip, BLK_NOT_FOUND);
 900                 }
 901
 902                 xd_set_l2p_tbl(chip, zone_no, log_off, (u16) (phy_blk & 0x3FF));
 903                 return phy_blk;
 904         }
 905
 906         return (u32) zone->l2p_table[log_off] + ((u32) (zone_no) << 10);
 907 }
 908
 909 int rts51x_reset_xd_card(struct rts51x_chip *chip)
 910 {
 911         struct xd_info *xd_card = &(chip->xd_card);
 912         int retval;
 913
 914         memset(xd_card, 0, sizeof(struct xd_info));
 915
 916         xd_card->block_shift = 0;
 917         xd_card->page_off = 0;
 918         xd_card->addr_cycle = 0;
 919         xd_card->capacity = 0;
 920         xd_card->zone_cnt = 0;
 921         xd_card->cis_block = 0xFFFF;
 922         xd_card->delay_write.delay_write_flag = 0;
 923
 924         rts51x_enable_card_clock(chip, XD_CARD);
 925
 926         retval = reset_xd(chip);
 927         if (retval != STATUS_SUCCESS) {
 928                 if (chip->option.reset_or_rw_fail_set_pad_drive) {
 929                         rts51x_write_register(chip, CARD_DRIVE_SEL,
 930                                               SD20_DRIVE_MASK, DRIVE_8mA);
 931                 }
 932                 TRACE_RET(chip, retval);
 933         }
 934
 935         retval = xd_init_l2p_tbl(chip);
 936         if (retval != STATUS_SUCCESS)
 937                 TRACE_RET(chip, retval);
 938
 939         return STATUS_SUCCESS;
 940 }
 941
 942 static int xd_mark_bad_block(struct rts51x_chip *chip, u32 phy_blk)
 943 {
 944         struct xd_info *xd_card = &(chip->xd_card);
 945         int retval;
 946         u32 page_addr;
 947         u8 reg = 0;
 948
 949         RTS51X_DEBUGP("mark block 0x%x as bad block\n", phy_blk);
 950
 951         if (phy_blk == BLK_NOT_FOUND)
 952                 TRACE_RET(chip, STATUS_FAIL);
 953
 954         rts51x_init_cmd(chip);
 955
 956         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, XD_GPG);
 957         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF,
 958                        XD_LATER_BBLK);
 959         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H, 0xFF, 0xFF);
 960         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF, 0xFF);
 961         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR2_H, 0xFF, 0xFF);
 962         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR2_L, 0xFF, 0xFF);
 963         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED0, 0xFF, 0xFF);
 964         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED1, 0xFF, 0xFF);
 965         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED2, 0xFF, 0xFF);
 966         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED3, 0xFF, 0xFF);
 967
 968         page_addr = phy_blk << xd_card->block_shift;
 969
 970         xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
 971
 972         /* Specify page count */
 973         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF,
 974                        xd_card->page_off + 1);
 975
 976         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
 977                        XD_TRANSFER_START | XD_WRITE_REDUNDANT);
 978         rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END,
 979                        XD_TRANSFER_END);
 980
 981         retval = rts51x_send_cmd(chip, MODE_CR, 100);
 982         if (retval != STATUS_SUCCESS)
 983                 TRACE_RET(chip, STATUS_FAIL);
 984
 985         retval = rts51x_get_rsp(chip, 1, 100);
 986
 987         if (retval != STATUS_SUCCESS) {
 988                 rts51x_clear_xd_error(chip);
 989                 rts51x_ep0_read_register(chip, XD_DAT, &reg);
 990                 if (reg & PROGRAM_ERROR)
 991                         xd_set_err_code(chip, XD_PRG_ERROR);
 992                 else
 993                         xd_set_err_code(chip, XD_TO_ERROR);
 994                 TRACE_RET(chip, STATUS_FAIL);
 995         }
 996
 997         return STATUS_SUCCESS;
 998 }
 999
1000 static int xd_init_page(struct rts51x_chip *chip, u32 phy_blk, u16 logoff,
1001                         u8 start_page, u8 end_page)
1002 {
1003         struct xd_info *xd_card = &(chip->xd_card);
1004         int retval;
1005         u32 page_addr;
1006         u8 reg = 0;
1007
1008         RTS51X_DEBUGP("Init block 0x%x\n", phy_blk);
1009
1010         if (start_page > end_page)
1011                 TRACE_RET(chip, STATUS_FAIL);
1012         if (phy_blk == BLK_NOT_FOUND)
1013                 TRACE_RET(chip, STATUS_FAIL);
1014
1015         rts51x_init_cmd(chip);
1016
1017         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, 0xFF);
1018         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, 0xFF);
1019         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H, 0xFF,
1020                        (u8) (logoff >> 8));
1021         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF,
1022                        (u8) logoff);
1023
1024         page_addr = (phy_blk << xd_card->block_shift) + start_page;
1025
1026         xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
1027
1028         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CFG, XD_BA_TRANSFORM,
1029                        XD_BA_TRANSFORM);
1030
1031         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF,
1032                        (end_page - start_page));
1033
1034         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1035                        XD_TRANSFER_START | XD_WRITE_REDUNDANT);
1036         rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END,
1037                        XD_TRANSFER_END);
1038
1039         retval = rts51x_send_cmd(chip, MODE_CR, 100);
1040         if (retval != STATUS_SUCCESS)
1041                 TRACE_RET(chip, STATUS_FAIL);
1042
1043         retval = rts51x_get_rsp(chip, 1, 500);
1044
1045         if (retval != STATUS_SUCCESS) {
1046                 rts51x_clear_xd_error(chip);
1047                 rts51x_ep0_read_register(chip, XD_DAT, &reg);
1048                 if (reg & PROGRAM_ERROR) {
1049                         xd_mark_bad_block(chip, phy_blk);
1050                         xd_set_err_code(chip, XD_PRG_ERROR);
1051                 } else {
1052                         xd_set_err_code(chip, XD_TO_ERROR);
1053                 }
1054                 TRACE_RET(chip, STATUS_FAIL);
1055         }
1056
1057         return STATUS_SUCCESS;
1058 }
1059
1060 static int xd_copy_page(struct rts51x_chip *chip,
1061                         u32 old_blk, u32 new_blk, u8 start_page, u8 end_page)
1062 {
1063         struct xd_info *xd_card = &(chip->xd_card);
1064         u32 old_page, new_page;
1065         u8 i, reg = 0;
1066         int retval;
1067
1068         RTS51X_DEBUGP("Copy page from block 0x%x to block 0x%x\n", old_blk,
1069                        new_blk);
1070
1071         if (start_page > end_page)
1072                 TRACE_RET(chip, STATUS_FAIL);
1073
1074         if ((old_blk == BLK_NOT_FOUND) || (new_blk == BLK_NOT_FOUND))
1075                 TRACE_RET(chip, STATUS_FAIL);
1076
1077         old_page = (old_blk << xd_card->block_shift) + start_page;
1078         new_page = (new_blk << xd_card->block_shift) + start_page;
1079
1080         XD_CLR_BAD_NEWBLK(xd_card);
1081
1082         RTS51X_WRITE_REG(chip, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
1083
1084         for (i = start_page; i < end_page; i++) {
1085                 if (monitor_card_cd(chip, XD_CARD) == CD_NOT_EXIST) {
1086                         RTS51X_WRITE_REG(chip, CARD_STOP, XD_STOP | XD_CLR_ERR,
1087                                          XD_STOP | XD_CLR_ERR);
1088                         xd_set_err_code(chip, XD_NO_CARD);
1089                         TRACE_RET(chip, STATUS_FAIL);
1090                 }
1091
1092                 rts51x_init_cmd(chip);
1093
1094                 xd_assign_phy_addr(chip, old_page, XD_RW_ADDR);
1095
1096                 /* Single page read */
1097                 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1);
1098                 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS,
1099                                XD_AUTO_CHK_DATA_STATUS, 0);
1100                 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1101                                XD_TRANSFER_START | XD_READ_PAGES);
1102                 rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1103                                XD_TRANSFER_END, XD_TRANSFER_END);
1104
1105                 retval = rts51x_send_cmd(chip, MODE_CR | STAGE_XD_STATUS, 100);
1106                 if (retval != STATUS_SUCCESS)
1107                         TRACE_RET(chip, retval);
1108
1109                 retval = rts51x_get_rsp(chip, 4, 500);
1110                 if ((retval != STATUS_SUCCESS) ||
1111                     (chip->rsp_buf[2] & (XD_ECC1_ERROR | XD_ECC2_ERROR))) {
1112                         rts51x_clear_xd_error(chip);
1113                         reg = 0;
1114                         rts51x_ep0_read_register(chip, XD_CTL, &reg);
1115                         if (reg & (XD_ECC1_ERROR | XD_ECC2_ERROR)) {
1116                                 wait_timeout(100);
1117
1118                                 if (monitor_card_cd(chip, XD_CARD) ==
1119                                     CD_NOT_EXIST) {
1120                                         xd_set_err_code(chip, XD_NO_CARD);
1121                                         TRACE_RET(chip, STATUS_FAIL);
1122                                 }
1123
1124                                 if (((reg &
1125                                       (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE))
1126                                      == (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE))
1127                                     || ((reg & (XD_ECC2_ERROR |
1128                                         XD_ECC2_UNCORRECTABLE)) ==
1129                                      (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE))) {
1130                                         RTS51X_WRITE_REG(chip, XD_PAGE_STATUS,
1131                                                          0xFF, XD_BPG);
1132                                         RTS51X_WRITE_REG(chip, XD_BLOCK_STATUS,
1133                                                          0xFF, XD_GBLK);
1134                                         XD_SET_BAD_OLDBLK(xd_card);
1135                                         RTS51X_DEBUGP("old block 0x%x"
1136                                                 "ecc error\n", old_blk);
1137                                 }
1138                         } else {
1139                                 xd_set_err_code(chip, XD_TO_ERROR);
1140                                 TRACE_RET(chip, STATUS_FAIL);
1141                         }
1142                 }
1143                 if (XD_CHK_BAD_OLDBLK(xd_card))
1144                         rts51x_clear_xd_error(chip);
1145
1146                 rts51x_init_cmd(chip);
1147
1148                 xd_assign_phy_addr(chip, new_page, XD_RW_ADDR);
1149                 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1);
1150                 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1151                                XD_TRANSFER_START | XD_WRITE_PAGES);
1152                 rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1153                                XD_TRANSFER_END, XD_TRANSFER_END);
1154
1155                 retval = rts51x_send_cmd(chip, MODE_CR, 100);
1156                 if (retval != STATUS_SUCCESS)
1157                         TRACE_RET(chip, retval);
1158
1159                 retval = rts51x_get_rsp(chip, 1, 300);
1160                 if (retval != STATUS_SUCCESS) {
1161                         rts51x_clear_xd_error(chip);
1162                         reg = 0;
1163                         rts51x_ep0_read_register(chip, XD_DAT, &reg);
1164                         if (reg & PROGRAM_ERROR) {
1165                                 xd_mark_bad_block(chip, new_blk);
1166                                 xd_set_err_code(chip, XD_PRG_ERROR);
1167                                 XD_SET_BAD_NEWBLK(xd_card);
1168                         } else {
1169                                 xd_set_err_code(chip, XD_TO_ERROR);
1170                         }
1171                         TRACE_RET(chip, retval);
1172                 }
1173
1174                 old_page++;
1175                 new_page++;
1176         }
1177
1178         return STATUS_SUCCESS;
1179 }
1180
1181 static int xd_reset_cmd(struct rts51x_chip *chip)
1182 {
1183         int retval;
1184         u8 xd_dat, xd_ctl;
1185
1186         rts51x_init_cmd(chip);
1187
1188         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1189                        XD_TRANSFER_START | XD_RESET);
1190         rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END,
1191                        XD_TRANSFER_END);
1192         rts51x_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0);
1193         rts51x_add_cmd(chip, READ_REG_CMD, XD_CTL, 0, 0);
1194
1195         retval = rts51x_send_cmd(chip, MODE_CR, 100);
1196         if (retval != STATUS_SUCCESS)
1197                 TRACE_RET(chip, retval);
1198
1199         retval = rts51x_get_rsp(chip, 3, 100);
1200         if (retval != STATUS_SUCCESS) {
1201                 rts51x_clear_xd_error(chip);
1202                 TRACE_RET(chip, retval);
1203         }
1204
1205         xd_dat = chip->rsp_buf[1];
1206         xd_ctl = chip->rsp_buf[2];
1207         if (((xd_dat & READY_FLAG) == READY_STATE) && (xd_ctl & XD_RDY))
1208                 return STATUS_SUCCESS;
1209
1210         TRACE_RET(chip, STATUS_FAIL);
1211 }
1212
1213 static int xd_erase_block(struct rts51x_chip *chip, u32 phy_blk)
1214 {
1215         struct xd_info *xd_card = &(chip->xd_card);
1216         u32 page_addr;
1217         u8 reg = 0, xd_dat;
1218         int i, retval;
1219
1220         if (phy_blk == BLK_NOT_FOUND)
1221                 TRACE_RET(chip, STATUS_FAIL);
1222
1223         page_addr = phy_blk << xd_card->block_shift;
1224
1225         for (i = 0; i < 3; i++) {
1226                 rts51x_init_cmd(chip);
1227
1228                 xd_assign_phy_addr(chip, page_addr, XD_ERASE_ADDR);
1229
1230                 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1231                                XD_TRANSFER_START | XD_ERASE);
1232                 rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1233                                XD_TRANSFER_END, XD_TRANSFER_END);
1234                 rts51x_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0);
1235
1236                 retval = rts51x_send_cmd(chip, MODE_CR, 100);
1237                 if (retval != STATUS_SUCCESS)
1238                         TRACE_RET(chip, retval);
1239
1240                 retval = rts51x_get_rsp(chip, 2, 300);
1241                 if (retval != STATUS_SUCCESS) {
1242                         rts51x_clear_xd_error(chip);
1243                         rts51x_ep0_read_register(chip, XD_DAT, &reg);
1244                         if (reg & PROGRAM_ERROR) {
1245                                 xd_mark_bad_block(chip, phy_blk);
1246                                 xd_set_err_code(chip, XD_PRG_ERROR);
1247                                 TRACE_RET(chip, STATUS_FAIL);
1248                         } else {
1249                                 xd_set_err_code(chip, XD_ERASE_FAIL);
1250                         }
1251                         retval = xd_reset_cmd(chip);
1252                         if (retval != STATUS_SUCCESS)
1253                                 TRACE_RET(chip, retval);
1254                         continue;
1255                 }
1256                 xd_dat = chip->rsp_buf[1];
1257                 if (xd_dat & PROGRAM_ERROR) {
1258                         xd_mark_bad_block(chip, phy_blk);
1259                         xd_set_err_code(chip, XD_PRG_ERROR);
1260                         TRACE_RET(chip, STATUS_FAIL);
1261                 }
1262
1263                 return STATUS_SUCCESS;
1264         }
1265
1266         xd_mark_bad_block(chip, phy_blk);
1267         xd_set_err_code(chip, XD_ERASE_FAIL);
1268         TRACE_RET(chip, STATUS_FAIL);
1269 }
1270
1271 static int xd_build_l2p_tbl(struct rts51x_chip *chip, int zone_no)
1272 {
1273         struct xd_info *xd_card = &(chip->xd_card);
1274         struct zone_entry *zone;
1275         int retval;
1276         u32 start, end, i;
1277         u16 max_logoff, cur_fst_page_logoff, cur_lst_page_logoff,
1278             ent_lst_page_logoff;
1279         u8 redunt[11];
1280
1281         RTS51X_DEBUGP("xd_build_l2p_tbl: %d\n", zone_no);
1282
1283         if (xd_card->zone == NULL) {
1284                 retval = xd_init_l2p_tbl(chip);
1285                 if (retval != STATUS_SUCCESS)
1286                         TRACE_RET(chip, retval);
1287         }
1288
1289         if (xd_card->zone[zone_no].build_flag) {
1290                 RTS51X_DEBUGP("l2p table of zone %d has been built\n",
1291                                zone_no);
1292                 return STATUS_SUCCESS;
1293         }
1294
1295         zone = &(xd_card->zone[zone_no]);
1296
1297         if (zone->l2p_table == NULL) {
1298                 zone->l2p_table = vmalloc(2000);
1299                 if (zone->l2p_table == NULL)
1300                         TRACE_GOTO(chip, Build_Fail);
1301         }
1302         memset((u8 *) (zone->l2p_table), 0xff, 2000);
1303
1304         if (zone->free_table == NULL) {
1305                 zone->free_table = vmalloc(XD_FREE_TABLE_CNT * 2);
1306                 if (zone->free_table == NULL)
1307                         TRACE_GOTO(chip, Build_Fail);
1308         }
1309         memset((u8 *) (zone->free_table), 0xff, XD_FREE_TABLE_CNT * 2);
1310
1311         if (zone_no == 0) {
1312                 if (xd_card->cis_block == 0xFFFF)
1313                         start = 0;
1314                 else
1315                         start = xd_card->cis_block + 1;
1316                 if (XD_CHK_4MB(xd_card)) {
1317                         end = 0x200;
1318                         max_logoff = 499;
1319                 } else {
1320                         end = 0x400;
1321                         max_logoff = 999;
1322                 }
1323         } else {
1324                 start = (u32) (zone_no) << 10;
1325                 end = (u32) (zone_no + 1) << 10;
1326                 max_logoff = 999;
1327         }
1328
1329         RTS51X_DEBUGP("start block 0x%x, end block 0x%x\n", start, end);
1330
1331         zone->set_index = zone->get_index = 0;
1332         zone->unused_blk_cnt = 0;
1333
1334         for (i = start; i < end; i++) {
1335                 u32 page_addr = i << xd_card->block_shift;
1336                 u32 phy_block;
1337
1338                 retval = xd_read_redundant(chip, page_addr, redunt, 11);
1339                 if (retval != STATUS_SUCCESS)
1340                         continue;
1341
1342                 if (redunt[BLOCK_STATUS] != 0xFF) {
1343                         RTS51X_DEBUGP("bad block\n");
1344                         continue;
1345                 }
1346
1347                 if (xd_check_data_blank(redunt)) {
1348                         RTS51X_DEBUGP("blank block\n");
1349                         xd_set_unused_block(chip, i);
1350                         continue;
1351                 }
1352
1353                 cur_fst_page_logoff = xd_load_log_block_addr(redunt);
1354                 if ((cur_fst_page_logoff == 0xFFFF)
1355                     || (cur_fst_page_logoff > max_logoff)) {
1356                         retval = xd_erase_block(chip, i);
1357                         if (retval == STATUS_SUCCESS)
1358                                 xd_set_unused_block(chip, i);
1359                         continue;
1360                 }
1361                 if ((zone_no == 0) && (cur_fst_page_logoff == 0)
1362                     && (redunt[PAGE_STATUS] != XD_GPG))
1363                         XD_SET_MBR_FAIL(xd_card);
1364
1365                 if (zone->l2p_table[cur_fst_page_logoff] == 0xFFFF) {
1366                         zone->l2p_table[cur_fst_page_logoff] =
1367                             (u16) (i & 0x3FF);
1368                         continue;
1369                 }
1370
1371                 phy_block =
1372                     zone->l2p_table[cur_fst_page_logoff] +
1373                     ((u32) ((zone_no) << 10));
1374
1375                 page_addr = ((i + 1) << xd_card->block_shift) - 1;
1376
1377                 retval = xd_read_redundant(chip, page_addr, redunt, 11);
1378                 if (retval != STATUS_SUCCESS)
1379                         continue;
1380
1381                 cur_lst_page_logoff = xd_load_log_block_addr(redunt);
1382                 if (cur_lst_page_logoff == cur_fst_page_logoff) {
1383                         int m;
1384
1385                         page_addr =
1386                             ((phy_block + 1) << xd_card->block_shift) - 1;
1387
1388                         for (m = 0; m < 3; m++) {
1389                                 retval =
1390                                     xd_read_redundant(chip, page_addr, redunt,
1391                                                       11);
1392                                 if (retval == STATUS_SUCCESS)
1393                                         break;
1394                         }
1395
1396                         if (m == 3) {
1397                                 zone->l2p_table[cur_fst_page_logoff] =
1398                                     (u16) (i & 0x3FF);
1399                                 retval = xd_erase_block(chip, phy_block);
1400                                 if (retval == STATUS_SUCCESS)
1401                                         xd_set_unused_block(chip, phy_block);
1402                                 continue;
1403                         }
1404
1405                         ent_lst_page_logoff = xd_load_log_block_addr(redunt);
1406                         if (ent_lst_page_logoff != cur_fst_page_logoff) {
1407                                 zone->l2p_table[cur_fst_page_logoff] =
1408                                     (u16) (i & 0x3FF);
1409                                 retval = xd_erase_block(chip, phy_block);
1410                                 if (retval == STATUS_SUCCESS)
1411                                         xd_set_unused_block(chip, phy_block);
1412                                 continue;
1413                         } else {
1414                                 retval = xd_erase_block(chip, i);
1415                                 if (retval == STATUS_SUCCESS)
1416                                         xd_set_unused_block(chip, i);
1417                         }
1418                 } else {
1419                         retval = xd_erase_block(chip, i);
1420                         if (retval == STATUS_SUCCESS)
1421                                 xd_set_unused_block(chip, i);
1422                 }
1423         }
1424
1425         if (XD_CHK_4MB(xd_card))
1426                 end = 500;
1427         else
1428                 end = 1000;
1429
1430         i = 0;
1431         for (start = 0; start < end; start++) {
1432                 if (zone->l2p_table[start] == 0xFFFF)
1433                         i++;
1434         }
1435
1436         RTS51X_DEBUGP("Block count %d, invalid L2P entry %d\n", end, i);
1437         RTS51X_DEBUGP("Total unused block: %d\n", zone->unused_blk_cnt);
1438
1439         if ((zone->unused_blk_cnt - i) < 1)
1440                 chip->card_wp |= XD_CARD;
1441
1442         zone->build_flag = 1;
1443
1444         return STATUS_SUCCESS;
1445
1446 Build_Fail:
1447         if (zone->l2p_table) {
1448                 vfree(zone->l2p_table);
1449                 zone->l2p_table = NULL;
1450         }
1451         if (zone->free_table) {
1452                 vfree(zone->free_table);
1453                 zone->free_table = NULL;
1454         }
1455
1456         return STATUS_FAIL;
1457 }
1458
1459 static int xd_send_cmd(struct rts51x_chip *chip, u8 cmd)
1460 {
1461         int retval;
1462
1463         rts51x_init_cmd(chip);
1464
1465         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_DAT, 0xFF, cmd);
1466         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1467                        XD_TRANSFER_START | XD_SET_CMD);
1468         rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END,
1469                        XD_TRANSFER_END);
1470
1471         retval = rts51x_send_cmd(chip, MODE_CR, 100);
1472         if (retval != STATUS_SUCCESS)
1473                 TRACE_RET(chip, retval);
1474
1475         retval = rts51x_get_rsp(chip, 1, 200);
1476         if (retval != STATUS_SUCCESS) {
1477                 rts51x_clear_xd_error(chip);
1478                 TRACE_RET(chip, retval);
1479         }
1480
1481         return STATUS_SUCCESS;
1482 }
1483
1484 static int xd_read_multiple_pages(struct rts51x_chip *chip, u32 phy_blk,
1485                                   u32 log_blk, u8 start_page, u8 end_page,
1486                                   u8 *buf, void **ptr, unsigned int *offset)
1487 {
1488         struct xd_info *xd_card = &(chip->xd_card);
1489         u32 page_addr, new_blk;
1490         u16 log_off;
1491         u8 reg_val, page_cnt;
1492         int zone_no, retval, i;
1493
1494         if (start_page > end_page)
1495                 TRACE_RET(chip, STATUS_FAIL);
1496
1497         page_cnt = end_page - start_page;
1498         zone_no = (int)(log_blk / 1000);
1499         log_off = (u16) (log_blk % 1000);
1500
1501         if ((phy_blk & 0x3FF) == 0x3FF) {
1502                 for (i = 0; i < 256; i++) {
1503                         page_addr = ((u32) i) << xd_card->block_shift;
1504
1505                         retval = xd_read_redundant(chip, page_addr, NULL, 0);
1506                         if (retval == STATUS_SUCCESS)
1507                                 break;
1508
1509                         if (monitor_card_cd(chip, XD_CARD) == CD_NOT_EXIST) {
1510                                 xd_set_err_code(chip, XD_NO_CARD);
1511                                 TRACE_RET(chip, STATUS_FAIL);
1512                         }
1513                 }
1514         }
1515
1516         page_addr = (phy_blk << xd_card->block_shift) + start_page;
1517
1518         rts51x_init_cmd(chip);
1519
1520         xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
1521
1522         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CFG, XD_PPB_TO_SIE,
1523                        XD_PPB_TO_SIE);
1524         rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
1525                        RING_BUFFER);
1526         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, page_cnt);
1527         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS,
1528                        XD_AUTO_CHK_DATA_STATUS, XD_AUTO_CHK_DATA_STATUS);
1529
1530         rts51x_trans_dma_enable(chip->srb->sc_data_direction, chip,
1531                         page_cnt * 512, DMA_512);
1532
1533         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1534                        XD_TRANSFER_START | XD_READ_PAGES);
1535         rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1536                        XD_TRANSFER_END | XD_PPB_EMPTY,
1537                        XD_TRANSFER_END | XD_PPB_EMPTY);
1538
1539         retval = rts51x_send_cmd(chip, MODE_CDIR, 100);
1540         if (retval != STATUS_SUCCESS)
1541                 TRACE_RET(chip, retval);
1542
1543         retval =
1544             rts51x_transfer_data_partial(chip, RCV_BULK_PIPE(chip), (void *)buf,
1545                                          ptr, offset, page_cnt * 512,
1546                                          scsi_sg_count(chip->srb), NULL, 2000);
1547         if (retval != STATUS_SUCCESS) {
1548                 rts51x_clear_xd_error(chip);
1549
1550                 if (retval == STATUS_TIMEDOUT) {
1551                         xd_set_err_code(chip, XD_TO_ERROR);
1552                         TRACE_RET(chip, retval);
1553                 } else {
1554                         TRACE_GOTO(chip, Fail);
1555                 }
1556         }
1557         retval = rts51x_get_rsp(chip, 1, 200);
1558         if (retval != STATUS_SUCCESS) {
1559                 rts51x_clear_xd_error(chip);
1560
1561                 if (retval == STATUS_TIMEDOUT) {
1562                         xd_set_err_code(chip, XD_TO_ERROR);
1563                         TRACE_RET(chip, retval);
1564                 } else {
1565                         TRACE_GOTO(chip, Fail);
1566                 }
1567         }
1568
1569         return STATUS_SUCCESS;
1570
1571 Fail:
1572         rts51x_ep0_read_register(chip, XD_PAGE_STATUS, &reg_val);
1573         RTS51X_DEBUGP("XD_PAGE_STATUS: 0x%x\n", reg_val);
1574
1575         if (reg_val != XD_GPG)
1576                 xd_set_err_code(chip, XD_PRG_ERROR);
1577
1578         rts51x_ep0_read_register(chip, XD_CTL, &reg_val);
1579         RTS51X_DEBUGP("XD_CTL: 0x%x\n", reg_val);
1580
1581         /* Handle uncorrectable ECC error */
1582         if (((reg_val & (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE))
1583              == (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE))
1584             || ((reg_val & (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE))
1585                 == (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE))) {
1586                 wait_timeout(100);
1587
1588                 if (monitor_card_cd(chip, XD_CARD) == CD_NOT_EXIST) {
1589                         xd_set_err_code(chip, XD_NO_CARD);
1590                         TRACE_RET(chip, STATUS_FAIL);
1591                 }
1592
1593                 xd_set_err_code(chip, XD_ECC_ERROR);
1594
1595                 new_blk = xd_get_unused_block(chip, zone_no);
1596                 if (new_blk == NO_NEW_BLK) {
1597                         XD_CLR_BAD_OLDBLK(xd_card);
1598                         TRACE_RET(chip, STATUS_FAIL);
1599                 }
1600                 retval =
1601                     xd_copy_page(chip, phy_blk, new_blk, 0,
1602                                  xd_card->page_off + 1);
1603                 if (retval != STATUS_SUCCESS) {
1604                         if (!XD_CHK_BAD_NEWBLK(xd_card)) {
1605                                 retval = xd_erase_block(chip, new_blk);
1606                                 if (retval == STATUS_SUCCESS)
1607                                         xd_set_unused_block(chip, new_blk);
1608                         } else {
1609                                 XD_CLR_BAD_NEWBLK(xd_card);
1610                         }
1611                         XD_CLR_BAD_OLDBLK(xd_card);
1612                         TRACE_RET(chip, STATUS_FAIL);
1613                 }
1614                 xd_set_l2p_tbl(chip, zone_no, log_off, (u16) (new_blk & 0x3FF));
1615                 xd_erase_block(chip, phy_blk);
1616                 xd_mark_bad_block(chip, phy_blk);
1617                 XD_CLR_BAD_OLDBLK(xd_card);
1618         }
1619
1620         TRACE_RET(chip, STATUS_FAIL);
1621 }
1622
1623 static int xd_finish_write(struct rts51x_chip *chip,
1624                            u32 old_blk, u32 new_blk, u32 log_blk, u8 page_off)
1625 {
1626         struct xd_info *xd_card = &(chip->xd_card);
1627         int retval, zone_no;
1628         u16 log_off;
1629
1630         RTS51X_DEBUGP("xd_finish_write, old_blk = 0x%x, new_blk = 0x%x,"
1631                                 "log_blk = 0x%x\n", old_blk, new_blk, log_blk);
1632
1633         if (page_off > xd_card->page_off)
1634                 TRACE_RET(chip, STATUS_FAIL);
1635
1636         zone_no = (int)(log_blk / 1000);
1637         log_off = (u16) (log_blk % 1000);
1638
1639         if (old_blk == BLK_NOT_FOUND) {
1640                 retval = xd_init_page(chip, new_blk, log_off,
1641                                       page_off, xd_card->page_off + 1);
1642                 if (retval != STATUS_SUCCESS) {
1643                         retval = xd_erase_block(chip, new_blk);
1644                         if (retval == STATUS_SUCCESS)
1645                                 xd_set_unused_block(chip, new_blk);
1646                         TRACE_RET(chip, STATUS_FAIL);
1647                 }
1648         } else {
1649                 retval = xd_copy_page(chip, old_blk, new_blk,
1650                                       page_off, xd_card->page_off + 1);
1651                 if (retval != STATUS_SUCCESS) {
1652                         if (!XD_CHK_BAD_NEWBLK(xd_card)) {
1653                                 retval = xd_erase_block(chip, new_blk);
1654                                 if (retval == STATUS_SUCCESS)
1655                                         xd_set_unused_block(chip, new_blk);
1656                         }
1657                         XD_CLR_BAD_NEWBLK(xd_card);
1658                         TRACE_RET(chip, STATUS_FAIL);
1659                 }
1660
1661                 retval = xd_erase_block(chip, old_blk);
1662                 if (retval == STATUS_SUCCESS) {
1663                         if (XD_CHK_BAD_OLDBLK(xd_card)) {
1664                                 xd_mark_bad_block(chip, old_blk);
1665                                 XD_CLR_BAD_OLDBLK(xd_card);
1666                         } else {
1667                                 /* Add source block to unused block */
1668                                 xd_set_unused_block(chip, old_blk);
1669                         }
1670                 } else {
1671                         xd_set_err_code(chip, XD_NO_ERROR);
1672                         XD_CLR_BAD_OLDBLK(xd_card);
1673                 }
1674         }
1675
1676         /* Add target block to L2P table */
1677         xd_set_l2p_tbl(chip, zone_no, log_off, (u16) (new_blk & 0x3FF));
1678
1679         return STATUS_SUCCESS;
1680 }
1681
1682 static int xd_prepare_write(struct rts51x_chip *chip,
1683                             u32 old_blk, u32 new_blk, u32 log_blk, u8 page_off)
1684 {
1685         int retval;
1686
1687         RTS51X_DEBUGP("xd_prepare_write, old_blk = 0x%x, new_blk = 0x%x,"
1688                                 "log_blk = 0x%x, page_off = %d\n",
1689                                 old_blk, new_blk, log_blk, (int)page_off);
1690
1691         if (page_off) {
1692                 retval = xd_copy_page(chip, old_blk, new_blk, 0, page_off);
1693                 if (retval != STATUS_SUCCESS)
1694                         TRACE_RET(chip, retval);
1695         }
1696
1697         return STATUS_SUCCESS;
1698 }
1699
1700 static int xd_write_multiple_pages(struct rts51x_chip *chip, u32 old_blk,
1701                                    u32 new_blk, u32 log_blk, u8 start_page,
1702                                    u8 end_page, u8 *buf, void **ptr,
1703                                    unsigned int *offset)
1704 {
1705         struct xd_info *xd_card = &(chip->xd_card);
1706         u32 page_addr;
1707         int zone_no, retval;
1708         u16 log_off;
1709         u8 page_cnt, reg_val;
1710
1711         RTS51X_DEBUGP("xd_write_multiple_pages, old_blk = 0x%x,"
1712                                 "new_blk = 0x%x, log_blk = 0x%x\n",
1713                                 old_blk, new_blk, log_blk);
1714
1715         if (start_page > end_page)
1716                 TRACE_RET(chip, STATUS_FAIL);
1717
1718         page_cnt = end_page - start_page;
1719         zone_no = (int)(log_blk / 1000);
1720         log_off = (u16) (log_blk % 1000);
1721
1722         page_addr = (new_blk << xd_card->block_shift) + start_page;
1723
1724         /* Send index command */
1725         retval = xd_send_cmd(chip, READ1_1);
1726         if (retval != STATUS_SUCCESS)
1727                 TRACE_RET(chip, retval);
1728
1729         rts51x_init_cmd(chip);
1730
1731         /* Prepare redundant field */
1732         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H, 0xFF,
1733                        (u8) (log_off >> 8));
1734         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF,
1735                        (u8) log_off);
1736         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, XD_GBLK);
1737         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, XD_GPG);
1738
1739         xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
1740
1741         /* Transform the block address by hardware */
1742         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CFG, XD_BA_TRANSFORM,
1743                        XD_BA_TRANSFORM);
1744
1745         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, page_cnt);
1746         rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
1747                        RING_BUFFER);
1748
1749         rts51x_trans_dma_enable(chip->srb->sc_data_direction, chip,
1750                         page_cnt * 512, DMA_512);
1751
1752         rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1753                        XD_TRANSFER_START | XD_WRITE_PAGES);
1754         rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END,
1755                        XD_TRANSFER_END);
1756
1757         retval = rts51x_send_cmd(chip, MODE_CDOR, 100);
1758         if (retval != STATUS_SUCCESS)
1759                 TRACE_RET(chip, retval);
1760
1761         retval =
1762             rts51x_transfer_data_partial(chip, SND_BULK_PIPE(chip), (void *)buf,
1763                                          ptr, offset, page_cnt * 512,
1764                                          scsi_sg_count(chip->srb), NULL, 2000);
1765         if (retval != STATUS_SUCCESS) {
1766                 rts51x_clear_xd_error(chip);
1767
1768                 if (retval == STATUS_TIMEDOUT) {
1769                         xd_set_err_code(chip, XD_TO_ERROR);
1770                         TRACE_RET(chip, retval);
1771                 } else {
1772                         TRACE_GOTO(chip, Fail);
1773                 }
1774         }
1775         retval = rts51x_get_rsp(chip, 1, 200);
1776         if (retval != STATUS_SUCCESS) {
1777                 rts51x_clear_xd_error(chip);
1778
1779                 if (retval == STATUS_TIMEDOUT) {
1780                         xd_set_err_code(chip, XD_TO_ERROR);
1781                         TRACE_RET(chip, retval);
1782                 } else {
1783                         TRACE_GOTO(chip, Fail);
1784                 }
1785         }
1786
1787         if (end_page == (xd_card->page_off + 1)) {
1788                 xd_card->delay_write.delay_write_flag = 0;
1789
1790                 if (old_blk != BLK_NOT_FOUND) {
1791                         retval = xd_erase_block(chip, old_blk);
1792                         if (retval == STATUS_SUCCESS) {
1793                                 if (XD_CHK_BAD_OLDBLK(xd_card)) {
1794                                         xd_mark_bad_block(chip, old_blk);
1795                                         XD_CLR_BAD_OLDBLK(xd_card);
1796                                 } else {
1797                                         xd_set_unused_block(chip, old_blk);
1798                                 }
1799                         } else {
1800                                 xd_set_err_code(chip, XD_NO_ERROR);
1801                                 XD_CLR_BAD_OLDBLK(xd_card);
1802                         }
1803                 }
1804                 xd_set_l2p_tbl(chip, zone_no, log_off, (u16) (new_blk & 0x3FF));
1805         }
1806
1807         return STATUS_SUCCESS;
1808
1809 Fail:
1810         rts51x_ep0_read_register(chip, XD_DAT, &reg_val);
1811         RTS51X_DEBUGP("XD_DAT: 0x%x\n", reg_val);
1812
1813         if (reg_val & PROGRAM_ERROR) {
1814                 xd_set_err_code(chip, XD_PRG_ERROR);
1815                 xd_mark_bad_block(chip, new_blk);
1816         }
1817
1818         TRACE_RET(chip, STATUS_FAIL);
1819 }
1820
1821 static int xd_delay_write(struct rts51x_chip *chip)
1822 {
1823         struct xd_info *xd_card = &(chip->xd_card);
1824         struct xd_delay_write_tag *delay_write = &(xd_card->delay_write);
1825         int retval;
1826
1827         if (delay_write->delay_write_flag) {
1828                 RTS51X_DEBUGP("xd_delay_write\n");
1829                 retval = xd_switch_clock(chip);
1830                 if (retval != STATUS_SUCCESS)
1831                         TRACE_RET(chip, retval);
1832
1833                 delay_write->delay_write_flag = 0;
1834                 retval = xd_finish_write(chip,
1835                                          delay_write->old_phyblock,
1836                                          delay_write->new_phyblock,
1837                                          delay_write->logblock,
1838                                          delay_write->pageoff);
1839                 if (retval != STATUS_SUCCESS)
1840                         TRACE_RET(chip, retval);
1841         }
1842
1843         return STATUS_SUCCESS;
1844 }
1845
1846 int rts51x_xd_rw(struct scsi_cmnd *srb, struct rts51x_chip *chip,
1847         u32 start_sector, u16 sector_cnt)
1848 {
1849         struct xd_info *xd_card = &(chip->xd_card);
1850         unsigned int lun = SCSI_LUN(srb);
1851         struct xd_delay_write_tag *delay_write = &(xd_card->delay_write);
1852         int retval, zone_no;
1853         u32 log_blk, old_blk = 0, new_blk = 0;
1854         u16 log_off, total_sec_cnt = sector_cnt;
1855         u8 start_page, end_page = 0, page_cnt;
1856         u8 *buf;
1857         void *ptr = NULL;
1858         unsigned int offset = 0;
1859
1860         xd_set_err_code(chip, XD_NO_ERROR);
1861
1862         xd_card->counter = 0;
1863
1864         RTS51X_DEBUGP("rts51x_xd_rw: scsi_bufflen = %d, scsi_sg_count = %d\n",
1865                        scsi_bufflen(srb), scsi_sg_count(srb));
1866         RTS51X_DEBUGP("Data direction: %s\n",
1867                        (srb->sc_data_direction ==
1868                         DMA_TO_DEVICE) ? "write" : "read");
1869
1870         buf = (u8 *) scsi_sglist(srb);
1871
1872         retval = xd_switch_clock(chip);
1873         if (retval != STATUS_SUCCESS)
1874                 TRACE_RET(chip, retval);
1875
1876         log_blk = start_sector >> xd_card->block_shift;
1877         start_page = (u8) start_sector & xd_card->page_off;
1878         zone_no = (int)(log_blk / 1000);
1879         log_off = (u16) (log_blk % 1000);
1880
1881         RTS51X_DEBUGP("log_blk = 0x%x\n", log_blk);
1882
1883         if (xd_card->zone[zone_no].build_flag == 0) {
1884                 retval = xd_build_l2p_tbl(chip, zone_no);
1885                 if (retval != STATUS_SUCCESS) {
1886                         chip->card_fail |= XD_CARD;
1887                         rts51x_set_sense_type(chip, lun,
1888                                 SENSE_TYPE_MEDIA_NOT_PRESENT);
1889                         TRACE_RET(chip, retval);
1890                 }
1891         }
1892
1893         if (srb->sc_data_direction == DMA_TO_DEVICE) {
1894                 if (delay_write->delay_write_flag &&
1895                     (delay_write->logblock == log_blk) &&
1896                     (start_page > delay_write->pageoff)) {
1897                         delay_write->delay_write_flag = 0;
1898                         if (delay_write->old_phyblock != BLK_NOT_FOUND) {
1899                                 retval = xd_copy_page(chip,
1900                                                       delay_write->old_phyblock,
1901                                                       delay_write->new_phyblock,
1902                                                       delay_write->pageoff,
1903                                                       start_page);
1904                                 if (retval != STATUS_SUCCESS) {
1905                                         rts51x_set_sense_type(chip, lun,
1906                                                 SENSE_TYPE_MEDIA_WRITE_ERR);
1907                                         TRACE_RET(chip, retval);
1908                                 }
1909                         }
1910                         old_blk = delay_write->old_phyblock;
1911                         new_blk = delay_write->new_phyblock;
1912                 } else if (delay_write->delay_write_flag &&
1913                            (delay_write->logblock == log_blk) &&
1914                            (start_page == delay_write->pageoff)) {
1915                         delay_write->delay_write_flag = 0;
1916                         old_blk = delay_write->old_phyblock;
1917                         new_blk = delay_write->new_phyblock;
1918                 } else {
1919                         retval = xd_delay_write(chip);
1920                         if (retval != STATUS_SUCCESS) {
1921                                 rts51x_set_sense_type(chip, lun,
1922                                                SENSE_TYPE_MEDIA_WRITE_ERR);
1923                                 TRACE_RET(chip, retval);
1924                         }
1925                         old_blk = xd_get_l2p_tbl(chip, zone_no, log_off);
1926                         new_blk = xd_get_unused_block(chip, zone_no);
1927                         if ((old_blk == BLK_NOT_FOUND)
1928                             || (new_blk == BLK_NOT_FOUND)) {
1929                                 rts51x_set_sense_type(chip, lun,
1930                                                SENSE_TYPE_MEDIA_WRITE_ERR);
1931                                 TRACE_RET(chip, retval);
1932                         }
1933
1934                         retval =
1935                             xd_prepare_write(chip, old_blk, new_blk, log_blk,
1936                                              start_page);
1937                         if (retval != STATUS_SUCCESS) {
1938                                 if (monitor_card_cd(chip, XD_CARD) ==
1939                                     CD_NOT_EXIST) {
1940                                         rts51x_set_sense_type(chip, lun,
1941                                                 SENSE_TYPE_MEDIA_NOT_PRESENT);
1942                                         TRACE_RET(chip, STATUS_FAIL);
1943                                 }
1944                                 rts51x_set_sense_type(chip, lun,
1945                                                SENSE_TYPE_MEDIA_WRITE_ERR);
1946                                 TRACE_RET(chip, retval);
1947                         }
1948                 }
1949         } else {
1950                 retval = xd_delay_write(chip);
1951                 if (retval != STATUS_SUCCESS) {
1952                         if (monitor_card_cd(chip, XD_CARD) == CD_NOT_EXIST) {
1953                                 rts51x_set_sense_type(chip, lun,
1954                                                SENSE_TYPE_MEDIA_NOT_PRESENT);
1955                                 TRACE_RET(chip, STATUS_FAIL);
1956                         }
1957                         rts51x_set_sense_type(chip, lun,
1958                                        SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
1959                         TRACE_RET(chip, retval);
1960                 }
1961
1962                 old_blk = xd_get_l2p_tbl(chip, zone_no, log_off);
1963                 if (old_blk == BLK_NOT_FOUND) {
1964                         rts51x_set_sense_type(chip, lun,
1965                                        SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
1966                         TRACE_RET(chip, STATUS_FAIL);
1967                 }
1968         }
1969
1970         RTS51X_DEBUGP("old_blk = 0x%x\n", old_blk);
1971         if (srb->sc_data_direction == DMA_TO_DEVICE)
1972                 RTS51X_DEBUGP("new_blk = 0x%x\n", new_blk);
1973
1974         while (total_sec_cnt) {
1975                 if ((start_page + total_sec_cnt) > (xd_card->page_off + 1))
1976                         end_page = xd_card->page_off + 1;
1977                 else
1978                         end_page = start_page + (u8) total_sec_cnt;
1979                 page_cnt = end_page - start_page;
1980                 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
1981                         retval = xd_read_multiple_pages(chip, old_blk, log_blk,
1982                                                         start_page, end_page,
1983                                                         buf, &ptr, &offset);
1984                         if (retval != STATUS_SUCCESS) {
1985                                 rts51x_set_sense_type(chip, lun,
1986                                         SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
1987                                 TRACE_RET(chip, STATUS_FAIL);
1988                         }
1989                 } else {
1990                         retval =
1991                             xd_write_multiple_pages(chip, old_blk, new_blk,
1992                                                     log_blk, start_page,
1993                                                     end_page, buf, &ptr,
1994                                                     &offset);
1995                         if (retval != STATUS_SUCCESS) {
1996                                 rts51x_set_sense_type(chip, lun,
1997                                                SENSE_TYPE_MEDIA_WRITE_ERR);
1998                                 TRACE_RET(chip, STATUS_FAIL);
1999                         }
2000                 }
2001
2002                 total_sec_cnt -= page_cnt;
2003
2004                 if (total_sec_cnt == 0)
2005                         break;
2006
2007                 log_blk++;
2008                 zone_no = (int)(log_blk / 1000);
2009                 log_off = (u16) (log_blk % 1000);
2010
2011                 if (xd_card->zone[zone_no].build_flag == 0) {
2012                         retval = xd_build_l2p_tbl(chip, zone_no);
2013                         if (retval != STATUS_SUCCESS) {
2014                                 chip->card_fail |= XD_CARD;
2015                                 rts51x_set_sense_type(chip, lun,
2016                                                SENSE_TYPE_MEDIA_NOT_PRESENT);
2017                                 TRACE_RET(chip, retval);
2018                         }
2019                 }
2020
2021                 old_blk = xd_get_l2p_tbl(chip, zone_no, log_off);
2022                 if (old_blk == BLK_NOT_FOUND) {
2023                         if (srb->sc_data_direction == DMA_FROM_DEVICE) {
2024                                 rts51x_set_sense_type(chip, lun,
2025                                         SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
2026                         } else {
2027                                 rts51x_set_sense_type(chip, lun,
2028                                                SENSE_TYPE_MEDIA_WRITE_ERR);
2029                         }
2030                         TRACE_RET(chip, STATUS_FAIL);
2031                 }
2032
2033                 if (srb->sc_data_direction == DMA_TO_DEVICE) {
2034                         new_blk = xd_get_unused_block(chip, zone_no);
2035                         if (new_blk == BLK_NOT_FOUND) {
2036                                 rts51x_set_sense_type(chip, lun,
2037                                                SENSE_TYPE_MEDIA_WRITE_ERR);
2038                                 TRACE_RET(chip, STATUS_FAIL);
2039                         }
2040                 }
2041
2042                 start_page = 0;
2043         }
2044
2045         if ((srb->sc_data_direction == DMA_TO_DEVICE) &&
2046             (end_page != (xd_card->page_off + 1))) {
2047                 delay_write->delay_write_flag = 1;
2048                 delay_write->old_phyblock = old_blk;
2049                 delay_write->new_phyblock = new_blk;
2050                 delay_write->logblock = log_blk;
2051                 delay_write->pageoff = end_page;
2052         }
2053
2054         scsi_set_resid(srb, 0);
2055
2056         return STATUS_SUCCESS;
2057 }
2058
2059 void rts51x_xd_free_l2p_tbl(struct rts51x_chip *chip)
2060 {
2061         struct xd_info *xd_card = &(chip->xd_card);
2062         int i = 0;
2063
2064         if (xd_card->zone != NULL) {
2065                 for (i = 0; i < xd_card->zone_cnt; i++) {
2066                         if (xd_card->zone[i].l2p_table != NULL) {
2067                                 vfree(xd_card->zone[i].l2p_table);
2068                                 xd_card->zone[i].l2p_table = NULL;
2069                         }
2070                         if (xd_card->zone[i].free_table != NULL) {
2071                                 vfree(xd_card->zone[i].free_table);
2072                                 xd_card->zone[i].free_table = NULL;
2073                         }
2074                 }
2075                 vfree(xd_card->zone);
2076                 xd_card->zone = NULL;
2077         }
2078 }
2079
2080 void rts51x_xd_cleanup_work(struct rts51x_chip *chip)
2081 {
2082         struct xd_info *xd_card = &(chip->xd_card);
2083
2084         if (xd_card->delay_write.delay_write_flag) {
2085                 RTS51X_DEBUGP("xD: delay write\n");
2086                 xd_delay_write(chip);
2087                 xd_card->counter = 0;
2088         }
2089 }
2090
2091 static int xd_power_off_card3v3(struct rts51x_chip *chip)
2092 {
2093         int retval;
2094
2095         rts51x_init_cmd(chip);
2096
2097         rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_CLK_EN, XD_CLK_EN, 0);
2098
2099         if (chip->asic_code)
2100                 xd_pull_ctl_disable(chip);
2101         else
2102                 rts51x_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF, 0xDF);
2103         rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN, 0);
2104         if (!chip->option.FT2_fast_mode) {
2105                 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, POWER_MASK,
2106                                POWER_OFF);
2107                 if (CHECK_PKG(chip, LQFP48)
2108                     || chip->option.rts5129_D3318_off_enable)
2109                         rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL,
2110                                        DV3318_AUTO_PWR_OFF, 0);
2111         }
2112
2113         retval = rts51x_send_cmd(chip, MODE_C, 100);
2114         if (retval != STATUS_SUCCESS)
2115                 TRACE_RET(chip, retval);
2116
2117         return STATUS_SUCCESS;
2118 }
2119
2120 int rts51x_release_xd_card(struct rts51x_chip *chip)
2121 {
2122         struct xd_info *xd_card = &(chip->xd_card);
2123         int retval;
2124
2125         RTS51X_DEBUGP("rts51x_release_xd_card\n");
2126
2127         chip->card_ready &= ~XD_CARD;
2128         chip->card_fail &= ~XD_CARD;
2129         chip->card_wp &= ~XD_CARD;
2130
2131         xd_card->delay_write.delay_write_flag = 0;
2132
2133         rts51x_xd_free_l2p_tbl(chip);
2134
2135         rts51x_write_register(chip, SFSM_ED, HW_CMD_STOP, HW_CMD_STOP);
2136
2137         retval = xd_power_off_card3v3(chip);
2138         if (retval != STATUS_SUCCESS)
2139                 TRACE_RET(chip, retval);
2140
2141         if (chip->asic_code && CHECK_PKG(chip, QFN24))
2142                 wait_timeout(20);
2143
2144         return STATUS_SUCCESS;
2145 }