drivers/staging/rts5208/rtsx_chip.c

   1 /* Driver for Realtek PCI-Express card reader
   2  *
   3  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2, or (at your option) any
   8  * later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * Author:
  19  *   Wei WANG (wei_wang@realsil.com.cn)
  20  *   Micky Ching (micky_ching@realsil.com.cn)
  21  */
  22
  23 #include <linux/blkdev.h>
  24 #include <linux/kthread.h>
  25 #include <linux/sched.h>
  26 #include <linux/workqueue.h>
  27 #include <linux/vmalloc.h>
  28
  29 #include "rtsx.h"
  30 #include "rtsx_transport.h"
  31 #include "rtsx_scsi.h"
  32 #include "rtsx_card.h"
  33 #include "rtsx_chip.h"
  34 #include "rtsx_sys.h"
  35 #include "general.h"
  36
  37 #include "sd.h"
  38 #include "xd.h"
  39 #include "ms.h"
  40
  41 static void rtsx_calibration(struct rtsx_chip *chip)
  42 {
  43         rtsx_write_phy_register(chip, 0x1B, 0x135E);
  44         wait_timeout(10);
  45         rtsx_write_phy_register(chip, 0x00, 0x0280);
  46         rtsx_write_phy_register(chip, 0x01, 0x7112);
  47         rtsx_write_phy_register(chip, 0x01, 0x7110);
  48         rtsx_write_phy_register(chip, 0x01, 0x7112);
  49         rtsx_write_phy_register(chip, 0x01, 0x7113);
  50         rtsx_write_phy_register(chip, 0x00, 0x0288);
  51 }
  52
  53 void rtsx_disable_card_int(struct rtsx_chip *chip)
  54 {
  55         u32 reg = rtsx_readl(chip, RTSX_BIER);
  56
  57         reg &= ~(XD_INT_EN | SD_INT_EN | MS_INT_EN);
  58         rtsx_writel(chip, RTSX_BIER, reg);
  59 }
  60
  61 void rtsx_enable_card_int(struct rtsx_chip *chip)
  62 {
  63         u32 reg = rtsx_readl(chip, RTSX_BIER);
  64         int i;
  65
  66         for (i = 0; i <= chip->max_lun; i++) {
  67                 if (chip->lun2card[i] & XD_CARD)
  68                         reg |= XD_INT_EN;
  69                 if (chip->lun2card[i] & SD_CARD)
  70                         reg |= SD_INT_EN;
  71                 if (chip->lun2card[i] & MS_CARD)
  72                         reg |= MS_INT_EN;
  73         }
  74         if (chip->hw_bypass_sd)
  75                 reg &= ~((u32)SD_INT_EN);
  76
  77         rtsx_writel(chip, RTSX_BIER, reg);
  78 }
  79
  80 void rtsx_enable_bus_int(struct rtsx_chip *chip)
  81 {
  82         u32 reg = 0;
  83 #ifndef DISABLE_CARD_INT
  84         int i;
  85 #endif
  86
  87         reg = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN;
  88
  89 #ifndef DISABLE_CARD_INT
  90         for (i = 0; i <= chip->max_lun; i++) {
  91                 dev_dbg(rtsx_dev(chip), "lun2card[%d] = 0x%02x\n",
  92                         i, chip->lun2card[i]);
  93
  94                 if (chip->lun2card[i] & XD_CARD)
  95                         reg |= XD_INT_EN;
  96                 if (chip->lun2card[i] & SD_CARD)
  97                         reg |= SD_INT_EN;
  98                 if (chip->lun2card[i] & MS_CARD)
  99                         reg |= MS_INT_EN;
 100         }
 101         if (chip->hw_bypass_sd)
 102                 reg &= ~((u32)SD_INT_EN);
 103 #endif
 104
 105         if (chip->ic_version >= IC_VER_C)
 106                 reg |= DELINK_INT_EN;
 107 #ifdef SUPPORT_OCP
 108         reg |= OC_INT_EN;
 109 #endif
 110         if (!chip->adma_mode)
 111                 reg |= DATA_DONE_INT_EN;
 112
 113         /* Enable Bus Interrupt */
 114         rtsx_writel(chip, RTSX_BIER, reg);
 115
 116         dev_dbg(rtsx_dev(chip), "RTSX_BIER: 0x%08x\n", reg);
 117 }
 118
 119 void rtsx_disable_bus_int(struct rtsx_chip *chip)
 120 {
 121         rtsx_writel(chip, RTSX_BIER, 0);
 122 }
 123
 124 static int rtsx_pre_handle_sdio_old(struct rtsx_chip *chip)
 125 {
 126         if (chip->ignore_sd && CHK_SDIO_EXIST(chip)) {
 127                 if (chip->asic_code) {
 128                         RTSX_WRITE_REG(chip, CARD_PULL_CTL5, 0xFF,
 129                                 MS_INS_PU | SD_WP_PU | SD_CD_PU | SD_CMD_PU);
 130                 } else {
 131                         RTSX_WRITE_REG(chip, FPGA_PULL_CTL, 0xFF,
 132                                 FPGA_SD_PULL_CTL_EN);
 133                 }
 134                 RTSX_WRITE_REG(chip, CARD_SHARE_MODE, 0xFF, CARD_SHARE_48_SD);
 135
 136                 /* Enable SDIO internal clock */
 137                 RTSX_WRITE_REG(chip, 0xFF2C, 0x01, 0x01);
 138
 139                 RTSX_WRITE_REG(chip, SDIO_CTRL, 0xFF,
 140                         SDIO_BUS_CTRL | SDIO_CD_CTRL);
 141
 142                 chip->sd_int = 1;
 143                 chip->sd_io = 1;
 144         } else {
 145                 chip->need_reset |= SD_CARD;
 146         }
 147
 148         return STATUS_SUCCESS;
 149 }
 150
 151 #ifdef HW_AUTO_SWITCH_SD_BUS
 152 static int rtsx_pre_handle_sdio_new(struct rtsx_chip *chip)
 153 {
 154         u8 tmp;
 155         int sw_bypass_sd = 0;
 156         int retval;
 157
 158         if (chip->driver_first_load) {
 159                 if (CHECK_PID(chip, 0x5288)) {
 160                         RTSX_READ_REG(chip, 0xFE5A, &tmp);
 161                         if (tmp & 0x08)
 162                                 sw_bypass_sd = 1;
 163                 } else if (CHECK_PID(chip, 0x5208)) {
 164                         RTSX_READ_REG(chip, 0xFE70, &tmp);
 165                         if (tmp & 0x80)
 166                                 sw_bypass_sd = 1;
 167                 }
 168         } else {
 169                 if (chip->sdio_in_charge)
 170                         sw_bypass_sd = 1;
 171         }
 172         dev_dbg(rtsx_dev(chip), "chip->sdio_in_charge = %d\n",
 173                 chip->sdio_in_charge);
 174         dev_dbg(rtsx_dev(chip), "chip->driver_first_load = %d\n",
 175                 chip->driver_first_load);
 176         dev_dbg(rtsx_dev(chip), "sw_bypass_sd = %d\n",
 177                 sw_bypass_sd);
 178
 179         if (sw_bypass_sd) {
 180                 u8 cd_toggle_mask = 0;
 181
 182                 RTSX_READ_REG(chip, TLPTISTAT, &tmp);
 183                 cd_toggle_mask = 0x08;
 184
 185                 if (tmp & cd_toggle_mask) {
 186                         /* Disable sdio_bus_auto_switch */
 187                         if (CHECK_PID(chip, 0x5288))
 188                                 RTSX_WRITE_REG(chip, 0xFE5A, 0x08, 0x00);
 189                         else if (CHECK_PID(chip, 0x5208))
 190                                 RTSX_WRITE_REG(chip, 0xFE70, 0x80, 0x00);
 191
 192                         RTSX_WRITE_REG(chip, TLPTISTAT, 0xFF, tmp);
 193
 194                         chip->need_reset |= SD_CARD;
 195                 } else {
 196                         dev_dbg(rtsx_dev(chip), "Chip inserted with SDIO!\n");
 197
 198                         if (chip->asic_code) {
 199                                 retval = sd_pull_ctl_enable(chip);
 200                                 if (retval != STATUS_SUCCESS)
 201                                         TRACE_RET(chip, STATUS_FAIL);
 202                         } else {
 203                                 RTSX_WRITE_REG(chip, FPGA_PULL_CTL,
 204                                         FPGA_SD_PULL_CTL_BIT | 0x20, 0);
 205                         }
 206                         retval = card_share_mode(chip, SD_CARD);
 207                         if (retval != STATUS_SUCCESS)
 208                                 TRACE_RET(chip, STATUS_FAIL);
 209
 210                         /* Enable sdio_bus_auto_switch */
 211                         if (CHECK_PID(chip, 0x5288))
 212                                 RTSX_WRITE_REG(chip, 0xFE5A, 0x08, 0x08);
 213                         else if (CHECK_PID(chip, 0x5208))
 214                                 RTSX_WRITE_REG(chip, 0xFE70, 0x80, 0x80);
 215
 216                         chip->chip_insert_with_sdio = 1;
 217                         chip->sd_io = 1;
 218                 }
 219         } else {
 220                 RTSX_WRITE_REG(chip, TLPTISTAT, 0x08, 0x08);
 221
 222                 chip->need_reset |= SD_CARD;
 223         }
 224
 225         return STATUS_SUCCESS;
 226 }
 227 #endif
 228
 229 int rtsx_reset_chip(struct rtsx_chip *chip)
 230 {
 231         int retval;
 232
 233         rtsx_writel(chip, RTSX_HCBAR, chip->host_cmds_addr);
 234
 235         rtsx_disable_aspm(chip);
 236
 237         RTSX_WRITE_REG(chip, HOST_SLEEP_STATE, 0x03, 0x00);
 238
 239         /* Disable card clock */
 240         RTSX_WRITE_REG(chip, CARD_CLK_EN, 0x1E, 0);
 241
 242 #ifdef SUPPORT_OCP
 243         /* SSC power on, OCD power on */
 244         if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
 245                 RTSX_WRITE_REG(chip, FPDCTL, OC_POWER_DOWN, 0);
 246         else
 247                 RTSX_WRITE_REG(chip, FPDCTL, OC_POWER_DOWN, MS_OC_POWER_DOWN);
 248
 249         RTSX_WRITE_REG(chip, OCPPARA1, OCP_TIME_MASK, OCP_TIME_800);
 250         RTSX_WRITE_REG(chip, OCPPARA2, OCP_THD_MASK, OCP_THD_244_946);
 251         RTSX_WRITE_REG(chip, OCPCTL, 0xFF, CARD_OC_INT_EN | CARD_DETECT_EN);
 252 #else
 253         /* OC power down */
 254         RTSX_WRITE_REG(chip, FPDCTL, OC_POWER_DOWN, OC_POWER_DOWN);
 255 #endif
 256
 257         if (!CHECK_PID(chip, 0x5288))
 258                 RTSX_WRITE_REG(chip, CARD_GPIO_DIR, 0xFF, 0x03);
 259
 260         /* Turn off LED */
 261         RTSX_WRITE_REG(chip, CARD_GPIO, 0xFF, 0x03);
 262
 263         /* Reset delink mode */
 264         RTSX_WRITE_REG(chip, CHANGE_LINK_STATE, 0x0A, 0);
 265
 266         /* Card driving select */
 267         RTSX_WRITE_REG(chip, CARD_DRIVE_SEL, 0xFF, chip->card_drive_sel);
 268
 269 #ifdef LED_AUTO_BLINK
 270         RTSX_WRITE_REG(chip, CARD_AUTO_BLINK, 0xFF,
 271                         LED_BLINK_SPEED | BLINK_EN | LED_GPIO0);
 272 #endif
 273
 274         if (chip->asic_code) {
 275                 /* Enable SSC Clock */
 276                 RTSX_WRITE_REG(chip, SSC_CTL1, 0xFF, SSC_8X_EN | SSC_SEL_4M);
 277                 RTSX_WRITE_REG(chip, SSC_CTL2, 0xFF, 0x12);
 278         }
 279
 280         /* Disable cd_pwr_save (u_force_rst_core_en=0, u_cd_rst_core_en=0)
 281               0xFE5B
 282               bit[1]    u_cd_rst_core_en        rst_value = 0
 283               bit[2]    u_force_rst_core_en     rst_value = 0
 284               bit[5]    u_mac_phy_rst_n_dbg     rst_value = 1
 285               bit[4]    u_non_sticky_rst_n_dbg  rst_value = 0
 286         */
 287         RTSX_WRITE_REG(chip, CHANGE_LINK_STATE, 0x16, 0x10);
 288
 289         /* Enable ASPM */
 290         if (chip->aspm_l0s_l1_en) {
 291                 if (chip->dynamic_aspm) {
 292                         if (CHK_SDIO_EXIST(chip)) {
 293                                 if (CHECK_PID(chip, 0x5288)) {
 294                                         retval = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFF, chip->aspm_l0s_l1_en);
 295                                         if (retval != STATUS_SUCCESS)
 296                                                 TRACE_RET(chip, STATUS_FAIL);
 297                                 }
 298                         }
 299                 } else {
 300                         if (CHECK_PID(chip, 0x5208))
 301                                 RTSX_WRITE_REG(chip, ASPM_FORCE_CTL,
 302                                         0xFF, 0x3F);
 303
 304                         retval = rtsx_write_config_byte(chip, LCTLR,
 305                                                         chip->aspm_l0s_l1_en);
 306                         if (retval != STATUS_SUCCESS)
 307                                 TRACE_RET(chip, STATUS_FAIL);
 308
 309                         chip->aspm_level[0] = chip->aspm_l0s_l1_en;
 310                         if (CHK_SDIO_EXIST(chip)) {
 311                                 chip->aspm_level[1] = chip->aspm_l0s_l1_en;
 312                                 if (CHECK_PID(chip, 0x5288))
 313                                         retval = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFF, chip->aspm_l0s_l1_en);
 314                                 else
 315                                         retval = rtsx_write_cfg_dw(chip, 1, 0xC0, 0xFF, chip->aspm_l0s_l1_en);
 316
 317                                 if (retval != STATUS_SUCCESS)
 318                                         TRACE_RET(chip, STATUS_FAIL);
 319
 320                         }
 321
 322                         chip->aspm_enabled = 1;
 323                 }
 324         } else {
 325                 if (chip->asic_code && CHECK_PID(chip, 0x5208)) {
 326                         retval = rtsx_write_phy_register(chip, 0x07, 0x0129);
 327                         if (retval != STATUS_SUCCESS)
 328                                 TRACE_RET(chip, STATUS_FAIL);
 329                 }
 330                 retval = rtsx_write_config_byte(chip, LCTLR,
 331                                                 chip->aspm_l0s_l1_en);
 332                 if (retval != STATUS_SUCCESS)
 333                         TRACE_RET(chip, STATUS_FAIL);
 334         }
 335
 336         retval = rtsx_write_config_byte(chip, 0x81, 1);
 337         if (retval != STATUS_SUCCESS)
 338                 TRACE_RET(chip, STATUS_FAIL);
 339
 340         if (CHK_SDIO_EXIST(chip)) {
 341                 if (CHECK_PID(chip, 0x5288))
 342                         retval = rtsx_write_cfg_dw(chip, 2, 0xC0,
 343                                                 0xFF00, 0x0100);
 344                 else
 345                         retval = rtsx_write_cfg_dw(chip, 1, 0xC0,
 346                                                 0xFF00, 0x0100);
 347
 348                 if (retval != STATUS_SUCCESS)
 349                         TRACE_RET(chip, STATUS_FAIL);
 350
 351         }
 352
 353         if (CHECK_PID(chip, 0x5288)) {
 354                 if (!CHK_SDIO_EXIST(chip)) {
 355                         retval = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFFFF,
 356                                                 0x0103);
 357                         if (retval != STATUS_SUCCESS)
 358                                 TRACE_RET(chip, STATUS_FAIL);
 359
 360                         retval = rtsx_write_cfg_dw(chip, 2, 0x84, 0xFF, 0x03);
 361                         if (retval != STATUS_SUCCESS)
 362                                 TRACE_RET(chip, STATUS_FAIL);
 363
 364                 }
 365         }
 366
 367         RTSX_WRITE_REG(chip, IRQSTAT0, LINK_RDY_INT, LINK_RDY_INT);
 368
 369         RTSX_WRITE_REG(chip, PERST_GLITCH_WIDTH, 0xFF, 0x80);
 370
 371         /* Enable PCIE interrupt */
 372         if (chip->asic_code) {
 373                 if (CHECK_PID(chip, 0x5208)) {
 374                         if (chip->phy_debug_mode) {
 375                                 RTSX_WRITE_REG(chip, CDRESUMECTL, 0x77, 0);
 376                                 rtsx_disable_bus_int(chip);
 377                         } else {
 378                                 rtsx_enable_bus_int(chip);
 379                         }
 380
 381                         if (chip->ic_version >= IC_VER_D) {
 382                                 u16 reg;
 383                                 retval = rtsx_read_phy_register(chip, 0x00,
 384                                                                 &reg);
 385                                 if (retval != STATUS_SUCCESS)
 386                                         TRACE_RET(chip, STATUS_FAIL);
 387
 388                                 reg &= 0xFE7F;
 389                                 reg |= 0x80;
 390                                 retval = rtsx_write_phy_register(chip, 0x00,
 391                                                                 reg);
 392                                 if (retval != STATUS_SUCCESS)
 393                                         TRACE_RET(chip, STATUS_FAIL);
 394
 395                                 retval = rtsx_read_phy_register(chip, 0x1C,
 396                                                                 &reg);
 397                                 if (retval != STATUS_SUCCESS)
 398                                         TRACE_RET(chip, STATUS_FAIL);
 399
 400                                 reg &= 0xFFF7;
 401                                 retval = rtsx_write_phy_register(chip, 0x1C,
 402                                                                 reg);
 403                                 if (retval != STATUS_SUCCESS)
 404                                         TRACE_RET(chip, STATUS_FAIL);
 405
 406                         }
 407
 408                         if (chip->driver_first_load &&
 409                                 (chip->ic_version < IC_VER_C))
 410                                 rtsx_calibration(chip);
 411
 412                 } else {
 413                         rtsx_enable_bus_int(chip);
 414                 }
 415         } else {
 416                 rtsx_enable_bus_int(chip);
 417         }
 418
 419         chip->need_reset = 0;
 420
 421         chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
 422
 423         if (chip->hw_bypass_sd)
 424                 goto NextCard;
 425         dev_dbg(rtsx_dev(chip), "In %s, chip->int_reg = 0x%x\n", __func__,
 426                 chip->int_reg);
 427         if (chip->int_reg & SD_EXIST) {
 428 #ifdef HW_AUTO_SWITCH_SD_BUS
 429                 if (CHECK_PID(chip, 0x5208) && (chip->ic_version < IC_VER_C))
 430                         retval = rtsx_pre_handle_sdio_old(chip);
 431                 else
 432                         retval = rtsx_pre_handle_sdio_new(chip);
 433
 434                 dev_dbg(rtsx_dev(chip), "chip->need_reset = 0x%x (rtsx_reset_chip)\n",
 435                         (unsigned int)(chip->need_reset));
 436 #else  /* HW_AUTO_SWITCH_SD_BUS */
 437                 retval = rtsx_pre_handle_sdio_old(chip);
 438 #endif  /* HW_AUTO_SWITCH_SD_BUS */
 439                 if (retval != STATUS_SUCCESS)
 440                         TRACE_RET(chip, STATUS_FAIL);
 441
 442         } else {
 443                 chip->sd_io = 0;
 444                 RTSX_WRITE_REG(chip, SDIO_CTRL, SDIO_BUS_CTRL | SDIO_CD_CTRL,
 445                         0);
 446         }
 447
 448 NextCard:
 449         if (chip->int_reg & XD_EXIST)
 450                 chip->need_reset |= XD_CARD;
 451         if (chip->int_reg & MS_EXIST)
 452                 chip->need_reset |= MS_CARD;
 453         if (chip->int_reg & CARD_EXIST)
 454                 RTSX_WRITE_REG(chip, SSC_CTL1, SSC_RSTB, SSC_RSTB);
 455
 456         dev_dbg(rtsx_dev(chip), "In %s, chip->need_reset = 0x%x\n", __func__,
 457                 (unsigned int)(chip->need_reset));
 458
 459         RTSX_WRITE_REG(chip, RCCTL, 0x01, 0x00);
 460
 461         if (CHECK_PID(chip, 0x5208) || CHECK_PID(chip, 0x5288)) {
 462                 /* Turn off main power when entering S3/S4 state */
 463                 RTSX_WRITE_REG(chip, MAIN_PWR_OFF_CTL, 0x03, 0x03);
 464         }
 465
 466         if (chip->remote_wakeup_en && !chip->auto_delink_en) {
 467                 RTSX_WRITE_REG(chip, WAKE_SEL_CTL, 0x07, 0x07);
 468                 if (chip->aux_pwr_exist)
 469                         RTSX_WRITE_REG(chip, PME_FORCE_CTL, 0xFF, 0x33);
 470         } else {
 471                 RTSX_WRITE_REG(chip, WAKE_SEL_CTL, 0x07, 0x04);
 472                 RTSX_WRITE_REG(chip, PME_FORCE_CTL, 0xFF, 0x30);
 473         }
 474
 475         if (CHECK_PID(chip, 0x5208) && (chip->ic_version >= IC_VER_D))
 476                 RTSX_WRITE_REG(chip, PETXCFG, 0x1C, 0x14);
 477
 478         if (chip->asic_code && CHECK_PID(chip, 0x5208)) {
 479                 retval = rtsx_clr_phy_reg_bit(chip, 0x1C, 2);
 480                 if (retval != STATUS_SUCCESS)
 481                         TRACE_RET(chip, STATUS_FAIL);
 482         }
 483
 484         if (chip->ft2_fast_mode) {
 485                 RTSX_WRITE_REG(chip, CARD_PWR_CTL, 0xFF,
 486                         MS_PARTIAL_POWER_ON | SD_PARTIAL_POWER_ON);
 487                 udelay(chip->pmos_pwr_on_interval);
 488                 RTSX_WRITE_REG(chip, CARD_PWR_CTL, 0xFF,
 489                         MS_POWER_ON | SD_POWER_ON);
 490
 491                 wait_timeout(200);
 492         }
 493
 494         /* Reset card */
 495         rtsx_reset_detected_cards(chip, 0);
 496
 497         chip->driver_first_load = 0;
 498
 499         return STATUS_SUCCESS;
 500 }
 501
 502 static inline int check_sd_speed_prior(u32 sd_speed_prior)
 503 {
 504         int i, fake_para = 0;
 505
 506         for (i = 0; i < 4; i++) {
 507                 u8 tmp = (u8)(sd_speed_prior >> (i*8));
 508                 if ((tmp < 0x01) || (tmp > 0x04)) {
 509                         fake_para = 1;
 510                         break;
 511                 }
 512         }
 513
 514         return !fake_para;
 515 }
 516
 517 static inline int check_sd_current_prior(u32 sd_current_prior)
 518 {
 519         int i, fake_para = 0;
 520
 521         for (i = 0; i < 4; i++) {
 522                 u8 tmp = (u8)(sd_current_prior >> (i*8));
 523                 if (tmp > 0x03) {
 524                         fake_para = 1;
 525                         break;
 526                 }
 527         }
 528
 529         return !fake_para;
 530 }
 531
 532 static int rts5208_init(struct rtsx_chip *chip)
 533 {
 534         int retval;
 535         u16 reg = 0;
 536         u8 val = 0;
 537
 538         RTSX_WRITE_REG(chip, CLK_SEL, 0x03, 0x03);
 539         RTSX_READ_REG(chip, CLK_SEL, &val);
 540         if (val == 0)
 541                 chip->asic_code = 1;
 542         else
 543                 chip->asic_code = 0;
 544
 545         if (chip->asic_code) {
 546                 retval = rtsx_read_phy_register(chip, 0x1C, &reg);
 547                 if (retval != STATUS_SUCCESS)
 548                         TRACE_RET(chip, STATUS_FAIL);
 549
 550                 dev_dbg(rtsx_dev(chip), "Value of phy register 0x1C is 0x%x\n",
 551                         reg);
 552                 chip->ic_version = (reg >> 4) & 0x07;
 553                 if (reg & PHY_DEBUG_MODE)
 554                         chip->phy_debug_mode = 1;
 555                 else
 556                         chip->phy_debug_mode = 0;
 557
 558         } else {
 559                 RTSX_READ_REG(chip, 0xFE80, &val);
 560                 chip->ic_version = val;
 561                 chip->phy_debug_mode = 0;
 562         }
 563
 564         RTSX_READ_REG(chip, PDINFO, &val);
 565         dev_dbg(rtsx_dev(chip), "PDINFO: 0x%x\n", val);
 566         if (val & AUX_PWR_DETECTED)
 567                 chip->aux_pwr_exist = 1;
 568         else
 569                 chip->aux_pwr_exist = 0;
 570
 571         RTSX_READ_REG(chip, 0xFE50, &val);
 572         if (val & 0x01)
 573                 chip->hw_bypass_sd = 1;
 574         else
 575                 chip->hw_bypass_sd = 0;
 576
 577         rtsx_read_config_byte(chip, 0x0E, &val);
 578         if (val & 0x80)
 579                 SET_SDIO_EXIST(chip);
 580         else
 581                 CLR_SDIO_EXIST(chip);
 582
 583         if (chip->use_hw_setting) {
 584                 RTSX_READ_REG(chip, CHANGE_LINK_STATE, &val);
 585                 if (val & 0x80)
 586                         chip->auto_delink_en = 1;
 587                 else
 588                         chip->auto_delink_en = 0;
 589         }
 590
 591         return STATUS_SUCCESS;
 592 }
 593
 594 static int rts5288_init(struct rtsx_chip *chip)
 595 {
 596         int retval;
 597         u8 val = 0, max_func;
 598         u32 lval = 0;
 599
 600         RTSX_WRITE_REG(chip, CLK_SEL, 0x03, 0x03);
 601         RTSX_READ_REG(chip, CLK_SEL, &val);
 602         if (val == 0)
 603                 chip->asic_code = 1;
 604         else
 605                 chip->asic_code = 0;
 606
 607         chip->ic_version = 0;
 608         chip->phy_debug_mode = 0;
 609
 610         RTSX_READ_REG(chip, PDINFO, &val);
 611         dev_dbg(rtsx_dev(chip), "PDINFO: 0x%x\n", val);
 612         if (val & AUX_PWR_DETECTED)
 613                 chip->aux_pwr_exist = 1;
 614         else
 615                 chip->aux_pwr_exist = 0;
 616
 617         RTSX_READ_REG(chip, CARD_SHARE_MODE, &val);
 618         dev_dbg(rtsx_dev(chip), "CARD_SHARE_MODE: 0x%x\n", val);
 619         if (val & 0x04)
 620                 chip->baro_pkg = QFN;
 621         else
 622                 chip->baro_pkg = LQFP;
 623
 624         RTSX_READ_REG(chip, 0xFE5A, &val);
 625         if (val & 0x10)
 626                 chip->hw_bypass_sd = 1;
 627         else
 628                 chip->hw_bypass_sd = 0;
 629
 630         retval = rtsx_read_cfg_dw(chip, 0, 0x718, &lval);
 631         if (retval != STATUS_SUCCESS)
 632                 TRACE_RET(chip, STATUS_FAIL);
 633
 634         max_func = (u8)((lval >> 29) & 0x07);
 635         dev_dbg(rtsx_dev(chip), "Max function number: %d\n", max_func);
 636         if (max_func == 0x02)
 637                 SET_SDIO_EXIST(chip);
 638         else
 639                 CLR_SDIO_EXIST(chip);
 640
 641         if (chip->use_hw_setting) {
 642                 RTSX_READ_REG(chip, CHANGE_LINK_STATE, &val);
 643                 if (val & 0x80)
 644                         chip->auto_delink_en = 1;
 645                 else
 646                         chip->auto_delink_en = 0;
 647
 648                 if (CHECK_BARO_PKG(chip, LQFP))
 649                         chip->lun_mode = SD_MS_1LUN;
 650                 else
 651                         chip->lun_mode = DEFAULT_SINGLE;
 652
 653         }
 654
 655         return STATUS_SUCCESS;
 656 }
 657
 658 int rtsx_init_chip(struct rtsx_chip *chip)
 659 {
 660         struct sd_info *sd_card = &(chip->sd_card);
 661         struct xd_info *xd_card = &(chip->xd_card);
 662         struct ms_info *ms_card = &(chip->ms_card);
 663         int retval;
 664         unsigned int i;
 665
 666         dev_dbg(rtsx_dev(chip), "Vendor ID: 0x%04x, Product ID: 0x%04x\n",
 667                 chip->vendor_id, chip->product_id);
 668
 669         chip->ic_version = 0;
 670
 671 #ifdef _MSG_TRACE
 672         chip->msg_idx = 0;
 673 #endif
 674
 675         memset(xd_card, 0, sizeof(struct xd_info));
 676         memset(sd_card, 0, sizeof(struct sd_info));
 677         memset(ms_card, 0, sizeof(struct ms_info));
 678
 679         chip->xd_reset_counter = 0;
 680         chip->sd_reset_counter = 0;
 681         chip->ms_reset_counter = 0;
 682
 683         chip->xd_show_cnt = MAX_SHOW_CNT;
 684         chip->sd_show_cnt = MAX_SHOW_CNT;
 685         chip->ms_show_cnt = MAX_SHOW_CNT;
 686
 687         chip->sd_io = 0;
 688         chip->auto_delink_cnt = 0;
 689         chip->auto_delink_allowed = 1;
 690         rtsx_set_stat(chip, RTSX_STAT_INIT);
 691
 692         chip->aspm_enabled = 0;
 693         chip->chip_insert_with_sdio = 0;
 694         chip->sdio_aspm = 0;
 695         chip->sdio_idle = 0;
 696         chip->sdio_counter = 0;
 697         chip->cur_card = 0;
 698         chip->phy_debug_mode = 0;
 699         chip->sdio_func_exist = 0;
 700         memset(chip->sdio_raw_data, 0, 12);
 701
 702         for (i = 0; i < MAX_ALLOWED_LUN_CNT; i++) {
 703                 set_sense_type(chip, i, SENSE_TYPE_NO_SENSE);
 704                 chip->rw_fail_cnt[i] = 0;
 705         }
 706
 707         if (!check_sd_speed_prior(chip->sd_speed_prior))
 708                 chip->sd_speed_prior = 0x01040203;
 709
 710         dev_dbg(rtsx_dev(chip), "sd_speed_prior = 0x%08x\n",
 711                 chip->sd_speed_prior);
 712
 713         if (!check_sd_current_prior(chip->sd_current_prior))
 714                 chip->sd_current_prior = 0x00010203;
 715
 716         dev_dbg(rtsx_dev(chip), "sd_current_prior = 0x%08x\n",
 717                 chip->sd_current_prior);
 718
 719         if ((chip->sd_ddr_tx_phase > 31) || (chip->sd_ddr_tx_phase < 0))
 720                 chip->sd_ddr_tx_phase = 0;
 721
 722         if ((chip->mmc_ddr_tx_phase > 31) || (chip->mmc_ddr_tx_phase < 0))
 723                 chip->mmc_ddr_tx_phase = 0;
 724
 725         RTSX_WRITE_REG(chip, FPDCTL, SSC_POWER_DOWN, 0);
 726         wait_timeout(200);
 727         RTSX_WRITE_REG(chip, CLK_DIV, 0x07, 0x07);
 728         dev_dbg(rtsx_dev(chip), "chip->use_hw_setting = %d\n",
 729                 chip->use_hw_setting);
 730
 731         if (CHECK_PID(chip, 0x5208)) {
 732                 retval = rts5208_init(chip);
 733                 if (retval != STATUS_SUCCESS)
 734                         TRACE_RET(chip, STATUS_FAIL);
 735
 736         } else if (CHECK_PID(chip, 0x5288)) {
 737                 retval = rts5288_init(chip);
 738                 if (retval != STATUS_SUCCESS)
 739                         TRACE_RET(chip, STATUS_FAIL);
 740
 741         }
 742
 743         if (chip->ss_en == 2)
 744                 chip->ss_en = 0;
 745
 746         dev_dbg(rtsx_dev(chip), "chip->asic_code = %d\n", chip->asic_code);
 747         dev_dbg(rtsx_dev(chip), "chip->ic_version = 0x%x\n", chip->ic_version);
 748         dev_dbg(rtsx_dev(chip), "chip->phy_debug_mode = %d\n",
 749                 chip->phy_debug_mode);
 750         dev_dbg(rtsx_dev(chip), "chip->aux_pwr_exist = %d\n",
 751                 chip->aux_pwr_exist);
 752         dev_dbg(rtsx_dev(chip), "chip->sdio_func_exist = %d\n",
 753                 chip->sdio_func_exist);
 754         dev_dbg(rtsx_dev(chip), "chip->hw_bypass_sd = %d\n",
 755                 chip->hw_bypass_sd);
 756         dev_dbg(rtsx_dev(chip), "chip->aspm_l0s_l1_en = %d\n",
 757                 chip->aspm_l0s_l1_en);
 758         dev_dbg(rtsx_dev(chip), "chip->lun_mode = %d\n", chip->lun_mode);
 759         dev_dbg(rtsx_dev(chip), "chip->auto_delink_en = %d\n",
 760                 chip->auto_delink_en);
 761         dev_dbg(rtsx_dev(chip), "chip->ss_en = %d\n", chip->ss_en);
 762         dev_dbg(rtsx_dev(chip), "chip->baro_pkg = %d\n", chip->baro_pkg);
 763
 764         if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
 765                 chip->card2lun[SD_CARD] = 0;
 766                 chip->card2lun[MS_CARD] = 1;
 767                 chip->card2lun[XD_CARD] = 0xFF;
 768                 chip->lun2card[0] = SD_CARD;
 769                 chip->lun2card[1] = MS_CARD;
 770                 chip->max_lun = 1;
 771                 SET_SDIO_IGNORED(chip);
 772         } else if (CHECK_LUN_MODE(chip, SD_MS_1LUN)) {
 773                 chip->card2lun[SD_CARD] = 0;
 774                 chip->card2lun[MS_CARD] = 0;
 775                 chip->card2lun[XD_CARD] = 0xFF;
 776                 chip->lun2card[0] = SD_CARD | MS_CARD;
 777                 chip->max_lun = 0;
 778         } else {
 779                 chip->card2lun[XD_CARD] = 0;
 780                 chip->card2lun[SD_CARD] = 0;
 781                 chip->card2lun[MS_CARD] = 0;
 782                 chip->lun2card[0] = XD_CARD | SD_CARD | MS_CARD;
 783                 chip->max_lun = 0;
 784         }
 785
 786         retval = rtsx_reset_chip(chip);
 787         if (retval != STATUS_SUCCESS)
 788                 TRACE_RET(chip, STATUS_FAIL);
 789
 790         return STATUS_SUCCESS;
 791 }
 792
 793 void rtsx_release_chip(struct rtsx_chip *chip)
 794 {
 795         xd_free_l2p_tbl(chip);
 796         ms_free_l2p_tbl(chip);
 797         chip->card_exist = 0;
 798         chip->card_ready = 0;
 799 }
 800
 801 #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK)
 802 static inline void rtsx_blink_led(struct rtsx_chip *chip)
 803 {
 804         if (chip->card_exist && chip->blink_led) {
 805                 if (chip->led_toggle_counter < LED_TOGGLE_INTERVAL) {
 806                         chip->led_toggle_counter++;
 807                 } else {
 808                         chip->led_toggle_counter = 0;
 809                         toggle_gpio(chip, LED_GPIO);
 810                 }
 811         }
 812 }
 813 #endif
 814
 815 static void rtsx_monitor_aspm_config(struct rtsx_chip *chip)
 816 {
 817         int maybe_support_aspm, reg_changed;
 818         u32 tmp = 0;
 819         u8 reg0 = 0, reg1 = 0;
 820
 821         maybe_support_aspm = 0;
 822         reg_changed = 0;
 823         rtsx_read_config_byte(chip, LCTLR, &reg0);
 824         if (chip->aspm_level[0] != reg0) {
 825                 reg_changed = 1;
 826                 chip->aspm_level[0] = reg0;
 827         }
 828         if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) {
 829                 rtsx_read_cfg_dw(chip, 1, 0xC0, &tmp);
 830                 reg1 = (u8)tmp;
 831                 if (chip->aspm_level[1] != reg1) {
 832                         reg_changed = 1;
 833                         chip->aspm_level[1] = reg1;
 834                 }
 835
 836                 if ((reg0 & 0x03) && (reg1 & 0x03))
 837                         maybe_support_aspm = 1;
 838
 839         } else {
 840                 if (reg0 & 0x03)
 841                         maybe_support_aspm = 1;
 842
 843         }
 844
 845         if (reg_changed) {
 846                 if (maybe_support_aspm)
 847                         chip->aspm_l0s_l1_en = 0x03;
 848
 849                 dev_dbg(rtsx_dev(chip), "aspm_level[0] = 0x%02x, aspm_level[1] = 0x%02x\n",
 850                         chip->aspm_level[0], chip->aspm_level[1]);
 851
 852                 if (chip->aspm_l0s_l1_en) {
 853                         chip->aspm_enabled = 1;
 854                 } else {
 855                         chip->aspm_enabled = 0;
 856                         chip->sdio_aspm = 0;
 857                 }
 858                 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFF,
 859                                 0x30 | chip->aspm_level[0] |
 860                                 (chip->aspm_level[1] << 2));
 861         }
 862 }
 863
 864 void rtsx_polling_func(struct rtsx_chip *chip)
 865 {
 866 #ifdef SUPPORT_SD_LOCK
 867         struct sd_info *sd_card = &(chip->sd_card);
 868 #endif
 869         int ss_allowed;
 870
 871         if (rtsx_chk_stat(chip, RTSX_STAT_SUSPEND))
 872                 return;
 873
 874         if (rtsx_chk_stat(chip, RTSX_STAT_DELINK))
 875                 goto Delink_Stage;
 876
 877         if (chip->polling_config) {
 878                 u8 val;
 879                 rtsx_read_config_byte(chip, 0, &val);
 880         }
 881
 882         if (rtsx_chk_stat(chip, RTSX_STAT_SS))
 883                 return;
 884
 885 #ifdef SUPPORT_OCP
 886         if (chip->ocp_int) {
 887                 rtsx_read_register(chip, OCPSTAT, &(chip->ocp_stat));
 888
 889                 if (chip->card_exist & SD_CARD)
 890                         sd_power_off_card3v3(chip);
 891                 else if (chip->card_exist & MS_CARD)
 892                         ms_power_off_card3v3(chip);
 893                 else if (chip->card_exist & XD_CARD)
 894                         xd_power_off_card3v3(chip);
 895
 896                 chip->ocp_int = 0;
 897         }
 898 #endif
 899
 900 #ifdef SUPPORT_SD_LOCK
 901         if (sd_card->sd_erase_status) {
 902                 if (chip->card_exist & SD_CARD) {
 903                         u8 val;
 904                         rtsx_read_register(chip, 0xFD30, &val);
 905                         if (val & 0x02) {
 906                                 sd_card->sd_erase_status = SD_NOT_ERASE;
 907                                 sd_card->sd_lock_notify = 1;
 908                                 chip->need_reinit |= SD_CARD;
 909                         }
 910                 } else {
 911                         sd_card->sd_erase_status = SD_NOT_ERASE;
 912                 }
 913         }
 914 #endif
 915
 916         rtsx_init_cards(chip);
 917
 918         if (chip->ss_en) {
 919                 ss_allowed = 1;
 920
 921                 if (CHECK_PID(chip, 0x5288)) {
 922                         ss_allowed = 0;
 923                 } else {
 924                         if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) {
 925                                 u32 val;
 926                                 rtsx_read_cfg_dw(chip, 1, 0x04, &val);
 927                                 if (val & 0x07)
 928                                         ss_allowed = 0;
 929
 930                         }
 931                 }
 932         } else {
 933                 ss_allowed = 0;
 934         }
 935
 936         if (ss_allowed && !chip->sd_io) {
 937                 if (rtsx_get_stat(chip) != RTSX_STAT_IDLE) {
 938                         chip->ss_counter = 0;
 939                 } else {
 940                         if (chip->ss_counter <
 941                                 (chip->ss_idle_period / POLLING_INTERVAL)) {
 942                                 chip->ss_counter++;
 943                         } else {
 944                                 rtsx_exclusive_enter_ss(chip);
 945                                 return;
 946                         }
 947                 }
 948         }
 949
 950         if (CHECK_PID(chip, 0x5208)) {
 951                 rtsx_monitor_aspm_config(chip);
 952
 953 #ifdef SUPPORT_SDIO_ASPM
 954                 if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip) &&
 955                                 chip->aspm_l0s_l1_en && chip->dynamic_aspm) {
 956                         if (chip->sd_io) {
 957                                 dynamic_configure_sdio_aspm(chip);
 958                         } else {
 959                                 if (!chip->sdio_aspm) {
 960                                         dev_dbg(rtsx_dev(chip), "SDIO enter ASPM!\n");
 961                                         rtsx_write_register(chip,
 962                                                 ASPM_FORCE_CTL, 0xFC,
 963                                                 0x30 | (chip->aspm_level[1] << 2));
 964                                         chip->sdio_aspm = 1;
 965                                 }
 966                         }
 967                 }
 968 #endif
 969         }
 970
 971         if (chip->idle_counter < IDLE_MAX_COUNT) {
 972                 chip->idle_counter++;
 973         } else {
 974                 if (rtsx_get_stat(chip) != RTSX_STAT_IDLE) {
 975                         dev_dbg(rtsx_dev(chip), "Idle state!\n");
 976                         rtsx_set_stat(chip, RTSX_STAT_IDLE);
 977
 978 #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK)
 979                         chip->led_toggle_counter = 0;
 980 #endif
 981                         rtsx_force_power_on(chip, SSC_PDCTL);
 982
 983                         turn_off_led(chip, LED_GPIO);
 984
 985                         if (chip->auto_power_down && !chip->card_ready && !chip->sd_io)
 986                                 rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL);
 987
 988                 }
 989         }
 990
 991         switch (rtsx_get_stat(chip)) {
 992         case RTSX_STAT_RUN:
 993 #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK)
 994                 rtsx_blink_led(chip);
 995 #endif
 996                 do_remaining_work(chip);
 997                 break;
 998
 999         case RTSX_STAT_IDLE:
1000                 if (chip->sd_io && !chip->sd_int)
1001                         try_to_switch_sdio_ctrl(chip);
1002
1003                 rtsx_enable_aspm(chip);
1004                 break;
1005
1006         default:
1007                 break;
1008         }
1009
1010
1011 #ifdef SUPPORT_OCP
1012         if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
1013                 if (chip->ocp_stat &
1014                         (SD_OC_NOW | SD_OC_EVER | MS_OC_NOW | MS_OC_EVER))
1015                         dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n",
1016                                 chip->ocp_stat);
1017
1018                 if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
1019                         if (chip->card_exist & SD_CARD) {
1020                                 rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN,
1021                                                 0);
1022                                 card_power_off(chip, SD_CARD);
1023                                 chip->card_fail |= SD_CARD;
1024                         }
1025                 }
1026                 if (chip->ocp_stat & (MS_OC_NOW | MS_OC_EVER)) {
1027                         if (chip->card_exist & MS_CARD) {
1028                                 rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN,
1029                                                 0);
1030                                 card_power_off(chip, MS_CARD);
1031                                 chip->card_fail |= MS_CARD;
1032                         }
1033                 }
1034         } else {
1035                 if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
1036                         dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n",
1037                                 chip->ocp_stat);
1038                         if (chip->card_exist & SD_CARD) {
1039                                 rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN,
1040                                                 0);
1041                                 chip->card_fail |= SD_CARD;
1042                         } else if (chip->card_exist & MS_CARD) {
1043                                 rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN,
1044                                                 0);
1045                                 chip->card_fail |= MS_CARD;
1046                         } else if (chip->card_exist & XD_CARD) {
1047                                 rtsx_write_register(chip, CARD_OE, XD_OUTPUT_EN,
1048                                                 0);
1049                                 chip->card_fail |= XD_CARD;
1050                         }
1051                         card_power_off(chip, SD_CARD);
1052                 }
1053         }
1054 #endif
1055
1056 Delink_Stage:
1057         if (chip->auto_delink_en && chip->auto_delink_allowed &&
1058                 !chip->card_ready && !chip->card_ejected && !chip->sd_io) {
1059                 int enter_L1 = chip->auto_delink_in_L1 && (
1060                         chip->aspm_l0s_l1_en || chip->ss_en);
1061                 int delink_stage1_cnt = chip->delink_stage1_step;
1062                 int delink_stage2_cnt = delink_stage1_cnt +
1063                         chip->delink_stage2_step;
1064                 int delink_stage3_cnt = delink_stage2_cnt +
1065                         chip->delink_stage3_step;
1066
1067                 if (chip->auto_delink_cnt <= delink_stage3_cnt) {
1068                         if (chip->auto_delink_cnt == delink_stage1_cnt) {
1069                                 rtsx_set_stat(chip, RTSX_STAT_DELINK);
1070
1071                                 if (chip->asic_code && CHECK_PID(chip, 0x5208))
1072                                         rtsx_set_phy_reg_bit(chip, 0x1C, 2);
1073
1074                                 if (chip->card_exist) {
1075                                         dev_dbg(rtsx_dev(chip), "False card inserted, do force delink\n");
1076
1077                                         if (enter_L1)
1078                                                 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, 1);
1079
1080                                         rtsx_write_register(chip,
1081                                                         CHANGE_LINK_STATE, 0x0A,
1082                                                         0x0A);
1083
1084                                         if (enter_L1)
1085                                                 rtsx_enter_L1(chip);
1086
1087                                         chip->auto_delink_cnt = delink_stage3_cnt + 1;
1088                                 } else {
1089                                         dev_dbg(rtsx_dev(chip), "No card inserted, do delink\n");
1090
1091                                         if (enter_L1)
1092                                                 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, 1);
1093
1094                                         rtsx_write_register(chip, CHANGE_LINK_STATE, 0x02, 0x02);
1095
1096                                         if (enter_L1)
1097                                                 rtsx_enter_L1(chip);
1098
1099                                 }
1100                         }
1101
1102                         if (chip->auto_delink_cnt == delink_stage2_cnt) {
1103                                 dev_dbg(rtsx_dev(chip), "Try to do force delink\n");
1104
1105                                 if (enter_L1)
1106                                         rtsx_exit_L1(chip);
1107
1108                                 if (chip->asic_code && CHECK_PID(chip, 0x5208))
1109                                         rtsx_set_phy_reg_bit(chip, 0x1C, 2);
1110
1111                                 rtsx_write_register(chip, CHANGE_LINK_STATE,
1112                                                 0x0A, 0x0A);
1113                         }
1114
1115                         chip->auto_delink_cnt++;
1116                 }
1117         } else {
1118                 chip->auto_delink_cnt = 0;
1119         }
1120 }
1121
1122 void rtsx_undo_delink(struct rtsx_chip *chip)
1123 {
1124         chip->auto_delink_allowed = 0;
1125         rtsx_write_register(chip, CHANGE_LINK_STATE, 0x0A, 0x00);
1126 }
1127
1128 /**
1129  * rtsx_stop_cmd - stop command transfer and DMA transfer
1130  * @chip: Realtek's card reader chip
1131  * @card: flash card type
1132  *
1133  * Stop command transfer and DMA transfer.
1134  * This function is called in error handler.
1135  */
1136 void rtsx_stop_cmd(struct rtsx_chip *chip, int card)
1137 {
1138         int i;
1139
1140         for (i = 0; i <= 8; i++) {
1141                 int addr = RTSX_HCBAR + i * 4;
1142                 u32 reg;
1143                 reg = rtsx_readl(chip, addr);
1144                 dev_dbg(rtsx_dev(chip), "BAR (0x%02x): 0x%08x\n", addr, reg);
1145         }
1146         rtsx_writel(chip, RTSX_HCBCTLR, STOP_CMD);
1147         rtsx_writel(chip, RTSX_HDBCTLR, STOP_DMA);
1148
1149         for (i = 0; i < 16; i++) {
1150                 u16 addr = 0xFE20 + (u16)i;
1151                 u8 val;
1152                 rtsx_read_register(chip, addr, &val);
1153                 dev_dbg(rtsx_dev(chip), "0x%04X: 0x%02x\n", addr, val);
1154         }
1155
1156         rtsx_write_register(chip, DMACTL, 0x80, 0x80);
1157         rtsx_write_register(chip, RBCTL, 0x80, 0x80);
1158 }
1159
1160 #define MAX_RW_REG_CNT          1024
1161
1162 int rtsx_write_register(struct rtsx_chip *chip, u16 addr, u8 mask, u8 data)
1163 {
1164         int i;
1165         u32 val = 3 << 30;
1166
1167         val |= (u32)(addr & 0x3FFF) << 16;
1168         val |= (u32)mask << 8;
1169         val |= (u32)data;
1170
1171         rtsx_writel(chip, RTSX_HAIMR, val);
1172
1173         for (i = 0; i < MAX_RW_REG_CNT; i++) {
1174                 val = rtsx_readl(chip, RTSX_HAIMR);
1175                 if ((val & (1 << 31)) == 0) {
1176                         if (data != (u8)val)
1177                                 TRACE_RET(chip, STATUS_FAIL);
1178
1179                         return STATUS_SUCCESS;
1180                 }
1181         }
1182
1183         TRACE_RET(chip, STATUS_TIMEDOUT);
1184 }
1185
1186 int rtsx_read_register(struct rtsx_chip *chip, u16 addr, u8 *data)
1187 {
1188         u32 val = 2 << 30;
1189         int i;
1190
1191         if (data)
1192                 *data = 0;
1193
1194         val |= (u32)(addr & 0x3FFF) << 16;
1195
1196         rtsx_writel(chip, RTSX_HAIMR, val);
1197
1198         for (i = 0; i < MAX_RW_REG_CNT; i++) {
1199                 val = rtsx_readl(chip, RTSX_HAIMR);
1200                 if ((val & (1 << 31)) == 0)
1201                         break;
1202         }
1203
1204         if (i >= MAX_RW_REG_CNT)
1205                 TRACE_RET(chip, STATUS_TIMEDOUT);
1206
1207         if (data)
1208                 *data = (u8)(val & 0xFF);
1209
1210         return STATUS_SUCCESS;
1211 }
1212
1213 int rtsx_write_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 mask,
1214                 u32 val)
1215 {
1216         u8 mode = 0, tmp;
1217         int i;
1218
1219         for (i = 0; i < 4; i++) {
1220                 if (mask & 0xFF) {
1221                         RTSX_WRITE_REG(chip, CFGDATA0 + i,
1222                                        0xFF, (u8)(val & mask & 0xFF));
1223                         mode |= (1 << i);
1224                 }
1225                 mask >>= 8;
1226                 val >>= 8;
1227         }
1228
1229         if (mode) {
1230                 RTSX_WRITE_REG(chip, CFGADDR0, 0xFF, (u8)addr);
1231                 RTSX_WRITE_REG(chip, CFGADDR1, 0xFF, (u8)(addr >> 8));
1232
1233                 RTSX_WRITE_REG(chip, CFGRWCTL, 0xFF,
1234                                0x80 | mode | ((func_no & 0x03) << 4));
1235
1236                 for (i = 0; i < MAX_RW_REG_CNT; i++) {
1237                         RTSX_READ_REG(chip, CFGRWCTL, &tmp);
1238                         if ((tmp & 0x80) == 0)
1239                                 break;
1240                 }
1241         }
1242
1243         return STATUS_SUCCESS;
1244 }
1245
1246 int rtsx_read_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 *val)
1247 {
1248         int i;
1249         u8 tmp;
1250         u32 data = 0;
1251
1252         RTSX_WRITE_REG(chip, CFGADDR0, 0xFF, (u8)addr);
1253         RTSX_WRITE_REG(chip, CFGADDR1, 0xFF, (u8)(addr >> 8));
1254         RTSX_WRITE_REG(chip, CFGRWCTL, 0xFF, 0x80 | ((func_no & 0x03) << 4));
1255
1256         for (i = 0; i < MAX_RW_REG_CNT; i++) {
1257                 RTSX_READ_REG(chip, CFGRWCTL, &tmp);
1258                 if ((tmp & 0x80) == 0)
1259                         break;
1260         }
1261
1262         for (i = 0; i < 4; i++) {
1263                 RTSX_READ_REG(chip, CFGDATA0 + i, &tmp);
1264                 data |= (u32)tmp << (i * 8);
1265         }
1266
1267         if (val)
1268                 *val = data;
1269
1270         return STATUS_SUCCESS;
1271 }
1272
1273 int rtsx_write_cfg_seq(struct rtsx_chip *chip, u8 func, u16 addr, u8 *buf,
1274                 int len)
1275 {
1276         u32 *data, *mask;
1277         u16 offset = addr % 4;
1278         u16 aligned_addr = addr - offset;
1279         int dw_len, i, j;
1280         int retval;
1281
1282         if (!buf)
1283                 TRACE_RET(chip, STATUS_NOMEM);
1284
1285         if ((len + offset) % 4)
1286                 dw_len = (len + offset) / 4 + 1;
1287         else
1288                 dw_len = (len + offset) / 4;
1289
1290         dev_dbg(rtsx_dev(chip), "dw_len = %d\n", dw_len);
1291
1292         data = vzalloc(dw_len * 4);
1293         if (!data)
1294                 TRACE_RET(chip, STATUS_NOMEM);
1295
1296         mask = vzalloc(dw_len * 4);
1297         if (!mask) {
1298                 vfree(data);
1299                 TRACE_RET(chip, STATUS_NOMEM);
1300         }
1301
1302         j = 0;
1303         for (i = 0; i < len; i++) {
1304                 mask[j] |= 0xFF << (offset * 8);
1305                 data[j] |= buf[i] << (offset * 8);
1306                 if (++offset == 4) {
1307                         j++;
1308                         offset = 0;
1309                 }
1310         }
1311
1312         RTSX_DUMP(mask, dw_len * 4);
1313         RTSX_DUMP(data, dw_len * 4);
1314
1315         for (i = 0; i < dw_len; i++) {
1316                 retval = rtsx_write_cfg_dw(chip, func, aligned_addr + i * 4,
1317                                         mask[i], data[i]);
1318                 if (retval != STATUS_SUCCESS) {
1319                         vfree(data);
1320                         vfree(mask);
1321                         TRACE_RET(chip, STATUS_FAIL);
1322                 }
1323         }
1324
1325         vfree(data);
1326         vfree(mask);
1327
1328         return STATUS_SUCCESS;
1329 }
1330
1331 int rtsx_read_cfg_seq(struct rtsx_chip *chip, u8 func, u16 addr, u8 *buf,
1332                 int len)
1333 {
1334         u32 *data;
1335         u16 offset = addr % 4;
1336         u16 aligned_addr = addr - offset;
1337         int dw_len, i, j;
1338         int retval;
1339
1340         if ((len + offset) % 4)
1341                 dw_len = (len + offset) / 4 + 1;
1342         else
1343                 dw_len = (len + offset) / 4;
1344
1345         dev_dbg(rtsx_dev(chip), "dw_len = %d\n", dw_len);
1346
1347         data = vmalloc(dw_len * 4);
1348         if (!data)
1349                 TRACE_RET(chip, STATUS_NOMEM);
1350
1351         for (i = 0; i < dw_len; i++) {
1352                 retval = rtsx_read_cfg_dw(chip, func, aligned_addr + i * 4,
1353                                         data + i);
1354                 if (retval != STATUS_SUCCESS) {
1355                         vfree(data);
1356                         TRACE_RET(chip, STATUS_FAIL);
1357                 }
1358         }
1359
1360         if (buf) {
1361                 j = 0;
1362
1363                 for (i = 0; i < len; i++) {
1364                         buf[i] = (u8)(data[j] >> (offset * 8));
1365                         if (++offset == 4) {
1366                                 j++;
1367                                 offset = 0;
1368                         }
1369                 }
1370         }
1371
1372         vfree(data);
1373
1374         return STATUS_SUCCESS;
1375 }
1376
1377 int rtsx_write_phy_register(struct rtsx_chip *chip, u8 addr, u16 val)
1378 {
1379         int i, finished = 0;
1380         u8 tmp;
1381
1382         RTSX_WRITE_REG(chip, PHYDATA0, 0xFF, (u8)val);
1383         RTSX_WRITE_REG(chip, PHYDATA1, 0xFF, (u8)(val >> 8));
1384         RTSX_WRITE_REG(chip, PHYADDR, 0xFF, addr);
1385         RTSX_WRITE_REG(chip, PHYRWCTL, 0xFF, 0x81);
1386
1387         for (i = 0; i < 100000; i++) {
1388                 RTSX_READ_REG(chip, PHYRWCTL, &tmp);
1389                 if (!(tmp & 0x80)) {
1390                         finished = 1;
1391                         break;
1392                 }
1393         }
1394
1395         if (!finished)
1396                 TRACE_RET(chip, STATUS_FAIL);
1397
1398         return STATUS_SUCCESS;
1399 }
1400
1401 int rtsx_read_phy_register(struct rtsx_chip *chip, u8 addr, u16 *val)
1402 {
1403         int i, finished = 0;
1404         u16 data = 0;
1405         u8 tmp;
1406
1407         RTSX_WRITE_REG(chip, PHYADDR, 0xFF, addr);
1408         RTSX_WRITE_REG(chip, PHYRWCTL, 0xFF, 0x80);
1409
1410         for (i = 0; i < 100000; i++) {
1411                 RTSX_READ_REG(chip, PHYRWCTL, &tmp);
1412                 if (!(tmp & 0x80)) {
1413                         finished = 1;
1414                         break;
1415                 }
1416         }
1417
1418         if (!finished)
1419                 TRACE_RET(chip, STATUS_FAIL);
1420
1421         RTSX_READ_REG(chip, PHYDATA0, &tmp);
1422         data = tmp;
1423         RTSX_READ_REG(chip, PHYDATA1, &tmp);
1424         data |= (u16)tmp << 8;
1425
1426         if (val)
1427                 *val = data;
1428
1429         return STATUS_SUCCESS;
1430 }
1431
1432 int rtsx_read_efuse(struct rtsx_chip *chip, u8 addr, u8 *val)
1433 {
1434         int i;
1435         u8 data = 0;
1436
1437         RTSX_WRITE_REG(chip, EFUSE_CTRL, 0xFF, 0x80|addr);
1438
1439         for (i = 0; i < 100; i++) {
1440                 RTSX_READ_REG(chip, EFUSE_CTRL, &data);
1441                 if (!(data & 0x80))
1442                         break;
1443                 udelay(1);
1444         }
1445
1446         if (data & 0x80)
1447                 TRACE_RET(chip, STATUS_TIMEDOUT);
1448
1449         RTSX_READ_REG(chip, EFUSE_DATA, &data);
1450         if (val)
1451                 *val = data;
1452
1453         return STATUS_SUCCESS;
1454 }
1455
1456 int rtsx_write_efuse(struct rtsx_chip *chip, u8 addr, u8 val)
1457 {
1458         int i, j;
1459         u8 data = 0, tmp = 0xFF;
1460
1461         for (i = 0; i < 8; i++) {
1462                 if (val & (u8)(1 << i))
1463                         continue;
1464
1465                 tmp &= (~(u8)(1 << i));
1466                 dev_dbg(rtsx_dev(chip), "Write 0x%x to 0x%x\n", tmp, addr);
1467
1468                 RTSX_WRITE_REG(chip, EFUSE_DATA, 0xFF, tmp);
1469                 RTSX_WRITE_REG(chip, EFUSE_CTRL, 0xFF, 0xA0|addr);
1470
1471                 for (j = 0; j < 100; j++) {
1472                         RTSX_READ_REG(chip, EFUSE_CTRL, &data);
1473                         if (!(data & 0x80))
1474                                 break;
1475                         wait_timeout(3);
1476                 }
1477
1478                 if (data & 0x80)
1479                         TRACE_RET(chip, STATUS_TIMEDOUT);
1480
1481                 wait_timeout(5);
1482         }
1483
1484         return STATUS_SUCCESS;
1485 }
1486
1487 int rtsx_clr_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit)
1488 {
1489         int retval;
1490         u16 value;
1491
1492         retval = rtsx_read_phy_register(chip, reg, &value);
1493         if (retval != STATUS_SUCCESS)
1494                 TRACE_RET(chip, STATUS_FAIL);
1495
1496         if (value & (1 << bit)) {
1497                 value &= ~(1 << bit);
1498                 retval = rtsx_write_phy_register(chip, reg, value);
1499                 if (retval != STATUS_SUCCESS)
1500                         TRACE_RET(chip, STATUS_FAIL);
1501         }
1502
1503         return STATUS_SUCCESS;
1504 }
1505
1506 int rtsx_set_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit)
1507 {
1508         int retval;
1509         u16 value;
1510
1511         retval = rtsx_read_phy_register(chip, reg, &value);
1512         if (retval != STATUS_SUCCESS)
1513                 TRACE_RET(chip, STATUS_FAIL);
1514
1515         if (0 == (value & (1 << bit))) {
1516                 value |= (1 << bit);
1517                 retval = rtsx_write_phy_register(chip, reg, value);
1518                 if (retval != STATUS_SUCCESS)
1519                         TRACE_RET(chip, STATUS_FAIL);
1520         }
1521
1522         return STATUS_SUCCESS;
1523 }
1524
1525 int rtsx_check_link_ready(struct rtsx_chip *chip)
1526 {
1527         u8 val;
1528
1529         RTSX_READ_REG(chip, IRQSTAT0, &val);
1530
1531         dev_dbg(rtsx_dev(chip), "IRQSTAT0: 0x%x\n", val);
1532         if (val & LINK_RDY_INT) {
1533                 dev_dbg(rtsx_dev(chip), "Delinked!\n");
1534                 rtsx_write_register(chip, IRQSTAT0, LINK_RDY_INT, LINK_RDY_INT);
1535                 return STATUS_FAIL;
1536         }
1537
1538         return STATUS_SUCCESS;
1539 }
1540
1541 static void rtsx_handle_pm_dstate(struct rtsx_chip *chip, u8 dstate)
1542 {
1543         u32 ultmp;
1544
1545         dev_dbg(rtsx_dev(chip), "%04x set pm_dstate to %d\n",
1546                 chip->product_id, dstate);
1547
1548         if (CHK_SDIO_EXIST(chip)) {
1549                 u8 func_no;
1550
1551                 if (CHECK_PID(chip, 0x5288))
1552                         func_no = 2;
1553                 else
1554                         func_no = 1;
1555
1556                 rtsx_read_cfg_dw(chip, func_no, 0x84, &ultmp);
1557                 dev_dbg(rtsx_dev(chip), "pm_dstate of function %d: 0x%x\n",
1558                         (int)func_no, ultmp);
1559                 rtsx_write_cfg_dw(chip, func_no, 0x84, 0xFF, dstate);
1560         }
1561
1562         rtsx_write_config_byte(chip, 0x44, dstate);
1563         rtsx_write_config_byte(chip, 0x45, 0);
1564 }
1565
1566 void rtsx_enter_L1(struct rtsx_chip *chip)
1567 {
1568         rtsx_handle_pm_dstate(chip, 2);
1569 }
1570
1571 void rtsx_exit_L1(struct rtsx_chip *chip)
1572 {
1573         rtsx_write_config_byte(chip, 0x44, 0);
1574         rtsx_write_config_byte(chip, 0x45, 0);
1575 }
1576
1577 void rtsx_enter_ss(struct rtsx_chip *chip)
1578 {
1579         dev_dbg(rtsx_dev(chip), "Enter Selective Suspend State!\n");
1580
1581         rtsx_write_register(chip, IRQSTAT0, LINK_RDY_INT, LINK_RDY_INT);
1582
1583         if (chip->power_down_in_ss) {
1584                 rtsx_power_off_card(chip);
1585                 rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL);
1586         }
1587
1588         if (CHK_SDIO_EXIST(chip)) {
1589                 if (CHECK_PID(chip, 0x5288))
1590                         rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFF00, 0x0100);
1591                 else
1592                         rtsx_write_cfg_dw(chip, 1, 0xC0, 0xFF00, 0x0100);
1593         }
1594
1595         if (chip->auto_delink_en) {
1596                 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x01, 0x01);
1597         } else {
1598                 if (!chip->phy_debug_mode) {
1599                         u32 tmp;
1600                         tmp = rtsx_readl(chip, RTSX_BIER);
1601                         tmp |= CARD_INT;
1602                         rtsx_writel(chip, RTSX_BIER, tmp);
1603                 }
1604
1605                 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x02, 0);
1606         }
1607
1608         rtsx_enter_L1(chip);
1609
1610         RTSX_CLR_DELINK(chip);
1611         rtsx_set_stat(chip, RTSX_STAT_SS);
1612 }
1613
1614 void rtsx_exit_ss(struct rtsx_chip *chip)
1615 {
1616         dev_dbg(rtsx_dev(chip), "Exit Selective Suspend State!\n");
1617
1618         rtsx_exit_L1(chip);
1619
1620         if (chip->power_down_in_ss) {
1621                 rtsx_force_power_on(chip, SSC_PDCTL | OC_PDCTL);
1622                 udelay(1000);
1623         }
1624
1625         if (RTSX_TST_DELINK(chip)) {
1626                 chip->need_reinit = SD_CARD | MS_CARD | XD_CARD;
1627                 rtsx_reinit_cards(chip, 1);
1628                 RTSX_CLR_DELINK(chip);
1629         } else if (chip->power_down_in_ss) {
1630                 chip->need_reinit = SD_CARD | MS_CARD | XD_CARD;
1631                 rtsx_reinit_cards(chip, 0);
1632         }
1633 }
1634
1635 int rtsx_pre_handle_interrupt(struct rtsx_chip *chip)
1636 {
1637         u32 status, int_enable;
1638         int exit_ss = 0;
1639 #ifdef SUPPORT_OCP
1640         u32 ocp_int = 0;
1641
1642         ocp_int = OC_INT;
1643 #endif
1644
1645         if (chip->ss_en) {
1646                 chip->ss_counter = 0;
1647                 if (rtsx_get_stat(chip) == RTSX_STAT_SS) {
1648                         exit_ss = 1;
1649                         rtsx_exit_L1(chip);
1650                         rtsx_set_stat(chip, RTSX_STAT_RUN);
1651                 }
1652         }
1653
1654         int_enable = rtsx_readl(chip, RTSX_BIER);
1655         chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
1656
1657         if (((chip->int_reg & int_enable) == 0) ||
1658                 (chip->int_reg == 0xFFFFFFFF))
1659                 return STATUS_FAIL;
1660
1661         status = chip->int_reg &= (int_enable | 0x7FFFFF);
1662
1663         if (status & CARD_INT) {
1664                 chip->auto_delink_cnt = 0;
1665
1666                 if (status & SD_INT) {
1667                         if (status & SD_EXIST) {
1668                                 set_bit(SD_NR, &(chip->need_reset));
1669                         } else {
1670                                 set_bit(SD_NR, &(chip->need_release));
1671                                 chip->sd_reset_counter = 0;
1672                                 chip->sd_show_cnt = 0;
1673                                 clear_bit(SD_NR, &(chip->need_reset));
1674                         }
1675                 } else {
1676                         /* If multi-luns, it's possible that
1677                            when plugging/unplugging one card
1678                            there is another card which still
1679                            exists in the slot. In this case,
1680                            all existed cards should be reset.
1681                         */
1682                         if (exit_ss && (status & SD_EXIST))
1683                                 set_bit(SD_NR, &(chip->need_reinit));
1684                 }
1685                 if (!CHECK_PID(chip, 0x5288) || CHECK_BARO_PKG(chip, QFN)) {
1686                         if (status & XD_INT) {
1687                                 if (status & XD_EXIST) {
1688                                         set_bit(XD_NR, &(chip->need_reset));
1689                                 } else {
1690                                         set_bit(XD_NR, &(chip->need_release));
1691                                         chip->xd_reset_counter = 0;
1692                                         chip->xd_show_cnt = 0;
1693                                         clear_bit(XD_NR, &(chip->need_reset));
1694                                 }
1695                         } else {
1696                                 if (exit_ss && (status & XD_EXIST))
1697                                         set_bit(XD_NR, &(chip->need_reinit));
1698                         }
1699                 }
1700                 if (status & MS_INT) {
1701                         if (status & MS_EXIST) {
1702                                 set_bit(MS_NR, &(chip->need_reset));
1703                         } else {
1704                                 set_bit(MS_NR, &(chip->need_release));
1705                                 chip->ms_reset_counter = 0;
1706                                 chip->ms_show_cnt = 0;
1707                                 clear_bit(MS_NR, &(chip->need_reset));
1708                         }
1709                 } else {
1710                         if (exit_ss && (status & MS_EXIST))
1711                                 set_bit(MS_NR, &(chip->need_reinit));
1712                 }
1713         }
1714
1715 #ifdef SUPPORT_OCP
1716         chip->ocp_int = ocp_int & status;
1717 #endif
1718
1719         if (chip->sd_io) {
1720                 if (chip->int_reg & DATA_DONE_INT)
1721                         chip->int_reg &= ~(u32)DATA_DONE_INT;
1722         }
1723
1724         return STATUS_SUCCESS;
1725 }
1726
1727 void rtsx_do_before_power_down(struct rtsx_chip *chip, int pm_stat)
1728 {
1729         int retval;
1730
1731         dev_dbg(rtsx_dev(chip), "%s, pm_stat = %d\n", __func__, pm_stat);
1732
1733         rtsx_set_stat(chip, RTSX_STAT_SUSPEND);
1734
1735         retval = rtsx_force_power_on(chip, SSC_PDCTL);
1736         if (retval != STATUS_SUCCESS)
1737                 return;
1738
1739         rtsx_release_cards(chip);
1740         rtsx_disable_bus_int(chip);
1741         turn_off_led(chip, LED_GPIO);
1742
1743 #ifdef HW_AUTO_SWITCH_SD_BUS
1744         if (chip->sd_io) {
1745                 chip->sdio_in_charge = 1;
1746                 if (CHECK_PID(chip, 0x5208)) {
1747                         rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08);
1748                         /* Enable sdio_bus_auto_switch */
1749                         rtsx_write_register(chip, 0xFE70, 0x80, 0x80);
1750                 } else if (CHECK_PID(chip, 0x5288)) {
1751                         rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08);
1752                         /* Enable sdio_bus_auto_switch */
1753                         rtsx_write_register(chip, 0xFE5A, 0x08, 0x08);
1754                 }
1755         }
1756 #endif
1757
1758         if (CHECK_PID(chip, 0x5208) && (chip->ic_version >= IC_VER_D)) {
1759                 /* u_force_clkreq_0 */
1760                 rtsx_write_register(chip, PETXCFG, 0x08, 0x08);
1761         }
1762
1763         if (pm_stat == PM_S1) {
1764                 dev_dbg(rtsx_dev(chip), "Host enter S1\n");
1765                 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03,
1766                                 HOST_ENTER_S1);
1767         } else if (pm_stat == PM_S3) {
1768                 if (chip->s3_pwr_off_delay > 0)
1769                         wait_timeout(chip->s3_pwr_off_delay);
1770
1771                 dev_dbg(rtsx_dev(chip), "Host enter S3\n");
1772                 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03,
1773                                 HOST_ENTER_S3);
1774         }
1775
1776         if (chip->do_delink_before_power_down && chip->auto_delink_en)
1777                 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x02, 2);
1778
1779         rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL);
1780
1781         chip->cur_clk = 0;
1782         chip->cur_card = 0;
1783         chip->card_exist = 0;
1784 }
1785
1786 void rtsx_enable_aspm(struct rtsx_chip *chip)
1787 {
1788         if (chip->aspm_l0s_l1_en && chip->dynamic_aspm) {
1789                 if (!chip->aspm_enabled) {
1790                         dev_dbg(rtsx_dev(chip), "Try to enable ASPM\n");
1791                         chip->aspm_enabled = 1;
1792
1793                         if (chip->asic_code && CHECK_PID(chip, 0x5208))
1794                                 rtsx_write_phy_register(chip, 0x07, 0);
1795                         if (CHECK_PID(chip, 0x5208)) {
1796                                 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xF3,
1797                                         0x30 | chip->aspm_level[0]);
1798                         } else {
1799                                 rtsx_write_config_byte(chip, LCTLR,
1800                                                 chip->aspm_l0s_l1_en);
1801                         }
1802
1803                         if (CHK_SDIO_EXIST(chip)) {
1804                                 u16 val = chip->aspm_l0s_l1_en | 0x0100;
1805                                 if (CHECK_PID(chip, 0x5288))
1806                                         rtsx_write_cfg_dw(chip, 2, 0xC0,
1807                                                         0xFFFF, val);
1808                                 else
1809                                         rtsx_write_cfg_dw(chip, 1, 0xC0,
1810                                                         0xFFFF, val);
1811                         }
1812                 }
1813         }
1814
1815         return;
1816 }
1817
1818 void rtsx_disable_aspm(struct rtsx_chip *chip)
1819 {
1820         if (CHECK_PID(chip, 0x5208))
1821                 rtsx_monitor_aspm_config(chip);
1822
1823         if (chip->aspm_l0s_l1_en && chip->dynamic_aspm) {
1824                 if (chip->aspm_enabled) {
1825                         dev_dbg(rtsx_dev(chip), "Try to disable ASPM\n");
1826                         chip->aspm_enabled = 0;
1827
1828                         if (chip->asic_code && CHECK_PID(chip, 0x5208))
1829                                 rtsx_write_phy_register(chip, 0x07, 0x0129);
1830                         if (CHECK_PID(chip, 0x5208))
1831                                 rtsx_write_register(chip, ASPM_FORCE_CTL,
1832                                                 0xF3, 0x30);
1833                         else
1834                                 rtsx_write_config_byte(chip, LCTLR, 0x00);
1835
1836                         wait_timeout(1);
1837                 }
1838         }
1839
1840         return;
1841 }
1842
1843 int rtsx_read_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len)
1844 {
1845         int retval;
1846         int i, j;
1847         u16 reg_addr;
1848         u8 *ptr;
1849
1850         if (!buf)
1851                 TRACE_RET(chip, STATUS_ERROR);
1852
1853         ptr = buf;
1854         reg_addr = PPBUF_BASE2;
1855         for (i = 0; i < buf_len/256; i++) {
1856                 rtsx_init_cmd(chip);
1857
1858                 for (j = 0; j < 256; j++)
1859                         rtsx_add_cmd(chip, READ_REG_CMD, reg_addr++, 0, 0);
1860
1861                 retval = rtsx_send_cmd(chip, 0, 250);
1862                 if (retval < 0)
1863                         TRACE_RET(chip, STATUS_FAIL);
1864
1865                 memcpy(ptr, rtsx_get_cmd_data(chip), 256);
1866                 ptr += 256;
1867         }
1868
1869         if (buf_len%256) {
1870                 rtsx_init_cmd(chip);
1871
1872                 for (j = 0; j < buf_len%256; j++)
1873                         rtsx_add_cmd(chip, READ_REG_CMD, reg_addr++, 0, 0);
1874
1875                 retval = rtsx_send_cmd(chip, 0, 250);
1876                 if (retval < 0)
1877                         TRACE_RET(chip, STATUS_FAIL);
1878         }
1879
1880         memcpy(ptr, rtsx_get_cmd_data(chip), buf_len%256);
1881
1882         return STATUS_SUCCESS;
1883 }
1884
1885 int rtsx_write_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len)
1886 {
1887         int retval;
1888         int i, j;
1889         u16 reg_addr;
1890         u8 *ptr;
1891
1892         if (!buf)
1893                 TRACE_RET(chip, STATUS_ERROR);
1894
1895         ptr = buf;
1896         reg_addr = PPBUF_BASE2;
1897         for (i = 0; i < buf_len/256; i++) {
1898                 rtsx_init_cmd(chip);
1899
1900                 for (j = 0; j < 256; j++) {
1901                         rtsx_add_cmd(chip, WRITE_REG_CMD, reg_addr++, 0xFF,
1902                                 *ptr);
1903                         ptr++;
1904                 }
1905
1906                 retval = rtsx_send_cmd(chip, 0, 250);
1907                 if (retval < 0)
1908                         TRACE_RET(chip, STATUS_FAIL);
1909         }
1910
1911         if (buf_len%256) {
1912                 rtsx_init_cmd(chip);
1913
1914                 for (j = 0; j < buf_len%256; j++) {
1915                         rtsx_add_cmd(chip, WRITE_REG_CMD, reg_addr++, 0xFF,
1916                                 *ptr);
1917                         ptr++;
1918                 }
1919
1920                 retval = rtsx_send_cmd(chip, 0, 250);
1921                 if (retval < 0)
1922                         TRACE_RET(chip, STATUS_FAIL);
1923         }
1924
1925         return STATUS_SUCCESS;
1926 }
1927
1928 int rtsx_check_chip_exist(struct rtsx_chip *chip)
1929 {
1930         if (rtsx_readl(chip, 0) == 0xFFFFFFFF)
1931                 TRACE_RET(chip, STATUS_FAIL);
1932
1933         return STATUS_SUCCESS;
1934 }
1935
1936 int rtsx_force_power_on(struct rtsx_chip *chip, u8 ctl)
1937 {
1938         int retval;
1939         u8 mask = 0;
1940
1941         if (ctl & SSC_PDCTL)
1942                 mask |= SSC_POWER_DOWN;
1943
1944 #ifdef SUPPORT_OCP
1945         if (ctl & OC_PDCTL) {
1946                 mask |= SD_OC_POWER_DOWN;
1947                 if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
1948                         mask |= MS_OC_POWER_DOWN;
1949         }
1950 #endif
1951
1952         if (mask) {
1953                 retval = rtsx_write_register(chip, FPDCTL, mask, 0);
1954                 if (retval != STATUS_SUCCESS)
1955                         TRACE_RET(chip, STATUS_FAIL);
1956
1957                 if (CHECK_PID(chip, 0x5288))
1958                         wait_timeout(200);
1959         }
1960
1961         return STATUS_SUCCESS;
1962 }
1963
1964 int rtsx_force_power_down(struct rtsx_chip *chip, u8 ctl)
1965 {
1966         int retval;
1967         u8 mask = 0, val = 0;
1968
1969         if (ctl & SSC_PDCTL)
1970                 mask |= SSC_POWER_DOWN;
1971
1972 #ifdef SUPPORT_OCP
1973         if (ctl & OC_PDCTL) {
1974                 mask |= SD_OC_POWER_DOWN;
1975                 if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
1976                         mask |= MS_OC_POWER_DOWN;
1977         }
1978 #endif
1979
1980         if (mask) {
1981                 val = mask;
1982                 retval = rtsx_write_register(chip, FPDCTL, mask, val);
1983                 if (retval != STATUS_SUCCESS)
1984                         TRACE_RET(chip, STATUS_FAIL);
1985         }
1986
1987         return STATUS_SUCCESS;
1988 }