1 /* Driver for Realtek PCI-Express card reader
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 * Wei WANG (wei_wang@realsil.com.cn)
20 * Micky Ching (micky_ching@realsil.com.cn)
23 #include <linux/blkdev.h>
24 #include <linux/kthread.h>
25 #include <linux/sched.h>
28 #include "rtsx_scsi.h"
29 #include "rtsx_transport.h"
30 #include "rtsx_chip.h"
31 #include "rtsx_card.h"
33 /***********************************************************************
34 * Scatter-gather transfer buffer access routines
35 ***********************************************************************/
37 /* Copy a buffer of length buflen to/from the srb's transfer buffer.
38 * (Note: for scatter-gather transfers (srb->use_sg > 0), srb->request_buffer
39 * points to a list of s-g entries and we ignore srb->request_bufflen.
40 * For non-scatter-gather transfers, srb->request_buffer points to the
41 * transfer buffer itself and srb->request_bufflen is the buffer's length.)
42 * Update the *index and *offset variables so that the next copy will
43 * pick up from where this one left off. */
45 unsigned int rtsx_stor_access_xfer_buf(unsigned char *buffer,
46 unsigned int buflen, struct scsi_cmnd *srb, unsigned int *index,
47 unsigned int *offset, enum xfer_buf_dir dir)
51 /* If not using scatter-gather, just transfer the data directly.
52 * Make certain it will fit in the available buffer space. */
53 if (scsi_sg_count(srb) == 0) {
54 if (*offset >= scsi_bufflen(srb))
56 cnt = min(buflen, scsi_bufflen(srb) - *offset);
57 if (dir == TO_XFER_BUF)
58 memcpy((unsigned char *) scsi_sglist(srb) + *offset,
61 memcpy(buffer, (unsigned char *) scsi_sglist(srb) +
65 /* Using scatter-gather. We have to go through the list one entry
66 * at a time. Each s-g entry contains some number of pages, and
67 * each page has to be kmap()'ed separately. If the page is already
68 * in kernel-addressable memory then kmap() will return its address.
69 * If the page is not directly accessible -- such as a user buffer
70 * located in high memory -- then kmap() will map it to a temporary
71 * position in the kernel's virtual address space. */
73 struct scatterlist *sg =
74 (struct scatterlist *) scsi_sglist(srb)
77 /* This loop handles a single s-g list entry, which may
78 * include multiple pages. Find the initial page structure
79 * and the starting offset within the page, and update
80 * the *offset and *index values for the next loop. */
82 while (cnt < buflen && *index < scsi_sg_count(srb)) {
83 struct page *page = sg_page(sg) +
84 ((sg->offset + *offset) >> PAGE_SHIFT);
86 (sg->offset + *offset) & (PAGE_SIZE-1);
87 unsigned int sglen = sg->length - *offset;
89 if (sglen > buflen - cnt) {
91 /* Transfer ends within this s-g entry */
96 /* Transfer continues to next s-g entry */
102 /* Transfer the data for all the pages in this
103 * s-g entry. For each page: call kmap(), do the
104 * transfer, and call kunmap() immediately after. */
106 unsigned int plen = min(sglen, (unsigned int)
108 unsigned char *ptr = kmap(page);
110 if (dir == TO_XFER_BUF)
111 memcpy(ptr + poff, buffer + cnt, plen);
113 memcpy(buffer + cnt, ptr + poff, plen);
116 /* Start at the beginning of the next page */
125 /* Return the amount actually transferred */
129 /* Store the contents of buffer into srb's transfer buffer and set the
131 void rtsx_stor_set_xfer_buf(unsigned char *buffer,
132 unsigned int buflen, struct scsi_cmnd *srb)
134 unsigned int index = 0, offset = 0;
136 rtsx_stor_access_xfer_buf(buffer, buflen, srb, &index, &offset,
138 if (buflen < scsi_bufflen(srb))
139 scsi_set_resid(srb, scsi_bufflen(srb) - buflen);
142 void rtsx_stor_get_xfer_buf(unsigned char *buffer,
143 unsigned int buflen, struct scsi_cmnd *srb)
145 unsigned int index = 0, offset = 0;
147 rtsx_stor_access_xfer_buf(buffer, buflen, srb, &index, &offset,
149 if (buflen < scsi_bufflen(srb))
150 scsi_set_resid(srb, scsi_bufflen(srb) - buflen);
154 /***********************************************************************
156 ***********************************************************************/
158 /* Invoke the transport and basic error-handling/recovery methods
160 * This is used to send the message to the device and receive the response.
162 void rtsx_invoke_transport(struct scsi_cmnd *srb, struct rtsx_chip *chip)
166 result = rtsx_scsi_handler(srb, chip);
168 /* if the command gets aborted by the higher layers, we need to
169 * short-circuit all other processing
171 if (rtsx_chk_stat(chip, RTSX_STAT_ABORT)) {
172 dev_dbg(rtsx_dev(chip), "-- command was aborted\n");
173 srb->result = DID_ABORT << 16;
177 /* if there is a transport error, reset and don't auto-sense */
178 if (result == TRANSPORT_ERROR) {
179 dev_dbg(rtsx_dev(chip), "-- transport indicates error, resetting\n");
180 srb->result = DID_ERROR << 16;
184 srb->result = SAM_STAT_GOOD;
187 * If we have a failure, we're going to do a REQUEST_SENSE
188 * automatically. Note that we differentiate between a command
189 * "failure" and an "error" in the transport mechanism.
191 if (result == TRANSPORT_FAILED) {
192 /* set the result so the higher layers expect this data */
193 srb->result = SAM_STAT_CHECK_CONDITION;
194 memcpy(srb->sense_buffer,
195 (unsigned char *)&(chip->sense_buffer[SCSI_LUN(srb)]),
196 sizeof(struct sense_data_t));
201 /* Error and abort processing: try to resynchronize with the device
202 * by issuing a port reset. If that fails, try a class-specific
208 void rtsx_add_cmd(struct rtsx_chip *chip,
209 u8 cmd_type, u16 reg_addr, u8 mask, u8 data)
211 u32 *cb = (u32 *)(chip->host_cmds_ptr);
214 val |= (u32)(cmd_type & 0x03) << 30;
215 val |= (u32)(reg_addr & 0x3FFF) << 16;
216 val |= (u32)mask << 8;
219 spin_lock_irq(&chip->rtsx->reg_lock);
220 if (chip->ci < (HOST_CMDS_BUF_LEN / 4))
221 cb[(chip->ci)++] = cpu_to_le32(val);
223 spin_unlock_irq(&chip->rtsx->reg_lock);
226 void rtsx_send_cmd_no_wait(struct rtsx_chip *chip)
230 rtsx_writel(chip, RTSX_HCBAR, chip->host_cmds_addr);
232 val |= (u32)(chip->ci * 4) & 0x00FFFFFF;
233 /* Hardware Auto Response */
235 rtsx_writel(chip, RTSX_HCBCTLR, val);
238 int rtsx_send_cmd(struct rtsx_chip *chip, u8 card, int timeout)
240 struct rtsx_dev *rtsx = chip->rtsx;
241 struct completion trans_done;
247 rtsx->check_card_cd = SD_EXIST;
248 else if (card == MS_CARD)
249 rtsx->check_card_cd = MS_EXIST;
250 else if (card == XD_CARD)
251 rtsx->check_card_cd = XD_EXIST;
253 rtsx->check_card_cd = 0;
255 spin_lock_irq(&rtsx->reg_lock);
257 /* set up data structures for the wakeup system */
258 rtsx->done = &trans_done;
259 rtsx->trans_result = TRANS_NOT_READY;
260 init_completion(&trans_done);
261 rtsx->trans_state = STATE_TRANS_CMD;
263 rtsx_writel(chip, RTSX_HCBAR, chip->host_cmds_addr);
265 val |= (u32)(chip->ci * 4) & 0x00FFFFFF;
266 /* Hardware Auto Response */
268 rtsx_writel(chip, RTSX_HCBCTLR, val);
270 spin_unlock_irq(&rtsx->reg_lock);
272 /* Wait for TRANS_OK_INT */
273 timeleft = wait_for_completion_interruptible_timeout(
274 &trans_done, timeout * HZ / 1000);
276 dev_dbg(rtsx_dev(chip), "chip->int_reg = 0x%x\n",
279 TRACE_GOTO(chip, finish_send_cmd);
282 spin_lock_irq(&rtsx->reg_lock);
283 if (rtsx->trans_result == TRANS_RESULT_FAIL)
285 else if (rtsx->trans_result == TRANS_RESULT_OK)
288 spin_unlock_irq(&rtsx->reg_lock);
292 rtsx->trans_state = STATE_TRANS_NONE;
295 rtsx_stop_cmd(chip, card);
300 static inline void rtsx_add_sg_tbl(
301 struct rtsx_chip *chip, u32 addr, u32 len, u8 option)
303 u64 *sgb = (u64 *)(chip->host_sg_tbl_ptr);
311 temp_opt = option & (~SG_END);
316 val = ((u64)addr << 32) | ((u64)temp_len << 12) | temp_opt;
318 if (chip->sgi < (HOST_SG_TBL_BUF_LEN / 8))
319 sgb[(chip->sgi)++] = cpu_to_le64(val);
326 static int rtsx_transfer_sglist_adma_partial(struct rtsx_chip *chip, u8 card,
327 struct scatterlist *sg, int num_sg, unsigned int *index,
328 unsigned int *offset, int size,
329 enum dma_data_direction dma_dir, int timeout)
331 struct rtsx_dev *rtsx = chip->rtsx;
332 struct completion trans_done;
334 int sg_cnt, i, resid;
337 struct scatterlist *sg_ptr;
340 if ((sg == NULL) || (num_sg <= 0) || !offset || !index)
343 if (dma_dir == DMA_TO_DEVICE)
344 dir = HOST_TO_DEVICE;
345 else if (dma_dir == DMA_FROM_DEVICE)
346 dir = DEVICE_TO_HOST;
351 rtsx->check_card_cd = SD_EXIST;
352 else if (card == MS_CARD)
353 rtsx->check_card_cd = MS_EXIST;
354 else if (card == XD_CARD)
355 rtsx->check_card_cd = XD_EXIST;
357 rtsx->check_card_cd = 0;
359 spin_lock_irq(&rtsx->reg_lock);
361 /* set up data structures for the wakeup system */
362 rtsx->done = &trans_done;
364 rtsx->trans_state = STATE_TRANS_SG;
365 rtsx->trans_result = TRANS_NOT_READY;
367 spin_unlock_irq(&rtsx->reg_lock);
369 sg_cnt = dma_map_sg(&(rtsx->pci->dev), sg, num_sg, dma_dir);
374 /* Usually the next entry will be @sg@ + 1, but if this sg element
375 * is part of a chained scatterlist, it could jump to the start of
376 * a new scatterlist array. So here we use sg_next to move to
379 for (i = 0; i < *index; i++)
380 sg_ptr = sg_next(sg_ptr);
381 for (i = *index; i < sg_cnt; i++) {
386 addr = sg_dma_address(sg_ptr);
387 len = sg_dma_len(sg_ptr);
389 dev_dbg(rtsx_dev(chip), "DMA addr: 0x%x, Len: 0x%x\n",
390 (unsigned int)addr, len);
391 dev_dbg(rtsx_dev(chip), "*index = %d, *offset = %d\n",
396 if ((len - *offset) > resid) {
401 resid -= (len - *offset);
406 if ((i == (sg_cnt - 1)) || !resid)
407 option = SG_VALID | SG_END | SG_TRANS_DATA;
409 option = SG_VALID | SG_TRANS_DATA;
411 rtsx_add_sg_tbl(chip, (u32)addr, (u32)len, option);
416 sg_ptr = sg_next(sg_ptr);
419 dev_dbg(rtsx_dev(chip), "SG table count = %d\n", chip->sgi);
421 val |= (u32)(dir & 0x01) << 29;
424 spin_lock_irq(&rtsx->reg_lock);
426 init_completion(&trans_done);
428 rtsx_writel(chip, RTSX_HDBAR, chip->host_sg_tbl_addr);
429 rtsx_writel(chip, RTSX_HDBCTLR, val);
431 spin_unlock_irq(&rtsx->reg_lock);
433 timeleft = wait_for_completion_interruptible_timeout(
434 &trans_done, timeout * HZ / 1000);
436 dev_dbg(rtsx_dev(chip), "Timeout (%s %d)\n",
438 dev_dbg(rtsx_dev(chip), "chip->int_reg = 0x%x\n",
444 spin_lock_irq(&rtsx->reg_lock);
445 if (rtsx->trans_result == TRANS_RESULT_FAIL) {
447 spin_unlock_irq(&rtsx->reg_lock);
450 spin_unlock_irq(&rtsx->reg_lock);
452 /* Wait for TRANS_OK_INT */
453 spin_lock_irq(&rtsx->reg_lock);
454 if (rtsx->trans_result == TRANS_NOT_READY) {
455 init_completion(&trans_done);
456 spin_unlock_irq(&rtsx->reg_lock);
457 timeleft = wait_for_completion_interruptible_timeout(
458 &trans_done, timeout * HZ / 1000);
460 dev_dbg(rtsx_dev(chip), "Timeout (%s %d)\n",
462 dev_dbg(rtsx_dev(chip), "chip->int_reg = 0x%x\n",
468 spin_unlock_irq(&rtsx->reg_lock);
471 spin_lock_irq(&rtsx->reg_lock);
472 if (rtsx->trans_result == TRANS_RESULT_FAIL)
474 else if (rtsx->trans_result == TRANS_RESULT_OK)
477 spin_unlock_irq(&rtsx->reg_lock);
481 rtsx->trans_state = STATE_TRANS_NONE;
482 dma_unmap_sg(&(rtsx->pci->dev), sg, num_sg, dma_dir);
485 rtsx_stop_cmd(chip, card);
490 static int rtsx_transfer_sglist_adma(struct rtsx_chip *chip, u8 card,
491 struct scatterlist *sg, int num_sg,
492 enum dma_data_direction dma_dir, int timeout)
494 struct rtsx_dev *rtsx = chip->rtsx;
495 struct completion trans_done;
500 struct scatterlist *sg_ptr;
502 if ((sg == NULL) || (num_sg <= 0))
505 if (dma_dir == DMA_TO_DEVICE)
506 dir = HOST_TO_DEVICE;
507 else if (dma_dir == DMA_FROM_DEVICE)
508 dir = DEVICE_TO_HOST;
513 rtsx->check_card_cd = SD_EXIST;
514 else if (card == MS_CARD)
515 rtsx->check_card_cd = MS_EXIST;
516 else if (card == XD_CARD)
517 rtsx->check_card_cd = XD_EXIST;
519 rtsx->check_card_cd = 0;
521 spin_lock_irq(&rtsx->reg_lock);
523 /* set up data structures for the wakeup system */
524 rtsx->done = &trans_done;
526 rtsx->trans_state = STATE_TRANS_SG;
527 rtsx->trans_result = TRANS_NOT_READY;
529 spin_unlock_irq(&rtsx->reg_lock);
531 buf_cnt = dma_map_sg(&(rtsx->pci->dev), sg, num_sg, dma_dir);
535 for (i = 0; i <= buf_cnt / (HOST_SG_TBL_BUF_LEN / 8); i++) {
539 if (i == buf_cnt / (HOST_SG_TBL_BUF_LEN / 8))
540 sg_cnt = buf_cnt % (HOST_SG_TBL_BUF_LEN / 8);
542 sg_cnt = (HOST_SG_TBL_BUF_LEN / 8);
545 for (j = 0; j < sg_cnt; j++) {
546 dma_addr_t addr = sg_dma_address(sg_ptr);
547 unsigned int len = sg_dma_len(sg_ptr);
550 dev_dbg(rtsx_dev(chip), "DMA addr: 0x%x, Len: 0x%x\n",
551 (unsigned int)addr, len);
553 if (j == (sg_cnt - 1))
554 option = SG_VALID | SG_END | SG_TRANS_DATA;
556 option = SG_VALID | SG_TRANS_DATA;
558 rtsx_add_sg_tbl(chip, (u32)addr, (u32)len, option);
560 sg_ptr = sg_next(sg_ptr);
563 dev_dbg(rtsx_dev(chip), "SG table count = %d\n", chip->sgi);
565 val |= (u32)(dir & 0x01) << 29;
568 spin_lock_irq(&rtsx->reg_lock);
570 init_completion(&trans_done);
572 rtsx_writel(chip, RTSX_HDBAR, chip->host_sg_tbl_addr);
573 rtsx_writel(chip, RTSX_HDBCTLR, val);
575 spin_unlock_irq(&rtsx->reg_lock);
577 timeleft = wait_for_completion_interruptible_timeout(
578 &trans_done, timeout * HZ / 1000);
580 dev_dbg(rtsx_dev(chip), "Timeout (%s %d)\n",
582 dev_dbg(rtsx_dev(chip), "chip->int_reg = 0x%x\n",
588 spin_lock_irq(&rtsx->reg_lock);
589 if (rtsx->trans_result == TRANS_RESULT_FAIL) {
591 spin_unlock_irq(&rtsx->reg_lock);
594 spin_unlock_irq(&rtsx->reg_lock);
599 /* Wait for TRANS_OK_INT */
600 spin_lock_irq(&rtsx->reg_lock);
601 if (rtsx->trans_result == TRANS_NOT_READY) {
602 init_completion(&trans_done);
603 spin_unlock_irq(&rtsx->reg_lock);
604 timeleft = wait_for_completion_interruptible_timeout(
605 &trans_done, timeout * HZ / 1000);
607 dev_dbg(rtsx_dev(chip), "Timeout (%s %d)\n",
609 dev_dbg(rtsx_dev(chip), "chip->int_reg = 0x%x\n",
615 spin_unlock_irq(&rtsx->reg_lock);
618 spin_lock_irq(&rtsx->reg_lock);
619 if (rtsx->trans_result == TRANS_RESULT_FAIL)
621 else if (rtsx->trans_result == TRANS_RESULT_OK)
624 spin_unlock_irq(&rtsx->reg_lock);
628 rtsx->trans_state = STATE_TRANS_NONE;
629 dma_unmap_sg(&(rtsx->pci->dev), sg, num_sg, dma_dir);
632 rtsx_stop_cmd(chip, card);
637 static int rtsx_transfer_buf(struct rtsx_chip *chip, u8 card, void *buf,
638 size_t len, enum dma_data_direction dma_dir, int timeout)
640 struct rtsx_dev *rtsx = chip->rtsx;
641 struct completion trans_done;
648 if ((buf == NULL) || (len <= 0))
651 if (dma_dir == DMA_TO_DEVICE)
652 dir = HOST_TO_DEVICE;
653 else if (dma_dir == DMA_FROM_DEVICE)
654 dir = DEVICE_TO_HOST;
658 addr = dma_map_single(&(rtsx->pci->dev), buf, len, dma_dir);
663 rtsx->check_card_cd = SD_EXIST;
664 else if (card == MS_CARD)
665 rtsx->check_card_cd = MS_EXIST;
666 else if (card == XD_CARD)
667 rtsx->check_card_cd = XD_EXIST;
669 rtsx->check_card_cd = 0;
671 val |= (u32)(dir & 0x01) << 29;
672 val |= (u32)(len & 0x00FFFFFF);
674 spin_lock_irq(&rtsx->reg_lock);
676 /* set up data structures for the wakeup system */
677 rtsx->done = &trans_done;
679 init_completion(&trans_done);
681 rtsx->trans_state = STATE_TRANS_BUF;
682 rtsx->trans_result = TRANS_NOT_READY;
684 rtsx_writel(chip, RTSX_HDBAR, addr);
685 rtsx_writel(chip, RTSX_HDBCTLR, val);
687 spin_unlock_irq(&rtsx->reg_lock);
689 /* Wait for TRANS_OK_INT */
690 timeleft = wait_for_completion_interruptible_timeout(
691 &trans_done, timeout * HZ / 1000);
693 dev_dbg(rtsx_dev(chip), "Timeout (%s %d)\n",
695 dev_dbg(rtsx_dev(chip), "chip->int_reg = 0x%x\n",
701 spin_lock_irq(&rtsx->reg_lock);
702 if (rtsx->trans_result == TRANS_RESULT_FAIL)
704 else if (rtsx->trans_result == TRANS_RESULT_OK)
707 spin_unlock_irq(&rtsx->reg_lock);
711 rtsx->trans_state = STATE_TRANS_NONE;
712 dma_unmap_single(&(rtsx->pci->dev), addr, len, dma_dir);
715 rtsx_stop_cmd(chip, card);
720 int rtsx_transfer_data_partial(struct rtsx_chip *chip, u8 card,
721 void *buf, size_t len, int use_sg, unsigned int *index,
722 unsigned int *offset, enum dma_data_direction dma_dir,
727 /* don't transfer data during abort processing */
728 if (rtsx_chk_stat(chip, RTSX_STAT_ABORT))
732 err = rtsx_transfer_sglist_adma_partial(chip, card,
733 (struct scatterlist *)buf, use_sg,
734 index, offset, (int)len, dma_dir, timeout);
736 err = rtsx_transfer_buf(chip, card,
737 buf, len, dma_dir, timeout);
741 if (RTSX_TST_DELINK(chip)) {
742 RTSX_CLR_DELINK(chip);
743 chip->need_reinit = SD_CARD | MS_CARD | XD_CARD;
744 rtsx_reinit_cards(chip, 1);
751 int rtsx_transfer_data(struct rtsx_chip *chip, u8 card, void *buf, size_t len,
752 int use_sg, enum dma_data_direction dma_dir, int timeout)
756 dev_dbg(rtsx_dev(chip), "use_sg = %d\n", use_sg);
758 /* don't transfer data during abort processing */
759 if (rtsx_chk_stat(chip, RTSX_STAT_ABORT))
763 err = rtsx_transfer_sglist_adma(chip, card,
764 (struct scatterlist *)buf,
765 use_sg, dma_dir, timeout);
767 err = rtsx_transfer_buf(chip, card, buf, len, dma_dir, timeout);
771 if (RTSX_TST_DELINK(chip)) {
772 RTSX_CLR_DELINK(chip);
773 chip->need_reinit = SD_CARD | MS_CARD | XD_CARD;
774 rtsx_reinit_cards(chip, 1);