1 /* Driver for Realtek PCI-Express card reader
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 * wwang (wei_wang@realsil.com.cn)
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
23 #include <linux/blkdev.h>
24 #include <linux/kthread.h>
25 #include <linux/sched.h>
26 #include <linux/workqueue.h>
27 #include <linux/vmalloc.h>
30 #include "rtsx_transport.h"
31 #include "rtsx_scsi.h"
32 #include "rtsx_card.h"
33 #include "rtsx_chip.h"
41 static void rtsx_calibration(struct rtsx_chip *chip)
43 rtsx_write_phy_register(chip, 0x1B, 0x135E);
45 rtsx_write_phy_register(chip, 0x00, 0x0280);
46 rtsx_write_phy_register(chip, 0x01, 0x7112);
47 rtsx_write_phy_register(chip, 0x01, 0x7110);
48 rtsx_write_phy_register(chip, 0x01, 0x7112);
49 rtsx_write_phy_register(chip, 0x01, 0x7113);
50 rtsx_write_phy_register(chip, 0x00, 0x0288);
53 void rtsx_disable_card_int(struct rtsx_chip *chip)
55 u32 reg = rtsx_readl(chip, RTSX_BIER);
57 reg &= ~(XD_INT_EN | SD_INT_EN | MS_INT_EN);
58 rtsx_writel(chip, RTSX_BIER, reg);
61 void rtsx_enable_card_int(struct rtsx_chip *chip)
63 u32 reg = rtsx_readl(chip, RTSX_BIER);
66 for (i = 0; i <= chip->max_lun; i++) {
67 if (chip->lun2card[i] & XD_CARD)
69 if (chip->lun2card[i] & SD_CARD)
71 if (chip->lun2card[i] & MS_CARD)
74 if (chip->hw_bypass_sd)
75 reg &= ~((u32)SD_INT_EN);
77 rtsx_writel(chip, RTSX_BIER, reg);
80 void rtsx_enable_bus_int(struct rtsx_chip *chip)
83 #ifndef DISABLE_CARD_INT
87 reg = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN;
89 #ifndef DISABLE_CARD_INT
90 for (i = 0; i <= chip->max_lun; i++) {
91 RTSX_DEBUGP("lun2card[%d] = 0x%02x\n", i, chip->lun2card[i]);
93 if (chip->lun2card[i] & XD_CARD)
95 if (chip->lun2card[i] & SD_CARD)
97 if (chip->lun2card[i] & MS_CARD)
100 if (chip->hw_bypass_sd)
101 reg &= ~((u32)SD_INT_EN);
104 if (chip->ic_version >= IC_VER_C)
105 reg |= DELINK_INT_EN;
107 if (CHECK_PID(chip, 0x5209)) {
108 if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
109 reg |= MS_OC_INT_EN | SD_OC_INT_EN;
116 if (!chip->adma_mode)
117 reg |= DATA_DONE_INT_EN;
119 /* Enable Bus Interrupt */
120 rtsx_writel(chip, RTSX_BIER, reg);
122 RTSX_DEBUGP("RTSX_BIER: 0x%08x\n", reg);
125 void rtsx_disable_bus_int(struct rtsx_chip *chip)
127 rtsx_writel(chip, RTSX_BIER, 0);
130 static int rtsx_pre_handle_sdio_old(struct rtsx_chip *chip)
132 if (chip->ignore_sd && CHK_SDIO_EXIST(chip)) {
133 if (chip->asic_code) {
134 RTSX_WRITE_REG(chip, CARD_PULL_CTL5, 0xFF,
135 MS_INS_PU | SD_WP_PU | SD_CD_PU | SD_CMD_PU);
137 RTSX_WRITE_REG(chip, FPGA_PULL_CTL, 0xFF, FPGA_SD_PULL_CTL_EN);
139 RTSX_WRITE_REG(chip, CARD_SHARE_MODE, 0xFF, CARD_SHARE_48_SD);
141 /* Enable SDIO internal clock */
142 RTSX_WRITE_REG(chip, 0xFF2C, 0x01, 0x01);
144 RTSX_WRITE_REG(chip, SDIO_CTRL, 0xFF, SDIO_BUS_CTRL | SDIO_CD_CTRL);
149 chip->need_reset |= SD_CARD;
152 return STATUS_SUCCESS;
155 #ifdef HW_AUTO_SWITCH_SD_BUS
156 static int rtsx_pre_handle_sdio_new(struct rtsx_chip *chip)
159 int sw_bypass_sd = 0;
162 if (chip->driver_first_load) {
163 if (CHECK_PID(chip, 0x5288)) {
164 RTSX_READ_REG(chip, 0xFE5A, &tmp);
167 } else if (CHECK_PID(chip, 0x5208)) {
168 RTSX_READ_REG(chip, 0xFE70, &tmp);
171 } else if (CHECK_PID(chip, 0x5209)) {
172 RTSX_READ_REG(chip, SDIO_CFG, &tmp);
173 if (tmp & SDIO_BUS_AUTO_SWITCH)
177 if (chip->sdio_in_charge)
180 RTSX_DEBUGP("chip->sdio_in_charge = %d\n", chip->sdio_in_charge);
181 RTSX_DEBUGP("chip->driver_first_load = %d\n", chip->driver_first_load);
182 RTSX_DEBUGP("sw_bypass_sd = %d\n", sw_bypass_sd);
185 u8 cd_toggle_mask = 0;
187 RTSX_READ_REG(chip, TLPTISTAT, &tmp);
188 if (CHECK_PID(chip, 0x5209))
189 cd_toggle_mask = 0x10;
191 cd_toggle_mask = 0x08;
193 if (tmp & cd_toggle_mask) {
194 /* Disable sdio_bus_auto_switch */
195 if (CHECK_PID(chip, 0x5288))
196 RTSX_WRITE_REG(chip, 0xFE5A, 0x08, 0x00);
197 else if (CHECK_PID(chip, 0x5208))
198 RTSX_WRITE_REG(chip, 0xFE70, 0x80, 0x00);
200 RTSX_WRITE_REG(chip, SDIO_CFG, SDIO_BUS_AUTO_SWITCH, 0);
202 RTSX_WRITE_REG(chip, TLPTISTAT, 0xFF, tmp);
204 chip->need_reset |= SD_CARD;
206 RTSX_DEBUGP("Chip inserted with SDIO!\n");
208 if (chip->asic_code) {
209 retval = sd_pull_ctl_enable(chip);
210 if (retval != STATUS_SUCCESS)
211 TRACE_RET(chip, STATUS_FAIL);
213 RTSX_WRITE_REG(chip, FPGA_PULL_CTL, FPGA_SD_PULL_CTL_BIT | 0x20, 0);
215 retval = card_share_mode(chip, SD_CARD);
216 if (retval != STATUS_SUCCESS)
217 TRACE_RET(chip, STATUS_FAIL);
219 /* Enable sdio_bus_auto_switch */
220 if (CHECK_PID(chip, 0x5288)) {
221 RTSX_WRITE_REG(chip, 0xFE5A, 0x08, 0x08);
222 } else if (CHECK_PID(chip, 0x5208)) {
223 RTSX_WRITE_REG(chip, 0xFE70, 0x80, 0x80);
225 RTSX_WRITE_REG(chip, SDIO_CFG,
226 SDIO_BUS_AUTO_SWITCH, SDIO_BUS_AUTO_SWITCH);
228 chip->chip_insert_with_sdio = 1;
232 if (CHECK_PID(chip, 0x5209))
233 RTSX_WRITE_REG(chip, TLPTISTAT, 0x10, 0x10);
235 RTSX_WRITE_REG(chip, TLPTISTAT, 0x08, 0x08);
237 chip->need_reset |= SD_CARD;
240 return STATUS_SUCCESS;
244 int rtsx_reset_chip(struct rtsx_chip *chip)
248 rtsx_writel(chip, RTSX_HCBAR, chip->host_cmds_addr);
250 rtsx_disable_aspm(chip);
252 if (CHECK_PID(chip, 0x5209) && chip->asic_code) {
256 retval = rtsx_write_phy_register(chip, 0x00, 0xB966);
257 if (retval != STATUS_SUCCESS)
258 TRACE_RET(chip, STATUS_FAIL);
260 retval = rtsx_write_phy_register(chip, 0x01, 0x713F);
261 if (retval != STATUS_SUCCESS)
262 TRACE_RET(chip, STATUS_FAIL);
264 retval = rtsx_write_phy_register(chip, 0x03, 0xA549);
265 if (retval != STATUS_SUCCESS)
266 TRACE_RET(chip, STATUS_FAIL);
268 retval = rtsx_write_phy_register(chip, 0x06, 0xB235);
269 if (retval != STATUS_SUCCESS)
270 TRACE_RET(chip, STATUS_FAIL);
272 retval = rtsx_write_phy_register(chip, 0x07, 0xEF40);
273 if (retval != STATUS_SUCCESS)
274 TRACE_RET(chip, STATUS_FAIL);
276 retval = rtsx_write_phy_register(chip, 0x1E, 0xF8EB);
277 if (retval != STATUS_SUCCESS)
278 TRACE_RET(chip, STATUS_FAIL);
280 retval = rtsx_write_phy_register(chip, 0x19, 0xFE6C);
281 if (retval != STATUS_SUCCESS)
282 TRACE_RET(chip, STATUS_FAIL);
285 retval = rtsx_write_phy_register(chip, 0x0A, 0x05C0);
286 if (retval != STATUS_SUCCESS)
287 TRACE_RET(chip, STATUS_FAIL);
290 retval = rtsx_write_cfg_dw(chip, 1, 0x110, 0xFFFF, 0xFFFF);
291 if (retval != STATUS_SUCCESS)
292 TRACE_RET(chip, STATUS_FAIL);
294 retval = rtsx_read_phy_register(chip, 0x08, &val);
295 if (retval != STATUS_SUCCESS)
296 TRACE_RET(chip, STATUS_FAIL);
298 RTSX_DEBUGP("Read from phy 0x08: 0x%04x\n", val);
300 if (chip->phy_voltage) {
301 chip->phy_voltage &= 0x3F;
302 RTSX_DEBUGP("chip->phy_voltage = 0x%x\n", chip->phy_voltage);
304 val |= chip->phy_voltage;
305 RTSX_DEBUGP("Write to phy 0x08: 0x%04x\n", val);
306 retval = rtsx_write_phy_register(chip, 0x08, val);
307 if (retval != STATUS_SUCCESS)
308 TRACE_RET(chip, STATUS_FAIL);
311 chip->phy_voltage = (u8)(val & 0x3F);
312 RTSX_DEBUGP("Default, chip->phy_voltage = 0x%x\n", chip->phy_voltage);
316 RTSX_WRITE_REG(chip, HOST_SLEEP_STATE, 0x03, 0x00);
318 /* Disable card clock */
319 RTSX_WRITE_REG(chip, CARD_CLK_EN, 0x1E, 0);
322 /* SSC power on, OCD power on */
323 if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
324 RTSX_WRITE_REG(chip, FPDCTL, OC_POWER_DOWN, 0);
326 RTSX_WRITE_REG(chip, FPDCTL, OC_POWER_DOWN, MS_OC_POWER_DOWN);
328 if (CHECK_PID(chip, 0x5209)) {
329 RTSX_WRITE_REG(chip, OCPPARA1, SD_OCP_TIME_MASK | MS_OCP_TIME_MASK,
330 SD_OCP_TIME_800 | MS_OCP_TIME_800);
331 RTSX_WRITE_REG(chip, OCPPARA2, SD_OCP_THD_MASK | MS_OCP_THD_MASK,
332 chip->sd_400mA_ocp_thd | (chip->ms_ocp_thd << 4));
333 if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
334 RTSX_WRITE_REG(chip, OCPGLITCH, SD_OCP_GLITCH_MASK | MS_OCP_GLITCH_MASK,
335 SD_OCP_GLITCH_10000 | MS_OCP_GLITCH_10000);
337 RTSX_WRITE_REG(chip, OCPGLITCH, SD_OCP_GLITCH_MASK, SD_OCP_GLITCH_10000);
339 RTSX_WRITE_REG(chip, OCPCTL, 0xFF,
340 SD_OCP_INT_EN | SD_DETECT_EN | MS_OCP_INT_EN | MS_DETECT_EN);
342 RTSX_WRITE_REG(chip, OCPPARA1, OCP_TIME_MASK, OCP_TIME_800);
343 RTSX_WRITE_REG(chip, OCPPARA2, OCP_THD_MASK, OCP_THD_244_946);
344 RTSX_WRITE_REG(chip, OCPCTL, 0xFF, CARD_OC_INT_EN | CARD_DETECT_EN);
348 RTSX_WRITE_REG(chip, FPDCTL, OC_POWER_DOWN, OC_POWER_DOWN);
351 if (!CHECK_PID(chip, 0x5288))
352 RTSX_WRITE_REG(chip, CARD_GPIO_DIR, 0xFF, 0x03);
355 RTSX_WRITE_REG(chip, CARD_GPIO, 0xFF, 0x03);
357 /* Reset delink mode */
358 RTSX_WRITE_REG(chip, CHANGE_LINK_STATE, 0x0A, 0);
360 /* Card driving select */
361 RTSX_WRITE_REG(chip, CARD_DRIVE_SEL, 0xFF, chip->card_drive_sel);
362 if (CHECK_PID(chip, 0x5209))
363 RTSX_WRITE_REG(chip, SD30_DRIVE_SEL, 0x07, chip->sd30_drive_sel_3v3);
365 #ifdef LED_AUTO_BLINK
366 RTSX_WRITE_REG(chip, CARD_AUTO_BLINK, 0xFF,
367 LED_BLINK_SPEED | BLINK_EN | LED_GPIO0);
370 if (chip->asic_code) {
371 /* Enable SSC Clock */
372 RTSX_WRITE_REG(chip, SSC_CTL1, 0xFF, SSC_8X_EN | SSC_SEL_4M);
373 RTSX_WRITE_REG(chip, SSC_CTL2, 0xFF, 0x12);
376 /* Disable cd_pwr_save (u_force_rst_core_en=0, u_cd_rst_core_en=0)
378 bit[1] u_cd_rst_core_en rst_value = 0
379 bit[2] u_force_rst_core_en rst_value = 0
380 bit[5] u_mac_phy_rst_n_dbg rst_value = 1
381 bit[4] u_non_sticky_rst_n_dbg rst_value = 0
383 RTSX_WRITE_REG(chip, CHANGE_LINK_STATE, 0x16, 0x10);
386 if (chip->aspm_l0s_l1_en) {
387 if (chip->dynamic_aspm) {
388 if (CHK_SDIO_EXIST(chip)) {
389 if (CHECK_PID(chip, 0x5209)) {
390 retval = rtsx_write_cfg_dw(chip, 1, 0xC0, 0xFF, chip->aspm_l0s_l1_en);
391 if (retval != STATUS_SUCCESS)
392 TRACE_RET(chip, STATUS_FAIL);
394 } else if (CHECK_PID(chip, 0x5288)) {
395 retval = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFF, chip->aspm_l0s_l1_en);
396 if (retval != STATUS_SUCCESS)
397 TRACE_RET(chip, STATUS_FAIL);
401 if (CHECK_PID(chip, 0x5208))
402 RTSX_WRITE_REG(chip, ASPM_FORCE_CTL, 0xFF, 0x3F);
404 retval = rtsx_write_config_byte(chip, LCTLR, chip->aspm_l0s_l1_en);
405 if (retval != STATUS_SUCCESS)
406 TRACE_RET(chip, STATUS_FAIL);
408 chip->aspm_level[0] = chip->aspm_l0s_l1_en;
409 if (CHK_SDIO_EXIST(chip)) {
410 chip->aspm_level[1] = chip->aspm_l0s_l1_en;
411 if (CHECK_PID(chip, 0x5288))
412 retval = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFF, chip->aspm_l0s_l1_en);
414 retval = rtsx_write_cfg_dw(chip, 1, 0xC0, 0xFF, chip->aspm_l0s_l1_en);
416 if (retval != STATUS_SUCCESS)
417 TRACE_RET(chip, STATUS_FAIL);
421 chip->aspm_enabled = 1;
424 if (chip->asic_code && CHECK_PID(chip, 0x5208)) {
425 retval = rtsx_write_phy_register(chip, 0x07, 0x0129);
426 if (retval != STATUS_SUCCESS)
427 TRACE_RET(chip, STATUS_FAIL);
429 retval = rtsx_write_config_byte(chip, LCTLR, chip->aspm_l0s_l1_en);
430 if (retval != STATUS_SUCCESS)
431 TRACE_RET(chip, STATUS_FAIL);
434 retval = rtsx_write_config_byte(chip, 0x81, 1);
435 if (retval != STATUS_SUCCESS)
436 TRACE_RET(chip, STATUS_FAIL);
438 if (CHK_SDIO_EXIST(chip)) {
439 if (CHECK_PID(chip, 0x5288))
440 retval = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFF00, 0x0100);
442 retval = rtsx_write_cfg_dw(chip, 1, 0xC0, 0xFF00, 0x0100);
444 if (retval != STATUS_SUCCESS)
445 TRACE_RET(chip, STATUS_FAIL);
449 if (CHECK_PID(chip, 0x5209)) {
450 retval = rtsx_write_cfg_dw(chip, 0, 0x70C, 0xFF000000, 0x5B);
451 if (retval != STATUS_SUCCESS)
452 TRACE_RET(chip, STATUS_FAIL);
455 if (CHECK_PID(chip, 0x5288)) {
456 if (!CHK_SDIO_EXIST(chip)) {
457 retval = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFFFF, 0x0103);
458 if (retval != STATUS_SUCCESS)
459 TRACE_RET(chip, STATUS_FAIL);
461 retval = rtsx_write_cfg_dw(chip, 2, 0x84, 0xFF, 0x03);
462 if (retval != STATUS_SUCCESS)
463 TRACE_RET(chip, STATUS_FAIL);
468 RTSX_WRITE_REG(chip, IRQSTAT0, LINK_RDY_INT, LINK_RDY_INT);
470 RTSX_WRITE_REG(chip, PERST_GLITCH_WIDTH, 0xFF, 0x80);
472 if (CHECK_PID(chip, 0x5209)) {
473 RTSX_WRITE_REG(chip, PWD_SUSPEND_EN, 0xFF, 0xFF);
474 RTSX_WRITE_REG(chip, PWR_GATE_CTRL, PWR_GATE_EN, PWR_GATE_EN);
477 /* Enable PCIE interrupt */
478 if (chip->asic_code) {
479 if (CHECK_PID(chip, 0x5208)) {
480 if (chip->phy_debug_mode) {
481 RTSX_WRITE_REG(chip, CDRESUMECTL, 0x77, 0);
482 rtsx_disable_bus_int(chip);
484 rtsx_enable_bus_int(chip);
487 if (chip->ic_version >= IC_VER_D) {
489 retval = rtsx_read_phy_register(chip, 0x00, ®);
490 if (retval != STATUS_SUCCESS)
491 TRACE_RET(chip, STATUS_FAIL);
495 retval = rtsx_write_phy_register(chip, 0x00, reg);
496 if (retval != STATUS_SUCCESS)
497 TRACE_RET(chip, STATUS_FAIL);
499 retval = rtsx_read_phy_register(chip, 0x1C, ®);
500 if (retval != STATUS_SUCCESS)
501 TRACE_RET(chip, STATUS_FAIL);
504 retval = rtsx_write_phy_register(chip, 0x1C, reg);
505 if (retval != STATUS_SUCCESS)
506 TRACE_RET(chip, STATUS_FAIL);
510 if (chip->driver_first_load && (chip->ic_version < IC_VER_C))
511 rtsx_calibration(chip);
514 rtsx_enable_bus_int(chip);
517 rtsx_enable_bus_int(chip);
520 #ifdef HW_INT_WRITE_CLR
521 if (CHECK_PID(chip, 0x5209)) {
522 /* Set interrupt write clear */
523 RTSX_WRITE_REG(chip, NFTS_TX_CTRL, 0x02, 0);
527 chip->need_reset = 0;
529 chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
530 #ifdef HW_INT_WRITE_CLR
531 if (CHECK_PID(chip, 0x5209)) {
532 /* Clear interrupt flag */
533 rtsx_writel(chip, RTSX_BIPR, chip->int_reg);
536 if (chip->hw_bypass_sd)
538 RTSX_DEBUGP("In rtsx_reset_chip, chip->int_reg = 0x%x\n", chip->int_reg);
539 if (chip->int_reg & SD_EXIST) {
540 #ifdef HW_AUTO_SWITCH_SD_BUS
541 if (CHECK_PID(chip, 0x5208) && (chip->ic_version < IC_VER_C))
542 retval = rtsx_pre_handle_sdio_old(chip);
544 retval = rtsx_pre_handle_sdio_new(chip);
546 RTSX_DEBUGP("chip->need_reset = 0x%x (rtsx_reset_chip)\n", (unsigned int)(chip->need_reset));
547 #else /* HW_AUTO_SWITCH_SD_BUS */
548 retval = rtsx_pre_handle_sdio_old(chip);
549 #endif /* HW_AUTO_SWITCH_SD_BUS */
550 if (retval != STATUS_SUCCESS)
551 TRACE_RET(chip, STATUS_FAIL);
555 RTSX_WRITE_REG(chip, SDIO_CTRL, SDIO_BUS_CTRL | SDIO_CD_CTRL, 0);
559 if (chip->int_reg & XD_EXIST)
560 chip->need_reset |= XD_CARD;
561 if (chip->int_reg & MS_EXIST)
562 chip->need_reset |= MS_CARD;
563 if (chip->int_reg & CARD_EXIST)
564 RTSX_WRITE_REG(chip, SSC_CTL1, SSC_RSTB, SSC_RSTB);
566 RTSX_DEBUGP("In rtsx_init_chip, chip->need_reset = 0x%x\n", (unsigned int)(chip->need_reset));
568 RTSX_WRITE_REG(chip, RCCTL, 0x01, 0x00);
570 if (CHECK_PID(chip, 0x5208) || CHECK_PID(chip, 0x5288)) {
571 /* Turn off main power when entering S3/S4 state */
572 RTSX_WRITE_REG(chip, MAIN_PWR_OFF_CTL, 0x03, 0x03);
575 if (chip->remote_wakeup_en && !chip->auto_delink_en) {
576 RTSX_WRITE_REG(chip, WAKE_SEL_CTL, 0x07, 0x07);
577 if (chip->aux_pwr_exist)
578 RTSX_WRITE_REG(chip, PME_FORCE_CTL, 0xFF, 0x33);
580 RTSX_WRITE_REG(chip, WAKE_SEL_CTL, 0x07, 0x04);
581 RTSX_WRITE_REG(chip, PME_FORCE_CTL, 0xFF, 0x30);
584 if (CHECK_PID(chip, 0x5208) && (chip->ic_version >= IC_VER_D)) {
585 RTSX_WRITE_REG(chip, PETXCFG, 0x1C, 0x14);
586 } else if (CHECK_PID(chip, 0x5209)) {
587 if (chip->force_clkreq_0)
588 RTSX_WRITE_REG(chip, PETXCFG, 0x08, 0x08);
590 RTSX_WRITE_REG(chip, PETXCFG, 0x08, 0x00);
593 if (chip->asic_code && CHECK_PID(chip, 0x5208)) {
594 retval = rtsx_clr_phy_reg_bit(chip, 0x1C, 2);
595 if (retval != STATUS_SUCCESS)
596 TRACE_RET(chip, STATUS_FAIL);
599 if (chip->ft2_fast_mode) {
600 RTSX_WRITE_REG(chip, CARD_PWR_CTL, 0xFF, MS_PARTIAL_POWER_ON | SD_PARTIAL_POWER_ON);
601 udelay(chip->pmos_pwr_on_interval);
602 RTSX_WRITE_REG(chip, CARD_PWR_CTL, 0xFF, MS_POWER_ON | SD_POWER_ON);
608 rtsx_reset_detected_cards(chip, 0);
610 chip->driver_first_load = 0;
612 return STATUS_SUCCESS;
615 static inline int check_sd_speed_prior(u32 sd_speed_prior)
617 int i, fake_para = 0;
619 for (i = 0; i < 4; i++) {
620 u8 tmp = (u8)(sd_speed_prior >> (i*8));
621 if ((tmp < 0x01) || (tmp > 0x04)) {
630 static inline int check_sd_current_prior(u32 sd_current_prior)
632 int i, fake_para = 0;
634 for (i = 0; i < 4; i++) {
635 u8 tmp = (u8)(sd_current_prior >> (i*8));
645 static int rts5209_init(struct rtsx_chip *chip)
651 val = rtsx_readb(chip, 0x1C);
652 if ((val & 0x10) == 0)
657 chip->ic_version = val & 0x0F;
658 chip->phy_debug_mode = 0;
660 chip->aux_pwr_exist = 0;
662 chip->ms_power_class_en = 0x03;
664 retval = rtsx_read_cfg_dw(chip, 0, 0x724, &lval);
665 if (retval != STATUS_SUCCESS)
666 TRACE_RET(chip, STATUS_FAIL);
668 RTSX_DEBUGP("dw in 0x724: 0x%x\n", lval);
672 chip->lun_mode = DEFAULT_SINGLE;
674 chip->lun_mode = SD_MS_2LUN;
677 SET_SDIO_EXIST(chip);
679 CLR_SDIO_EXIST(chip);
682 chip->hw_bypass_sd = 0;
684 chip->hw_bypass_sd = 1;
687 SET_SDIO_EXIST(chip);
688 chip->hw_bypass_sd = 0;
691 if (chip->use_hw_setting) {
694 chip->aspm_l0s_l1_en = (val >> 5) & 0x03;
696 val = (u8)(lval >> 8);
698 clk = (val >> 5) & 0x07;
700 chip->asic_sd_sdr50_clk = 98 - clk * 2;
703 chip->auto_delink_en = 1;
705 chip->auto_delink_en = 0;
707 if (chip->ss_en == 2) {
718 chip->asic_ms_hg_clk = (59 - clk) * 2;
720 val = (u8)(lval >> 16);
722 clk = (val >> 6) & 0x03;
724 chip->asic_sd_hs_clk = (49 - clk * 2) * 2;
725 chip->asic_mmc_52m_clk = (49 - clk * 2) * 2;
728 clk = (val >> 4) & 0x03;
730 chip->asic_sd_ddr50_clk = (48 - clk * 2) * 2;
748 val = (u8)(lval >> 24);
750 clk = (val >> 5) & 0x07;
752 chip->asic_sd_sdr104_clk = 206 - clk * 3;
755 chip->power_down_in_ss = 1;
757 chip->power_down_in_ss = 0;
759 chip->ms_power_class_en = val & 0x03;
762 if (chip->hp_watch_bios_hotplug && chip->auto_delink_en) {
765 retval = rtsx_read_pci_cfg_byte(0x00,
766 0x1C, 0x02, 0x58, ®58);
768 return STATUS_SUCCESS;
770 retval = rtsx_read_pci_cfg_byte(0x00,
771 0x1C, 0x02, 0x5B, ®5b);
773 return STATUS_SUCCESS;
775 RTSX_DEBUGP("reg58 = 0x%x, reg5b = 0x%x\n", reg58, reg5b);
777 if ((reg58 == 0x00) && (reg5b == 0x01))
778 chip->auto_delink_en = 0;
782 return STATUS_SUCCESS;
785 static int rts5208_init(struct rtsx_chip *chip)
791 RTSX_WRITE_REG(chip, CLK_SEL, 0x03, 0x03);
792 RTSX_READ_REG(chip, CLK_SEL, &val);
798 if (chip->asic_code) {
799 retval = rtsx_read_phy_register(chip, 0x1C, ®);
800 if (retval != STATUS_SUCCESS)
801 TRACE_RET(chip, STATUS_FAIL);
803 RTSX_DEBUGP("Value of phy register 0x1C is 0x%x\n", reg);
804 chip->ic_version = (reg >> 4) & 0x07;
805 if (reg & PHY_DEBUG_MODE)
806 chip->phy_debug_mode = 1;
808 chip->phy_debug_mode = 0;
811 RTSX_READ_REG(chip, 0xFE80, &val);
812 chip->ic_version = val;
813 chip->phy_debug_mode = 0;
816 RTSX_READ_REG(chip, PDINFO, &val);
817 RTSX_DEBUGP("PDINFO: 0x%x\n", val);
818 if (val & AUX_PWR_DETECTED)
819 chip->aux_pwr_exist = 1;
821 chip->aux_pwr_exist = 0;
823 RTSX_READ_REG(chip, 0xFE50, &val);
825 chip->hw_bypass_sd = 1;
827 chip->hw_bypass_sd = 0;
829 rtsx_read_config_byte(chip, 0x0E, &val);
831 SET_SDIO_EXIST(chip);
833 CLR_SDIO_EXIST(chip);
835 if (chip->use_hw_setting) {
836 RTSX_READ_REG(chip, CHANGE_LINK_STATE, &val);
838 chip->auto_delink_en = 1;
840 chip->auto_delink_en = 0;
843 return STATUS_SUCCESS;
846 static int rts5288_init(struct rtsx_chip *chip)
849 u8 val = 0, max_func;
852 RTSX_WRITE_REG(chip, CLK_SEL, 0x03, 0x03);
853 RTSX_READ_REG(chip, CLK_SEL, &val);
859 chip->ic_version = 0;
860 chip->phy_debug_mode = 0;
862 RTSX_READ_REG(chip, PDINFO, &val);
863 RTSX_DEBUGP("PDINFO: 0x%x\n", val);
864 if (val & AUX_PWR_DETECTED)
865 chip->aux_pwr_exist = 1;
867 chip->aux_pwr_exist = 0;
869 RTSX_READ_REG(chip, CARD_SHARE_MODE, &val);
870 RTSX_DEBUGP("CARD_SHARE_MODE: 0x%x\n", val);
872 chip->baro_pkg = QFN;
874 chip->baro_pkg = LQFP;
876 RTSX_READ_REG(chip, 0xFE5A, &val);
878 chip->hw_bypass_sd = 1;
880 chip->hw_bypass_sd = 0;
882 retval = rtsx_read_cfg_dw(chip, 0, 0x718, &lval);
883 if (retval != STATUS_SUCCESS)
884 TRACE_RET(chip, STATUS_FAIL);
886 max_func = (u8)((lval >> 29) & 0x07);
887 RTSX_DEBUGP("Max function number: %d\n", max_func);
888 if (max_func == 0x02)
889 SET_SDIO_EXIST(chip);
891 CLR_SDIO_EXIST(chip);
893 if (chip->use_hw_setting) {
894 RTSX_READ_REG(chip, CHANGE_LINK_STATE, &val);
896 chip->auto_delink_en = 1;
898 chip->auto_delink_en = 0;
900 if (CHECK_BARO_PKG(chip, LQFP))
901 chip->lun_mode = SD_MS_1LUN;
903 chip->lun_mode = DEFAULT_SINGLE;
907 return STATUS_SUCCESS;
910 int rtsx_init_chip(struct rtsx_chip *chip)
912 struct sd_info *sd_card = &(chip->sd_card);
913 struct xd_info *xd_card = &(chip->xd_card);
914 struct ms_info *ms_card = &(chip->ms_card);
918 RTSX_DEBUGP("Vendor ID: 0x%04x, Product ID: 0x%04x\n",
919 chip->vendor_id, chip->product_id);
921 chip->ic_version = 0;
927 memset(xd_card, 0, sizeof(struct xd_info));
928 memset(sd_card, 0, sizeof(struct sd_info));
929 memset(ms_card, 0, sizeof(struct ms_info));
931 chip->xd_reset_counter = 0;
932 chip->sd_reset_counter = 0;
933 chip->ms_reset_counter = 0;
935 chip->xd_show_cnt = MAX_SHOW_CNT;
936 chip->sd_show_cnt = MAX_SHOW_CNT;
937 chip->ms_show_cnt = MAX_SHOW_CNT;
940 chip->auto_delink_cnt = 0;
941 chip->auto_delink_allowed = 1;
942 rtsx_set_stat(chip, RTSX_STAT_INIT);
944 chip->aspm_enabled = 0;
945 chip->chip_insert_with_sdio = 0;
948 chip->sdio_counter = 0;
950 chip->phy_debug_mode = 0;
951 chip->sdio_func_exist = 0;
952 memset(chip->sdio_raw_data, 0, 12);
954 for (i = 0; i < MAX_ALLOWED_LUN_CNT; i++) {
955 set_sense_type(chip, i, SENSE_TYPE_NO_SENSE);
956 chip->rw_fail_cnt[i] = 0;
959 if (!check_sd_speed_prior(chip->sd_speed_prior))
960 chip->sd_speed_prior = 0x01040203;
962 RTSX_DEBUGP("sd_speed_prior = 0x%08x\n", chip->sd_speed_prior);
964 if (!check_sd_current_prior(chip->sd_current_prior))
965 chip->sd_current_prior = 0x00010203;
967 RTSX_DEBUGP("sd_current_prior = 0x%08x\n", chip->sd_current_prior);
969 if ((chip->sd_ddr_tx_phase > 31) || (chip->sd_ddr_tx_phase < 0))
970 chip->sd_ddr_tx_phase = 0;
972 if ((chip->mmc_ddr_tx_phase > 31) || (chip->mmc_ddr_tx_phase < 0))
973 chip->mmc_ddr_tx_phase = 0;
975 RTSX_WRITE_REG(chip, FPDCTL, SSC_POWER_DOWN, 0);
977 RTSX_WRITE_REG(chip, CLK_DIV, 0x07, 0x07);
978 RTSX_DEBUGP("chip->use_hw_setting = %d\n", chip->use_hw_setting);
980 if (CHECK_PID(chip, 0x5209)) {
981 retval = rts5209_init(chip);
982 if (retval != STATUS_SUCCESS)
983 TRACE_RET(chip, STATUS_FAIL);
985 } else if (CHECK_PID(chip, 0x5208)) {
986 retval = rts5208_init(chip);
987 if (retval != STATUS_SUCCESS)
988 TRACE_RET(chip, STATUS_FAIL);
990 } else if (CHECK_PID(chip, 0x5288)) {
991 retval = rts5288_init(chip);
992 if (retval != STATUS_SUCCESS)
993 TRACE_RET(chip, STATUS_FAIL);
997 if (chip->ss_en == 2)
1000 RTSX_DEBUGP("chip->asic_code = %d\n", chip->asic_code);
1001 RTSX_DEBUGP("chip->ic_version = 0x%x\n", chip->ic_version);
1002 RTSX_DEBUGP("chip->phy_debug_mode = %d\n", chip->phy_debug_mode);
1003 RTSX_DEBUGP("chip->aux_pwr_exist = %d\n", chip->aux_pwr_exist);
1004 RTSX_DEBUGP("chip->sdio_func_exist = %d\n", chip->sdio_func_exist);
1005 RTSX_DEBUGP("chip->hw_bypass_sd = %d\n", chip->hw_bypass_sd);
1006 RTSX_DEBUGP("chip->aspm_l0s_l1_en = %d\n", chip->aspm_l0s_l1_en);
1007 RTSX_DEBUGP("chip->lun_mode = %d\n", chip->lun_mode);
1008 RTSX_DEBUGP("chip->auto_delink_en = %d\n", chip->auto_delink_en);
1009 RTSX_DEBUGP("chip->ss_en = %d\n", chip->ss_en);
1010 RTSX_DEBUGP("chip->baro_pkg = %d\n", chip->baro_pkg);
1012 if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
1013 chip->card2lun[SD_CARD] = 0;
1014 chip->card2lun[MS_CARD] = 1;
1015 chip->card2lun[XD_CARD] = 0xFF;
1016 chip->lun2card[0] = SD_CARD;
1017 chip->lun2card[1] = MS_CARD;
1019 SET_SDIO_IGNORED(chip);
1020 } else if (CHECK_LUN_MODE(chip, SD_MS_1LUN)) {
1021 chip->card2lun[SD_CARD] = 0;
1022 chip->card2lun[MS_CARD] = 0;
1023 chip->card2lun[XD_CARD] = 0xFF;
1024 chip->lun2card[0] = SD_CARD | MS_CARD;
1027 chip->card2lun[XD_CARD] = 0;
1028 chip->card2lun[SD_CARD] = 0;
1029 chip->card2lun[MS_CARD] = 0;
1030 chip->lun2card[0] = XD_CARD | SD_CARD | MS_CARD;
1034 retval = rtsx_reset_chip(chip);
1035 if (retval != STATUS_SUCCESS)
1036 TRACE_RET(chip, STATUS_FAIL);
1038 return STATUS_SUCCESS;
1041 void rtsx_release_chip(struct rtsx_chip *chip)
1043 xd_free_l2p_tbl(chip);
1044 ms_free_l2p_tbl(chip);
1045 chip->card_exist = 0;
1046 chip->card_ready = 0;
1049 #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK)
1050 static inline void rtsx_blink_led(struct rtsx_chip *chip)
1052 if (chip->card_exist && chip->blink_led) {
1053 if (chip->led_toggle_counter < LED_TOGGLE_INTERVAL) {
1054 chip->led_toggle_counter++;
1056 chip->led_toggle_counter = 0;
1057 toggle_gpio(chip, LED_GPIO);
1063 static void rtsx_monitor_aspm_config(struct rtsx_chip *chip)
1065 int maybe_support_aspm, reg_changed;
1067 u8 reg0 = 0, reg1 = 0;
1069 maybe_support_aspm = 0;
1071 rtsx_read_config_byte(chip, LCTLR, ®0);
1072 if (chip->aspm_level[0] != reg0) {
1074 chip->aspm_level[0] = reg0;
1076 if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) {
1077 rtsx_read_cfg_dw(chip, 1, 0xC0, &tmp);
1079 if (chip->aspm_level[1] != reg1) {
1081 chip->aspm_level[1] = reg1;
1084 if ((reg0 & 0x03) && (reg1 & 0x03))
1085 maybe_support_aspm = 1;
1089 maybe_support_aspm = 1;
1094 if (maybe_support_aspm)
1095 chip->aspm_l0s_l1_en = 0x03;
1097 RTSX_DEBUGP("aspm_level[0] = 0x%02x, aspm_level[1] = 0x%02x\n",
1098 chip->aspm_level[0], chip->aspm_level[1]);
1100 if (chip->aspm_l0s_l1_en) {
1101 chip->aspm_enabled = 1;
1103 chip->aspm_enabled = 0;
1104 chip->sdio_aspm = 0;
1106 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFF,
1107 0x30 | chip->aspm_level[0] | (chip->aspm_level[1] << 2));
1111 void rtsx_polling_func(struct rtsx_chip *chip)
1113 #ifdef SUPPORT_SD_LOCK
1114 struct sd_info *sd_card = &(chip->sd_card);
1118 if (rtsx_chk_stat(chip, RTSX_STAT_SUSPEND))
1121 if (rtsx_chk_stat(chip, RTSX_STAT_DELINK))
1124 if (chip->polling_config) {
1126 rtsx_read_config_byte(chip, 0, &val);
1129 if (rtsx_chk_stat(chip, RTSX_STAT_SS))
1133 if (chip->ocp_int) {
1134 rtsx_read_register(chip, OCPSTAT, &(chip->ocp_stat));
1136 if (CHECK_PID(chip, 0x5209) &&
1137 CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
1138 if (chip->ocp_int & SD_OC_INT)
1139 sd_power_off_card3v3(chip);
1140 if (chip->ocp_int & MS_OC_INT)
1141 ms_power_off_card3v3(chip);
1143 if (chip->card_exist & SD_CARD)
1144 sd_power_off_card3v3(chip);
1145 else if (chip->card_exist & MS_CARD)
1146 ms_power_off_card3v3(chip);
1147 else if (chip->card_exist & XD_CARD)
1148 xd_power_off_card3v3(chip);
1156 #ifdef SUPPORT_SD_LOCK
1157 if (sd_card->sd_erase_status) {
1158 if (chip->card_exist & SD_CARD) {
1160 if (CHECK_PID(chip, 0x5209)) {
1161 rtsx_read_register(chip, SD_BUS_STAT, &val);
1162 if (val & SD_DAT0_STATUS) {
1163 sd_card->sd_erase_status = SD_NOT_ERASE;
1164 sd_card->sd_lock_notify = 1;
1165 chip->need_reinit |= SD_CARD;
1168 rtsx_read_register(chip, 0xFD30, &val);
1170 sd_card->sd_erase_status = SD_NOT_ERASE;
1171 sd_card->sd_lock_notify = 1;
1172 chip->need_reinit |= SD_CARD;
1176 sd_card->sd_erase_status = SD_NOT_ERASE;
1181 rtsx_init_cards(chip);
1186 if (CHECK_PID(chip, 0x5288)) {
1189 if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) {
1191 rtsx_read_cfg_dw(chip, 1, 0x04, &val);
1201 if (ss_allowed && !chip->sd_io) {
1202 if (rtsx_get_stat(chip) != RTSX_STAT_IDLE) {
1203 chip->ss_counter = 0;
1205 if (chip->ss_counter <
1206 (chip->ss_idle_period / POLLING_INTERVAL)) {
1209 rtsx_exclusive_enter_ss(chip);
1215 if (CHECK_PID(chip, 0x5208)) {
1216 rtsx_monitor_aspm_config(chip);
1218 #ifdef SUPPORT_SDIO_ASPM
1219 if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip) &&
1220 chip->aspm_l0s_l1_en && chip->dynamic_aspm) {
1222 dynamic_configure_sdio_aspm(chip);
1224 if (!chip->sdio_aspm) {
1225 RTSX_DEBUGP("SDIO enter ASPM!\n");
1226 rtsx_write_register(chip,
1227 ASPM_FORCE_CTL, 0xFC,
1228 0x30 | (chip->aspm_level[1] << 2));
1229 chip->sdio_aspm = 1;
1236 if (chip->idle_counter < IDLE_MAX_COUNT) {
1237 chip->idle_counter++;
1239 if (rtsx_get_stat(chip) != RTSX_STAT_IDLE) {
1240 RTSX_DEBUGP("Idle state!\n");
1241 rtsx_set_stat(chip, RTSX_STAT_IDLE);
1243 #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK)
1244 chip->led_toggle_counter = 0;
1246 rtsx_force_power_on(chip, SSC_PDCTL);
1248 turn_off_led(chip, LED_GPIO);
1250 if (chip->auto_power_down && !chip->card_ready && !chip->sd_io)
1251 rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL);
1256 switch (rtsx_get_stat(chip)) {
1258 #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK)
1259 rtsx_blink_led(chip);
1261 do_remaining_work(chip);
1264 case RTSX_STAT_IDLE:
1265 if (chip->sd_io && !chip->sd_int)
1266 try_to_switch_sdio_ctrl(chip);
1268 rtsx_enable_aspm(chip);
1277 if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
1278 #ifdef CONFIG_RTS_PSTOR_DEBUG
1279 if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER | MS_OC_NOW | MS_OC_EVER))
1280 RTSX_DEBUGP("Over current, OCPSTAT is 0x%x\n", chip->ocp_stat);
1283 if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
1284 if (chip->card_exist & SD_CARD) {
1285 rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, 0);
1286 card_power_off(chip, SD_CARD);
1287 chip->card_fail |= SD_CARD;
1290 if (chip->ocp_stat & (MS_OC_NOW | MS_OC_EVER)) {
1291 if (chip->card_exist & MS_CARD) {
1292 rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0);
1293 card_power_off(chip, MS_CARD);
1294 chip->card_fail |= MS_CARD;
1298 if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
1299 RTSX_DEBUGP("Over current, OCPSTAT is 0x%x\n", chip->ocp_stat);
1300 if (chip->card_exist & SD_CARD) {
1301 rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, 0);
1302 chip->card_fail |= SD_CARD;
1303 } else if (chip->card_exist & MS_CARD) {
1304 rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0);
1305 chip->card_fail |= MS_CARD;
1306 } else if (chip->card_exist & XD_CARD) {
1307 rtsx_write_register(chip, CARD_OE, XD_OUTPUT_EN, 0);
1308 chip->card_fail |= XD_CARD;
1310 card_power_off(chip, SD_CARD);
1316 if (chip->auto_delink_en && chip->auto_delink_allowed &&
1317 !chip->card_ready && !chip->card_ejected && !chip->sd_io) {
1318 int enter_L1 = chip->auto_delink_in_L1 && (chip->aspm_l0s_l1_en || chip->ss_en);
1319 int delink_stage1_cnt = chip->delink_stage1_step;
1320 int delink_stage2_cnt = delink_stage1_cnt + chip->delink_stage2_step;
1321 int delink_stage3_cnt = delink_stage2_cnt + chip->delink_stage3_step;
1323 if (chip->auto_delink_cnt <= delink_stage3_cnt) {
1324 if (chip->auto_delink_cnt == delink_stage1_cnt) {
1325 rtsx_set_stat(chip, RTSX_STAT_DELINK);
1327 if (chip->asic_code && CHECK_PID(chip, 0x5208))
1328 rtsx_set_phy_reg_bit(chip, 0x1C, 2);
1330 if (chip->card_exist) {
1331 RTSX_DEBUGP("False card inserted, do force delink\n");
1334 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, 1);
1336 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x0A, 0x0A);
1339 rtsx_enter_L1(chip);
1341 chip->auto_delink_cnt = delink_stage3_cnt + 1;
1343 RTSX_DEBUGP("No card inserted, do delink\n");
1346 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, 1);
1348 #ifdef HW_INT_WRITE_CLR
1349 if (CHECK_PID(chip, 0x5209)) {
1350 rtsx_writel(chip, RTSX_BIPR, 0xFFFFFFFF);
1351 RTSX_DEBUGP("RTSX_BIPR: 0x%x\n", rtsx_readl(chip, RTSX_BIPR));
1354 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x02, 0x02);
1357 rtsx_enter_L1(chip);
1362 if (chip->auto_delink_cnt == delink_stage2_cnt) {
1363 RTSX_DEBUGP("Try to do force delink\n");
1368 if (chip->asic_code && CHECK_PID(chip, 0x5208))
1369 rtsx_set_phy_reg_bit(chip, 0x1C, 2);
1371 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x0A, 0x0A);
1374 chip->auto_delink_cnt++;
1377 chip->auto_delink_cnt = 0;
1381 void rtsx_undo_delink(struct rtsx_chip *chip)
1383 chip->auto_delink_allowed = 0;
1384 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x0A, 0x00);
1388 * rtsx_stop_cmd - stop command transfer and DMA transfer
1389 * @chip: Realtek's card reader chip
1390 * @card: flash card type
1392 * Stop command transfer and DMA transfer.
1393 * This function is called in error handler.
1395 void rtsx_stop_cmd(struct rtsx_chip *chip, int card)
1399 for (i = 0; i <= 8; i++) {
1400 int addr = RTSX_HCBAR + i * 4;
1402 reg = rtsx_readl(chip, addr);
1403 RTSX_DEBUGP("BAR (0x%02x): 0x%08x\n", addr, reg);
1405 rtsx_writel(chip, RTSX_HCBCTLR, STOP_CMD);
1406 rtsx_writel(chip, RTSX_HDBCTLR, STOP_DMA);
1408 for (i = 0; i < 16; i++) {
1409 u16 addr = 0xFE20 + (u16)i;
1411 rtsx_read_register(chip, addr, &val);
1412 RTSX_DEBUGP("0x%04X: 0x%02x\n", addr, val);
1415 rtsx_write_register(chip, DMACTL, 0x80, 0x80);
1416 rtsx_write_register(chip, RBCTL, 0x80, 0x80);
1419 #define MAX_RW_REG_CNT 1024
1421 int rtsx_write_register(struct rtsx_chip *chip, u16 addr, u8 mask, u8 data)
1426 val |= (u32)(addr & 0x3FFF) << 16;
1427 val |= (u32)mask << 8;
1430 rtsx_writel(chip, RTSX_HAIMR, val);
1432 for (i = 0; i < MAX_RW_REG_CNT; i++) {
1433 val = rtsx_readl(chip, RTSX_HAIMR);
1434 if ((val & (1 << 31)) == 0) {
1435 if (data != (u8)val)
1436 TRACE_RET(chip, STATUS_FAIL);
1438 return STATUS_SUCCESS;
1442 TRACE_RET(chip, STATUS_TIMEDOUT);
1445 int rtsx_read_register(struct rtsx_chip *chip, u16 addr, u8 *data)
1453 val |= (u32)(addr & 0x3FFF) << 16;
1455 rtsx_writel(chip, RTSX_HAIMR, val);
1457 for (i = 0; i < MAX_RW_REG_CNT; i++) {
1458 val = rtsx_readl(chip, RTSX_HAIMR);
1459 if ((val & (1 << 31)) == 0)
1463 if (i >= MAX_RW_REG_CNT)
1464 TRACE_RET(chip, STATUS_TIMEDOUT);
1467 *data = (u8)(val & 0xFF);
1469 return STATUS_SUCCESS;
1472 int rtsx_write_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 mask, u32 val)
1477 for (i = 0; i < 4; i++) {
1479 RTSX_WRITE_REG(chip, CFGDATA0 + i,
1480 0xFF, (u8)(val & mask & 0xFF));
1488 RTSX_WRITE_REG(chip, CFGADDR0, 0xFF, (u8)addr);
1489 RTSX_WRITE_REG(chip, CFGADDR1, 0xFF, (u8)(addr >> 8));
1491 RTSX_WRITE_REG(chip, CFGRWCTL, 0xFF,
1492 0x80 | mode | ((func_no & 0x03) << 4));
1494 for (i = 0; i < MAX_RW_REG_CNT; i++) {
1495 RTSX_READ_REG(chip, CFGRWCTL, &tmp);
1496 if ((tmp & 0x80) == 0)
1501 return STATUS_SUCCESS;
1504 int rtsx_read_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 *val)
1510 RTSX_WRITE_REG(chip, CFGADDR0, 0xFF, (u8)addr);
1511 RTSX_WRITE_REG(chip, CFGADDR1, 0xFF, (u8)(addr >> 8));
1512 RTSX_WRITE_REG(chip, CFGRWCTL, 0xFF, 0x80 | ((func_no & 0x03) << 4));
1514 for (i = 0; i < MAX_RW_REG_CNT; i++) {
1515 RTSX_READ_REG(chip, CFGRWCTL, &tmp);
1516 if ((tmp & 0x80) == 0)
1520 for (i = 0; i < 4; i++) {
1521 RTSX_READ_REG(chip, CFGDATA0 + i, &tmp);
1522 data |= (u32)tmp << (i * 8);
1528 return STATUS_SUCCESS;
1531 int rtsx_write_cfg_seq(struct rtsx_chip *chip, u8 func, u16 addr, u8 *buf, int len)
1534 u16 offset = addr % 4;
1535 u16 aligned_addr = addr - offset;
1539 RTSX_DEBUGP("%s\n", __func__);
1542 TRACE_RET(chip, STATUS_NOMEM);
1544 if ((len + offset) % 4)
1545 dw_len = (len + offset) / 4 + 1;
1547 dw_len = (len + offset) / 4;
1549 RTSX_DEBUGP("dw_len = %d\n", dw_len);
1551 data = vzalloc(dw_len * 4);
1553 TRACE_RET(chip, STATUS_NOMEM);
1555 mask = vzalloc(dw_len * 4);
1558 TRACE_RET(chip, STATUS_NOMEM);
1562 for (i = 0; i < len; i++) {
1563 mask[j] |= 0xFF << (offset * 8);
1564 data[j] |= buf[i] << (offset * 8);
1565 if (++offset == 4) {
1571 RTSX_DUMP(mask, dw_len * 4);
1572 RTSX_DUMP(data, dw_len * 4);
1574 for (i = 0; i < dw_len; i++) {
1575 retval = rtsx_write_cfg_dw(chip, func, aligned_addr + i * 4, mask[i], data[i]);
1576 if (retval != STATUS_SUCCESS) {
1579 TRACE_RET(chip, STATUS_FAIL);
1586 return STATUS_SUCCESS;
1589 int rtsx_read_cfg_seq(struct rtsx_chip *chip, u8 func, u16 addr, u8 *buf, int len)
1592 u16 offset = addr % 4;
1593 u16 aligned_addr = addr - offset;
1597 RTSX_DEBUGP("%s\n", __func__);
1599 if ((len + offset) % 4)
1600 dw_len = (len + offset) / 4 + 1;
1602 dw_len = (len + offset) / 4;
1604 RTSX_DEBUGP("dw_len = %d\n", dw_len);
1606 data = (u32 *)vmalloc(dw_len * 4);
1608 TRACE_RET(chip, STATUS_NOMEM);
1610 for (i = 0; i < dw_len; i++) {
1611 retval = rtsx_read_cfg_dw(chip, func, aligned_addr + i * 4, data + i);
1612 if (retval != STATUS_SUCCESS) {
1614 TRACE_RET(chip, STATUS_FAIL);
1621 for (i = 0; i < len; i++) {
1622 buf[i] = (u8)(data[j] >> (offset * 8));
1623 if (++offset == 4) {
1632 return STATUS_SUCCESS;
1635 int rtsx_write_phy_register(struct rtsx_chip *chip, u8 addr, u16 val)
1637 int i, finished = 0;
1640 RTSX_WRITE_REG(chip, PHYDATA0, 0xFF, (u8)val);
1641 RTSX_WRITE_REG(chip, PHYDATA1, 0xFF, (u8)(val >> 8));
1642 RTSX_WRITE_REG(chip, PHYADDR, 0xFF, addr);
1643 RTSX_WRITE_REG(chip, PHYRWCTL, 0xFF, 0x81);
1645 for (i = 0; i < 100000; i++) {
1646 RTSX_READ_REG(chip, PHYRWCTL, &tmp);
1647 if (!(tmp & 0x80)) {
1654 TRACE_RET(chip, STATUS_FAIL);
1656 return STATUS_SUCCESS;
1659 int rtsx_read_phy_register(struct rtsx_chip *chip, u8 addr, u16 *val)
1661 int i, finished = 0;
1665 RTSX_WRITE_REG(chip, PHYADDR, 0xFF, addr);
1666 RTSX_WRITE_REG(chip, PHYRWCTL, 0xFF, 0x80);
1668 for (i = 0; i < 100000; i++) {
1669 RTSX_READ_REG(chip, PHYRWCTL, &tmp);
1670 if (!(tmp & 0x80)) {
1677 TRACE_RET(chip, STATUS_FAIL);
1679 RTSX_READ_REG(chip, PHYDATA0, &tmp);
1681 RTSX_READ_REG(chip, PHYDATA1, &tmp);
1682 data |= (u16)tmp << 8;
1687 return STATUS_SUCCESS;
1690 int rtsx_read_efuse(struct rtsx_chip *chip, u8 addr, u8 *val)
1695 RTSX_WRITE_REG(chip, EFUSE_CTRL, 0xFF, 0x80|addr);
1697 for (i = 0; i < 100; i++) {
1698 RTSX_READ_REG(chip, EFUSE_CTRL, &data);
1705 TRACE_RET(chip, STATUS_TIMEDOUT);
1707 RTSX_READ_REG(chip, EFUSE_DATA, &data);
1711 return STATUS_SUCCESS;
1714 int rtsx_write_efuse(struct rtsx_chip *chip, u8 addr, u8 val)
1717 u8 data = 0, tmp = 0xFF;
1719 for (i = 0; i < 8; i++) {
1720 if (val & (u8)(1 << i))
1723 tmp &= (~(u8)(1 << i));
1724 RTSX_DEBUGP("Write 0x%x to 0x%x\n", tmp, addr);
1726 RTSX_WRITE_REG(chip, EFUSE_DATA, 0xFF, tmp);
1727 RTSX_WRITE_REG(chip, EFUSE_CTRL, 0xFF, 0xA0|addr);
1729 for (j = 0; j < 100; j++) {
1730 RTSX_READ_REG(chip, EFUSE_CTRL, &data);
1737 TRACE_RET(chip, STATUS_TIMEDOUT);
1742 return STATUS_SUCCESS;
1745 int rtsx_clr_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit)
1750 retval = rtsx_read_phy_register(chip, reg, &value);
1751 if (retval != STATUS_SUCCESS)
1752 TRACE_RET(chip, STATUS_FAIL);
1754 if (value & (1 << bit)) {
1755 value &= ~(1 << bit);
1756 retval = rtsx_write_phy_register(chip, reg, value);
1757 if (retval != STATUS_SUCCESS)
1758 TRACE_RET(chip, STATUS_FAIL);
1761 return STATUS_SUCCESS;
1764 int rtsx_set_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit)
1769 retval = rtsx_read_phy_register(chip, reg, &value);
1770 if (retval != STATUS_SUCCESS)
1771 TRACE_RET(chip, STATUS_FAIL);
1773 if (0 == (value & (1 << bit))) {
1774 value |= (1 << bit);
1775 retval = rtsx_write_phy_register(chip, reg, value);
1776 if (retval != STATUS_SUCCESS)
1777 TRACE_RET(chip, STATUS_FAIL);
1780 return STATUS_SUCCESS;
1783 int rtsx_check_link_ready(struct rtsx_chip *chip)
1787 RTSX_READ_REG(chip, IRQSTAT0, &val);
1789 RTSX_DEBUGP("IRQSTAT0: 0x%x\n", val);
1790 if (val & LINK_RDY_INT) {
1791 RTSX_DEBUGP("Delinked!\n");
1792 rtsx_write_register(chip, IRQSTAT0, LINK_RDY_INT, LINK_RDY_INT);
1796 return STATUS_SUCCESS;
1799 static void rtsx_handle_pm_dstate(struct rtsx_chip *chip, u8 dstate)
1803 RTSX_DEBUGP("%04x set pm_dstate to %d\n", chip->product_id, dstate);
1805 if (CHK_SDIO_EXIST(chip)) {
1808 if (CHECK_PID(chip, 0x5288))
1813 rtsx_read_cfg_dw(chip, func_no, 0x84, &ultmp);
1814 RTSX_DEBUGP("pm_dstate of function %d: 0x%x\n", (int)func_no, ultmp);
1815 rtsx_write_cfg_dw(chip, func_no, 0x84, 0xFF, dstate);
1818 rtsx_write_config_byte(chip, 0x44, dstate);
1819 rtsx_write_config_byte(chip, 0x45, 0);
1822 void rtsx_enter_L1(struct rtsx_chip *chip)
1824 rtsx_handle_pm_dstate(chip, 2);
1827 void rtsx_exit_L1(struct rtsx_chip *chip)
1829 rtsx_write_config_byte(chip, 0x44, 0);
1830 rtsx_write_config_byte(chip, 0x45, 0);
1833 void rtsx_enter_ss(struct rtsx_chip *chip)
1835 RTSX_DEBUGP("Enter Selective Suspend State!\n");
1837 rtsx_write_register(chip, IRQSTAT0, LINK_RDY_INT, LINK_RDY_INT);
1839 if (chip->power_down_in_ss) {
1840 rtsx_power_off_card(chip);
1841 rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL);
1844 if (CHK_SDIO_EXIST(chip)) {
1845 if (CHECK_PID(chip, 0x5288))
1846 rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFF00, 0x0100);
1848 rtsx_write_cfg_dw(chip, 1, 0xC0, 0xFF00, 0x0100);
1851 if (chip->auto_delink_en) {
1852 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x01, 0x01);
1854 if (!chip->phy_debug_mode) {
1856 tmp = rtsx_readl(chip, RTSX_BIER);
1858 rtsx_writel(chip, RTSX_BIER, tmp);
1861 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x02, 0);
1864 rtsx_enter_L1(chip);
1866 RTSX_CLR_DELINK(chip);
1867 rtsx_set_stat(chip, RTSX_STAT_SS);
1870 void rtsx_exit_ss(struct rtsx_chip *chip)
1872 RTSX_DEBUGP("Exit Selective Suspend State!\n");
1876 if (chip->power_down_in_ss) {
1877 rtsx_force_power_on(chip, SSC_PDCTL | OC_PDCTL);
1881 if (RTSX_TST_DELINK(chip)) {
1882 chip->need_reinit = SD_CARD | MS_CARD | XD_CARD;
1883 rtsx_reinit_cards(chip, 1);
1884 RTSX_CLR_DELINK(chip);
1885 } else if (chip->power_down_in_ss) {
1886 chip->need_reinit = SD_CARD | MS_CARD | XD_CARD;
1887 rtsx_reinit_cards(chip, 0);
1891 int rtsx_pre_handle_interrupt(struct rtsx_chip *chip)
1893 u32 status, int_enable;
1898 if (CHECK_PID(chip, 0x5209)) {
1899 if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
1900 ocp_int = MS_OC_INT | SD_OC_INT;
1902 ocp_int = SD_OC_INT;
1910 chip->ss_counter = 0;
1911 if (rtsx_get_stat(chip) == RTSX_STAT_SS) {
1914 rtsx_set_stat(chip, RTSX_STAT_RUN);
1918 int_enable = rtsx_readl(chip, RTSX_BIER);
1919 chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
1921 #ifdef HW_INT_WRITE_CLR
1922 if (CHECK_PID(chip, 0x5209))
1923 rtsx_writel(chip, RTSX_BIPR, chip->int_reg);
1926 if (((chip->int_reg & int_enable) == 0) || (chip->int_reg == 0xFFFFFFFF))
1929 if (!chip->msi_en) {
1930 if (CHECK_PID(chip, 0x5209)) {
1932 rtsx_read_config_byte(chip, 0x05, &val);
1938 status = chip->int_reg &= (int_enable | 0x7FFFFF);
1940 if (status & CARD_INT) {
1941 chip->auto_delink_cnt = 0;
1943 if (status & SD_INT) {
1944 if (status & SD_EXIST) {
1945 set_bit(SD_NR, &(chip->need_reset));
1947 set_bit(SD_NR, &(chip->need_release));
1948 chip->sd_reset_counter = 0;
1949 chip->sd_show_cnt = 0;
1950 clear_bit(SD_NR, &(chip->need_reset));
1953 /* If multi-luns, it's possible that
1954 when plugging/unplugging one card
1955 there is another card which still
1956 exists in the slot. In this case,
1957 all existed cards should be reset.
1959 if (exit_ss && (status & SD_EXIST))
1960 set_bit(SD_NR, &(chip->need_reinit));
1962 if (!CHECK_PID(chip, 0x5288) || CHECK_BARO_PKG(chip, QFN)) {
1963 if (status & XD_INT) {
1964 if (status & XD_EXIST) {
1965 set_bit(XD_NR, &(chip->need_reset));
1967 set_bit(XD_NR, &(chip->need_release));
1968 chip->xd_reset_counter = 0;
1969 chip->xd_show_cnt = 0;
1970 clear_bit(XD_NR, &(chip->need_reset));
1973 if (exit_ss && (status & XD_EXIST))
1974 set_bit(XD_NR, &(chip->need_reinit));
1977 if (status & MS_INT) {
1978 if (status & MS_EXIST) {
1979 set_bit(MS_NR, &(chip->need_reset));
1981 set_bit(MS_NR, &(chip->need_release));
1982 chip->ms_reset_counter = 0;
1983 chip->ms_show_cnt = 0;
1984 clear_bit(MS_NR, &(chip->need_reset));
1987 if (exit_ss && (status & MS_EXIST))
1988 set_bit(MS_NR, &(chip->need_reinit));
1993 chip->ocp_int = ocp_int & status;
1997 if (chip->int_reg & DATA_DONE_INT)
1998 chip->int_reg &= ~(u32)DATA_DONE_INT;
2001 return STATUS_SUCCESS;
2004 void rtsx_do_before_power_down(struct rtsx_chip *chip, int pm_stat)
2008 RTSX_DEBUGP("rtsx_do_before_power_down, pm_stat = %d\n", pm_stat);
2010 rtsx_set_stat(chip, RTSX_STAT_SUSPEND);
2012 retval = rtsx_force_power_on(chip, SSC_PDCTL);
2013 if (retval != STATUS_SUCCESS)
2016 rtsx_release_cards(chip);
2017 rtsx_disable_bus_int(chip);
2018 turn_off_led(chip, LED_GPIO);
2020 #ifdef HW_AUTO_SWITCH_SD_BUS
2022 chip->sdio_in_charge = 1;
2023 if (CHECK_PID(chip, 0x5208)) {
2024 rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08);
2025 /* Enable sdio_bus_auto_switch */
2026 rtsx_write_register(chip, 0xFE70, 0x80, 0x80);
2027 } else if (CHECK_PID(chip, 0x5288)) {
2028 rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08);
2029 /* Enable sdio_bus_auto_switch */
2030 rtsx_write_register(chip, 0xFE5A, 0x08, 0x08);
2031 } else if (CHECK_PID(chip, 0x5209)) {
2032 rtsx_write_register(chip, TLPTISTAT, 0x10, 0x10);
2033 /* Enable sdio_bus_auto_switch */
2034 rtsx_write_register(chip, SDIO_CFG, SDIO_BUS_AUTO_SWITCH, SDIO_BUS_AUTO_SWITCH);
2039 if (CHECK_PID(chip, 0x5208) && (chip->ic_version >= IC_VER_D)) {
2040 /* u_force_clkreq_0 */
2041 rtsx_write_register(chip, PETXCFG, 0x08, 0x08);
2042 } else if (CHECK_PID(chip, 0x5209)) {
2043 /* u_force_clkreq_0 */
2044 rtsx_write_register(chip, PETXCFG, 0x08, 0x08);
2047 if (pm_stat == PM_S1) {
2048 RTSX_DEBUGP("Host enter S1\n");
2049 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, HOST_ENTER_S1);
2050 } else if (pm_stat == PM_S3) {
2051 if (chip->s3_pwr_off_delay > 0)
2052 wait_timeout(chip->s3_pwr_off_delay);
2054 RTSX_DEBUGP("Host enter S3\n");
2055 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, HOST_ENTER_S3);
2058 if (chip->do_delink_before_power_down && chip->auto_delink_en)
2059 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x02, 2);
2061 rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL);
2065 chip->card_exist = 0;
2068 void rtsx_enable_aspm(struct rtsx_chip *chip)
2070 if (chip->aspm_l0s_l1_en && chip->dynamic_aspm) {
2071 if (!chip->aspm_enabled) {
2072 RTSX_DEBUGP("Try to enable ASPM\n");
2073 chip->aspm_enabled = 1;
2075 if (chip->asic_code && CHECK_PID(chip, 0x5208))
2076 rtsx_write_phy_register(chip, 0x07, 0);
2077 if (CHECK_PID(chip, 0x5208)) {
2078 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xF3,
2079 0x30 | chip->aspm_level[0]);
2081 rtsx_write_config_byte(chip, LCTLR, chip->aspm_l0s_l1_en);
2084 if (CHK_SDIO_EXIST(chip)) {
2085 u16 val = chip->aspm_l0s_l1_en | 0x0100;
2086 if (CHECK_PID(chip, 0x5288))
2087 rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFFFF, val);
2089 rtsx_write_cfg_dw(chip, 1, 0xC0, 0xFFFF, val);
2097 void rtsx_disable_aspm(struct rtsx_chip *chip)
2099 if (CHECK_PID(chip, 0x5208))
2100 rtsx_monitor_aspm_config(chip);
2102 if (chip->aspm_l0s_l1_en && chip->dynamic_aspm) {
2103 if (chip->aspm_enabled) {
2104 RTSX_DEBUGP("Try to disable ASPM\n");
2105 chip->aspm_enabled = 0;
2107 if (chip->asic_code && CHECK_PID(chip, 0x5208))
2108 rtsx_write_phy_register(chip, 0x07, 0x0129);
2109 if (CHECK_PID(chip, 0x5208))
2110 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xF3, 0x30);
2112 rtsx_write_config_byte(chip, LCTLR, 0x00);
2121 int rtsx_read_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len)
2129 TRACE_RET(chip, STATUS_ERROR);
2132 reg_addr = PPBUF_BASE2;
2133 for (i = 0; i < buf_len/256; i++) {
2134 rtsx_init_cmd(chip);
2136 for (j = 0; j < 256; j++)
2137 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr++, 0, 0);
2139 retval = rtsx_send_cmd(chip, 0, 250);
2141 TRACE_RET(chip, STATUS_FAIL);
2143 memcpy(ptr, rtsx_get_cmd_data(chip), 256);
2148 rtsx_init_cmd(chip);
2150 for (j = 0; j < buf_len%256; j++)
2151 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr++, 0, 0);
2153 retval = rtsx_send_cmd(chip, 0, 250);
2155 TRACE_RET(chip, STATUS_FAIL);
2158 memcpy(ptr, rtsx_get_cmd_data(chip), buf_len%256);
2160 return STATUS_SUCCESS;
2163 int rtsx_write_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len)
2171 TRACE_RET(chip, STATUS_ERROR);
2174 reg_addr = PPBUF_BASE2;
2175 for (i = 0; i < buf_len/256; i++) {
2176 rtsx_init_cmd(chip);
2178 for (j = 0; j < 256; j++) {
2179 rtsx_add_cmd(chip, WRITE_REG_CMD, reg_addr++, 0xFF, *ptr);
2183 retval = rtsx_send_cmd(chip, 0, 250);
2185 TRACE_RET(chip, STATUS_FAIL);
2189 rtsx_init_cmd(chip);
2191 for (j = 0; j < buf_len%256; j++) {
2192 rtsx_add_cmd(chip, WRITE_REG_CMD, reg_addr++, 0xFF, *ptr);
2196 retval = rtsx_send_cmd(chip, 0, 250);
2198 TRACE_RET(chip, STATUS_FAIL);
2201 return STATUS_SUCCESS;
2204 int rtsx_check_chip_exist(struct rtsx_chip *chip)
2206 if (rtsx_readl(chip, 0) == 0xFFFFFFFF)
2207 TRACE_RET(chip, STATUS_FAIL);
2209 return STATUS_SUCCESS;
2212 int rtsx_force_power_on(struct rtsx_chip *chip, u8 ctl)
2217 if (ctl & SSC_PDCTL)
2218 mask |= SSC_POWER_DOWN;
2221 if (ctl & OC_PDCTL) {
2222 mask |= SD_OC_POWER_DOWN;
2223 if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
2224 mask |= MS_OC_POWER_DOWN;
2229 retval = rtsx_write_register(chip, FPDCTL, mask, 0);
2230 if (retval != STATUS_SUCCESS)
2231 TRACE_RET(chip, STATUS_FAIL);
2233 if (CHECK_PID(chip, 0x5288))
2237 return STATUS_SUCCESS;
2240 int rtsx_force_power_down(struct rtsx_chip *chip, u8 ctl)
2243 u8 mask = 0, val = 0;
2245 if (ctl & SSC_PDCTL)
2246 mask |= SSC_POWER_DOWN;
2249 if (ctl & OC_PDCTL) {
2250 mask |= SD_OC_POWER_DOWN;
2251 if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
2252 mask |= MS_OC_POWER_DOWN;
2258 retval = rtsx_write_register(chip, FPDCTL, mask, val);
2259 if (retval != STATUS_SUCCESS)
2260 TRACE_RET(chip, STATUS_FAIL);
2263 return STATUS_SUCCESS;