1 /******************************************************************************/
3 /* Bypass Control utility, Copyright (c) 2005-2011 Silicom */
5 /* This program is free software; you can redistribute it and/or modify */
6 /* it under the terms of the GNU General Public License as published by */
7 /* the Free Software Foundation, located in the file LICENSE. */
8 /* Copyright(c) 2007 - 2009, 2013 Intel Corporation. All rights reserved. */
11 /******************************************************************************/
13 #include <linux/kernel.h> /* We're doing kernel work */
14 #include <linux/module.h> /* Specifically, a module */
16 #include <linux/pci.h>
17 #include <linux/delay.h>
18 #include <linux/netdevice.h>
19 #include <linux/rtnetlink.h>
20 #include <linux/rcupdate.h>
21 #include <linux/etherdevice.h>
23 #include <linux/uaccess.h> /* for get_user and put_user */
24 #include <linux/sched.h>
25 #include <linux/ethtool.h>
26 #include <linux/proc_fs.h>
34 #define BP_MOD_VER "9.0.4"
35 #define BP_MOD_DESCR "Silicom Bypass-SD Control driver"
36 #define BP_SYNC_FLAG 1
40 MODULE_AUTHOR("Anna Lukin, annal@silicom.co.il");
41 MODULE_LICENSE("GPL");
42 MODULE_DESCRIPTION(BP_MOD_DESCR);
43 MODULE_VERSION(BP_MOD_VER);
46 #define unlock_bpctl() \
57 struct bypass_pfs_sd {
59 struct proc_dir_entry *bypass_entry;
65 struct pci_dev *pdev; /* PCI device */
66 struct net_device *ndev; /* net device */
67 unsigned long mem_map;
81 unsigned long bypass_wdt_on_time;
82 uint32_t bypass_timer_interval;
83 struct timer_list bp_timer;
87 enum bp_media_type media_type;
89 struct timer_list bp_tpl_timer;
90 spinlock_t bypass_wr_lock;
97 int (*hard_start_xmit_save) (struct sk_buff *skb,
98 struct net_device *dev);
99 const struct net_device_ops *old_ops;
100 struct net_device_ops new_ops;
101 int bp_self_test_flag;
103 struct bypass_pfs_sd bypass_pfs_set;
107 static struct bpctl_dev *bpctl_dev_arr;
109 static struct semaphore bpctl_sema;
110 static int device_num;
112 static int get_dev_idx(int ifindex);
113 static struct bpctl_dev *get_master_port_fn(struct bpctl_dev *pbpctl_dev);
114 static int disc_status(struct bpctl_dev *pbpctl_dev);
115 static int bypass_status(struct bpctl_dev *pbpctl_dev);
116 static int wdt_timer(struct bpctl_dev *pbpctl_dev, int *time_left);
117 static struct bpctl_dev *get_status_port_fn(struct bpctl_dev *pbpctl_dev);
118 static void if_scan_init(void);
120 int bypass_proc_create_dev_sd(struct bpctl_dev *pbp_device_block);
121 int bypass_proc_remove_dev_sd(struct bpctl_dev *pbp_device_block);
122 int bp_proc_create(void);
124 int is_bypass_fn(struct bpctl_dev *pbpctl_dev);
125 int get_dev_idx_bsf(int bus, int slot, int func);
127 static int bp_get_dev_idx_bsf(struct net_device *dev, int *index)
129 struct ethtool_drvinfo drvinfo = {0};
133 if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo)
134 dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
138 if (!drvinfo.bus_info)
140 if (!strcmp(drvinfo.bus_info, "N/A"))
143 buf = strchr(drvinfo.bus_info, ':');
147 if (sscanf(buf, "%x:%x.%x", &bus, &slot, &func) != 3)
150 *index = get_dev_idx_bsf(bus, slot, func);
154 static int bp_device_event(struct notifier_block *unused,
155 unsigned long event, void *ptr)
157 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
158 static struct bpctl_dev *pbpctl_dev, *pbpctl_dev_m;
159 int dev_num = 0, ret = 0, ret_d = 0, time_left = 0;
161 /* printk("BP_PROC_SUPPORT event =%d %s %d\n", event,dev->name, dev->ifindex ); */
162 /* return NOTIFY_DONE; */
166 if (event == NETDEV_REGISTER) {
169 if (bp_get_dev_idx_bsf(dev, &idx_dev))
175 bpctl_dev_arr[idx_dev].ifindex = dev->ifindex;
176 bpctl_dev_arr[idx_dev].ndev = dev;
178 bypass_proc_remove_dev_sd(&bpctl_dev_arr[idx_dev]);
179 bypass_proc_create_dev_sd(&bpctl_dev_arr[idx_dev]);
182 if (event == NETDEV_UNREGISTER) {
185 ((bpctl_dev_arr[idx_dev].pdev != NULL)
186 && (idx_dev < device_num)); idx_dev++) {
187 if (bpctl_dev_arr[idx_dev].ndev == dev) {
188 bypass_proc_remove_dev_sd(&bpctl_dev_arr
190 bpctl_dev_arr[idx_dev].ndev = NULL;
199 if (event == NETDEV_CHANGENAME) {
202 ((bpctl_dev_arr[idx_dev].pdev != NULL)
203 && (idx_dev < device_num)); idx_dev++) {
204 if (bpctl_dev_arr[idx_dev].ndev == dev) {
205 bypass_proc_remove_dev_sd(&bpctl_dev_arr
207 bypass_proc_create_dev_sd(&bpctl_dev_arr
222 if (netif_carrier_ok(dev))
225 if (((dev_num = get_dev_idx(dev->ifindex)) == -1) ||
226 (!(pbpctl_dev = &bpctl_dev_arr[dev_num])))
229 if ((is_bypass_fn(pbpctl_dev)) == 1)
230 pbpctl_dev_m = pbpctl_dev;
232 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
235 ret = bypass_status(pbpctl_dev_m);
237 printk("bpmod: %s is in the Bypass mode now",
239 ret_d = disc_status(pbpctl_dev_m);
242 ("bpmod: %s is in the Disconnect mode now",
245 wdt_timer(pbpctl_dev_m, &time_left);
247 printk("; WDT has expired");
263 static struct notifier_block bp_notifier_block = {
264 .notifier_call = bp_device_event,
267 int is_bypass_fn(struct bpctl_dev *pbpctl_dev);
268 int wdt_time_left(struct bpctl_dev *pbpctl_dev);
270 static void write_pulse(struct bpctl_dev *pbpctl_dev,
271 unsigned int ctrl_ext,
272 unsigned char value, unsigned char len)
274 unsigned char ctrl_val = 0;
275 unsigned int i = len;
276 unsigned int ctrl = 0;
277 struct bpctl_dev *pbpctl_dev_c = NULL;
279 if (pbpctl_dev->bp_i80)
280 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
281 if (pbpctl_dev->bp_540)
282 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
284 if (pbpctl_dev->bp_10g9) {
285 pbpctl_dev_c = get_status_port_fn(pbpctl_dev);
288 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
292 ctrl_val = (value >> i) & 0x1;
294 if (pbpctl_dev->bp_10g9) {
296 /* To start management : MCLK 1, MDIO 1, output */
298 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext|BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9)); */
299 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
301 BP10G_MDIO_DATA_OUT9);
302 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
303 (ctrl | BP10G_MCLK_DATA_OUT9 |
304 BP10G_MCLK_DIR_OUT9));
306 } else if (pbpctl_dev->bp_fiber5) {
307 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, (ctrl_ext |
308 BPCTLI_CTRL_EXT_MCLK_DIR5
310 BPCTLI_CTRL_EXT_MDIO_DIR5
312 BPCTLI_CTRL_EXT_MDIO_DATA5
314 BPCTLI_CTRL_EXT_MCLK_DATA5));
316 } else if (pbpctl_dev->bp_i80) {
317 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, (ctrl_ext |
318 BPCTLI_CTRL_EXT_MDIO_DIR80
320 BPCTLI_CTRL_EXT_MDIO_DATA80));
322 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, (ctrl |
323 BPCTLI_CTRL_EXT_MCLK_DIR80
325 BPCTLI_CTRL_EXT_MCLK_DATA80));
327 } else if (pbpctl_dev->bp_540) {
328 BP10G_WRITE_REG(pbpctl_dev, ESDP, (ctrl |
337 } else if (pbpctl_dev->bp_10gb) {
338 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
339 (ctrl_ext | BP10GB_MDIO_SET |
346 } else if (!pbpctl_dev->bp_10g)
347 /* To start management : MCLK 1, MDIO 1, output */
348 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
350 BPCTLI_CTRL_EXT_MCLK_DIR |
351 BPCTLI_CTRL_EXT_MDIO_DIR |
352 BPCTLI_CTRL_EXT_MDIO_DATA |
353 BPCTLI_CTRL_EXT_MCLK_DATA));
356 /* To start management : MCLK 1, MDIO 1, output*/
357 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
358 (ctrl_ext | BP10G_MCLK_DATA_OUT
359 | BP10G_MDIO_DATA_OUT));
363 usec_delay(PULSE_TIME);
364 if (pbpctl_dev->bp_10g9) {
366 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, ((ctrl_ext|BP10G_MDIO_DATA_OUT9)&~(BP10G_MCLK_DATA_OUT9))); */
368 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
370 BP10G_MDIO_DATA_OUT9);
371 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
372 (ctrl | BP10G_MCLK_DIR_OUT9) &
373 ~BP10G_MCLK_DATA_OUT9);
375 } else if (pbpctl_dev->bp_fiber5) {
376 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
378 BPCTLI_CTRL_EXT_MCLK_DIR5 |
379 BPCTLI_CTRL_EXT_MDIO_DIR5 |
380 BPCTLI_CTRL_EXT_MDIO_DATA5)
383 (BPCTLI_CTRL_EXT_MCLK_DATA5)));
385 } else if (pbpctl_dev->bp_i80) {
386 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, (ctrl_ext |
387 BPCTLI_CTRL_EXT_MDIO_DIR80
389 BPCTLI_CTRL_EXT_MDIO_DATA80));
390 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
392 BPCTLI_CTRL_EXT_MCLK_DIR80)
395 (BPCTLI_CTRL_EXT_MCLK_DATA80)));
397 } else if (pbpctl_dev->bp_540) {
398 BP10G_WRITE_REG(pbpctl_dev, ESDP,
399 (ctrl | BP540_MDIO_DIR |
404 } else if (pbpctl_dev->bp_10gb) {
406 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
407 (ctrl_ext | BP10GB_MDIO_SET |
414 } else if (!pbpctl_dev->bp_10g)
416 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
418 BPCTLI_CTRL_EXT_MCLK_DIR |
419 BPCTLI_CTRL_EXT_MDIO_DIR |
420 BPCTLI_CTRL_EXT_MDIO_DATA)
423 (BPCTLI_CTRL_EXT_MCLK_DATA)));
426 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
428 BP10G_MDIO_DATA_OUT) &
429 ~(BP10G_MCLK_DATA_OUT)));
432 usec_delay(PULSE_TIME);
435 if (pbpctl_dev->bp_10g9) {
437 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, ((ctrl_ext|BP10G_MCLK_DATA_OUT9)&~BP10G_MDIO_DATA_OUT9)); */
438 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
440 ~BP10G_MDIO_DATA_OUT9));
441 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
442 (ctrl | BP10G_MCLK_DATA_OUT9 |
443 BP10G_MCLK_DIR_OUT9));
445 } else if (pbpctl_dev->bp_fiber5) {
446 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
448 BPCTLI_CTRL_EXT_MCLK_DIR5 |
449 BPCTLI_CTRL_EXT_MDIO_DIR5 |
450 BPCTLI_CTRL_EXT_MCLK_DATA5)
453 (BPCTLI_CTRL_EXT_MDIO_DATA5)));
455 } else if (pbpctl_dev->bp_i80) {
456 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
458 BPCTLI_CTRL_EXT_MDIO_DIR80)
461 (BPCTLI_CTRL_EXT_MDIO_DATA80)));
462 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
464 BPCTLI_CTRL_EXT_MCLK_DIR80 |
465 BPCTLI_CTRL_EXT_MCLK_DATA80));
467 } else if (pbpctl_dev->bp_540) {
468 BP10G_WRITE_REG(pbpctl_dev, ESDP,
469 ((ctrl | BP540_MCLK_DIR |
472 ~(BP540_MDIO_DATA)));
474 } else if (pbpctl_dev->bp_10gb) {
475 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
476 (ctrl_ext | BP10GB_MDIO_CLR |
483 } else if (!pbpctl_dev->bp_10g)
485 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
487 BPCTLI_CTRL_EXT_MCLK_DIR |
488 BPCTLI_CTRL_EXT_MDIO_DIR |
489 BPCTLI_CTRL_EXT_MCLK_DATA)
492 (BPCTLI_CTRL_EXT_MDIO_DATA)));
495 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
497 BP10G_MCLK_DATA_OUT) &
498 ~BP10G_MDIO_DATA_OUT));
501 usec_delay(PULSE_TIME);
502 if (pbpctl_dev->bp_10g9) {
504 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
505 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
507 ~BP10G_MDIO_DATA_OUT9));
508 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
509 ((ctrl | BP10G_MCLK_DIR_OUT9) &
510 ~(BP10G_MCLK_DATA_OUT9)));
512 } else if (pbpctl_dev->bp_fiber5) {
513 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
515 BPCTLI_CTRL_EXT_MCLK_DIR5 |
516 BPCTLI_CTRL_EXT_MDIO_DIR5)
518 ~(BPCTLI_CTRL_EXT_MCLK_DATA5
520 BPCTLI_CTRL_EXT_MDIO_DATA5)));
522 } else if (pbpctl_dev->bp_i80) {
523 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
525 BPCTLI_CTRL_EXT_MDIO_DIR80)
527 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
528 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
530 BPCTLI_CTRL_EXT_MCLK_DIR80)
533 (BPCTLI_CTRL_EXT_MCLK_DATA80)));
535 } else if (pbpctl_dev->bp_540) {
536 BP10G_WRITE_REG(pbpctl_dev, ESDP,
537 ((ctrl | BP540_MCLK_DIR |
541 } else if (pbpctl_dev->bp_10gb) {
543 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
544 (ctrl_ext | BP10GB_MDIO_CLR |
551 } else if (!pbpctl_dev->bp_10g)
552 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
554 BPCTLI_CTRL_EXT_MCLK_DIR |
555 BPCTLI_CTRL_EXT_MDIO_DIR) &
556 ~(BPCTLI_CTRL_EXT_MCLK_DATA
558 BPCTLI_CTRL_EXT_MDIO_DATA)));
561 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
563 ~(BP10G_MCLK_DATA_OUT |
564 BP10G_MDIO_DATA_OUT)));
567 usec_delay(PULSE_TIME);
573 static int read_pulse(struct bpctl_dev *pbpctl_dev, unsigned int ctrl_ext,
576 unsigned char ctrl_val = 0;
577 unsigned int i = len;
578 unsigned int ctrl = 0;
579 struct bpctl_dev *pbpctl_dev_c = NULL;
581 if (pbpctl_dev->bp_i80)
582 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
583 if (pbpctl_dev->bp_540)
584 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
585 if (pbpctl_dev->bp_10g9) {
586 pbpctl_dev_c = get_status_port_fn(pbpctl_dev);
589 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
594 if (pbpctl_dev->bp_10g9) {
595 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, ((ctrl_ext|BP10G_MDIO_DATA_OUT9)&~BP10G_MCLK_DATA_OUT9)); */
597 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
598 ((ctrl | BP10G_MCLK_DIR_OUT9) &
599 ~(BP10G_MCLK_DATA_OUT9)));
601 } else if (pbpctl_dev->bp_fiber5) {
602 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
603 BPCTLI_CTRL_EXT_MCLK_DIR5)
606 (BPCTLI_CTRL_EXT_MDIO_DIR5
608 BPCTLI_CTRL_EXT_MCLK_DATA5)));
610 } else if (pbpctl_dev->bp_i80) {
611 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
613 ~BPCTLI_CTRL_EXT_MDIO_DIR80));
614 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
615 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80)
616 & ~(BPCTLI_CTRL_EXT_MCLK_DATA80)));
618 } else if (pbpctl_dev->bp_540) {
619 BP10G_WRITE_REG(pbpctl_dev, ESDP,
620 ((ctrl | BP540_MCLK_DIR) &
621 ~(BP540_MDIO_DIR | BP540_MCLK_DATA)));
623 } else if (pbpctl_dev->bp_10gb) {
625 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
626 (ctrl_ext | BP10GB_MDIO_DIR |
627 BP10GB_MCLK_CLR) & ~(BP10GB_MCLK_DIR |
632 } else if (!pbpctl_dev->bp_10g)
633 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
634 BPCTLI_CTRL_EXT_MCLK_DIR)
637 (BPCTLI_CTRL_EXT_MDIO_DIR
639 BPCTLI_CTRL_EXT_MCLK_DATA)));
642 BP10G_WRITE_REG(pbpctl_dev, EODSDP, ((ctrl_ext | BP10G_MDIO_DATA_OUT) & ~BP10G_MCLK_DATA_OUT)); /* ? */
643 /* printk("0x28=0x%x\n",BP10G_READ_REG(pbpctl_dev,EODSDP);); */
647 usec_delay(PULSE_TIME);
648 if (pbpctl_dev->bp_10g9) {
649 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext|BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9)); */
651 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
652 (ctrl | BP10G_MCLK_DATA_OUT9 |
653 BP10G_MCLK_DIR_OUT9));
655 } else if (pbpctl_dev->bp_fiber5) {
656 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
657 BPCTLI_CTRL_EXT_MCLK_DIR5
659 BPCTLI_CTRL_EXT_MCLK_DATA5)
662 (BPCTLI_CTRL_EXT_MDIO_DIR5)));
664 } else if (pbpctl_dev->bp_i80) {
665 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
667 ~(BPCTLI_CTRL_EXT_MDIO_DIR80)));
668 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
669 (ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80 |
670 BPCTLI_CTRL_EXT_MCLK_DATA80));
672 } else if (pbpctl_dev->bp_540) {
673 BP10G_WRITE_REG(pbpctl_dev, ESDP,
674 ((ctrl | BP540_MCLK_DIR |
678 } else if (pbpctl_dev->bp_10gb) {
679 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
680 (ctrl_ext | BP10GB_MDIO_DIR |
681 BP10GB_MCLK_SET) & ~(BP10GB_MCLK_DIR |
686 } else if (!pbpctl_dev->bp_10g)
687 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
688 BPCTLI_CTRL_EXT_MCLK_DIR
690 BPCTLI_CTRL_EXT_MCLK_DATA)
693 (BPCTLI_CTRL_EXT_MDIO_DIR)));
696 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
697 (ctrl_ext | BP10G_MCLK_DATA_OUT |
698 BP10G_MDIO_DATA_OUT));
702 if (pbpctl_dev->bp_10g9)
703 ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
704 else if ((pbpctl_dev->bp_fiber5) || (pbpctl_dev->bp_i80))
705 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
706 else if (pbpctl_dev->bp_540)
707 ctrl_ext = BP10G_READ_REG(pbpctl_dev, ESDP);
708 else if (pbpctl_dev->bp_10gb)
709 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
710 else if (!pbpctl_dev->bp_10g)
711 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
713 ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
715 usec_delay(PULSE_TIME);
716 if (pbpctl_dev->bp_10g9) {
717 if (ctrl_ext & BP10G_MDIO_DATA_IN9)
720 } else if (pbpctl_dev->bp_fiber5) {
721 if (ctrl_ext & BPCTLI_CTRL_EXT_MDIO_DATA5)
723 } else if (pbpctl_dev->bp_i80) {
724 if (ctrl_ext & BPCTLI_CTRL_EXT_MDIO_DATA80)
726 } else if (pbpctl_dev->bp_540) {
727 if (ctrl_ext & BP540_MDIO_DATA)
729 } else if (pbpctl_dev->bp_10gb) {
730 if (ctrl_ext & BP10GB_MDIO_DATA)
733 } else if (!pbpctl_dev->bp_10g) {
735 if (ctrl_ext & BPCTLI_CTRL_EXT_MDIO_DATA)
739 if (ctrl_ext & BP10G_MDIO_DATA_IN)
748 static void write_reg(struct bpctl_dev *pbpctl_dev, unsigned char value,
751 uint32_t ctrl_ext = 0, ctrl = 0;
752 struct bpctl_dev *pbpctl_dev_c = NULL;
754 if (pbpctl_dev->bp_10g9) {
755 pbpctl_dev_c = get_status_port_fn(pbpctl_dev);
759 if ((pbpctl_dev->wdt_status == WDT_STATUS_EN) &&
760 (pbpctl_dev->bp_ext_ver < PXG4BPFI_VER))
761 wdt_time_left(pbpctl_dev);
764 spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
766 atomic_set(&pbpctl_dev->wdt_busy, 1);
768 if (pbpctl_dev->bp_10g9) {
770 ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
771 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
773 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
774 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
775 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
776 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
777 ((ctrl | BP10G_MCLK_DIR_OUT9) &
778 ~(BP10G_MCLK_DATA_OUT9)));
780 } else if (pbpctl_dev->bp_fiber5) {
781 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
782 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
783 BPCTLI_CTRL_EXT_MCLK_DIR5
785 BPCTLI_CTRL_EXT_MDIO_DIR5)
788 (BPCTLI_CTRL_EXT_MDIO_DATA5
790 BPCTLI_CTRL_EXT_MCLK_DATA5)));
791 } else if (pbpctl_dev->bp_i80) {
792 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
793 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
794 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
795 BPCTLI_CTRL_EXT_MDIO_DIR80)
797 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
798 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
799 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
800 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
802 } else if (pbpctl_dev->bp_540) {
803 ctrl = ctrl_ext = BP10G_READ_REG(pbpctl_dev, ESDP);
804 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl |
810 } else if (pbpctl_dev->bp_10gb) {
811 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
813 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
814 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
815 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
816 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
818 } else if (!pbpctl_dev->bp_10g) {
820 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
821 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
822 BPCTLI_CTRL_EXT_MCLK_DIR
824 BPCTLI_CTRL_EXT_MDIO_DIR)
827 (BPCTLI_CTRL_EXT_MDIO_DATA
829 BPCTLI_CTRL_EXT_MCLK_DATA)));
831 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
832 ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
833 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
835 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
837 usec_delay(CMND_INTERVAL);
840 write_pulse(pbpctl_dev, ctrl_ext, SYNC_CMD_VAL, SYNC_CMD_LEN);
842 write_pulse(pbpctl_dev, ctrl_ext, WR_CMD_VAL, WR_CMD_LEN);
843 write_pulse(pbpctl_dev, ctrl_ext, addr, ADDR_CMD_LEN);
846 write_pulse(pbpctl_dev, ctrl_ext, value, WR_DATA_LEN);
847 if (pbpctl_dev->bp_10g9) {
848 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
850 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
851 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
852 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
853 ((ctrl | BP10G_MCLK_DIR_OUT9) &
854 ~(BP10G_MCLK_DATA_OUT9)));
856 } else if (pbpctl_dev->bp_fiber5) {
857 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
858 BPCTLI_CTRL_EXT_MCLK_DIR5
860 BPCTLI_CTRL_EXT_MDIO_DIR5)
863 (BPCTLI_CTRL_EXT_MDIO_DATA5
865 BPCTLI_CTRL_EXT_MCLK_DATA5)));
866 } else if (pbpctl_dev->bp_i80) {
867 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
868 BPCTLI_CTRL_EXT_MDIO_DIR80)
870 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
871 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
872 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
873 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
874 } else if (pbpctl_dev->bp_540) {
875 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl |
880 } else if (pbpctl_dev->bp_10gb) {
881 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
882 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
883 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
884 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
886 } else if (!pbpctl_dev->bp_10g)
888 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
889 BPCTLI_CTRL_EXT_MCLK_DIR
891 BPCTLI_CTRL_EXT_MDIO_DIR)
894 (BPCTLI_CTRL_EXT_MDIO_DATA
896 BPCTLI_CTRL_EXT_MCLK_DATA)));
898 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
900 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
904 usec_delay(CMND_INTERVAL * 4);
906 if ((pbpctl_dev->wdt_status == WDT_STATUS_EN) &&
907 (pbpctl_dev->bp_ext_ver < PXG4BPFI_VER) && (addr == CMND_REG_ADDR))
908 pbpctl_dev->bypass_wdt_on_time = jiffies;
910 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
912 atomic_set(&pbpctl_dev->wdt_busy, 0);
917 static void write_data(struct bpctl_dev *pbpctl_dev, unsigned char value)
919 write_reg(pbpctl_dev, value, CMND_REG_ADDR);
922 static int read_reg(struct bpctl_dev *pbpctl_dev, unsigned char addr)
924 uint32_t ctrl_ext = 0, ctrl = 0, ctrl_value = 0;
925 struct bpctl_dev *pbpctl_dev_c = NULL;
929 spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
931 atomic_set(&pbpctl_dev->wdt_busy, 1);
933 if (pbpctl_dev->bp_10g9) {
934 pbpctl_dev_c = get_status_port_fn(pbpctl_dev);
939 if (pbpctl_dev->bp_10g9) {
940 ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
941 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
943 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
945 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
946 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
947 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
948 ((ctrl | BP10G_MCLK_DIR_OUT9) &
949 ~(BP10G_MCLK_DATA_OUT9)));
951 } else if (pbpctl_dev->bp_fiber5) {
952 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
954 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
955 BPCTLI_CTRL_EXT_MCLK_DIR5
957 BPCTLI_CTRL_EXT_MDIO_DIR5)
960 (BPCTLI_CTRL_EXT_MDIO_DATA5
962 BPCTLI_CTRL_EXT_MCLK_DATA5)));
963 } else if (pbpctl_dev->bp_i80) {
964 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
965 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
967 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
968 BPCTLI_CTRL_EXT_MDIO_DIR80)
970 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
971 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
972 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
973 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
974 } else if (pbpctl_dev->bp_540) {
975 ctrl_ext = BP10G_READ_REG(pbpctl_dev, ESDP);
976 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
978 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl | BP540_MCLK_DIR |
982 } else if (pbpctl_dev->bp_10gb) {
983 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
985 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
986 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
987 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
988 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
991 /*BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO, (ctrl_ext | BP10GB_MCLK_DIR | BP10GB_MDIO_DIR|
992 BP10GB_MCLK_CLR|BP10GB_MDIO_CLR));
993 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
994 printk("1reg=%x\n", ctrl_ext); */
996 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO, ((ctrl_ext |
999 & ~(BP10GB_MCLK_CLR | BP10GB_MDIO_SET |
1000 BP10GB_MCLK_DIR | BP10GB_MDIO_DIR));
1002 /* bnx2x_set_spio(pbpctl_dev, 5, MISC_REGISTERS_SPIO_OUTPUT_LOW);
1003 bnx2x_set_spio(pbpctl_dev, 4, MISC_REGISTERS_SPIO_OUTPUT_LOW);
1004 bnx2x_set_spio(pbpctl_dev, 4, MISC_REGISTERS_SPIO_INPUT_HI_Z); */
1006 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1008 printk("2reg=%x\n", ctrl_ext);
1011 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1013 atomic_set(&pbpctl_dev->wdt_busy, 0);
1020 } else if (!pbpctl_dev->bp_10g) {
1022 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1024 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1025 BPCTLI_CTRL_EXT_MCLK_DIR
1027 BPCTLI_CTRL_EXT_MDIO_DIR)
1030 (BPCTLI_CTRL_EXT_MDIO_DATA
1032 BPCTLI_CTRL_EXT_MCLK_DATA)));
1035 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1036 ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
1037 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1039 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
1043 usec_delay(CMND_INTERVAL);
1046 write_pulse(pbpctl_dev, ctrl_ext, SYNC_CMD_VAL, SYNC_CMD_LEN);
1048 write_pulse(pbpctl_dev, ctrl_ext, RD_CMD_VAL, RD_CMD_LEN);
1050 write_pulse(pbpctl_dev, ctrl_ext, addr, ADDR_CMD_LEN);
1053 if (pbpctl_dev->bp_10g9) {
1055 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext|BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9)); */
1056 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1057 (ctrl_ext | BP10G_MDIO_DATA_OUT9));
1058 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1059 (ctrl | BP10G_MCLK_DATA_OUT9 |
1060 BP10G_MCLK_DIR_OUT9));
1062 } else if (pbpctl_dev->bp_fiber5) {
1063 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1064 BPCTLI_CTRL_EXT_MCLK_DIR5
1066 BPCTLI_CTRL_EXT_MCLK_DATA5)
1069 (BPCTLI_CTRL_EXT_MDIO_DIR5
1071 BPCTLI_CTRL_EXT_MDIO_DATA5)));
1073 } else if (pbpctl_dev->bp_i80) {
1074 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
1076 ~(BPCTLI_CTRL_EXT_MDIO_DATA80 |
1077 BPCTLI_CTRL_EXT_MDIO_DIR80)));
1078 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1079 (ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80 |
1080 BPCTLI_CTRL_EXT_MCLK_DATA80));
1082 } else if (pbpctl_dev->bp_540) {
1083 BP10G_WRITE_REG(pbpctl_dev, ESDP,
1084 (((ctrl | BP540_MDIO_DIR | BP540_MCLK_DIR |
1085 BP540_MCLK_DATA) & ~BP540_MDIO_DATA)));
1087 } else if (pbpctl_dev->bp_10gb) {
1089 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1090 (ctrl_ext | BP10GB_MDIO_DIR | BP10GB_MCLK_SET)
1091 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_SET |
1092 BP10GB_MDIO_CLR | BP10GB_MCLK_CLR));
1094 } else if (!pbpctl_dev->bp_10g)
1095 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1096 BPCTLI_CTRL_EXT_MCLK_DIR
1098 BPCTLI_CTRL_EXT_MCLK_DATA)
1101 (BPCTLI_CTRL_EXT_MDIO_DIR
1103 BPCTLI_CTRL_EXT_MDIO_DATA)));
1106 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1107 (ctrl_ext | BP10G_MCLK_DATA_OUT |
1108 BP10G_MDIO_DATA_OUT));
1112 usec_delay(PULSE_TIME);
1114 ctrl_value = read_pulse(pbpctl_dev, ctrl_ext, RD_DATA_LEN);
1116 if (pbpctl_dev->bp_10g9) {
1117 ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
1118 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
1120 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
1122 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1123 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
1124 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1125 ((ctrl | BP10G_MCLK_DIR_OUT9) &
1126 ~(BP10G_MCLK_DATA_OUT9)));
1128 } else if (pbpctl_dev->bp_fiber5) {
1129 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1130 BPCTLI_CTRL_EXT_MCLK_DIR5
1132 BPCTLI_CTRL_EXT_MDIO_DIR5)
1135 (BPCTLI_CTRL_EXT_MDIO_DATA5
1137 BPCTLI_CTRL_EXT_MCLK_DATA5)));
1138 } else if (pbpctl_dev->bp_i80) {
1139 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1140 BPCTLI_CTRL_EXT_MDIO_DIR80)
1142 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
1143 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1144 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
1145 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
1147 } else if (pbpctl_dev->bp_540) {
1148 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1149 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl | BP540_MCLK_DIR |
1154 } else if (pbpctl_dev->bp_10gb) {
1155 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1156 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1157 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
1158 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
1159 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
1161 } else if (!pbpctl_dev->bp_10g) {
1162 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1163 BPCTLI_CTRL_EXT_MCLK_DIR
1165 BPCTLI_CTRL_EXT_MDIO_DIR)
1168 (BPCTLI_CTRL_EXT_MDIO_DATA
1170 BPCTLI_CTRL_EXT_MCLK_DATA)));
1173 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1174 ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
1175 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1177 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
1181 usec_delay(CMND_INTERVAL * 4);
1183 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1185 atomic_set(&pbpctl_dev->wdt_busy, 0);
1191 static int wdt_pulse(struct bpctl_dev *pbpctl_dev)
1193 uint32_t ctrl_ext = 0, ctrl = 0;
1194 struct bpctl_dev *pbpctl_dev_c = NULL;
1197 unsigned long flags;
1199 spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
1202 if ((atomic_read(&pbpctl_dev->wdt_busy)) == 1)
1205 if (pbpctl_dev->bp_10g9) {
1206 pbpctl_dev_c = get_status_port_fn(pbpctl_dev);
1211 if (pbpctl_dev->bp_10g9) {
1212 ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
1213 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
1215 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
1217 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1218 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
1219 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1220 ((ctrl | BP10G_MCLK_DIR_OUT9) &
1221 ~(BP10G_MCLK_DATA_OUT9)));
1223 } else if (pbpctl_dev->bp_fiber5) {
1224 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
1225 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1226 BPCTLI_CTRL_EXT_MCLK_DIR5
1228 BPCTLI_CTRL_EXT_MDIO_DIR5)
1231 (BPCTLI_CTRL_EXT_MDIO_DATA5
1233 BPCTLI_CTRL_EXT_MCLK_DATA5)));
1234 } else if (pbpctl_dev->bp_i80) {
1235 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
1236 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1237 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1238 BPCTLI_CTRL_EXT_MDIO_DIR80)
1240 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
1241 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1242 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
1243 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
1244 } else if (pbpctl_dev->bp_540) {
1245 ctrl_ext = ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1246 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl | BP540_MCLK_DIR |
1250 } else if (pbpctl_dev->bp_10gb) {
1251 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1252 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1253 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
1254 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
1255 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
1257 } else if (!pbpctl_dev->bp_10g) {
1259 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1260 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1261 BPCTLI_CTRL_EXT_MCLK_DIR
1263 BPCTLI_CTRL_EXT_MDIO_DIR)
1266 (BPCTLI_CTRL_EXT_MDIO_DATA
1268 BPCTLI_CTRL_EXT_MCLK_DATA)));
1271 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1272 ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
1273 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1275 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
1278 if (pbpctl_dev->bp_10g9) {
1279 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, ((ctrl_ext|BP10G_MCLK_DATA_OUT9)&~BP10G_MDIO_DATA_OUT9)); */
1281 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1282 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
1283 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1284 (ctrl | BP10G_MCLK_DATA_OUT9 |
1285 BP10G_MCLK_DIR_OUT9));
1287 } else if (pbpctl_dev->bp_fiber5) {
1288 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1289 BPCTLI_CTRL_EXT_MCLK_DIR5
1291 BPCTLI_CTRL_EXT_MDIO_DIR5
1293 BPCTLI_CTRL_EXT_MCLK_DATA5)
1296 (BPCTLI_CTRL_EXT_MDIO_DATA5)));
1297 } else if (pbpctl_dev->bp_i80) {
1298 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1299 BPCTLI_CTRL_EXT_MDIO_DIR80)
1301 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
1302 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1303 (ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80 |
1304 BPCTLI_CTRL_EXT_MCLK_DATA80));
1306 } else if (pbpctl_dev->bp_540) {
1307 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl |
1313 } else if (pbpctl_dev->bp_10gb) {
1314 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1316 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1317 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_SET)
1318 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
1319 BP10GB_MDIO_SET | BP10GB_MCLK_CLR));
1321 } else if (!pbpctl_dev->bp_10g)
1322 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1323 BPCTLI_CTRL_EXT_MCLK_DIR
1325 BPCTLI_CTRL_EXT_MDIO_DIR
1327 BPCTLI_CTRL_EXT_MCLK_DATA)
1330 (BPCTLI_CTRL_EXT_MDIO_DATA)));
1333 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1334 ((ctrl_ext | BP10G_MCLK_DATA_OUT) &
1335 ~BP10G_MDIO_DATA_OUT));
1339 usec_delay(WDT_INTERVAL);
1340 if (pbpctl_dev->bp_10g9) {
1341 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
1343 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1344 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
1345 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1346 ((ctrl | BP10G_MCLK_DIR_OUT9) &
1347 ~(BP10G_MCLK_DATA_OUT9)));
1349 } else if (pbpctl_dev->bp_fiber5) {
1350 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1351 BPCTLI_CTRL_EXT_MCLK_DIR5
1353 BPCTLI_CTRL_EXT_MDIO_DIR5)
1356 (BPCTLI_CTRL_EXT_MCLK_DATA5
1358 BPCTLI_CTRL_EXT_MDIO_DATA5)));
1359 } else if (pbpctl_dev->bp_i80) {
1360 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1361 BPCTLI_CTRL_EXT_MDIO_DIR80)
1363 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
1364 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1365 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
1366 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
1368 } else if (pbpctl_dev->bp_540) {
1369 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl | BP540_MCLK_DIR |
1374 } else if (pbpctl_dev->bp_10gb) {
1375 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1376 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1377 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
1378 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
1379 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
1381 } else if (!pbpctl_dev->bp_10g)
1382 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1383 BPCTLI_CTRL_EXT_MCLK_DIR
1385 BPCTLI_CTRL_EXT_MDIO_DIR)
1388 (BPCTLI_CTRL_EXT_MCLK_DATA
1390 BPCTLI_CTRL_EXT_MDIO_DATA)));
1393 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1395 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
1397 if ((pbpctl_dev->wdt_status == WDT_STATUS_EN))
1398 /*&& (pbpctl_dev->bp_ext_ver<PXG4BPFI_VER) */
1399 pbpctl_dev->bypass_wdt_on_time = jiffies;
1401 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1403 usec_delay(CMND_INTERVAL * 4);
1407 static void data_pulse(struct bpctl_dev *pbpctl_dev, unsigned char value)
1410 uint32_t ctrl_ext = 0;
1412 unsigned long flags;
1414 wdt_time_left(pbpctl_dev);
1416 spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
1418 atomic_set(&pbpctl_dev->wdt_busy, 1);
1421 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1422 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1423 BPCTLI_CTRL_EXT_SDP6_DIR |
1424 BPCTLI_CTRL_EXT_SDP7_DIR) &
1425 ~(BPCTLI_CTRL_EXT_SDP6_DATA |
1426 BPCTLI_CTRL_EXT_SDP7_DATA)));
1428 usec_delay(INIT_CMND_INTERVAL);
1429 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1430 BPCTLI_CTRL_EXT_SDP6_DIR |
1431 BPCTLI_CTRL_EXT_SDP7_DIR |
1432 BPCTLI_CTRL_EXT_SDP6_DATA) &
1434 (BPCTLI_CTRL_EXT_SDP7_DATA)));
1435 usec_delay(INIT_CMND_INTERVAL);
1438 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext |
1439 BPCTLI_CTRL_EXT_SDP6_DIR |
1440 BPCTLI_CTRL_EXT_SDP7_DIR |
1441 BPCTLI_CTRL_EXT_SDP6_DATA |
1442 BPCTLI_CTRL_EXT_SDP7_DATA);
1443 usec_delay(PULSE_INTERVAL);
1444 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1445 BPCTLI_CTRL_EXT_SDP6_DIR
1447 BPCTLI_CTRL_EXT_SDP7_DIR
1449 BPCTLI_CTRL_EXT_SDP6_DATA)
1451 ~BPCTLI_CTRL_EXT_SDP7_DATA));
1452 usec_delay(PULSE_INTERVAL);
1456 usec_delay(INIT_CMND_INTERVAL - PULSE_INTERVAL);
1457 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1458 BPCTLI_CTRL_EXT_SDP6_DIR |
1459 BPCTLI_CTRL_EXT_SDP7_DIR) &
1460 ~(BPCTLI_CTRL_EXT_SDP6_DATA |
1461 BPCTLI_CTRL_EXT_SDP7_DATA)));
1462 usec_delay(WDT_TIME_CNT);
1463 if (pbpctl_dev->wdt_status == WDT_STATUS_EN)
1464 pbpctl_dev->bypass_wdt_on_time = jiffies;
1466 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1468 atomic_set(&pbpctl_dev->wdt_busy, 0);
1473 static int send_wdt_pulse(struct bpctl_dev *pbpctl_dev)
1475 uint32_t ctrl_ext = 0;
1478 unsigned long flags;
1480 spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
1483 if ((atomic_read(&pbpctl_dev->wdt_busy)) == 1)
1486 wdt_time_left(pbpctl_dev);
1487 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1489 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext | /* 1 */
1490 BPCTLI_CTRL_EXT_SDP7_DIR |
1491 BPCTLI_CTRL_EXT_SDP7_DATA);
1492 usec_delay(PULSE_INTERVAL);
1493 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext | /* 0 */
1494 BPCTLI_CTRL_EXT_SDP7_DIR) &
1495 ~BPCTLI_CTRL_EXT_SDP7_DATA));
1497 usec_delay(PULSE_INTERVAL);
1498 if (pbpctl_dev->wdt_status == WDT_STATUS_EN)
1499 pbpctl_dev->bypass_wdt_on_time = jiffies;
1501 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1507 void send_bypass_clear_pulse(struct bpctl_dev *pbpctl_dev, unsigned int value)
1509 uint32_t ctrl_ext = 0;
1511 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1512 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext | /* 0 */
1513 BPCTLI_CTRL_EXT_SDP6_DIR) &
1514 ~BPCTLI_CTRL_EXT_SDP6_DATA));
1516 usec_delay(PULSE_INTERVAL);
1518 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext | /* 1 */
1519 BPCTLI_CTRL_EXT_SDP6_DIR |
1520 BPCTLI_CTRL_EXT_SDP6_DATA);
1521 usec_delay(PULSE_INTERVAL);
1524 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext | /* 0 */
1525 BPCTLI_CTRL_EXT_SDP6_DIR) &
1526 ~BPCTLI_CTRL_EXT_SDP6_DATA));
1527 usec_delay(PULSE_INTERVAL);
1533 int pulse_set_fn(struct bpctl_dev *pbpctl_dev, unsigned int counter)
1535 uint32_t ctrl_ext = 0;
1540 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1541 write_pulse_1(pbpctl_dev, ctrl_ext, counter, counter);
1543 pbpctl_dev->bypass_wdt_status = 0;
1544 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1545 write_pulse_1(pbpctl_dev, ctrl_ext, counter, counter);
1547 wdt_time_left(pbpctl_dev);
1548 if (pbpctl_dev->wdt_status == WDT_STATUS_EN) {
1549 pbpctl_dev->wdt_status = 0;
1550 data_pulse(pbpctl_dev, counter);
1551 pbpctl_dev->wdt_status = WDT_STATUS_EN;
1552 pbpctl_dev->bypass_wdt_on_time = jiffies;
1555 data_pulse(pbpctl_dev, counter);
1561 int zero_set_fn(struct bpctl_dev *pbpctl_dev)
1563 uint32_t ctrl_ext = 0, ctrl_value = 0;
1567 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1570 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1572 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1573 BPCTLI_CTRL_EXT_MCLK_DIR)
1576 (BPCTLI_CTRL_EXT_MCLK_DATA
1578 BPCTLI_CTRL_EXT_MDIO_DIR
1580 BPCTLI_CTRL_EXT_MDIO_DATA)));
1586 int pulse_get2_fn(struct bpctl_dev *pbpctl_dev)
1588 uint32_t ctrl_ext = 0, ctrl_value = 0;
1592 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1593 printk("pulse_get_fn\n");
1594 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1595 ctrl_value = read_pulse_2(pbpctl_dev, ctrl_ext);
1596 printk("read:%d\n", ctrl_value);
1601 int pulse_get1_fn(struct bpctl_dev *pbpctl_dev)
1603 uint32_t ctrl_ext = 0, ctrl_value = 0;
1607 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1609 printk("pulse_get_fn\n");
1611 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1612 ctrl_value = read_pulse_1(pbpctl_dev, ctrl_ext);
1613 printk("read:%d\n", ctrl_value);
1618 int gpio6_set_fn(struct bpctl_dev *pbpctl_dev)
1620 uint32_t ctrl_ext = 0;
1622 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1623 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext |
1624 BPCTLI_CTRL_EXT_SDP6_DIR |
1625 BPCTLI_CTRL_EXT_SDP6_DATA);
1629 int gpio7_set_fn(struct bpctl_dev *pbpctl_dev)
1631 uint32_t ctrl_ext = 0;
1633 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1634 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext |
1635 BPCTLI_CTRL_EXT_SDP7_DIR |
1636 BPCTLI_CTRL_EXT_SDP7_DATA);
1640 int gpio7_clear_fn(struct bpctl_dev *pbpctl_dev)
1642 uint32_t ctrl_ext = 0;
1644 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1645 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1646 BPCTLI_CTRL_EXT_SDP7_DIR) &
1647 ~BPCTLI_CTRL_EXT_SDP7_DATA));
1651 int gpio6_clear_fn(struct bpctl_dev *pbpctl_dev)
1653 uint32_t ctrl_ext = 0;
1655 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1656 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1657 BPCTLI_CTRL_EXT_SDP6_DIR) &
1658 ~BPCTLI_CTRL_EXT_SDP6_DATA));
1661 #endif /*BYPASS_DEBUG */
1663 static struct bpctl_dev *lookup_port(struct bpctl_dev *dev)
1665 struct bpctl_dev *p;
1667 for (n = 0, p = bpctl_dev_arr; n < device_num && p->pdev; n++) {
1668 if (p->bus == dev->bus
1669 && p->slot == dev->slot
1670 && p->func == (dev->func ^ 1))
1676 static struct bpctl_dev *get_status_port_fn(struct bpctl_dev *pbpctl_dev)
1679 if (pbpctl_dev->func == 0 || pbpctl_dev->func == 2)
1680 return lookup_port(pbpctl_dev);
1685 static struct bpctl_dev *get_master_port_fn(struct bpctl_dev *pbpctl_dev)
1688 if (pbpctl_dev->func == 1 || pbpctl_dev->func == 3)
1689 return lookup_port(pbpctl_dev);
1694 /**************************************/
1695 /**************INTEL API***************/
1696 /**************************************/
1698 static void write_data_port_int(struct bpctl_dev *pbpctl_dev,
1699 unsigned char ctrl_value)
1703 value = BPCTL_READ_REG(pbpctl_dev, CTRL);
1704 /* Make SDP0 Pin Directonality to Output */
1705 value |= BPCTLI_CTRL_SDP0_DIR;
1706 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, value);
1708 value &= ~BPCTLI_CTRL_SDP0_DATA;
1709 value |= ((ctrl_value & 0x1) << BPCTLI_CTRL_SDP0_SHIFT);
1710 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, value);
1712 value = (BPCTL_READ_REG(pbpctl_dev, CTRL_EXT));
1713 /* Make SDP2 Pin Directonality to Output */
1714 value |= BPCTLI_CTRL_EXT_SDP6_DIR;
1715 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, value);
1717 value &= ~BPCTLI_CTRL_EXT_SDP6_DATA;
1718 value |= (((ctrl_value & 0x2) >> 1) << BPCTLI_CTRL_EXT_SDP6_SHIFT);
1719 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, value);
1723 static int write_data_int(struct bpctl_dev *pbpctl_dev, unsigned char value)
1725 struct bpctl_dev *pbpctl_dev_b = NULL;
1727 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
1730 atomic_set(&pbpctl_dev->wdt_busy, 1);
1731 write_data_port_int(pbpctl_dev, value & 0x3);
1732 write_data_port_int(pbpctl_dev_b, ((value & 0xc) >> 2));
1733 atomic_set(&pbpctl_dev->wdt_busy, 0);
1738 static int wdt_pulse_int(struct bpctl_dev *pbpctl_dev)
1741 if ((atomic_read(&pbpctl_dev->wdt_busy)) == 1)
1744 if ((write_data_int(pbpctl_dev, RESET_WDT_INT)) < 0)
1746 msec_delay_bp(CMND_INTERVAL_INT);
1747 if ((write_data_int(pbpctl_dev, CMND_OFF_INT)) < 0)
1749 msec_delay_bp(CMND_INTERVAL_INT);
1751 if (pbpctl_dev->wdt_status == WDT_STATUS_EN)
1752 pbpctl_dev->bypass_wdt_on_time = jiffies;
1757 /*************************************/
1758 /************* COMMANDS **************/
1759 /*************************************/
1761 /* CMND_ON 0x4 (100)*/
1762 int cmnd_on(struct bpctl_dev *pbpctl_dev)
1764 int ret = BP_NOT_CAP;
1766 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
1767 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
1769 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
1770 write_data(pbpctl_dev, CMND_ON);
1772 data_pulse(pbpctl_dev, CMND_ON);
1778 /* CMND_OFF 0x2 (10)*/
1779 int cmnd_off(struct bpctl_dev *pbpctl_dev)
1781 int ret = BP_NOT_CAP;
1783 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
1784 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
1785 write_data_int(pbpctl_dev, CMND_OFF_INT);
1786 msec_delay_bp(CMND_INTERVAL_INT);
1787 } else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
1788 write_data(pbpctl_dev, CMND_OFF);
1790 data_pulse(pbpctl_dev, CMND_OFF);
1796 /* BYPASS_ON (0xa)*/
1797 int bypass_on(struct bpctl_dev *pbpctl_dev)
1799 int ret = BP_NOT_CAP;
1801 if (pbpctl_dev->bp_caps & BP_CAP) {
1802 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
1803 write_data_int(pbpctl_dev, BYPASS_ON_INT);
1804 msec_delay_bp(BYPASS_DELAY_INT);
1805 pbpctl_dev->bp_status_un = 0;
1806 } else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1807 write_data(pbpctl_dev, BYPASS_ON);
1808 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
1809 msec_delay_bp(LATCH_DELAY);
1811 data_pulse(pbpctl_dev, BYPASS_ON);
1817 /* BYPASS_OFF (0x8 111)*/
1818 int bypass_off(struct bpctl_dev *pbpctl_dev)
1820 int ret = BP_NOT_CAP;
1822 if (pbpctl_dev->bp_caps & BP_CAP) {
1823 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
1824 write_data_int(pbpctl_dev, DIS_BYPASS_CAP_INT);
1825 msec_delay_bp(BYPASS_DELAY_INT);
1826 write_data_int(pbpctl_dev, PWROFF_BYPASS_ON_INT);
1827 msec_delay_bp(BYPASS_DELAY_INT);
1828 pbpctl_dev->bp_status_un = 0;
1829 } else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1830 write_data(pbpctl_dev, BYPASS_OFF);
1831 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
1832 msec_delay_bp(LATCH_DELAY);
1834 data_pulse(pbpctl_dev, BYPASS_OFF);
1841 int tap_off(struct bpctl_dev *pbpctl_dev)
1843 int ret = BP_NOT_CAP;
1844 if ((pbpctl_dev->bp_caps & TAP_CAP)
1845 && (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)) {
1846 write_data(pbpctl_dev, TAP_OFF);
1847 msec_delay_bp(LATCH_DELAY);
1854 int tap_on(struct bpctl_dev *pbpctl_dev)
1856 int ret = BP_NOT_CAP;
1857 if ((pbpctl_dev->bp_caps & TAP_CAP)
1858 && (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)) {
1859 write_data(pbpctl_dev, TAP_ON);
1860 msec_delay_bp(LATCH_DELAY);
1867 int disc_off(struct bpctl_dev *pbpctl_dev)
1870 if ((pbpctl_dev->bp_caps & DISC_CAP) && (pbpctl_dev->bp_ext_ver >= 0x8)) {
1871 write_data(pbpctl_dev, DISC_OFF);
1872 msec_delay_bp(LATCH_DELAY);
1879 int disc_on(struct bpctl_dev *pbpctl_dev)
1882 if ((pbpctl_dev->bp_caps & DISC_CAP) && (pbpctl_dev->bp_ext_ver >= 0x8)) {
1883 write_data(pbpctl_dev, /*DISC_ON */ 0x85);
1884 msec_delay_bp(LATCH_DELAY);
1891 int disc_port_on(struct bpctl_dev *pbpctl_dev)
1894 struct bpctl_dev *pbpctl_dev_m;
1896 if ((is_bypass_fn(pbpctl_dev)) == 1)
1897 pbpctl_dev_m = pbpctl_dev;
1899 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
1900 if (pbpctl_dev_m == NULL)
1903 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
1904 if (is_bypass_fn(pbpctl_dev) == 1)
1905 write_data(pbpctl_dev_m, TX_DISA);
1907 write_data(pbpctl_dev_m, TX_DISB);
1909 msec_delay_bp(LATCH_DELAY);
1916 int disc_port_off(struct bpctl_dev *pbpctl_dev)
1919 struct bpctl_dev *pbpctl_dev_m;
1921 if ((is_bypass_fn(pbpctl_dev)) == 1)
1922 pbpctl_dev_m = pbpctl_dev;
1924 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
1925 if (pbpctl_dev_m == NULL)
1928 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
1929 if (is_bypass_fn(pbpctl_dev) == 1)
1930 write_data(pbpctl_dev_m, TX_ENA);
1932 write_data(pbpctl_dev_m, TX_ENB);
1934 msec_delay_bp(LATCH_DELAY);
1940 /*TWO_PORT_LINK_HW_EN (0xe)*/
1941 int tpl_hw_on(struct bpctl_dev *pbpctl_dev)
1943 int ret = 0, ctrl = 0;
1944 struct bpctl_dev *pbpctl_dev_b = NULL;
1946 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
1950 if (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX) {
1951 cmnd_on(pbpctl_dev);
1952 write_data(pbpctl_dev, TPL2_ON);
1953 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
1954 cmnd_off(pbpctl_dev);
1958 if (TPL_IF_SERIES(pbpctl_dev->subdevice)) {
1959 ctrl = BPCTL_READ_REG(pbpctl_dev_b, CTRL);
1960 BPCTL_BP_WRITE_REG(pbpctl_dev_b, CTRL,
1961 ((ctrl | BPCTLI_CTRL_SWDPIO0) &
1962 ~BPCTLI_CTRL_SWDPIN0));
1968 /*TWO_PORT_LINK_HW_DIS (0xc)*/
1969 int tpl_hw_off(struct bpctl_dev *pbpctl_dev)
1971 int ret = 0, ctrl = 0;
1972 struct bpctl_dev *pbpctl_dev_b = NULL;
1974 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
1977 if (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX) {
1978 cmnd_on(pbpctl_dev);
1979 write_data(pbpctl_dev, TPL2_OFF);
1980 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
1981 cmnd_off(pbpctl_dev);
1984 if (TPL_IF_SERIES(pbpctl_dev->subdevice)) {
1985 ctrl = BPCTL_READ_REG(pbpctl_dev_b, CTRL);
1986 BPCTL_BP_WRITE_REG(pbpctl_dev_b, CTRL,
1987 (ctrl | BPCTLI_CTRL_SWDPIO0 |
1988 BPCTLI_CTRL_SWDPIN0));
1994 /* WDT_OFF (0x6 110)*/
1995 int wdt_off(struct bpctl_dev *pbpctl_dev)
1997 int ret = BP_NOT_CAP;
1999 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
2000 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
2001 bypass_off(pbpctl_dev);
2002 else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
2003 write_data(pbpctl_dev, WDT_OFF);
2005 data_pulse(pbpctl_dev, WDT_OFF);
2006 pbpctl_dev->wdt_status = WDT_STATUS_DIS;
2016 wdt_val_array[] = { 1000, 1500, 2000, 3000, 4000, 8000, 16000, 32000, 0 };
2018 int wdt_on(struct bpctl_dev *pbpctl_dev, unsigned int timeout)
2021 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
2022 unsigned int pulse = 0, temp_value = 0, temp_cnt = 0;
2023 pbpctl_dev->wdt_status = 0;
2025 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2026 for (; wdt_val_array[temp_cnt]; temp_cnt++)
2027 if (timeout <= wdt_val_array[temp_cnt])
2030 if (!wdt_val_array[temp_cnt])
2033 timeout = wdt_val_array[temp_cnt];
2036 write_data_int(pbpctl_dev, DIS_BYPASS_CAP_INT);
2037 msec_delay_bp(BYPASS_DELAY_INT);
2038 pbpctl_dev->bp_status_un = 0;
2039 write_data_int(pbpctl_dev, temp_cnt);
2040 pbpctl_dev->bypass_wdt_on_time = jiffies;
2041 msec_delay_bp(CMND_INTERVAL_INT);
2042 pbpctl_dev->bypass_timer_interval = timeout;
2046 TIMEOUT_UNIT ? TIMEOUT_UNIT : (timeout >
2050 temp_value = timeout / 100;
2051 while ((temp_value >>= 1))
2053 if (timeout > ((1 << temp_cnt) * 100))
2055 pbpctl_dev->bypass_wdt_on_time = jiffies;
2056 pulse = (WDT_ON | temp_cnt);
2057 if (pbpctl_dev->bp_ext_ver == OLD_IF_VER)
2058 data_pulse(pbpctl_dev, pulse);
2060 write_data(pbpctl_dev, pulse);
2061 pbpctl_dev->bypass_timer_interval =
2062 (1 << temp_cnt) * 100;
2064 pbpctl_dev->wdt_status = WDT_STATUS_EN;
2070 void bp75_put_hw_semaphore_generic(struct bpctl_dev *pbpctl_dev)
2074 swsm = BPCTL_READ_REG(pbpctl_dev, SWSM);
2076 swsm &= ~(BPCTLI_SWSM_SMBI | BPCTLI_SWSM_SWESMBI);
2078 BPCTL_WRITE_REG(pbpctl_dev, SWSM, swsm);
2081 s32 bp75_get_hw_semaphore_generic(struct bpctl_dev *pbpctl_dev)
2085 s32 timeout = 8192 + 1;
2088 /* Get the SW semaphore */
2089 while (i < timeout) {
2090 swsm = BPCTL_READ_REG(pbpctl_dev, SWSM);
2091 if (!(swsm & BPCTLI_SWSM_SMBI))
2100 ("bpctl_mod: Driver can't access device - SMBI bit is set.\n");
2105 /* Get the FW semaphore. */
2106 for (i = 0; i < timeout; i++) {
2107 swsm = BPCTL_READ_REG(pbpctl_dev, SWSM);
2108 BPCTL_WRITE_REG(pbpctl_dev, SWSM, swsm | BPCTLI_SWSM_SWESMBI);
2110 /* Semaphore acquired if bit latched */
2111 if (BPCTL_READ_REG(pbpctl_dev, SWSM) & BPCTLI_SWSM_SWESMBI)
2118 /* Release semaphores */
2119 bp75_put_hw_semaphore_generic(pbpctl_dev);
2120 printk("bpctl_mod: Driver can't access the NVM\n");
2129 static void bp75_release_phy(struct bpctl_dev *pbpctl_dev)
2131 u16 mask = BPCTLI_SWFW_PHY0_SM;
2135 if ((pbpctl_dev->func == 1) || (pbpctl_dev->func == 3))
2136 mask = BPCTLI_SWFW_PHY1_SM;
2139 ret_val = bp75_get_hw_semaphore_generic(pbpctl_dev);
2140 while (ret_val != 0);
2142 swfw_sync = BPCTL_READ_REG(pbpctl_dev, SW_FW_SYNC);
2144 BPCTL_WRITE_REG(pbpctl_dev, SW_FW_SYNC, swfw_sync);
2146 bp75_put_hw_semaphore_generic(pbpctl_dev);
2149 static s32 bp75_acquire_phy(struct bpctl_dev *pbpctl_dev)
2151 u16 mask = BPCTLI_SWFW_PHY0_SM;
2156 s32 i = 0, timeout = 200;
2158 if ((pbpctl_dev->func == 1) || (pbpctl_dev->func == 3))
2159 mask = BPCTLI_SWFW_PHY1_SM;
2162 fwmask = mask << 16;
2164 while (i < timeout) {
2165 if (bp75_get_hw_semaphore_generic(pbpctl_dev)) {
2170 swfw_sync = BPCTL_READ_REG(pbpctl_dev, SW_FW_SYNC);
2171 if (!(swfw_sync & (fwmask | swmask)))
2174 bp75_put_hw_semaphore_generic(pbpctl_dev);
2181 ("bpctl_mod: Driver can't access resource, SW_FW_SYNC timeout.\n");
2186 swfw_sync |= swmask;
2187 BPCTL_WRITE_REG(pbpctl_dev, SW_FW_SYNC, swfw_sync);
2189 bp75_put_hw_semaphore_generic(pbpctl_dev);
2195 s32 bp75_read_phy_reg_mdic(struct bpctl_dev *pbpctl_dev, u32 offset, u16 *data)
2201 mdic = ((offset << BPCTLI_MDIC_REG_SHIFT) |
2202 (phy_addr << BPCTLI_MDIC_PHY_SHIFT) | (BPCTLI_MDIC_OP_READ));
2204 BPCTL_WRITE_REG(pbpctl_dev, MDIC, mdic);
2206 for (i = 0; i < (BPCTLI_GEN_POLL_TIMEOUT * 3); i++) {
2208 mdic = BPCTL_READ_REG(pbpctl_dev, MDIC);
2209 if (mdic & BPCTLI_MDIC_READY)
2212 if (!(mdic & BPCTLI_MDIC_READY)) {
2213 printk("bpctl_mod: MDI Read did not complete\n");
2217 if (mdic & BPCTLI_MDIC_ERROR) {
2218 printk("bpctl_mod: MDI Error\n");
2228 s32 bp75_write_phy_reg_mdic(struct bpctl_dev *pbpctl_dev, u32 offset, u16 data)
2234 mdic = (((u32) data) |
2235 (offset << BPCTLI_MDIC_REG_SHIFT) |
2236 (phy_addr << BPCTLI_MDIC_PHY_SHIFT) | (BPCTLI_MDIC_OP_WRITE));
2238 BPCTL_WRITE_REG(pbpctl_dev, MDIC, mdic);
2240 for (i = 0; i < (BPCTLI_GEN_POLL_TIMEOUT * 3); i++) {
2242 mdic = BPCTL_READ_REG(pbpctl_dev, MDIC);
2243 if (mdic & BPCTLI_MDIC_READY)
2246 if (!(mdic & BPCTLI_MDIC_READY)) {
2247 printk("bpctl_mod: MDI Write did not complete\n");
2251 if (mdic & BPCTLI_MDIC_ERROR) {
2252 printk("bpctl_mod: MDI Error\n");
2261 static s32 bp75_read_phy_reg(struct bpctl_dev *pbpctl_dev, u32 offset, u16 *data)
2265 ret_val = bp75_acquire_phy(pbpctl_dev);
2269 if (offset > BPCTLI_MAX_PHY_MULTI_PAGE_REG) {
2270 ret_val = bp75_write_phy_reg_mdic(pbpctl_dev,
2271 BPCTLI_IGP01E1000_PHY_PAGE_SELECT,
2278 bp75_read_phy_reg_mdic(pbpctl_dev,
2279 BPCTLI_MAX_PHY_REG_ADDRESS & offset, data);
2282 bp75_release_phy(pbpctl_dev);
2287 static s32 bp75_write_phy_reg(struct bpctl_dev *pbpctl_dev, u32 offset, u16 data)
2291 ret_val = bp75_acquire_phy(pbpctl_dev);
2295 if (offset > BPCTLI_MAX_PHY_MULTI_PAGE_REG) {
2296 ret_val = bp75_write_phy_reg_mdic(pbpctl_dev,
2297 BPCTLI_IGP01E1000_PHY_PAGE_SELECT,
2304 bp75_write_phy_reg_mdic(pbpctl_dev,
2305 BPCTLI_MAX_PHY_REG_ADDRESS & offset, data);
2308 bp75_release_phy(pbpctl_dev);
2314 /* SET_TX (non-Bypass command :)) */
2315 static int set_tx(struct bpctl_dev *pbpctl_dev, int tx_state)
2317 int ret = 0, ctrl = 0;
2318 struct bpctl_dev *pbpctl_dev_m;
2319 if ((is_bypass_fn(pbpctl_dev)) == 1)
2320 pbpctl_dev_m = pbpctl_dev;
2322 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
2323 if (pbpctl_dev_m == NULL)
2325 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
2326 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
2328 if (pbpctl_dev->bp_540) {
2329 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2330 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2331 (ctrl | BP10G_SDP1_DIR |
2335 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2336 (ctrl | BPCTLI_CTRL_SDP1_DIR
2337 | BPCTLI_CTRL_SWDPIN1));
2340 if (pbpctl_dev->bp_540) {
2341 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2342 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2343 ((ctrl | BP10G_SDP1_DIR) &
2346 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2348 BPCTLI_CTRL_SDP1_DIR) &
2349 ~BPCTLI_CTRL_SWDPIN1));
2354 } else if (pbpctl_dev->bp_caps & TX_CTL_CAP) {
2355 if (PEG5_IF_SERIES(pbpctl_dev->subdevice)) {
2360 bp75_read_phy_reg(pbpctl_dev,
2363 if (mii_reg & BPCTLI_MII_CR_POWER_DOWN) {
2369 ~BPCTLI_MII_CR_POWER_DOWN);
2376 bp75_read_phy_reg(pbpctl_dev,
2380 mii_reg |= BPCTLI_MII_CR_POWER_DOWN;
2382 bp75_write_phy_reg(pbpctl_dev,
2389 if (pbpctl_dev->bp_fiber5)
2390 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
2391 else if (pbpctl_dev->bp_10gb)
2392 ctrl = BP10GB_READ_REG(pbpctl_dev, MISC_REG_GPIO);
2393 else if (!pbpctl_dev->bp_10g)
2394 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
2396 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2399 if (pbpctl_dev->bp_10g9) {
2400 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2401 (ctrl | BP10G_SDP3_DATA |
2404 } else if (pbpctl_dev->bp_fiber5) {
2405 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
2407 BPCTLI_CTRL_EXT_SDP6_DIR |
2408 BPCTLI_CTRL_EXT_SDP6_DATA));
2410 } else if (pbpctl_dev->bp_10gb) {
2411 if ((pbpctl_dev->func == 1)
2412 || (pbpctl_dev->func == 3))
2413 BP10GB_WRITE_REG(pbpctl_dev,
2416 BP10GB_GPIO0_SET_P1) &
2417 ~(BP10GB_GPIO0_CLR_P1 |
2418 BP10GB_GPIO0_OE_P1));
2420 BP10GB_WRITE_REG(pbpctl_dev,
2423 BP10GB_GPIO0_OE_P0 |
2424 BP10GB_GPIO0_SET_P0));
2426 } else if (pbpctl_dev->bp_i80) {
2427 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2428 (ctrl | BPCTLI_CTRL_SDP1_DIR
2429 | BPCTLI_CTRL_SWDPIN1));
2431 } else if (pbpctl_dev->bp_540) {
2432 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2433 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2434 (ctrl | BP10G_SDP1_DIR |
2439 else if (!pbpctl_dev->bp_10g)
2440 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2441 (ctrl | BPCTLI_CTRL_SWDPIO0 |
2442 BPCTLI_CTRL_SWDPIN0));
2445 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2446 (ctrl | BP10G_SDP0_DATA |
2450 if (pbpctl_dev->bp_10g9) {
2451 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2452 ((ctrl | BP10G_SDP3_DIR) &
2455 } else if (pbpctl_dev->bp_fiber5) {
2456 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
2458 BPCTLI_CTRL_EXT_SDP6_DIR) &
2459 ~BPCTLI_CTRL_EXT_SDP6_DATA));
2461 } else if (pbpctl_dev->bp_10gb) {
2462 if ((bpctl_dev_arr->func == 1)
2463 || (bpctl_dev_arr->func == 3))
2464 BP10GB_WRITE_REG(pbpctl_dev,
2467 BP10GB_GPIO0_CLR_P1) &
2468 ~(BP10GB_GPIO0_SET_P1 |
2469 BP10GB_GPIO0_OE_P1));
2471 BP10GB_WRITE_REG(pbpctl_dev,
2474 BP10GB_GPIO0_OE_P0 |
2475 BP10GB_GPIO0_CLR_P0));
2477 } else if (pbpctl_dev->bp_i80) {
2478 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2480 BPCTLI_CTRL_SDP1_DIR) &
2481 ~BPCTLI_CTRL_SWDPIN1));
2482 } else if (pbpctl_dev->bp_540) {
2483 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2484 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2485 ((ctrl | BP10G_SDP1_DIR) &
2489 else if (!pbpctl_dev->bp_10g) {
2490 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2491 ((ctrl | BPCTLI_CTRL_SWDPIO0)
2492 & ~BPCTLI_CTRL_SWDPIN0));
2493 if (!PEGF_IF_SERIES(pbpctl_dev->subdevice)) {
2494 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2497 (BPCTLI_CTRL_SDP0_DATA
2499 BPCTLI_CTRL_SDP0_DIR)));
2502 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2503 ((ctrl | BP10G_SDP0_DIR) &
2514 /* SET_FORCE_LINK (non-Bypass command :)) */
2515 static int set_bp_force_link(struct bpctl_dev *pbpctl_dev, int tx_state)
2517 int ret = 0, ctrl = 0;
2519 if (DBI_IF_SERIES(pbpctl_dev->subdevice)) {
2521 if ((pbpctl_dev->bp_10g) || (pbpctl_dev->bp_10g9)) {
2523 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
2525 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2526 ctrl & ~BP10G_SDP1_DIR);
2528 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2529 ((ctrl | BP10G_SDP1_DIR) &
2538 /*RESET_CONT 0x20 */
2539 int reset_cont(struct bpctl_dev *pbpctl_dev)
2541 int ret = BP_NOT_CAP;
2543 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
2544 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
2546 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
2547 write_data(pbpctl_dev, RESET_CONT);
2549 data_pulse(pbpctl_dev, RESET_CONT);
2555 /*DIS_BYPASS_CAP 0x22 */
2556 int dis_bypass_cap(struct bpctl_dev *pbpctl_dev)
2559 if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
2560 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2561 write_data_int(pbpctl_dev, DIS_BYPASS_CAP_INT);
2562 msec_delay_bp(BYPASS_DELAY_INT);
2564 write_data(pbpctl_dev, BYPASS_OFF);
2565 msec_delay_bp(LATCH_DELAY);
2566 write_data(pbpctl_dev, DIS_BYPASS_CAP);
2567 msec_delay_bp(BYPASS_CAP_DELAY);
2574 /*EN_BYPASS_CAP 0x24 */
2575 int en_bypass_cap(struct bpctl_dev *pbpctl_dev)
2577 if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
2578 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2579 write_data_int(pbpctl_dev, PWROFF_BYPASS_ON_INT);
2580 msec_delay_bp(BYPASS_DELAY_INT);
2582 write_data(pbpctl_dev, EN_BYPASS_CAP);
2583 msec_delay_bp(BYPASS_CAP_DELAY);
2590 /* BYPASS_STATE_PWRON 0x26*/
2591 int bypass_state_pwron(struct bpctl_dev *pbpctl_dev)
2593 if (pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP) {
2594 write_data(pbpctl_dev, BYPASS_STATE_PWRON);
2595 if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
2596 msec_delay_bp(DFLT_PWRON_DELAY);
2598 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2604 /* NORMAL_STATE_PWRON 0x28*/
2605 int normal_state_pwron(struct bpctl_dev *pbpctl_dev)
2607 if ((pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP)
2608 || (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP)) {
2609 write_data(pbpctl_dev, NORMAL_STATE_PWRON);
2610 if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
2611 msec_delay_bp(DFLT_PWRON_DELAY);
2613 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2619 /* BYPASS_STATE_PWROFF 0x27*/
2620 int bypass_state_pwroff(struct bpctl_dev *pbpctl_dev)
2622 if (pbpctl_dev->bp_caps & BP_PWOFF_CTL_CAP) {
2623 write_data(pbpctl_dev, BYPASS_STATE_PWROFF);
2624 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2630 /* NORMAL_STATE_PWROFF 0x29*/
2631 int normal_state_pwroff(struct bpctl_dev *pbpctl_dev)
2633 if ((pbpctl_dev->bp_caps & BP_PWOFF_CTL_CAP)) {
2634 write_data(pbpctl_dev, NORMAL_STATE_PWROFF);
2635 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2641 /*TAP_STATE_PWRON 0x2a*/
2642 int tap_state_pwron(struct bpctl_dev *pbpctl_dev)
2644 if (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP) {
2645 write_data(pbpctl_dev, TAP_STATE_PWRON);
2646 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2652 /*DIS_TAP_CAP 0x2c*/
2653 int dis_tap_cap(struct bpctl_dev *pbpctl_dev)
2655 if (pbpctl_dev->bp_caps & TAP_DIS_CAP) {
2656 write_data(pbpctl_dev, DIS_TAP_CAP);
2657 msec_delay_bp(BYPASS_CAP_DELAY);
2664 int en_tap_cap(struct bpctl_dev *pbpctl_dev)
2666 if (pbpctl_dev->bp_caps & TAP_DIS_CAP) {
2667 write_data(pbpctl_dev, EN_TAP_CAP);
2668 msec_delay_bp(BYPASS_CAP_DELAY);
2674 /*DISC_STATE_PWRON 0x2a*/
2675 int disc_state_pwron(struct bpctl_dev *pbpctl_dev)
2677 if (pbpctl_dev->bp_caps & DISC_PWUP_CTL_CAP) {
2678 if (pbpctl_dev->bp_ext_ver >= 0x8) {
2679 write_data(pbpctl_dev, DISC_STATE_PWRON);
2680 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2687 /*DIS_DISC_CAP 0x2c*/
2688 int dis_disc_cap(struct bpctl_dev *pbpctl_dev)
2690 if (pbpctl_dev->bp_caps & DISC_DIS_CAP) {
2691 if (pbpctl_dev->bp_ext_ver >= 0x8) {
2692 write_data(pbpctl_dev, DIS_DISC_CAP);
2693 msec_delay_bp(BYPASS_CAP_DELAY);
2700 /*DISC_STATE_PWRON 0x2a*/
2701 int disc_port_state_pwron(struct bpctl_dev *pbpctl_dev)
2704 struct bpctl_dev *pbpctl_dev_m;
2708 if ((is_bypass_fn(pbpctl_dev)) == 1)
2709 pbpctl_dev_m = pbpctl_dev;
2711 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
2712 if (pbpctl_dev_m == NULL)
2715 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
2716 if (is_bypass_fn(pbpctl_dev) == 1)
2717 write_data(pbpctl_dev_m, TX_DISA_PWRUP);
2719 write_data(pbpctl_dev_m, TX_DISB_PWRUP);
2721 msec_delay_bp(LATCH_DELAY);
2727 int normal_port_state_pwron(struct bpctl_dev *pbpctl_dev)
2730 struct bpctl_dev *pbpctl_dev_m;
2733 if ((is_bypass_fn(pbpctl_dev)) == 1)
2734 pbpctl_dev_m = pbpctl_dev;
2736 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
2737 if (pbpctl_dev_m == NULL)
2740 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
2741 if (is_bypass_fn(pbpctl_dev) == 1)
2742 write_data(pbpctl_dev_m, TX_ENA_PWRUP);
2744 write_data(pbpctl_dev_m, TX_ENB_PWRUP);
2746 msec_delay_bp(LATCH_DELAY);
2753 int en_disc_cap(struct bpctl_dev *pbpctl_dev)
2755 if (pbpctl_dev->bp_caps & DISC_DIS_CAP) {
2756 if (pbpctl_dev->bp_ext_ver >= 0x8) {
2757 write_data(pbpctl_dev, EN_DISC_CAP);
2758 msec_delay_bp(BYPASS_CAP_DELAY);
2765 int std_nic_on(struct bpctl_dev *pbpctl_dev)
2768 if (pbpctl_dev->bp_caps & STD_NIC_CAP) {
2770 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2771 write_data_int(pbpctl_dev, DIS_BYPASS_CAP_INT);
2772 msec_delay_bp(BYPASS_DELAY_INT);
2773 pbpctl_dev->bp_status_un = 0;
2777 if (pbpctl_dev->bp_ext_ver >= 0x8) {
2778 write_data(pbpctl_dev, STD_NIC_ON);
2779 msec_delay_bp(BYPASS_CAP_DELAY);
2784 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
2785 wdt_off(pbpctl_dev);
2787 if (pbpctl_dev->bp_caps & BP_CAP) {
2788 write_data(pbpctl_dev, BYPASS_OFF);
2789 msec_delay_bp(LATCH_DELAY);
2792 if (pbpctl_dev->bp_caps & TAP_CAP) {
2793 write_data(pbpctl_dev, TAP_OFF);
2794 msec_delay_bp(LATCH_DELAY);
2797 write_data(pbpctl_dev, NORMAL_STATE_PWRON);
2798 if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
2799 msec_delay_bp(DFLT_PWRON_DELAY);
2801 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2803 if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
2804 write_data(pbpctl_dev, DIS_BYPASS_CAP);
2805 msec_delay_bp(BYPASS_CAP_DELAY);
2808 if (pbpctl_dev->bp_caps & TAP_DIS_CAP) {
2809 write_data(pbpctl_dev, DIS_TAP_CAP);
2810 msec_delay_bp(BYPASS_CAP_DELAY);
2819 int std_nic_off(struct bpctl_dev *pbpctl_dev)
2822 if (pbpctl_dev->bp_caps & STD_NIC_CAP) {
2823 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2824 write_data_int(pbpctl_dev, PWROFF_BYPASS_ON_INT);
2825 msec_delay_bp(BYPASS_DELAY_INT);
2828 if (pbpctl_dev->bp_ext_ver >= 0x8) {
2829 write_data(pbpctl_dev, STD_NIC_OFF);
2830 msec_delay_bp(BYPASS_CAP_DELAY);
2835 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
2837 if (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP) {
2838 write_data(pbpctl_dev, TAP_STATE_PWRON);
2839 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2842 if (pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP) {
2843 write_data(pbpctl_dev, BYPASS_STATE_PWRON);
2844 if (pbpctl_dev->bp_ext_ver > PXG2BPI_VER)
2845 msec_delay_bp(LATCH_DELAY +
2848 msec_delay_bp(DFLT_PWRON_DELAY);
2851 if (pbpctl_dev->bp_caps & TAP_DIS_CAP) {
2852 write_data(pbpctl_dev, EN_TAP_CAP);
2853 msec_delay_bp(BYPASS_CAP_DELAY);
2855 if (pbpctl_dev->bp_caps & DISC_DIS_CAP) {
2856 write_data(pbpctl_dev, EN_DISC_CAP);
2857 msec_delay_bp(BYPASS_CAP_DELAY);
2860 if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
2861 write_data(pbpctl_dev, EN_BYPASS_CAP);
2862 msec_delay_bp(BYPASS_CAP_DELAY);
2871 int wdt_time_left(struct bpctl_dev *pbpctl_dev)
2874 /* unsigned long curr_time=((long long)(jiffies*1000))/HZ, delta_time=0,wdt_on_time=((long long)(pbpctl_dev->bypass_wdt_on_time*1000))/HZ; */
2875 unsigned long curr_time = jiffies, delta_time = 0, wdt_on_time =
2876 pbpctl_dev->bypass_wdt_on_time, delta_time_msec = 0;
2879 switch (pbpctl_dev->wdt_status) {
2880 case WDT_STATUS_DIS:
2886 wdt_on_time) ? (curr_time - wdt_on_time) : (~wdt_on_time +
2888 delta_time_msec = jiffies_to_msecs(delta_time);
2889 time_left = pbpctl_dev->bypass_timer_interval - delta_time_msec;
2890 if (time_left < 0) {
2892 pbpctl_dev->wdt_status = WDT_STATUS_EXP;
2895 case WDT_STATUS_EXP:
2903 static int wdt_timer(struct bpctl_dev *pbpctl_dev, int *time_left)
2906 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
2908 if (pbpctl_dev->wdt_status == WDT_STATUS_UNKNOWN)
2911 *time_left = wdt_time_left(pbpctl_dev);
2919 static int wdt_timer_reload(struct bpctl_dev *pbpctl_dev)
2924 if ((pbpctl_dev->bp_caps & WD_CTL_CAP) &&
2925 (pbpctl_dev->wdt_status != WDT_STATUS_UNKNOWN)) {
2926 if (pbpctl_dev->wdt_status == WDT_STATUS_DIS)
2928 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
2929 ret = wdt_pulse(pbpctl_dev);
2930 else if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
2931 ret = wdt_pulse_int(pbpctl_dev);
2933 ret = send_wdt_pulse(pbpctl_dev);
2935 mod_timer(&pbpctl_dev->bp_timer, jiffies+1);*/
2941 static void wd_reset_timer(unsigned long param)
2943 struct bpctl_dev *pbpctl_dev = (struct bpctl_dev *) param;
2945 struct sk_buff *skb_tmp;
2948 if ((pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) &&
2949 ((atomic_read(&pbpctl_dev->wdt_busy)) == 1)) {
2950 mod_timer(&pbpctl_dev->bp_timer, jiffies + 1);
2955 if (pbpctl_dev->bp_self_test_flag == 1) {
2956 skb_tmp = dev_alloc_skb(BPTEST_DATA_LEN + 2);
2957 if ((skb_tmp) && (pbpctl_dev->ndev) && (pbpctl_dev->bp_tx_data)) {
2958 memcpy(skb_put(skb_tmp, BPTEST_DATA_LEN),
2959 pbpctl_dev->bp_tx_data, BPTEST_DATA_LEN);
2960 skb_tmp->dev = pbpctl_dev->ndev;
2962 eth_type_trans(skb_tmp, pbpctl_dev->ndev);
2963 skb_tmp->ip_summed = CHECKSUM_UNNECESSARY;
2964 netif_receive_skb(skb_tmp);
2965 goto bp_timer_reload;
2971 wdt_timer_reload(pbpctl_dev);
2975 if (pbpctl_dev->reset_time) {
2976 mod_timer(&pbpctl_dev->bp_timer,
2977 jiffies + (HZ * pbpctl_dev->reset_time) / 1000);
2981 /*WAIT_AT_PWRUP 0x80 */
2982 int bp_wait_at_pwup_en(struct bpctl_dev *pbpctl_dev)
2985 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
2986 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
2987 write_data(pbpctl_dev, BP_WAIT_AT_PWUP_EN);
2988 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2996 /*DIS_WAIT_AT_PWRUP 0x81 */
2997 int bp_wait_at_pwup_dis(struct bpctl_dev *pbpctl_dev)
3000 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3002 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
3003 write_data(pbpctl_dev, BP_WAIT_AT_PWUP_DIS);
3004 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
3012 /*EN_HW_RESET 0x82 */
3014 int bp_hw_reset_en(struct bpctl_dev *pbpctl_dev)
3017 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3018 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
3019 write_data(pbpctl_dev, BP_HW_RESET_EN);
3020 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
3028 /*DIS_HW_RESET 0x83 */
3030 int bp_hw_reset_dis(struct bpctl_dev *pbpctl_dev)
3033 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3034 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
3035 write_data(pbpctl_dev, BP_HW_RESET_DIS);
3036 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
3045 int wdt_exp_mode(struct bpctl_dev *pbpctl_dev, int mode)
3047 uint32_t status_reg = 0, status_reg1 = 0;
3049 if ((pbpctl_dev->bp_caps & (TAP_STATUS_CAP | DISC_CAP)) &&
3050 (pbpctl_dev->bp_caps & BP_CAP)) {
3051 if (pbpctl_dev->bp_ext_ver >= PXE2TBPI_VER) {
3053 if ((pbpctl_dev->bp_ext_ver >= 0x8) &&
3054 (mode == 2) && (pbpctl_dev->bp_caps & DISC_CAP)) {
3056 read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR);
3057 if (!(status_reg1 & WDTE_DISC_BPN_MASK))
3058 write_reg(pbpctl_dev,
3061 STATUS_DISC_REG_ADDR);
3065 status_reg = read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR);
3067 if ((mode == 0) && (pbpctl_dev->bp_caps & BP_CAP)) {
3068 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3070 read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR);
3071 if (status_reg1 & WDTE_DISC_BPN_MASK)
3072 write_reg(pbpctl_dev,
3074 ~WDTE_DISC_BPN_MASK,
3075 STATUS_DISC_REG_ADDR);
3077 if (status_reg & WDTE_TAP_BPN_MASK)
3078 write_reg(pbpctl_dev,
3079 status_reg & ~WDTE_TAP_BPN_MASK,
3080 STATUS_TAP_REG_ADDR);
3083 } else if ((mode == 1) && (pbpctl_dev->bp_caps & TAP_CAP)) {
3084 if (!(status_reg & WDTE_TAP_BPN_MASK))
3085 write_reg(pbpctl_dev,
3086 status_reg | WDTE_TAP_BPN_MASK,
3087 STATUS_TAP_REG_ADDR);
3088 /*else return BP_NOT_CAP; */
3096 int bypass_fw_ver(struct bpctl_dev *pbpctl_dev)
3098 if (is_bypass_fn(pbpctl_dev))
3099 return read_reg(pbpctl_dev, VER_REG_ADDR);
3104 int bypass_sign_check(struct bpctl_dev *pbpctl_dev)
3107 if (is_bypass_fn(pbpctl_dev))
3108 return (((read_reg(pbpctl_dev, PIC_SIGN_REG_ADDR)) ==
3109 PIC_SIGN_VALUE) ? 1 : 0);
3114 static int tx_status(struct bpctl_dev *pbpctl_dev)
3117 struct bpctl_dev *pbpctl_dev_m;
3118 if ((is_bypass_fn(pbpctl_dev)) == 1)
3119 pbpctl_dev_m = pbpctl_dev;
3121 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
3122 if (pbpctl_dev_m == NULL)
3124 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
3126 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
3127 if (pbpctl_dev->bp_i80)
3128 return ((ctrl & BPCTLI_CTRL_SWDPIN1) != 0 ? 0 : 1);
3129 if (pbpctl_dev->bp_540) {
3130 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
3132 return ((ctrl & BP10G_SDP1_DATA) != 0 ? 0 : 1);
3137 if (pbpctl_dev->bp_caps & TX_CTL_CAP) {
3138 if (PEG5_IF_SERIES(pbpctl_dev->subdevice)) {
3142 (pbpctl_dev, BPCTLI_PHY_CONTROL, &mii_reg))) {
3143 if (mii_reg & BPCTLI_MII_CR_POWER_DOWN)
3152 if (pbpctl_dev->bp_10g9) {
3153 return ((BP10G_READ_REG(pbpctl_dev, ESDP) &
3154 BP10G_SDP3_DATA) != 0 ? 0 : 1);
3156 } else if (pbpctl_dev->bp_fiber5) {
3157 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
3158 if (ctrl & BPCTLI_CTRL_EXT_SDP6_DATA)
3161 } else if (pbpctl_dev->bp_10gb) {
3162 ctrl = BP10GB_READ_REG(pbpctl_dev, MISC_REG_GPIO);
3163 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_GPIO,
3164 (ctrl | BP10GB_GPIO0_OE_P1) &
3165 ~(BP10GB_GPIO0_SET_P1 |
3166 BP10GB_GPIO0_CLR_P1));
3168 if ((pbpctl_dev->func == 1) || (pbpctl_dev->func == 3))
3169 return (((BP10GB_READ_REG
3171 MISC_REG_GPIO)) & BP10GB_GPIO0_P1) !=
3174 return (((BP10GB_READ_REG
3176 MISC_REG_GPIO)) & BP10GB_GPIO0_P0) !=
3180 if (!pbpctl_dev->bp_10g) {
3182 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
3183 if (pbpctl_dev->bp_i80)
3184 return ((ctrl & BPCTLI_CTRL_SWDPIN1) !=
3186 if (pbpctl_dev->bp_540) {
3187 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
3189 return ((ctrl & BP10G_SDP1_DATA) != 0 ? 0 : 1);
3192 return ((ctrl & BPCTLI_CTRL_SWDPIN0) != 0 ? 0 : 1);
3194 return ((BP10G_READ_REG(pbpctl_dev, ESDP) &
3195 BP10G_SDP0_DATA) != 0 ? 0 : 1);
3201 static int bp_force_link_status(struct bpctl_dev *pbpctl_dev)
3204 if (DBI_IF_SERIES(pbpctl_dev->subdevice)) {
3206 if ((pbpctl_dev->bp_10g) || (pbpctl_dev->bp_10g9)) {
3207 return ((BP10G_READ_REG(pbpctl_dev, ESDP) &
3208 BP10G_SDP1_DIR) != 0 ? 1 : 0);
3215 int bypass_from_last_read(struct bpctl_dev *pbpctl_dev)
3217 uint32_t ctrl_ext = 0;
3218 struct bpctl_dev *pbpctl_dev_b = NULL;
3220 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3221 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
3224 ctrl_ext = BPCTL_READ_REG(pbpctl_dev_b, CTRL_EXT);
3225 BPCTL_BP_WRITE_REG(pbpctl_dev_b, CTRL_EXT,
3226 (ctrl_ext & ~BPCTLI_CTRL_EXT_SDP7_DIR));
3227 ctrl_ext = BPCTL_READ_REG(pbpctl_dev_b, CTRL_EXT);
3228 if (ctrl_ext & BPCTLI_CTRL_EXT_SDP7_DATA)
3235 int bypass_status_clear(struct bpctl_dev *pbpctl_dev)
3237 struct bpctl_dev *pbpctl_dev_b = NULL;
3239 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3240 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
3243 send_bypass_clear_pulse(pbpctl_dev_b, 1);
3249 int bypass_flag_status(struct bpctl_dev *pbpctl_dev)
3252 if ((pbpctl_dev->bp_caps & BP_CAP)) {
3253 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3254 return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3255 BYPASS_FLAG_MASK) ==
3256 BYPASS_FLAG_MASK) ? 1 : 0);
3262 int bypass_flag_status_clear(struct bpctl_dev *pbpctl_dev)
3265 if (pbpctl_dev->bp_caps & BP_CAP) {
3266 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3267 uint32_t status_reg = 0;
3268 status_reg = read_reg(pbpctl_dev, STATUS_REG_ADDR);
3269 write_reg(pbpctl_dev, status_reg & ~BYPASS_FLAG_MASK,
3277 int bypass_change_status(struct bpctl_dev *pbpctl_dev)
3279 int ret = BP_NOT_CAP;
3281 if (pbpctl_dev->bp_caps & BP_STATUS_CHANGE_CAP) {
3282 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3283 ret = bypass_flag_status(pbpctl_dev);
3284 bypass_flag_status_clear(pbpctl_dev);
3285 } else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3286 ret = bypass_flag_status(pbpctl_dev);
3287 bypass_flag_status_clear(pbpctl_dev);
3289 ret = bypass_from_last_read(pbpctl_dev);
3290 bypass_status_clear(pbpctl_dev);
3296 int bypass_off_status(struct bpctl_dev *pbpctl_dev)
3299 if (pbpctl_dev->bp_caps & BP_CAP) {
3300 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3301 return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3302 BYPASS_OFF_MASK) == BYPASS_OFF_MASK) ? 1 : 0);
3308 static int bypass_status(struct bpctl_dev *pbpctl_dev)
3311 if (pbpctl_dev->bp_caps & BP_CAP) {
3313 struct bpctl_dev *pbpctl_dev_b = NULL;
3315 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
3319 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
3321 if (!pbpctl_dev->bp_status_un)
3322 return (((BPCTL_READ_REG
3325 BPCTLI_CTRL_EXT_SDP7_DATA) !=
3330 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3332 if (pbpctl_dev->bp_10g9) {
3333 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, I2CCTL);
3334 BP10G_WRITE_REG(pbpctl_dev_b, I2CCTL,
3335 (ctrl_ext | BP10G_I2C_CLK_OUT));
3336 return ((BP10G_READ_REG(pbpctl_dev_b, I2CCTL) &
3337 BP10G_I2C_CLK_IN) != 0 ? 0 : 1);
3339 } else if (pbpctl_dev->bp_540) {
3340 return (((BP10G_READ_REG(pbpctl_dev_b, ESDP)) &
3341 BP10G_SDP0_DATA) != 0 ? 0 : 1);
3344 else if ((pbpctl_dev->bp_fiber5)
3345 || (pbpctl_dev->bp_i80)) {
3346 return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL)) &
3347 BPCTLI_CTRL_SWDPIN0) != 0 ? 0 : 1);
3348 } else if (pbpctl_dev->bp_10gb) {
3350 BP10GB_READ_REG(pbpctl_dev, MISC_REG_GPIO);
3351 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_GPIO,
3352 (ctrl_ext | BP10GB_GPIO3_OE_P0)
3353 & ~(BP10GB_GPIO3_SET_P0 |
3354 BP10GB_GPIO3_CLR_P0));
3356 return (((BP10GB_READ_REG
3358 MISC_REG_GPIO)) & BP10GB_GPIO3_P0) !=
3362 else if (!pbpctl_dev->bp_10g)
3363 return (((BPCTL_READ_REG
3366 BPCTLI_CTRL_EXT_SDP7_DATA) !=
3370 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, EODSDP);
3371 BP10G_WRITE_REG(pbpctl_dev_b, EODSDP,
3373 BP10G_SDP7_DATA_OUT));
3374 return ((BP10G_READ_REG(pbpctl_dev_b, EODSDP) &
3375 BP10G_SDP7_DATA_IN) != 0 ? 0 : 1);
3378 } else if (pbpctl_dev->media_type == BP_COPPER) {
3380 return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL)) &
3381 BPCTLI_CTRL_SWDPIN1) != 0 ? 1 : 0);
3383 if ((bypass_status_clear(pbpctl_dev)) >= 0)
3384 return bypass_from_last_read(pbpctl_dev);
3391 int default_pwron_status(struct bpctl_dev *pbpctl_dev)
3394 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3395 if (pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP) {
3396 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3399 STATUS_REG_ADDR)) & DFLT_PWRON_MASK)
3400 == DFLT_PWRON_MASK) ? 0 : 1);
3402 } /*else if ((!pbpctl_dev->bp_caps&BP_DIS_CAP)&&
3403 (pbpctl_dev->bp_caps&BP_PWUP_ON_CAP))
3409 static int default_pwroff_status(struct bpctl_dev *pbpctl_dev)
3412 /*if ((!pbpctl_dev->bp_caps&BP_DIS_CAP)&&
3413 (pbpctl_dev->bp_caps&BP_PWOFF_ON_CAP))
3415 if ((pbpctl_dev->bp_caps & SW_CTL_CAP)
3416 && (pbpctl_dev->bp_caps & BP_PWOFF_CTL_CAP)) {
3417 return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3418 DFLT_PWROFF_MASK) == DFLT_PWROFF_MASK) ? 0 : 1);
3423 int dis_bypass_cap_status(struct bpctl_dev *pbpctl_dev)
3426 if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
3427 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3428 return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3429 DIS_BYPASS_CAP_MASK) ==
3430 DIS_BYPASS_CAP_MASK) ? 1 : 0);
3436 int cmd_en_status(struct bpctl_dev *pbpctl_dev)
3439 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3440 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3441 return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3442 CMND_EN_MASK) == CMND_EN_MASK) ? 1 : 0);
3448 int wdt_en_status(struct bpctl_dev *pbpctl_dev)
3451 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
3452 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3453 return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3454 WDT_EN_MASK) == WDT_EN_MASK) ? 1 : 0);
3460 int wdt_programmed(struct bpctl_dev *pbpctl_dev, int *timeout)
3463 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
3464 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3465 if ((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3468 wdt_val = read_reg(pbpctl_dev, WDT_REG_ADDR);
3469 *timeout = (1 << wdt_val) * 100;
3473 int curr_wdt_status = pbpctl_dev->wdt_status;
3474 if (curr_wdt_status == WDT_STATUS_UNKNOWN)
3479 0 ? 0 : pbpctl_dev->bypass_timer_interval;
3486 int bypass_support(struct bpctl_dev *pbpctl_dev)
3490 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3491 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3493 ((((read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR)) &
3494 BYPASS_SUPPORT_MASK) ==
3495 BYPASS_SUPPORT_MASK) ? 1 : 0);
3496 } else if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
3503 int tap_support(struct bpctl_dev *pbpctl_dev)
3507 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3508 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3510 ((((read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR)) &
3511 TAP_SUPPORT_MASK) == TAP_SUPPORT_MASK) ? 1 : 0);
3512 } else if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
3519 int normal_support(struct bpctl_dev *pbpctl_dev)
3521 int ret = BP_NOT_CAP;
3523 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3524 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3526 ((((read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR)) &
3527 NORMAL_UNSUPPORT_MASK) ==
3528 NORMAL_UNSUPPORT_MASK) ? 0 : 1);
3535 int get_bp_prod_caps(struct bpctl_dev *pbpctl_dev)
3537 if ((pbpctl_dev->bp_caps & SW_CTL_CAP) &&
3538 (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER))
3539 return read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR);
3544 int tap_flag_status(struct bpctl_dev *pbpctl_dev)
3547 if (pbpctl_dev->bp_caps & TAP_STATUS_CAP) {
3548 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
3549 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3550 TAP_FLAG_MASK) == TAP_FLAG_MASK) ? 1 : 0);
3556 int tap_flag_status_clear(struct bpctl_dev *pbpctl_dev)
3558 uint32_t status_reg = 0;
3559 if (pbpctl_dev->bp_caps & TAP_STATUS_CAP) {
3560 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3561 status_reg = read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR);
3562 write_reg(pbpctl_dev, status_reg & ~TAP_FLAG_MASK,
3563 STATUS_TAP_REG_ADDR);
3570 int tap_change_status(struct bpctl_dev *pbpctl_dev)
3572 int ret = BP_NOT_CAP;
3573 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3574 if (pbpctl_dev->bp_caps & TAP_CAP) {
3575 if (pbpctl_dev->bp_caps & BP_CAP) {
3576 ret = tap_flag_status(pbpctl_dev);
3577 tap_flag_status_clear(pbpctl_dev);
3579 ret = bypass_from_last_read(pbpctl_dev);
3580 bypass_status_clear(pbpctl_dev);
3587 int tap_off_status(struct bpctl_dev *pbpctl_dev)
3589 if (pbpctl_dev->bp_caps & TAP_CAP) {
3590 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
3591 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3592 TAP_OFF_MASK) == TAP_OFF_MASK) ? 1 : 0);
3597 int tap_status(struct bpctl_dev *pbpctl_dev)
3601 if (pbpctl_dev->bp_caps & TAP_CAP) {
3602 struct bpctl_dev *pbpctl_dev_b = NULL;
3604 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
3608 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3609 if (!pbpctl_dev->bp_10g)
3610 return (((BPCTL_READ_REG
3613 BPCTLI_CTRL_EXT_SDP6_DATA) !=
3616 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, EODSDP);
3617 BP10G_WRITE_REG(pbpctl_dev_b, EODSDP,
3619 BP10G_SDP6_DATA_OUT));
3620 return ((BP10G_READ_REG(pbpctl_dev_b, EODSDP) &
3621 BP10G_SDP6_DATA_IN) != 0 ? 0 : 1);
3624 } else if (pbpctl_dev->media_type == BP_COPPER)
3625 return (((BPCTL_READ_REG(pbpctl_dev, CTRL)) &
3626 BPCTLI_CTRL_SWDPIN0) != 0 ? 1 : 0);
3628 if ((bypass_status_clear(pbpctl_dev)) >= 0)
3629 return bypass_from_last_read(pbpctl_dev);
3636 int default_pwron_tap_status(struct bpctl_dev *pbpctl_dev)
3638 if (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP) {
3639 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
3640 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3641 DFLT_PWRON_TAP_MASK) ==
3642 DFLT_PWRON_TAP_MASK) ? 1 : 0);
3647 int dis_tap_cap_status(struct bpctl_dev *pbpctl_dev)
3649 if (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP) {
3650 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
3651 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3652 DIS_TAP_CAP_MASK) ==
3653 DIS_TAP_CAP_MASK) ? 1 : 0);
3658 int disc_flag_status(struct bpctl_dev *pbpctl_dev)
3661 if (pbpctl_dev->bp_caps & DISC_CAP) {
3662 if (pbpctl_dev->bp_ext_ver >= 0x8)
3663 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3664 DISC_FLAG_MASK) == DISC_FLAG_MASK) ? 1 : 0);
3670 int disc_flag_status_clear(struct bpctl_dev *pbpctl_dev)
3672 uint32_t status_reg = 0;
3673 if (pbpctl_dev->bp_caps & DISC_CAP) {
3674 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3675 status_reg = read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR);
3676 write_reg(pbpctl_dev, status_reg & ~DISC_FLAG_MASK,
3677 STATUS_DISC_REG_ADDR);
3684 int disc_change_status(struct bpctl_dev *pbpctl_dev)
3686 int ret = BP_NOT_CAP;
3687 if (pbpctl_dev->bp_caps & DISC_CAP) {
3688 ret = disc_flag_status(pbpctl_dev);
3689 disc_flag_status_clear(pbpctl_dev);
3695 int disc_off_status(struct bpctl_dev *pbpctl_dev)
3697 struct bpctl_dev *pbpctl_dev_b = NULL;
3700 if (pbpctl_dev->bp_caps & DISC_CAP) {
3701 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
3704 if (DISCF_IF_SERIES(pbpctl_dev->subdevice))
3705 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3706 DISC_OFF_MASK) == DISC_OFF_MASK) ? 1 : 0);
3708 if (pbpctl_dev->bp_i80) {
3709 return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL_EXT)) &
3710 BPCTLI_CTRL_EXT_SDP6_DATA) != 0 ? 1 : 0);
3713 if (pbpctl_dev->bp_540) {
3714 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, ESDP);
3715 return ((BP10G_READ_REG(pbpctl_dev_b, ESDP) &
3716 BP10G_SDP2_DATA) != 0 ? 1 : 0);
3719 if (pbpctl_dev->media_type == BP_COPPER) {
3722 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3723 DISC_OFF_MASK) == DISC_OFF_MASK) ? 1 : 0);
3725 if (!pbpctl_dev->bp_10g)
3726 return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL)) &
3727 BPCTLI_CTRL_SWDPIN1) != 0 ? 1 : 0);
3729 return ((BP10G_READ_REG(pbpctl_dev_b, ESDP) &
3730 BP10G_SDP1_DATA) != 0 ? 1 : 0);
3734 if (pbpctl_dev->bp_10g9) {
3735 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, I2CCTL);
3736 BP10G_WRITE_REG(pbpctl_dev_b, I2CCTL,
3738 BP10G_I2C_DATA_OUT));
3739 return ((BP10G_READ_REG(pbpctl_dev_b, I2CCTL) &
3740 BP10G_I2C_DATA_IN) != 0 ? 1 : 0);
3742 } else if (pbpctl_dev->bp_fiber5) {
3743 return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL)) &
3744 BPCTLI_CTRL_SWDPIN1) != 0 ? 1 : 0);
3745 } else if (pbpctl_dev->bp_10gb) {
3747 BP10GB_READ_REG(pbpctl_dev, MISC_REG_GPIO);
3748 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_GPIO,
3749 (ctrl_ext | BP10GB_GPIO3_OE_P1)
3750 & ~(BP10GB_GPIO3_SET_P1 |
3751 BP10GB_GPIO3_CLR_P1));
3753 return (((BP10GB_READ_REG
3755 MISC_REG_GPIO)) & BP10GB_GPIO3_P1) !=
3758 if (!pbpctl_dev->bp_10g) {
3760 return (((BPCTL_READ_REG
3763 BPCTLI_CTRL_EXT_SDP6_DATA) !=
3766 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, EODSDP);
3767 BP10G_WRITE_REG(pbpctl_dev_b, EODSDP,
3769 BP10G_SDP6_DATA_OUT));
3770 return (((BP10G_READ_REG(pbpctl_dev_b, EODSDP))
3771 & BP10G_SDP6_DATA_IN) != 0 ? 1 : 0);
3779 static int disc_status(struct bpctl_dev *pbpctl_dev)
3782 if (pbpctl_dev->bp_caps & DISC_CAP) {
3783 ctrl = disc_off_status(pbpctl_dev);
3786 return ((ctrl == 0) ? 1 : 0);
3791 int default_pwron_disc_status(struct bpctl_dev *pbpctl_dev)
3793 if (pbpctl_dev->bp_caps & DISC_PWUP_CTL_CAP) {
3794 if (pbpctl_dev->bp_ext_ver >= 0x8)
3795 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3796 DFLT_PWRON_DISC_MASK) ==
3797 DFLT_PWRON_DISC_MASK) ? 1 : 0);
3802 int dis_disc_cap_status(struct bpctl_dev *pbpctl_dev)
3804 if (pbpctl_dev->bp_caps & DIS_DISC_CAP) {
3805 if (pbpctl_dev->bp_ext_ver >= 0x8)
3806 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3807 DIS_DISC_CAP_MASK) ==
3808 DIS_DISC_CAP_MASK) ? 1 : 0);
3813 int disc_port_status(struct bpctl_dev *pbpctl_dev)
3815 int ret = BP_NOT_CAP;
3816 struct bpctl_dev *pbpctl_dev_m;
3818 if ((is_bypass_fn(pbpctl_dev)) == 1)
3819 pbpctl_dev_m = pbpctl_dev;
3821 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
3822 if (pbpctl_dev_m == NULL)
3825 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
3826 if (is_bypass_fn(pbpctl_dev) == 1) {
3827 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3828 TX_DISA_MASK) == TX_DISA_MASK) ? 1 : 0);
3830 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3831 TX_DISB_MASK) == TX_DISB_MASK) ? 1 : 0);
3837 int default_pwron_disc_port_status(struct bpctl_dev *pbpctl_dev)
3839 int ret = BP_NOT_CAP;
3840 struct bpctl_dev *pbpctl_dev_m;
3842 if ((is_bypass_fn(pbpctl_dev)) == 1)
3843 pbpctl_dev_m = pbpctl_dev;
3845 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
3846 if (pbpctl_dev_m == NULL)
3849 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
3850 if (is_bypass_fn(pbpctl_dev) == 1)
3852 /* return((((read_reg(pbpctl_dev,STATUS_TAP_REG_ADDR)) & TX_DISA_MASK)==TX_DISA_MASK)?1:0); */
3855 /* return((((read_reg(pbpctl_dev,STATUS_TAP_REG_ADDR)) & TX_DISA_MASK)==TX_DISA_MASK)?1:0); */
3861 int wdt_exp_mode_status(struct bpctl_dev *pbpctl_dev)
3863 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
3864 if (pbpctl_dev->bp_ext_ver <= PXG2BPI_VER)
3865 return 0; /* bypass mode */
3866 else if (pbpctl_dev->bp_ext_ver == PXG2TBPI_VER)
3867 return 1; /* tap mode */
3868 else if (pbpctl_dev->bp_ext_ver >= PXE2TBPI_VER) {
3869 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3872 STATUS_DISC_REG_ADDR)) &
3873 WDTE_DISC_BPN_MASK) == WDTE_DISC_BPN_MASK)
3876 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3877 WDTE_TAP_BPN_MASK) ==
3878 WDTE_TAP_BPN_MASK) ? 1 : 0);
3884 int tpl2_flag_status(struct bpctl_dev *pbpctl_dev)
3887 if (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX) {
3888 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3889 TPL2_FLAG_MASK) == TPL2_FLAG_MASK) ? 1 : 0);
3895 int tpl_hw_status(struct bpctl_dev *pbpctl_dev)
3897 struct bpctl_dev *pbpctl_dev_b = NULL;
3899 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
3903 if (TPL_IF_SERIES(pbpctl_dev->subdevice))
3904 return (((BPCTL_READ_REG(pbpctl_dev, CTRL)) &
3905 BPCTLI_CTRL_SWDPIN0) != 0 ? 1 : 0);
3910 int bp_wait_at_pwup_status(struct bpctl_dev *pbpctl_dev)
3912 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3913 if (pbpctl_dev->bp_ext_ver >= 0x8)
3914 return ((((read_reg(pbpctl_dev, CONT_CONFIG_REG_ADDR)) &
3915 WAIT_AT_PWUP_MASK) ==
3916 WAIT_AT_PWUP_MASK) ? 1 : 0);
3921 int bp_hw_reset_status(struct bpctl_dev *pbpctl_dev)
3924 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3926 if (pbpctl_dev->bp_ext_ver >= 0x8)
3927 return ((((read_reg(pbpctl_dev, CONT_CONFIG_REG_ADDR)) &
3928 EN_HW_RESET_MASK) ==
3929 EN_HW_RESET_MASK) ? 1 : 0);
3935 int std_nic_status(struct bpctl_dev *pbpctl_dev)
3939 if (pbpctl_dev->bp_caps & STD_NIC_CAP) {
3940 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
3942 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
3943 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3944 STD_NIC_ON_MASK) == STD_NIC_ON_MASK) ? 1 : 0);
3947 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3948 if (pbpctl_dev->bp_caps & BP_CAP) {
3950 read_reg(pbpctl_dev, STATUS_REG_ADDR);
3951 if (((!(status_val & WDT_EN_MASK))
3952 && ((status_val & STD_NIC_MASK) ==
3958 if (pbpctl_dev->bp_caps & TAP_CAP) {
3960 read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR);
3961 if ((status_val & STD_NIC_TAP_MASK) ==
3967 if (pbpctl_dev->bp_caps & TAP_CAP) {
3968 if ((disc_off_status(pbpctl_dev)))
3980 /******************************************************/
3981 /**************SW_INIT*********************************/
3982 /******************************************************/
3983 void bypass_caps_init(struct bpctl_dev *pbpctl_dev)
3985 u_int32_t ctrl_ext = 0;
3986 struct bpctl_dev *pbpctl_dev_m = NULL;
3990 if (!(INTEL_IF_SERIES(adapter->bp_device_block.subdevice))) {
3991 ret = read_reg(pbpctl_dev, VER_REG_ADDR);
3992 printk("VER_REG reg1=%x\n", ret);
3993 ret = read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR);
3994 printk("PRODUCT_CAP reg=%x\n", ret);
3995 ret = read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR);
3996 printk("STATUS_TAP reg1=%x\n", ret);
3997 ret = read_reg(pbpctl_dev, 0x7);
3998 printk("SIG_REG reg1=%x\n", ret);
3999 ret = read_reg(pbpctl_dev, STATUS_REG_ADDR);
4000 printk("STATUS_REG_ADDR=%x\n", ret);
4001 ret = read_reg(pbpctl_dev, WDT_REG_ADDR);
4002 printk("WDT_REG_ADDR=%x\n", ret);
4003 ret = read_reg(pbpctl_dev, TMRL_REG_ADDR);
4004 printk("TMRL_REG_ADDR=%x\n", ret);
4005 ret = read_reg(pbpctl_dev, TMRH_REG_ADDR);
4006 printk("TMRH_REG_ADDR=%x\n", ret);
4009 if ((pbpctl_dev->bp_fiber5) || (pbpctl_dev->bp_10g9)) {
4010 pbpctl_dev->media_type = BP_FIBER;
4011 } else if (pbpctl_dev->bp_10gb) {
4012 if (BP10GB_CX4_SERIES(pbpctl_dev->subdevice))
4013 pbpctl_dev->media_type = BP_CX4;
4015 pbpctl_dev->media_type = BP_FIBER;
4019 else if (pbpctl_dev->bp_540)
4020 pbpctl_dev->media_type = BP_NONE;
4021 else if (!pbpctl_dev->bp_10g) {
4023 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
4024 if ((ctrl_ext & BPCTLI_CTRL_EXT_LINK_MODE_MASK) == 0x0)
4025 pbpctl_dev->media_type = BP_COPPER;
4027 pbpctl_dev->media_type = BP_FIBER;
4030 if (BP10G_CX4_SERIES(pbpctl_dev->subdevice))
4031 pbpctl_dev->media_type = BP_CX4;
4033 pbpctl_dev->media_type = BP_FIBER;
4036 if (is_bypass_fn(pbpctl_dev)) {
4038 pbpctl_dev->bp_caps |= BP_PWOFF_ON_CAP;
4039 if (pbpctl_dev->media_type == BP_FIBER)
4040 pbpctl_dev->bp_caps |=
4041 (TX_CTL_CAP | TX_STATUS_CAP | TPL_CAP);
4043 if (TPL_IF_SERIES(pbpctl_dev->subdevice))
4044 pbpctl_dev->bp_caps |= TPL_CAP;
4046 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
4047 pbpctl_dev->bp_caps |=
4048 (BP_CAP | BP_STATUS_CAP | SW_CTL_CAP |
4049 BP_PWUP_ON_CAP | BP_PWUP_OFF_CAP | BP_PWOFF_OFF_CAP
4050 | WD_CTL_CAP | WD_STATUS_CAP | STD_NIC_CAP |
4053 pbpctl_dev->bp_ext_ver = OLD_IF_VER;
4057 if ((pbpctl_dev->bp_fw_ver == 0xff) &&
4058 OLD_IF_SERIES(pbpctl_dev->subdevice)) {
4060 pbpctl_dev->bp_caps |=
4061 (BP_CAP | BP_STATUS_CAP | BP_STATUS_CHANGE_CAP |
4062 SW_CTL_CAP | BP_PWUP_ON_CAP | WD_CTL_CAP |
4063 WD_STATUS_CAP | WD_TIMEOUT_CAP);
4065 pbpctl_dev->bp_ext_ver = OLD_IF_VER;
4070 switch (pbpctl_dev->bp_fw_ver) {
4073 pbpctl_dev->bp_ext_ver =
4075 bp_fw_ver & EXT_VER_MASK);
4079 if ((bypass_sign_check(pbpctl_dev)) !=
4081 pbpctl_dev->bp_caps = 0;
4084 pbpctl_dev->bp_ext_ver =
4086 bp_fw_ver & EXT_VER_MASK);
4091 if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
4092 pbpctl_dev->bp_caps |=
4093 (BP_CAP | BP_STATUS_CAP | BP_STATUS_CHANGE_CAP |
4094 SW_CTL_CAP | BP_DIS_CAP | BP_DIS_STATUS_CAP |
4095 BP_PWUP_ON_CAP | BP_PWUP_OFF_CAP | BP_PWUP_CTL_CAP
4096 | WD_CTL_CAP | STD_NIC_CAP | WD_STATUS_CAP |
4098 else if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
4101 pbpctl_dev->bp_caps |=
4102 (SW_CTL_CAP | WD_CTL_CAP | WD_STATUS_CAP |
4104 cap_reg = get_bp_prod_caps(pbpctl_dev);
4106 if ((cap_reg & NORMAL_UNSUPPORT_MASK) ==
4107 NORMAL_UNSUPPORT_MASK)
4108 pbpctl_dev->bp_caps |= NIC_CAP_NEG;
4110 pbpctl_dev->bp_caps |= STD_NIC_CAP;
4112 if ((normal_support(pbpctl_dev)) == 1)
4114 pbpctl_dev->bp_caps |= STD_NIC_CAP;
4117 pbpctl_dev->bp_caps |= NIC_CAP_NEG;
4118 if ((cap_reg & BYPASS_SUPPORT_MASK) ==
4119 BYPASS_SUPPORT_MASK) {
4120 pbpctl_dev->bp_caps |=
4121 (BP_CAP | BP_STATUS_CAP |
4122 BP_STATUS_CHANGE_CAP | BP_DIS_CAP |
4123 BP_DIS_STATUS_CAP | BP_PWUP_ON_CAP |
4124 BP_PWUP_OFF_CAP | BP_PWUP_CTL_CAP);
4125 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER7)
4126 pbpctl_dev->bp_caps |=
4127 BP_PWOFF_ON_CAP | BP_PWOFF_OFF_CAP |
4130 if ((cap_reg & TAP_SUPPORT_MASK) == TAP_SUPPORT_MASK) {
4131 pbpctl_dev->bp_caps |=
4132 (TAP_CAP | TAP_STATUS_CAP |
4133 TAP_STATUS_CHANGE_CAP | TAP_DIS_CAP |
4134 TAP_DIS_STATUS_CAP | TAP_PWUP_ON_CAP |
4135 TAP_PWUP_OFF_CAP | TAP_PWUP_CTL_CAP);
4137 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
4138 if ((cap_reg & DISC_SUPPORT_MASK) ==
4140 pbpctl_dev->bp_caps |=
4141 (DISC_CAP | DISC_DIS_CAP |
4143 if ((cap_reg & TPL2_SUPPORT_MASK) ==
4144 TPL2_SUPPORT_MASK) {
4145 pbpctl_dev->bp_caps_ex |= TPL2_CAP_EX;
4146 pbpctl_dev->bp_caps |= TPL_CAP;
4147 pbpctl_dev->bp_tpl_flag =
4148 tpl2_flag_status(pbpctl_dev);
4153 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER9) {
4154 if ((cap_reg & DISC_PORT_SUPPORT_MASK) ==
4155 DISC_PORT_SUPPORT_MASK) {
4156 pbpctl_dev->bp_caps_ex |=
4158 pbpctl_dev->bp_caps |=
4159 (TX_CTL_CAP | TX_STATUS_CAP);
4165 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
4166 if ((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
4168 pbpctl_dev->wdt_status = WDT_STATUS_EN;
4170 pbpctl_dev->wdt_status = WDT_STATUS_DIS;
4173 } else if ((P2BPFI_IF_SERIES(pbpctl_dev->subdevice)) ||
4174 (PEGF5_IF_SERIES(pbpctl_dev->subdevice)) ||
4175 (PEGF80_IF_SERIES(pbpctl_dev->subdevice)) ||
4176 (BP10G9_IF_SERIES(pbpctl_dev->subdevice))) {
4177 pbpctl_dev->bp_caps |= (TX_CTL_CAP | TX_STATUS_CAP);
4179 if ((pbpctl_dev->subdevice & 0xa00) == 0xa00)
4180 pbpctl_dev->bp_caps |= (TX_CTL_CAP | TX_STATUS_CAP);
4181 if (PEG5_IF_SERIES(pbpctl_dev->subdevice))
4182 pbpctl_dev->bp_caps |= (TX_CTL_CAP | TX_STATUS_CAP);
4184 if (BP10GB_IF_SERIES(pbpctl_dev->subdevice))
4185 pbpctl_dev->bp_caps &= ~(TX_CTL_CAP | TX_STATUS_CAP);
4187 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
4188 if (pbpctl_dev_m != NULL) {
4190 if (pbpctl_dev_m->bp_ext_ver >= 0x9) {
4191 cap_reg = get_bp_prod_caps(pbpctl_dev_m);
4192 if ((cap_reg & DISC_PORT_SUPPORT_MASK) ==
4193 DISC_PORT_SUPPORT_MASK)
4194 pbpctl_dev->bp_caps |=
4195 (TX_CTL_CAP | TX_STATUS_CAP);
4196 pbpctl_dev->bp_caps_ex |= DISC_PORT_CAP_EX;
4201 int bypass_off_init(struct bpctl_dev *pbpctl_dev)
4203 int ret = cmnd_on(pbpctl_dev);
4206 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
4207 return dis_bypass_cap(pbpctl_dev);
4208 wdt_off(pbpctl_dev);
4209 if (pbpctl_dev->bp_caps & BP_CAP)
4210 bypass_off(pbpctl_dev);
4211 if (pbpctl_dev->bp_caps & TAP_CAP)
4212 tap_off(pbpctl_dev);
4213 cmnd_off(pbpctl_dev);
4217 void remove_bypass_wd_auto(struct bpctl_dev *pbpctl_dev)
4220 struct bpctl_dev *pbpctl_dev_sl = NULL;
4223 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4225 del_timer_sync(&pbpctl_dev->bp_timer);
4227 pbpctl_dev_sl = get_status_port_fn(pbpctl_dev);
4228 if (pbpctl_dev_sl && (pbpctl_dev_sl->ndev)) {
4229 if ((pbpctl_dev_sl->ndev->netdev_ops)
4230 && (pbpctl_dev_sl->old_ops)) {
4232 pbpctl_dev_sl->ndev->netdev_ops =
4233 pbpctl_dev_sl->old_ops;
4234 pbpctl_dev_sl->old_ops = NULL;
4246 int init_bypass_wd_auto(struct bpctl_dev *pbpctl_dev)
4248 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4249 init_timer(&pbpctl_dev->bp_timer);
4250 pbpctl_dev->bp_timer.function = &wd_reset_timer;
4251 pbpctl_dev->bp_timer.data = (unsigned long)pbpctl_dev;
4258 int bp_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
4260 struct bpctl_dev *pbpctl_dev = NULL, *pbpctl_dev_m = NULL;
4262 struct ethhdr *eth = (struct ethhdr *)skb->data;
4265 ((bpctl_dev_arr[idx_dev].ndev != NULL) && (idx_dev < device_num));
4267 if (bpctl_dev_arr[idx_dev].ndev == dev) {
4268 pbpctl_dev = &bpctl_dev_arr[idx_dev];
4274 if ((htons(ETH_P_BPTEST) == eth->h_proto)) {
4276 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
4279 if (bypass_status(pbpctl_dev_m)) {
4280 cmnd_on(pbpctl_dev_m);
4281 bypass_off(pbpctl_dev_m);
4282 cmnd_off(pbpctl_dev_m);
4284 wdt_timer_reload(pbpctl_dev_m);
4286 dev_kfree_skb_irq(skb);
4289 return pbpctl_dev->hard_start_xmit_save(skb, dev);
4293 int set_bypass_wd_auto(struct bpctl_dev *pbpctl_dev, unsigned int param)
4295 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4296 if (pbpctl_dev->reset_time != param) {
4297 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
4298 pbpctl_dev->reset_time =
4300 WDT_AUTO_MIN_INT) ? WDT_AUTO_MIN_INT :
4303 pbpctl_dev->reset_time = param;
4305 mod_timer(&pbpctl_dev->bp_timer, jiffies);
4312 int get_bypass_wd_auto(struct bpctl_dev *pbpctl_dev)
4314 if (pbpctl_dev->bp_caps & WD_CTL_CAP)
4315 return pbpctl_dev->reset_time;
4322 int set_bp_self_test(struct bpctl_dev *pbpctl_dev, unsigned int param)
4324 struct bpctl_dev *pbpctl_dev_sl = NULL;
4326 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4327 pbpctl_dev->bp_self_test_flag = param == 0 ? 0 : 1;
4328 pbpctl_dev_sl = get_status_port_fn(pbpctl_dev);
4330 if ((pbpctl_dev_sl->ndev) && (pbpctl_dev_sl->ndev->netdev_ops)) {
4332 if (pbpctl_dev->bp_self_test_flag == 1) {
4334 pbpctl_dev_sl->old_ops =
4335 pbpctl_dev_sl->ndev->netdev_ops;
4336 pbpctl_dev_sl->new_ops =
4337 *pbpctl_dev_sl->old_ops;
4338 pbpctl_dev_sl->new_ops.ndo_start_xmit =
4340 pbpctl_dev_sl->ndev->netdev_ops =
4341 &pbpctl_dev_sl->new_ops;
4343 } else if (pbpctl_dev_sl->old_ops) {
4344 pbpctl_dev_sl->ndev->netdev_ops =
4345 pbpctl_dev_sl->old_ops;
4346 pbpctl_dev_sl->old_ops = NULL;
4351 set_bypass_wd_auto(pbpctl_dev, param);
4357 int get_bp_self_test(struct bpctl_dev *pbpctl_dev)
4360 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4361 if (pbpctl_dev->bp_self_test_flag == 1)
4362 return pbpctl_dev->reset_time;
4371 /**************************************************************/
4372 /************************* API ********************************/
4373 /**************************************************************/
4375 int is_bypass_fn(struct bpctl_dev *pbpctl_dev)
4380 return (((pbpctl_dev->func == 0) || (pbpctl_dev->func == 2)) ? 1 : 0);
4383 int set_bypass_fn(struct bpctl_dev *pbpctl_dev, int bypass_mode)
4387 if (!(pbpctl_dev->bp_caps & BP_CAP))
4389 ret = cmnd_on(pbpctl_dev);
4393 ret = bypass_off(pbpctl_dev);
4395 ret = bypass_on(pbpctl_dev);
4396 cmnd_off(pbpctl_dev);
4401 int get_bypass_fn(struct bpctl_dev *pbpctl_dev)
4403 return bypass_status(pbpctl_dev);
4406 int get_bypass_change_fn(struct bpctl_dev *pbpctl_dev)
4411 return bypass_change_status(pbpctl_dev);
4414 int set_dis_bypass_fn(struct bpctl_dev *pbpctl_dev, int dis_param)
4420 if (!(pbpctl_dev->bp_caps & BP_DIS_CAP))
4422 ret = cmnd_on(pbpctl_dev);
4426 ret = dis_bypass_cap(pbpctl_dev);
4428 ret = en_bypass_cap(pbpctl_dev);
4429 cmnd_off(pbpctl_dev);
4433 int get_dis_bypass_fn(struct bpctl_dev *pbpctl_dev)
4438 return dis_bypass_cap_status(pbpctl_dev);
4441 int set_bypass_pwoff_fn(struct bpctl_dev *pbpctl_dev, int bypass_mode)
4447 if (!(pbpctl_dev->bp_caps & BP_PWOFF_CTL_CAP))
4449 ret = cmnd_on(pbpctl_dev);
4453 ret = bypass_state_pwroff(pbpctl_dev);
4455 ret = normal_state_pwroff(pbpctl_dev);
4456 cmnd_off(pbpctl_dev);
4460 int get_bypass_pwoff_fn(struct bpctl_dev *pbpctl_dev)
4465 return default_pwroff_status(pbpctl_dev);
4468 int set_bypass_pwup_fn(struct bpctl_dev *pbpctl_dev, int bypass_mode)
4474 if (!(pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP))
4476 ret = cmnd_on(pbpctl_dev);
4480 ret = bypass_state_pwron(pbpctl_dev);
4482 ret = normal_state_pwron(pbpctl_dev);
4483 cmnd_off(pbpctl_dev);
4487 int get_bypass_pwup_fn(struct bpctl_dev *pbpctl_dev)
4492 return default_pwron_status(pbpctl_dev);
4495 int set_bypass_wd_fn(struct bpctl_dev *pbpctl_dev, int timeout)
4501 if (!(pbpctl_dev->bp_caps & WD_CTL_CAP))
4504 ret = cmnd_on(pbpctl_dev);
4508 ret = wdt_off(pbpctl_dev);
4510 wdt_on(pbpctl_dev, timeout);
4511 ret = pbpctl_dev->bypass_timer_interval;
4513 cmnd_off(pbpctl_dev);
4517 int get_bypass_wd_fn(struct bpctl_dev *pbpctl_dev, int *timeout)
4522 return wdt_programmed(pbpctl_dev, timeout);
4525 int get_wd_expire_time_fn(struct bpctl_dev *pbpctl_dev, int *time_left)
4530 return wdt_timer(pbpctl_dev, time_left);
4533 int reset_bypass_wd_timer_fn(struct bpctl_dev *pbpctl_dev)
4538 return wdt_timer_reload(pbpctl_dev);
4541 int get_wd_set_caps_fn(struct bpctl_dev *pbpctl_dev)
4545 unsigned int step_value = TIMEOUT_MAX_STEP + 1, bit_cnt = 0;
4549 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
4552 while ((step_value >>= 1))
4555 if (is_bypass_fn(pbpctl_dev)) {
4557 WD_STEP_COUNT_MASK(bit_cnt) | WDT_STEP_TIME |
4558 WD_MIN_TIME_MASK(TIMEOUT_UNIT / 100);
4565 int set_std_nic_fn(struct bpctl_dev *pbpctl_dev, int nic_mode)
4571 if (!(pbpctl_dev->bp_caps & STD_NIC_CAP))
4574 ret = cmnd_on(pbpctl_dev);
4578 ret = std_nic_on(pbpctl_dev);
4580 ret = std_nic_off(pbpctl_dev);
4581 cmnd_off(pbpctl_dev);
4585 int get_std_nic_fn(struct bpctl_dev *pbpctl_dev)
4590 return std_nic_status(pbpctl_dev);
4593 int set_tap_fn(struct bpctl_dev *pbpctl_dev, int tap_mode)
4598 if ((pbpctl_dev->bp_caps & TAP_CAP) && ((cmnd_on(pbpctl_dev)) >= 0)) {
4600 tap_off(pbpctl_dev);
4603 cmnd_off(pbpctl_dev);
4609 int get_tap_fn(struct bpctl_dev *pbpctl_dev)
4614 return tap_status(pbpctl_dev);
4617 int set_tap_pwup_fn(struct bpctl_dev *pbpctl_dev, int tap_mode)
4623 if ((pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP)
4624 && ((cmnd_on(pbpctl_dev)) >= 0)) {
4626 ret = tap_state_pwron(pbpctl_dev);
4628 ret = normal_state_pwron(pbpctl_dev);
4629 cmnd_off(pbpctl_dev);
4635 int get_tap_pwup_fn(struct bpctl_dev *pbpctl_dev)
4641 ret = default_pwron_tap_status(pbpctl_dev);
4644 return ((ret == 0) ? 1 : 0);
4647 int get_tap_change_fn(struct bpctl_dev *pbpctl_dev)
4652 return tap_change_status(pbpctl_dev);
4655 int set_dis_tap_fn(struct bpctl_dev *pbpctl_dev, int dis_param)
4661 if ((pbpctl_dev->bp_caps & TAP_DIS_CAP) && ((cmnd_on(pbpctl_dev)) >= 0)) {
4663 ret = dis_tap_cap(pbpctl_dev);
4665 ret = en_tap_cap(pbpctl_dev);
4666 cmnd_off(pbpctl_dev);
4672 int get_dis_tap_fn(struct bpctl_dev *pbpctl_dev)
4677 return dis_tap_cap_status(pbpctl_dev);
4680 int set_disc_fn(struct bpctl_dev *pbpctl_dev, int disc_mode)
4685 if ((pbpctl_dev->bp_caps & DISC_CAP) && ((cmnd_on(pbpctl_dev)) >= 0)) {
4687 disc_off(pbpctl_dev);
4689 disc_on(pbpctl_dev);
4690 cmnd_off(pbpctl_dev);
4697 int get_disc_fn(struct bpctl_dev *pbpctl_dev)
4703 ret = disc_status(pbpctl_dev);
4708 int set_disc_pwup_fn(struct bpctl_dev *pbpctl_dev, int disc_mode)
4714 if ((pbpctl_dev->bp_caps & DISC_PWUP_CTL_CAP)
4715 && ((cmnd_on(pbpctl_dev)) >= 0)) {
4717 ret = disc_state_pwron(pbpctl_dev);
4719 ret = normal_state_pwron(pbpctl_dev);
4720 cmnd_off(pbpctl_dev);
4726 int get_disc_pwup_fn(struct bpctl_dev *pbpctl_dev)
4732 ret = default_pwron_disc_status(pbpctl_dev);
4733 return (ret == 0 ? 1 : (ret < 0 ? BP_NOT_CAP : 0));
4736 int get_disc_change_fn(struct bpctl_dev *pbpctl_dev)
4742 ret = disc_change_status(pbpctl_dev);
4746 int set_dis_disc_fn(struct bpctl_dev *pbpctl_dev, int dis_param)
4752 if ((pbpctl_dev->bp_caps & DISC_DIS_CAP)
4753 && ((cmnd_on(pbpctl_dev)) >= 0)) {
4755 ret = dis_disc_cap(pbpctl_dev);
4757 ret = en_disc_cap(pbpctl_dev);
4758 cmnd_off(pbpctl_dev);
4764 int get_dis_disc_fn(struct bpctl_dev *pbpctl_dev)
4770 ret = dis_disc_cap_status(pbpctl_dev);
4775 int set_disc_port_fn(struct bpctl_dev *pbpctl_dev, int disc_mode)
4777 int ret = BP_NOT_CAP;
4782 ret = disc_port_off(pbpctl_dev);
4784 ret = disc_port_on(pbpctl_dev);
4789 int get_disc_port_fn(struct bpctl_dev *pbpctl_dev)
4794 return disc_port_status(pbpctl_dev);
4797 int set_disc_port_pwup_fn(struct bpctl_dev *pbpctl_dev, int disc_mode)
4799 int ret = BP_NOT_CAP;
4804 ret = normal_port_state_pwron(pbpctl_dev);
4806 ret = disc_port_state_pwron(pbpctl_dev);
4811 int get_disc_port_pwup_fn(struct bpctl_dev *pbpctl_dev)
4817 ret = default_pwron_disc_port_status(pbpctl_dev);
4820 return ((ret == 0) ? 1 : 0);
4823 int get_wd_exp_mode_fn(struct bpctl_dev *pbpctl_dev)
4828 return wdt_exp_mode_status(pbpctl_dev);
4831 int set_wd_exp_mode_fn(struct bpctl_dev *pbpctl_dev, int param)
4836 return wdt_exp_mode(pbpctl_dev, param);
4839 int reset_cont_fn(struct bpctl_dev *pbpctl_dev)
4845 ret = cmnd_on(pbpctl_dev);
4848 return reset_cont(pbpctl_dev);
4851 int set_tx_fn(struct bpctl_dev *pbpctl_dev, int tx_state)
4854 struct bpctl_dev *pbpctl_dev_b = NULL;
4858 if ((pbpctl_dev->bp_caps & TPL_CAP) &&
4859 (pbpctl_dev->bp_caps & SW_CTL_CAP)) {
4860 if ((pbpctl_dev->bp_tpl_flag))
4863 pbpctl_dev_b = get_master_port_fn(pbpctl_dev);
4865 (pbpctl_dev_b->bp_caps & TPL_CAP) &&
4866 (pbpctl_dev_b->bp_tpl_flag))
4869 return set_tx(pbpctl_dev, tx_state);
4872 int set_bp_force_link_fn(int dev_num, int tx_state)
4874 static struct bpctl_dev *bpctl_dev_curr;
4876 if ((dev_num < 0) || (dev_num > device_num)
4877 || (bpctl_dev_arr[dev_num].pdev == NULL))
4879 bpctl_dev_curr = &bpctl_dev_arr[dev_num];
4881 return set_bp_force_link(bpctl_dev_curr, tx_state);
4884 int set_wd_autoreset_fn(struct bpctl_dev *pbpctl_dev, int param)
4889 return set_bypass_wd_auto(pbpctl_dev, param);
4892 int get_wd_autoreset_fn(struct bpctl_dev *pbpctl_dev)
4897 return get_bypass_wd_auto(pbpctl_dev);
4901 int set_bp_self_test_fn(struct bpctl_dev *pbpctl_dev, int param)
4906 return set_bp_self_test(pbpctl_dev, param);
4909 int get_bp_self_test_fn(struct bpctl_dev *pbpctl_dev)
4914 return get_bp_self_test(pbpctl_dev);
4919 int get_bypass_caps_fn(struct bpctl_dev *pbpctl_dev)
4924 return pbpctl_dev->bp_caps;
4928 int get_bypass_slave_fn(struct bpctl_dev *pbpctl_dev, struct bpctl_dev **pbpctl_dev_out)
4934 if ((pbpctl_dev->func == 0) || (pbpctl_dev->func == 2)) {
4936 ((bpctl_dev_arr[idx_dev].pdev != NULL)
4937 && (idx_dev < device_num)); idx_dev++) {
4938 if ((bpctl_dev_arr[idx_dev].bus == pbpctl_dev->bus)
4939 && (bpctl_dev_arr[idx_dev].slot ==
4940 pbpctl_dev->slot)) {
4941 if ((pbpctl_dev->func == 0)
4942 && (bpctl_dev_arr[idx_dev].func == 1)) {
4944 &bpctl_dev_arr[idx_dev];
4947 if ((pbpctl_dev->func == 2) &&
4948 (bpctl_dev_arr[idx_dev].func == 3)) {
4950 &bpctl_dev_arr[idx_dev];
4960 int is_bypass(struct bpctl_dev *pbpctl_dev)
4965 if ((pbpctl_dev->func == 0) || (pbpctl_dev->func == 2))
4971 int get_tx_fn(struct bpctl_dev *pbpctl_dev)
4973 struct bpctl_dev *pbpctl_dev_b = NULL;
4977 if ((pbpctl_dev->bp_caps & TPL_CAP) &&
4978 (pbpctl_dev->bp_caps & SW_CTL_CAP)) {
4979 if ((pbpctl_dev->bp_tpl_flag))
4982 pbpctl_dev_b = get_master_port_fn(pbpctl_dev);
4984 (pbpctl_dev_b->bp_caps & TPL_CAP) &&
4985 (pbpctl_dev_b->bp_tpl_flag))
4988 return tx_status(pbpctl_dev);
4991 int get_bp_force_link_fn(int dev_num)
4993 static struct bpctl_dev *bpctl_dev_curr;
4995 if ((dev_num < 0) || (dev_num > device_num)
4996 || (bpctl_dev_arr[dev_num].pdev == NULL))
4998 bpctl_dev_curr = &bpctl_dev_arr[dev_num];
5000 return bp_force_link_status(bpctl_dev_curr);
5003 static int get_bypass_link_status(struct bpctl_dev *pbpctl_dev)
5008 if (pbpctl_dev->media_type == BP_FIBER)
5009 return ((BPCTL_READ_REG(pbpctl_dev, CTRL) &
5010 BPCTLI_CTRL_SWDPIN1));
5012 return ((BPCTL_READ_REG(pbpctl_dev, STATUS) &
5017 static void bp_tpl_timer_fn(unsigned long param)
5019 struct bpctl_dev *pbpctl_dev = (struct bpctl_dev *) param;
5020 uint32_t link1, link2;
5021 struct bpctl_dev *pbpctl_dev_b = NULL;
5023 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
5027 if (!pbpctl_dev->bp_tpl_flag) {
5028 set_tx(pbpctl_dev_b, 1);
5029 set_tx(pbpctl_dev, 1);
5032 link1 = get_bypass_link_status(pbpctl_dev);
5034 link2 = get_bypass_link_status(pbpctl_dev_b);
5035 if ((link1) && (tx_status(pbpctl_dev))) {
5036 if ((!link2) && (tx_status(pbpctl_dev_b)))
5037 set_tx(pbpctl_dev, 0);
5038 else if (!tx_status(pbpctl_dev_b))
5039 set_tx(pbpctl_dev_b, 1);
5040 } else if ((!link1) && (tx_status(pbpctl_dev))) {
5041 if ((link2) && (tx_status(pbpctl_dev_b)))
5042 set_tx(pbpctl_dev_b, 0);
5043 } else if ((link1) && (!tx_status(pbpctl_dev))) {
5044 if ((link2) && (tx_status(pbpctl_dev_b)))
5045 set_tx(pbpctl_dev, 1);
5046 } else if ((!link1) && (!tx_status(pbpctl_dev))) {
5047 if ((link2) && (tx_status(pbpctl_dev_b)))
5048 set_tx(pbpctl_dev, 1);
5051 mod_timer(&pbpctl_dev->bp_tpl_timer, jiffies + BP_LINK_MON_DELAY * HZ);
5054 void remove_bypass_tpl_auto(struct bpctl_dev *pbpctl_dev)
5056 struct bpctl_dev *pbpctl_dev_b = NULL;
5059 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
5061 if (pbpctl_dev->bp_caps & TPL_CAP) {
5062 del_timer_sync(&pbpctl_dev->bp_tpl_timer);
5063 pbpctl_dev->bp_tpl_flag = 0;
5064 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
5066 set_tx(pbpctl_dev_b, 1);
5067 set_tx(pbpctl_dev, 1);
5072 int init_bypass_tpl_auto(struct bpctl_dev *pbpctl_dev)
5076 if (pbpctl_dev->bp_caps & TPL_CAP) {
5077 init_timer(&pbpctl_dev->bp_tpl_timer);
5078 pbpctl_dev->bp_tpl_timer.function = &bp_tpl_timer_fn;
5079 pbpctl_dev->bp_tpl_timer.data = (unsigned long)pbpctl_dev;
5085 int set_bypass_tpl_auto(struct bpctl_dev *pbpctl_dev, unsigned int param)
5089 if (pbpctl_dev->bp_caps & TPL_CAP) {
5090 if ((param) && (!pbpctl_dev->bp_tpl_flag)) {
5091 pbpctl_dev->bp_tpl_flag = param;
5092 mod_timer(&pbpctl_dev->bp_tpl_timer, jiffies + 1);
5095 if ((!param) && (pbpctl_dev->bp_tpl_flag))
5096 remove_bypass_tpl_auto(pbpctl_dev);
5103 int get_bypass_tpl_auto(struct bpctl_dev *pbpctl_dev)
5107 if (pbpctl_dev->bp_caps & TPL_CAP)
5108 return pbpctl_dev->bp_tpl_flag;
5113 int set_tpl_fn(struct bpctl_dev *pbpctl_dev, int tpl_mode)
5116 struct bpctl_dev *pbpctl_dev_b = NULL;
5120 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
5122 if (pbpctl_dev->bp_caps & TPL_CAP) {
5124 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
5126 set_tx(pbpctl_dev_b, 1);
5127 set_tx(pbpctl_dev, 1);
5129 if ((TPL_IF_SERIES(pbpctl_dev->subdevice)) ||
5130 (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX)) {
5131 pbpctl_dev->bp_tpl_flag = tpl_mode;
5133 tpl_hw_off(pbpctl_dev);
5135 tpl_hw_on(pbpctl_dev);
5137 set_bypass_tpl_auto(pbpctl_dev, tpl_mode);
5143 int get_tpl_fn(struct bpctl_dev *pbpctl_dev)
5145 int ret = BP_NOT_CAP;
5149 if (pbpctl_dev->bp_caps & TPL_CAP) {
5150 if (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX)
5151 return tpl2_flag_status(pbpctl_dev);
5152 ret = pbpctl_dev->bp_tpl_flag;
5157 int set_bp_wait_at_pwup_fn(struct bpctl_dev *pbpctl_dev, int tap_mode)
5162 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
5163 /* bp_lock(pbp_device_block); */
5164 cmnd_on(pbpctl_dev);
5166 bp_wait_at_pwup_dis(pbpctl_dev);
5168 bp_wait_at_pwup_en(pbpctl_dev);
5169 cmnd_off(pbpctl_dev);
5171 /* bp_unlock(pbp_device_block); */
5177 int get_bp_wait_at_pwup_fn(struct bpctl_dev *pbpctl_dev)
5183 /* bp_lock(pbp_device_block); */
5184 ret = bp_wait_at_pwup_status(pbpctl_dev);
5185 /* bp_unlock(pbp_device_block); */
5190 int set_bp_hw_reset_fn(struct bpctl_dev *pbpctl_dev, int tap_mode)
5195 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
5196 /* bp_lock(pbp_device_block); */
5197 cmnd_on(pbpctl_dev);
5200 bp_hw_reset_dis(pbpctl_dev);
5202 bp_hw_reset_en(pbpctl_dev);
5203 cmnd_off(pbpctl_dev);
5204 /* bp_unlock(pbp_device_block); */
5210 int get_bp_hw_reset_fn(struct bpctl_dev *pbpctl_dev)
5216 /* bp_lock(pbp_device_block); */
5217 ret = bp_hw_reset_status(pbpctl_dev);
5219 /* bp_unlock(pbp_device_block); */
5225 int get_bypass_info_fn(struct bpctl_dev *pbpctl_dev, char *dev_name,
5230 if (!is_bypass_fn(pbpctl_dev))
5232 strcpy(dev_name, pbpctl_dev->name);
5233 *add_param = pbpctl_dev->bp_fw_ver;
5237 int get_dev_idx_bsf(int bus, int slot, int func)
5241 ((bpctl_dev_arr[idx_dev].pdev != NULL) && (idx_dev < device_num));
5243 if ((bus == bpctl_dev_arr[idx_dev].bus)
5244 && (slot == bpctl_dev_arr[idx_dev].slot)
5245 && (func == bpctl_dev_arr[idx_dev].func))
5252 static int get_dev_idx(int ifindex)
5257 ((bpctl_dev_arr[idx_dev].pdev != NULL) && (idx_dev < device_num));
5259 if (ifindex == bpctl_dev_arr[idx_dev].ifindex)
5266 static struct bpctl_dev *get_dev_idx_p(int ifindex)
5271 ((bpctl_dev_arr[idx_dev].pdev != NULL) && (idx_dev < device_num));
5273 if (ifindex == bpctl_dev_arr[idx_dev].ifindex)
5274 return &bpctl_dev_arr[idx_dev];
5280 static void if_scan_init(void)
5282 struct net_device *dev;
5284 /* rcu_read_lock(); */
5286 /* rcu_read_lock(); */
5288 for_each_netdev(&init_net, dev) {
5291 if (bp_get_dev_idx_bsf(dev, &idx_dev))
5297 bpctl_dev_arr[idx_dev].ifindex = dev->ifindex;
5298 bpctl_dev_arr[idx_dev].ndev = dev;
5300 /* rtnl_unlock(); */
5301 /* rcu_read_unlock(); */
5304 static long device_ioctl(struct file *file, /* see include/linux/fs.h */
5305 unsigned int ioctl_num, /* number and param for ioctl */
5306 unsigned long ioctl_param)
5308 struct bpctl_cmd bpctl_cmd;
5310 struct bpctl_dev *pbpctl_dev_out;
5311 void __user *argp = (void __user *)ioctl_param;
5313 unsigned long flags;
5315 static struct bpctl_dev *pbpctl_dev;
5317 /* lock_kernel(); */
5318 if (down_interruptible(&bpctl_sema))
5319 return -ERESTARTSYS;
5320 /* local_irq_save(flags); */
5321 /* if(!spin_trylock_irqsave(&bpvm_lock)){
5322 local_irq_restore(flags);
5327 /* spin_lock_irqsave(&bpvm_lock, flags); */
5330 * Switch according to the ioctl called
5332 if (ioctl_num == IOCTL_TX_MSG(IF_SCAN)) {
5337 if (copy_from_user(&bpctl_cmd, argp, sizeof(struct bpctl_cmd))) {
5343 if (ioctl_num == IOCTL_TX_MSG(GET_DEV_NUM)) {
5344 bpctl_cmd.out_param[0] = device_num;
5346 (argp, (void *)&bpctl_cmd, sizeof(struct bpctl_cmd))) {
5355 /* preempt_disable(); */
5356 local_irq_save(flags);
5357 if (!spin_trylock(&bpvm_lock)) {
5358 local_irq_restore(flags);
5363 /* preempt_disable();
5365 spin_lock_irqsave(&bpvm_lock, flags);
5367 if ((bpctl_cmd.in_param[5]) ||
5368 (bpctl_cmd.in_param[6]) || (bpctl_cmd.in_param[7]))
5369 dev_idx = get_dev_idx_bsf(bpctl_cmd.in_param[5],
5370 bpctl_cmd.in_param[6],
5371 bpctl_cmd.in_param[7]);
5372 else if (bpctl_cmd.in_param[1] == 0)
5373 dev_idx = bpctl_cmd.in_param[0];
5375 dev_idx = get_dev_idx(bpctl_cmd.in_param[1]);
5377 if (dev_idx < 0 || dev_idx > device_num) {
5379 preempt_enable(); */
5381 /* preempt_enable();
5382 rcu_read_unlock(); */
5383 spin_unlock_irqrestore(&bpvm_lock, flags);
5387 bpctl_cmd.out_param[0] = bpctl_dev_arr[dev_idx].bus;
5388 bpctl_cmd.out_param[1] = bpctl_dev_arr[dev_idx].slot;
5389 bpctl_cmd.out_param[2] = bpctl_dev_arr[dev_idx].func;
5390 bpctl_cmd.out_param[3] = bpctl_dev_arr[dev_idx].ifindex;
5392 if ((bpctl_dev_arr[dev_idx].bp_10gb)
5393 && (!(bpctl_dev_arr[dev_idx].ifindex))) {
5394 printk("Please load network driver for %s adapter!\n",
5395 bpctl_dev_arr[dev_idx].name);
5396 bpctl_cmd.status = -1;
5398 /* preempt_enable(); */
5399 /* rcu_read_unlock(); */
5400 spin_unlock_irqrestore(&bpvm_lock, flags);
5404 if ((bpctl_dev_arr[dev_idx].bp_10gb) && (bpctl_dev_arr[dev_idx].ndev)) {
5405 if (!(bpctl_dev_arr[dev_idx].ndev->flags & IFF_UP)) {
5406 if (!(bpctl_dev_arr[dev_idx].ndev->flags & IFF_UP)) {
5408 ("Please bring up network interfaces for %s adapter!\n",
5409 bpctl_dev_arr[dev_idx].name);
5410 bpctl_cmd.status = -1;
5412 /* preempt_enable(); */
5413 /* rcu_read_unlock(); */
5414 spin_unlock_irqrestore(&bpvm_lock, flags);
5421 if ((dev_idx < 0) || (dev_idx > device_num)
5422 || (bpctl_dev_arr[dev_idx].pdev == NULL)) {
5423 bpctl_cmd.status = -1;
5427 pbpctl_dev = &bpctl_dev_arr[dev_idx];
5429 switch (ioctl_num) {
5430 case IOCTL_TX_MSG(SET_BYPASS_PWOFF):
5432 set_bypass_pwoff_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5435 case IOCTL_TX_MSG(GET_BYPASS_PWOFF):
5436 bpctl_cmd.status = get_bypass_pwoff_fn(pbpctl_dev);
5439 case IOCTL_TX_MSG(SET_BYPASS_PWUP):
5441 set_bypass_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5444 case IOCTL_TX_MSG(GET_BYPASS_PWUP):
5445 bpctl_cmd.status = get_bypass_pwup_fn(pbpctl_dev);
5448 case IOCTL_TX_MSG(SET_BYPASS_WD):
5450 set_bypass_wd_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5453 case IOCTL_TX_MSG(GET_BYPASS_WD):
5455 get_bypass_wd_fn(pbpctl_dev, (int *)&(bpctl_cmd.data[0]));
5458 case IOCTL_TX_MSG(GET_WD_EXPIRE_TIME):
5460 get_wd_expire_time_fn(pbpctl_dev,
5461 (int *)&(bpctl_cmd.data[0]));
5464 case IOCTL_TX_MSG(RESET_BYPASS_WD_TIMER):
5465 bpctl_cmd.status = reset_bypass_wd_timer_fn(pbpctl_dev);
5468 case IOCTL_TX_MSG(GET_WD_SET_CAPS):
5469 bpctl_cmd.status = get_wd_set_caps_fn(pbpctl_dev);
5472 case IOCTL_TX_MSG(SET_STD_NIC):
5474 set_std_nic_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5477 case IOCTL_TX_MSG(GET_STD_NIC):
5478 bpctl_cmd.status = get_std_nic_fn(pbpctl_dev);
5481 case IOCTL_TX_MSG(SET_TAP):
5483 set_tap_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5486 case IOCTL_TX_MSG(GET_TAP):
5487 bpctl_cmd.status = get_tap_fn(pbpctl_dev);
5490 case IOCTL_TX_MSG(GET_TAP_CHANGE):
5491 bpctl_cmd.status = get_tap_change_fn(pbpctl_dev);
5494 case IOCTL_TX_MSG(SET_DIS_TAP):
5496 set_dis_tap_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5499 case IOCTL_TX_MSG(GET_DIS_TAP):
5500 bpctl_cmd.status = get_dis_tap_fn(pbpctl_dev);
5503 case IOCTL_TX_MSG(SET_TAP_PWUP):
5505 set_tap_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5508 case IOCTL_TX_MSG(GET_TAP_PWUP):
5509 bpctl_cmd.status = get_tap_pwup_fn(pbpctl_dev);
5512 case IOCTL_TX_MSG(SET_WD_EXP_MODE):
5514 set_wd_exp_mode_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5517 case IOCTL_TX_MSG(GET_WD_EXP_MODE):
5518 bpctl_cmd.status = get_wd_exp_mode_fn(pbpctl_dev);
5521 case IOCTL_TX_MSG(GET_DIS_BYPASS):
5522 bpctl_cmd.status = get_dis_bypass_fn(pbpctl_dev);
5525 case IOCTL_TX_MSG(SET_DIS_BYPASS):
5527 set_dis_bypass_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5530 case IOCTL_TX_MSG(GET_BYPASS_CHANGE):
5531 bpctl_cmd.status = get_bypass_change_fn(pbpctl_dev);
5534 case IOCTL_TX_MSG(GET_BYPASS):
5535 bpctl_cmd.status = get_bypass_fn(pbpctl_dev);
5538 case IOCTL_TX_MSG(SET_BYPASS):
5540 set_bypass_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5543 case IOCTL_TX_MSG(GET_BYPASS_CAPS):
5544 bpctl_cmd.status = get_bypass_caps_fn(pbpctl_dev);
5545 /*preempt_enable(); */
5546 /*rcu_read_unlock();*/
5547 spin_unlock_irqrestore(&bpvm_lock, flags);
5549 (argp, (void *)&bpctl_cmd, sizeof(struct bpctl_cmd))) {
5550 /*unlock_bpctl(); */
5551 /*preempt_enable(); */
5557 case IOCTL_TX_MSG(GET_BYPASS_SLAVE):
5559 get_bypass_slave_fn(pbpctl_dev, &pbpctl_dev_out);
5560 if (bpctl_cmd.status == 1) {
5561 bpctl_cmd.out_param[4] = pbpctl_dev_out->bus;
5562 bpctl_cmd.out_param[5] = pbpctl_dev_out->slot;
5563 bpctl_cmd.out_param[6] = pbpctl_dev_out->func;
5564 bpctl_cmd.out_param[7] = pbpctl_dev_out->ifindex;
5568 case IOCTL_TX_MSG(IS_BYPASS):
5569 bpctl_cmd.status = is_bypass(pbpctl_dev);
5571 case IOCTL_TX_MSG(SET_TX):
5572 bpctl_cmd.status = set_tx_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5574 case IOCTL_TX_MSG(GET_TX):
5575 bpctl_cmd.status = get_tx_fn(pbpctl_dev);
5577 case IOCTL_TX_MSG(SET_WD_AUTORESET):
5579 set_wd_autoreset_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5582 case IOCTL_TX_MSG(GET_WD_AUTORESET):
5584 bpctl_cmd.status = get_wd_autoreset_fn(pbpctl_dev);
5586 case IOCTL_TX_MSG(SET_DISC):
5588 set_disc_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5590 case IOCTL_TX_MSG(GET_DISC):
5591 bpctl_cmd.status = get_disc_fn(pbpctl_dev);
5593 case IOCTL_TX_MSG(GET_DISC_CHANGE):
5594 bpctl_cmd.status = get_disc_change_fn(pbpctl_dev);
5596 case IOCTL_TX_MSG(SET_DIS_DISC):
5598 set_dis_disc_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5600 case IOCTL_TX_MSG(GET_DIS_DISC):
5601 bpctl_cmd.status = get_dis_disc_fn(pbpctl_dev);
5603 case IOCTL_TX_MSG(SET_DISC_PWUP):
5605 set_disc_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5607 case IOCTL_TX_MSG(GET_DISC_PWUP):
5608 bpctl_cmd.status = get_disc_pwup_fn(pbpctl_dev);
5611 case IOCTL_TX_MSG(GET_BYPASS_INFO):
5614 get_bypass_info_fn(pbpctl_dev, (char *)&bpctl_cmd.data,
5615 (char *)&bpctl_cmd.out_param[4]);
5618 case IOCTL_TX_MSG(SET_TPL):
5620 set_tpl_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5623 case IOCTL_TX_MSG(GET_TPL):
5624 bpctl_cmd.status = get_tpl_fn(pbpctl_dev);
5626 case IOCTL_TX_MSG(SET_BP_WAIT_AT_PWUP):
5628 set_bp_wait_at_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5631 case IOCTL_TX_MSG(GET_BP_WAIT_AT_PWUP):
5632 bpctl_cmd.status = get_bp_wait_at_pwup_fn(pbpctl_dev);
5634 case IOCTL_TX_MSG(SET_BP_HW_RESET):
5636 set_bp_hw_reset_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5639 case IOCTL_TX_MSG(GET_BP_HW_RESET):
5640 bpctl_cmd.status = get_bp_hw_reset_fn(pbpctl_dev);
5643 case IOCTL_TX_MSG(SET_BP_SELF_TEST):
5645 set_bp_self_test_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5648 case IOCTL_TX_MSG(GET_BP_SELF_TEST):
5649 bpctl_cmd.status = get_bp_self_test_fn(pbpctl_dev);
5654 case IOCTL_TX_MSG(SET_DISC_PORT):
5656 set_disc_port_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5659 case IOCTL_TX_MSG(GET_DISC_PORT):
5660 bpctl_cmd.status = get_disc_port_fn(pbpctl_dev);
5663 case IOCTL_TX_MSG(SET_DISC_PORT_PWUP):
5665 set_disc_port_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5668 case IOCTL_TX_MSG(GET_DISC_PORT_PWUP):
5669 bpctl_cmd.status = get_disc_port_pwup_fn(pbpctl_dev);
5672 case IOCTL_TX_MSG(SET_BP_FORCE_LINK):
5674 set_bp_force_link_fn(dev_idx, bpctl_cmd.in_param[2]);
5677 case IOCTL_TX_MSG(GET_BP_FORCE_LINK):
5678 bpctl_cmd.status = get_bp_force_link_fn(dev_idx);
5682 /* unlock_bpctl(); */
5685 /* preempt_enable(); */
5686 /* rcu_read_unlock();*/
5687 spin_unlock_irqrestore(&bpvm_lock, flags);
5690 /* unlock_bpctl(); */
5691 /* preempt_enable(); */
5693 /* rcu_read_unlock(); */
5694 spin_unlock_irqrestore(&bpvm_lock, flags);
5695 if (copy_to_user(argp, (void *)&bpctl_cmd, sizeof(struct bpctl_cmd)))
5699 /* unlock_kernel(); */
5700 /* spin_unlock_irqrestore(&bpvm_lock, flags); */
5702 /* unlock_kernel(); */
5706 static const struct file_operations Fops = {
5707 .owner = THIS_MODULE,
5708 .unlocked_ioctl = device_ioctl,
5712 #define PCI_DEVICE(vend, dev) \
5713 .vendor = (vend), .device = (dev), \
5714 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
5717 #define SILICOM_E1000BP_ETHERNET_DEVICE(device_id) {\
5718 PCI_DEVICE(SILICOM_VID, device_id)}
5881 unsigned int vendor;
5882 unsigned int device;
5883 unsigned int subvendor;
5884 unsigned int subdevice;
5893 {"Silicom Bypass PXG2BPFI-SD series adapter"},
5894 {"Silicom Bypass PXG2BPFIL-SD series adapter"},
5895 {"Silicom Bypass PXG2BPFILX-SD series adapter"},
5896 {"Silicom Bypass PXG2BPFILLX-SD series adapter"},
5897 {"Silicom Bypass PXG2BPI-SD series adapter"},
5898 {"Silicom Bypass PXG2BPIG-SD series adapter"},
5899 {"Silicom Bypass PXG2TBFI-SD series adapter"},
5900 {"Silicom Bypass PXG4BPI-SD series adapter"},
5901 {"Silicom Bypass PXG4BPFI-SD series adapter"},
5902 {"Silicom Bypass PEG4BPI-SD series adapter"},
5903 {"Silicom Bypass PEG2BPI-SD series adapter"},
5904 {"Silicom Bypass PEG4BPIN-SD series adapter"},
5905 {"Silicom Bypass PEG2BPFI-SD series adapter"},
5906 {"Silicom Bypass PEG2BPFI-LX-SD series adapter"},
5907 {"Silicom Bypass PMCX2BPFI-SD series adapter"},
5908 {"Silicom Bypass PMCX2BPFI-N series adapter"},
5909 {"Intel Bypass PEG2BPII series adapter"},
5910 {"Intel Bypass PEG2BPFII series adapter"},
5911 {"Silicom Bypass PXG4BPFILX-SD series adapter"},
5912 {"Silicom Bypass PMCX2BPI-N series adapter"},
5913 {"Silicom Bypass PMCX4BPI-N series adapter"},
5914 {"Silicom Bypass PXG2BISC1-SD series adapter"},
5915 {"Silicom Bypass PEG2TBFI-SD series adapter"},
5916 {"Silicom Bypass PXG2TBI-SD series adapter"},
5917 {"Silicom Bypass PXG4BPFID-SD series adapter"},
5918 {"Silicom Bypass PEG4BPFI-SD series adapter"},
5919 {"Silicom Bypass PEG4BPIPT-SD series adapter"},
5920 {"Silicom Bypass PXG6BPI-SD series adapter"},
5921 {"Silicom Bypass PEG4BPIL-SD series adapter"},
5922 {"Silicom Bypass PMCX2BPI-N2 series adapter"},
5923 {"Silicom Bypass PMCX4BPI-N2 series adapter"},
5924 {"Silicom Bypass PMCX2BPI-SD series adapter"},
5925 {"Silicom Bypass PEG2BPFID-SD series adapter"},
5926 {"Silicom Bypass PEG2BPFIDLX-SD series adapter"},
5927 {"Silicom Bypass PMCX4BPI-SD series adapter"},
5928 {"Silicom Bypass MEG2BPFILN-SD series adapter"},
5929 {"Silicom Bypass MEG2BPFINX-SD series adapter"},
5930 {"Silicom Bypass PEG4BPFILX-SD series adapter"},
5931 {"Silicom Bypass PE10G2BPISR-SD series adapter"},
5932 {"Silicom Bypass PE10G2BPILR-SD series adapter"},
5933 {"Silicom Bypass MHIO8AD-SD series adapter"},
5934 {"Silicom Bypass PE10G2BPICX4-SD series adapter"},
5935 {"Silicom Bypass PEG2BPI5-SD series adapter"},
5936 {"Silicom Bypass PEG6BPI5-SD series adapter"},
5937 {"Silicom Bypass PEG4BPFI5-SD series adapter"},
5938 {"Silicom Bypass PEG4BPFI5LX-SD series adapter"},
5939 {"Silicom Bypass MEG2BPFILXLN-SD series adapter"},
5940 {"Silicom Bypass PEG2BPIX1-SD series adapter"},
5941 {"Silicom Bypass MEG2BPFILXNX-SD series adapter"},
5942 {"Silicom Bypass XE10G2BPIT-SD series adapter"},
5943 {"Silicom Bypass XE10G2BPICX4-SD series adapter"},
5944 {"Silicom Bypass XE10G2BPISR-SD series adapter"},
5945 {"Silicom Bypass XE10G2BPILR-SD series adapter"},
5946 {"Intel Bypass PEG2BPFII0 series adapter"},
5947 {"Silicom Bypass XE10G2BPIXR series adapter"},
5948 {"Silicom Bypass PE10G2DBISR series adapter"},
5949 {"Silicom Bypass PEG2BI5SC6 series adapter"},
5950 {"Silicom Bypass PEG6BPI5FC series adapter"},
5952 {"Silicom Bypass PE10G2BPTCX4 series adapter"},
5953 {"Silicom Bypass PE10G2BPTSR series adapter"},
5954 {"Silicom Bypass PE10G2BPTLR series adapter"},
5955 {"Silicom Bypass PE10G2BPTT series adapter"},
5956 {"Silicom Bypass PEG4BPI6 series adapter"},
5957 {"Silicom Bypass PEG4BPFI6 series adapter"},
5958 {"Silicom Bypass PEG4BPFI6LX series adapter"},
5959 {"Silicom Bypass PEG4BPFI6ZX series adapter"},
5960 {"Silicom Bypass PEG2BPI6 series adapter"},
5961 {"Silicom Bypass PEG2BPFI6 series adapter"},
5962 {"Silicom Bypass PEG2BPFI6LX series adapter"},
5963 {"Silicom Bypass PEG2BPFI6ZX series adapter"},
5964 {"Silicom Bypass PEG2BPFI6FLXM series adapter"},
5965 {"Silicom Bypass PEG4BPI6FC series adapter"},
5966 {"Silicom Bypass PEG4BPFI6FC series adapter"},
5967 {"Silicom Bypass PEG4BPFI6FCLX series adapter"},
5968 {"Silicom Bypass PEG4BPFI6FCZX series adapter"},
5969 {"Silicom Bypass PEG6BPI6 series adapter"},
5970 {"Silicom Bypass PEG2BPI6SC6 series adapter"},
5971 {"Silicom Bypass MEG2BPI6 series adapter"},
5972 {"Silicom Bypass XEG2BPI6 series adapter"},
5973 {"Silicom Bypass MEG4BPI6 series adapter"},
5974 {"Silicom Bypass PEG2BPFI5-SD series adapter"},
5975 {"Silicom Bypass PEG2BPFI5LX-SD series adapter"},
5976 {"Silicom Bypass PXEG4BPFI-SD series adapter"},
5977 {"Silicom Bypass MxEG2BPI6 series adapter"},
5978 {"Silicom Bypass MxEG2BPFI6 series adapter"},
5979 {"Silicom Bypass MxEG2BPFI6LX series adapter"},
5980 {"Silicom Bypass MxEG2BPFI6ZX series adapter"},
5981 {"Silicom Bypass MxEG4BPI6 series adapter"},
5982 {"Silicom Bypass MxEG4BPFI6 series adapter"},
5983 {"Silicom Bypass MxEG4BPFI6LX series adapter"},
5984 {"Silicom Bypass MxEG4BPFI6ZX series adapter"},
5985 {"Silicom Bypass MxEG6BPI6 series adapter"},
5986 {"Silicom Bypass MxE2G4BPi80 series adapter"},
5987 {"Silicom Bypass MxE2G4BPFi80 series adapter"},
5988 {"Silicom Bypass MxE2G4BPFi80LX series adapter"},
5989 {"Silicom Bypass MxE2G4BPFi80ZX series adapter"},
5991 {"Silicom Bypass PE210G2SPI9 series adapter"},
5993 {"Silicom Bypass MxE210G2BPI9CX4 series adapter"},
5994 {"Silicom Bypass MxE210G2BPI9SR series adapter"},
5995 {"Silicom Bypass MxE210G2BPI9LR series adapter"},
5996 {"Silicom Bypass MxE210G2BPI9T series adapter"},
5998 {"Silicom Bypass PE210G2BPI9CX4 series adapter"},
5999 {"Silicom Bypass PE210G2BPI9SR series adapter"},
6000 {"Silicom Bypass PE210G2BPI9LR series adapter"},
6001 {"Silicom Bypass PE210G2BPI9T series adapter"},
6003 {"Silicom Bypass M2EG2BPFI6 series adapter"},
6004 {"Silicom Bypass M2EG2BPFI6LX series adapter"},
6005 {"Silicom Bypass M2EG2BPFI6ZX series adapter"},
6006 {"Silicom Bypass M2EG4BPI6 series adapter"},
6007 {"Silicom Bypass M2EG4BPFI6 series adapter"},
6008 {"Silicom Bypass M2EG4BPFI6LX series adapter"},
6009 {"Silicom Bypass M2EG4BPFI6ZX series adapter"},
6010 {"Silicom Bypass M2EG6BPI6 series adapter"},
6012 {"Silicom Bypass PEG2DBI6 series adapter"},
6013 {"Silicom Bypass PEG2DBFI6 series adapter"},
6014 {"Silicom Bypass PEG2DBFI6LX series adapter"},
6015 {"Silicom Bypass PEG2DBFI6ZX series adapter"},
6017 {"Silicom Bypass PE2G4BPi80 series adapter"},
6018 {"Silicom Bypass PE2G4BPFi80 series adapter"},
6019 {"Silicom Bypass PE2G4BPFi80LX series adapter"},
6020 {"Silicom Bypass PE2G4BPFi80ZX series adapter"},
6022 {"Silicom Bypass PE2G4BPi80L series adapter"},
6023 {"Silicom Bypass MxE2G8BPi80A series adapter"},
6025 {"Silicom Bypass PE2G2BPi35 series adapter"},
6026 {"Silicom Bypass PAC1200BPi35 series adapter"},
6027 {"Silicom Bypass PE2G2BPFi35 series adapter"},
6028 {"Silicom Bypass PE2G2BPFi35LX series adapter"},
6029 {"Silicom Bypass PE2G2BPFi35ZX series adapter"},
6031 {"Silicom Bypass PE2G4BPi35 series adapter"},
6032 {"Silicom Bypass PE2G4BPi35L series adapter"},
6033 {"Silicom Bypass PE2G4BPFi35 series adapter"},
6034 {"Silicom Bypass PE2G4BPFi35LX series adapter"},
6035 {"Silicom Bypass PE2G4BPFi35ZX series adapter"},
6037 {"Silicom Bypass PE2G6BPi35 series adapter"},
6038 {"Silicom Bypass PE2G6BPi35CX series adapter"},
6040 {"Silicom Bypass PE2G2BPi80 series adapter"},
6041 {"Silicom Bypass PE2G2BPFi80 series adapter"},
6042 {"Silicom Bypass PE2G2BPFi80LX series adapter"},
6043 {"Silicom Bypass PE2G2BPFi80ZX series adapter"},
6045 {"Silicom Bypass M2E10G2BPI9CX4 series adapter"},
6046 {"Silicom Bypass M2E10G2BPI9SR series adapter"},
6047 {"Silicom Bypass M2E10G2BPI9LR series adapter"},
6048 {"Silicom Bypass M2E10G2BPI9T series adapter"},
6049 {"Silicom Bypass MxE2G8BPi80 series adapter"},
6050 {"Silicom Bypass PE210G2DBi9SR series adapter"},
6051 {"Silicom Bypass PE210G2DBi9SRRB series adapter"},
6052 {"Silicom Bypass PE210G2DBi9LR series adapter"},
6053 {"Silicom Bypass PE210G2DBi9LRRB series adapter"},
6054 {"Silicom Bypass PE310G4DBi9-SR series adapter"},
6055 {"Silicom Bypass PE310G4BPi9T series adapter"},
6056 {"Silicom Bypass PE310G4BPi9SR series adapter"},
6057 {"Silicom Bypass PE310G4BPi9LR series adapter"},
6058 {"Silicom Bypass PE210G2BPi40T series adapter"},
6062 static struct bpmod_info tx_ctl_pci_tbl[] = {
6063 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2BPFI_SSID, PXG2BPFI,
6065 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2BPFIL_SSID, PXG2BPFIL,
6067 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2BPFILX_SSID, PXG2BPFILX,
6069 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2BPFILLX_SSID, PXG2BPFILLX,
6071 {0x8086, 0x1010, SILICOM_SVID, SILICOM_PXGBPI_SSID, PXGBPI,
6073 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXGBPIG_SSID, PXGBPIG,
6075 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2TBFI_SSID, PXG2TBFI,
6077 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXG4BPI_SSID, PXG4BPI,
6079 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG4BPFI_SSID, PXG4BPFI,
6081 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG4BPFILX_SSID, PXG4BPFILX,
6083 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PEG4BPI_SSID, PEG4BPI,
6085 {0x8086, 0x105e, SILICOM_SVID, SILICOM_PEG2BPI_SSID, PEG2BPI,
6087 {0x8086, 0x105e, SILICOM_SVID, SILICOM_PEG4BPIN_SSID, PEG4BPIN,
6089 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2BPFI_SSID, PEG2BPFI,
6091 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2BPFILX_SSID, PEG2BPFILX,
6093 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PMCXG2BPFI_SSID, PMCXG2BPFI,
6095 {0x8086, 0x107a, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG2BPFIN_SSID,
6096 PMCXG2BPFIN, "PMCX2BPFI-N"},
6097 {0x8086, INTEL_PEG4BPII_PID, 0x8086, INTEL_PEG4BPII_SSID, PEG4BPII,
6099 {0x8086, INTEL_PEG4BPIIO_PID, 0x8086, INTEL_PEG4BPIIO_SSID, PEG4BPIIO,
6101 {0x8086, INTEL_PEG4BPFII_PID, 0x8086, INTEL_PEG4BPFII_SSID, PEG4BPFII,
6103 {0x8086, 0x1079, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG2BPIN_SSID,
6104 PMCXG2BPIN, "PMCX2BPI-N"},
6105 {0x8086, 0x1079, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG4BPIN_SSID,
6106 PMCXG4BPIN, "PMCX4BPI-N"},
6107 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXG2BISC1_SSID, PXG2BISC1,
6109 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2TBFI_SSID, PEG2TBFI,
6111 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXG2TBI_SSID, PXG2TBI,
6113 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG4BPFID_SSID, PXG4BPFID,
6115 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG4BPFI_SSID, PEG4BPFI,
6117 {0x8086, 0x105e, SILICOM_SVID, SILICOM_PEG4BPIPT_SSID, PEG4BPIPT,
6119 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXG6BPI_SSID, PXG6BPI,
6121 {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
6122 SILICOM_PEG4BPIL_SSID /*PCI_ANY_ID */ , PEG4BPIL, "PEG4BPIL-SD"},
6123 {0x8086, 0x1079, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG2BPIN2_SSID,
6124 PMCXG2BPIN2, "PMCX2BPI-N2"},
6125 {0x8086, 0x1079, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG4BPIN2_SSID,
6126 PMCXG4BPIN2, "PMCX4BPI-N2"},
6127 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PMCX2BPI_SSID, PMCX2BPI,
6129 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PMCX4BPI_SSID, PMCX4BPI,
6131 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2BPFID_SSID, PEG2BPFID,
6133 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2BPFIDLX_SSID, PEG2BPFIDLX,
6135 {0x8086, 0x105f, SILICOM_SVID, SILICOM_MEG2BPFILN_SSID, MEG2BPFILN,
6137 {0x8086, 0x105f, SILICOM_SVID, SILICOM_MEG2BPFINX_SSID, MEG2BPFINX,
6139 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG4BPFILX_SSID, PEG4BPFILX,
6141 {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_PE10G2BPISR_SSID,
6142 PE10G2BPISR, "PE10G2BPISR"},
6143 {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_PE10G2BPILR_SSID,
6144 PE10G2BPILR, "PE10G2BPILR"},
6145 {0x8086, 0x10a9, SILICOM_SVID, SILICOM_MHIO8AD_SSID, MHIO8AD,
6147 {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_PE10G2BPICX4_SSID,
6148 PE10G2BPISR, "PE10G2BPICX4"},
6149 {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
6150 SILICOM_PEG2BPI5_SSID /*PCI_ANY_ID */ , PEG2BPI5, "PEG2BPI5-SD"},
6151 {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
6152 SILICOM_PEG6BPI_SSID /*PCI_ANY_ID */ , PEG6BPI, "PEG6BPI5"},
6153 {0x8086, 0x10a9, SILICOM_SVID /*PCI_ANY_ID */ , SILICOM_PEG4BPFI5_SSID,
6154 PEG4BPFI5, "PEG4BPFI5"},
6155 {0x8086, 0x10a9, SILICOM_SVID /*PCI_ANY_ID */ ,
6156 SILICOM_PEG4BPFI5LX_SSID, PEG4BPFI5LX, "PEG4BPFI5LX"},
6157 {0x8086, 0x105f, SILICOM_SVID, SILICOM_MEG2BPFILXLN_SSID, MEG2BPFILXLN,
6159 {0x8086, 0x105e, SILICOM_SVID, SILICOM_PEG2BPIX1_SSID, PEG2BPIX1,
6161 {0x8086, 0x105f, SILICOM_SVID, SILICOM_MEG2BPFILXNX_SSID, MEG2BPFILXNX,
6163 {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_XE10G2BPIT_SSID, XE10G2BPIT,
6165 {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_XE10G2BPICX4_SSID,
6166 XE10G2BPICX4, "XE10G2BPICX4"},
6167 {0x8086, 0x10C6, SILICOM_SVID, SILICOM_XE10G2BPISR_SSID, XE10G2BPISR,
6169 {0x8086, 0x10C6, SILICOM_SVID, SILICOM_XE10G2BPILR_SSID, XE10G2BPILR,
6171 {0x8086, 0x10C6, NOKIA_XE10G2BPIXR_SVID, NOKIA_XE10G2BPIXR_SSID,
6172 XE10G2BPIXR, "XE10G2BPIXR"},
6173 {0x8086, 0x10C6, SILICOM_SVID, SILICOM_PE10GDBISR_SSID, PE10GDBISR,
6175 {0x8086, 0x10C6, SILICOM_SVID, SILICOM_PE10GDBILR_SSID, PE10GDBILR,
6177 {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
6178 SILICOM_PEG2BISC6_SSID /*PCI_ANY_ID */ , PEG2BISC6, "PEG2BI5SC6"},
6179 {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
6180 SILICOM_PEG6BPIFC_SSID /*PCI_ANY_ID */ , PEG6BPIFC, "PEG6BPI5FC"},
6182 {BROADCOM_VID, BROADCOM_PE10G2_PID, SILICOM_SVID,
6183 SILICOM_PE10G2BPTCX4_SSID, PE10G2BPTCX4, "PE10G2BPTCX4"},
6184 {BROADCOM_VID, BROADCOM_PE10G2_PID, SILICOM_SVID,
6185 SILICOM_PE10G2BPTSR_SSID, PE10G2BPTSR, "PE10G2BPTSR"},
6186 {BROADCOM_VID, BROADCOM_PE10G2_PID, SILICOM_SVID,
6187 SILICOM_PE10G2BPTLR_SSID, PE10G2BPTLR, "PE10G2BPTLR"},
6188 {BROADCOM_VID, BROADCOM_PE10G2_PID, SILICOM_SVID,
6189 SILICOM_PE10G2BPTT_SSID, PE10G2BPTT, "PE10G2BPTT"},
6191 /* {BROADCOM_VID, BROADCOM_PE10G2_PID, PCI_ANY_ID, PCI_ANY_ID, PE10G2BPTCX4, "PE10G2BPTCX4"}, */
6193 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6194 SILICOM_PEG4BPI6_SSID /*PCI_ANY_ID */ , PEG4BPI6, "PEG4BPI6"},
6195 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6196 SILICOM_PEG4BPFI6_SSID /*PCI_ANY_ID */ , PEG4BPFI6, "PEG4BPFI6"},
6197 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6198 SILICOM_PEG4BPFI6LX_SSID /*PCI_ANY_ID */ , PEG4BPFI6LX, "PEG4BPFI6LX"},
6199 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6200 SILICOM_PEG4BPFI6ZX_SSID /*PCI_ANY_ID */ , PEG4BPFI6ZX, "PEG4BPFI6ZX"},
6201 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6202 SILICOM_PEG2BPI6_SSID /*PCI_ANY_ID */ , PEG2BPI6, "PEG2BPI6"},
6203 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6204 SILICOM_PEG2BPFI6_SSID /*PCI_ANY_ID */ , PEG2BPFI6, "PEG2BPFI6"},
6205 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6206 SILICOM_PEG2BPFI6LX_SSID /*PCI_ANY_ID */ , PEG2BPFI6LX, "PEG2BPFI6LX"},
6207 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6208 SILICOM_PEG2BPFI6ZX_SSID /*PCI_ANY_ID */ , PEG2BPFI6ZX, "PEG2BPFI6ZX"},
6209 {0x8086, 0x10e7, SILICOM_SVID /*PCI_ANY_ID */ ,
6210 SILICOM_PEG2BPFI6FLXM_SSID /*PCI_ANY_ID */ , PEG2BPFI6FLXM,
6212 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6213 SILICOM_PEG4BPI6FC_SSID /*PCI_ANY_ID */ , PEG4BPI6FC, "PEG4BPI6FC"},
6214 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6215 SILICOM_PEG4BPFI6FC_SSID /*PCI_ANY_ID */ , PEG4BPFI6FC, "PEG4BPFI6FC"},
6216 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6217 SILICOM_PEG4BPFI6FCLX_SSID /*PCI_ANY_ID */ , PEG4BPFI6FCLX,
6219 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6220 SILICOM_PEG4BPFI6FCZX_SSID /*PCI_ANY_ID */ , PEG4BPFI6FCZX,
6222 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6223 SILICOM_PEG6BPI6_SSID /*PCI_ANY_ID */ , PEG6BPI6, "PEG6BPI6"},
6224 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6225 SILICOM_PEG2BPI6SC6_SSID /*PCI_ANY_ID */ , PEG2BPI6SC6,
6227 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6228 SILICOM_MEG2BPI6_SSID /*PCI_ANY_ID */ , MEG2BPI6, "MEG2BPI6"},
6229 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6230 SILICOM_XEG2BPI6_SSID /*PCI_ANY_ID */ , XEG2BPI6, "XEG2BPI6"},
6231 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6232 SILICOM_MEG4BPI6_SSID /*PCI_ANY_ID */ , MEG4BPI6, "MEG4BPI6"},
6234 {0x8086, 0x10a9, SILICOM_SVID /*PCI_ANY_ID */ , SILICOM_PEG2BPFI5_SSID,
6235 PEG2BPFI5, "PEG2BPFI5"},
6236 {0x8086, 0x10a9, SILICOM_SVID /*PCI_ANY_ID */ ,
6237 SILICOM_PEG2BPFI5LX_SSID, PEG2BPFI5LX, "PEG2BPFI5LX"},
6239 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PXEG4BPFI_SSID, PXEG4BPFI,
6242 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6243 SILICOM_M1EG2BPI6_SSID /*PCI_ANY_ID */ , M1EG2BPI6, "MxEG2BPI6"},
6245 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6246 SILICOM_M1EG2BPFI6_SSID /*PCI_ANY_ID */ , M1EG2BPFI6, "MxEG2BPFI6"},
6247 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6248 SILICOM_M1EG2BPFI6LX_SSID /*PCI_ANY_ID */ , M1EG2BPFI6LX,
6250 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6251 SILICOM_M1EG2BPFI6ZX_SSID /*PCI_ANY_ID */ , M1EG2BPFI6ZX,
6254 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6255 SILICOM_M1EG4BPI6_SSID /*PCI_ANY_ID */ , M1EG4BPI6, "MxEG4BPI6"},
6257 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6258 SILICOM_M1EG4BPFI6_SSID /*PCI_ANY_ID */ , M1EG4BPFI6, "MxEG4BPFI6"},
6259 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6260 SILICOM_M1EG4BPFI6LX_SSID /*PCI_ANY_ID */ , M1EG4BPFI6LX,
6262 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6263 SILICOM_M1EG4BPFI6ZX_SSID /*PCI_ANY_ID */ , M1EG4BPFI6ZX,
6266 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6267 SILICOM_M1EG6BPI6_SSID /*PCI_ANY_ID */ , M1EG6BPI6, "MxEG6BPI6"},
6269 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6270 SILICOM_M1E2G4BPi80_SSID /*PCI_ANY_ID */ , M1E2G4BPi80, "MxE2G4BPi80"},
6271 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6272 SILICOM_M1E2G4BPFi80_SSID /*PCI_ANY_ID */ , M1E2G4BPFi80,
6274 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6275 SILICOM_M1E2G4BPFi80LX_SSID /*PCI_ANY_ID */ , M1E2G4BPFi80LX,
6277 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6278 SILICOM_M1E2G4BPFi80ZX_SSID /*PCI_ANY_ID */ , M1E2G4BPFi80ZX,
6281 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6282 SILICOM_M2EG2BPFI6_SSID /*PCI_ANY_ID */ , M2EG2BPFI6, "M2EG2BPFI6"},
6283 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6284 SILICOM_M2EG2BPFI6LX_SSID /*PCI_ANY_ID */ , M2EG2BPFI6LX,
6286 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6287 SILICOM_M2EG2BPFI6ZX_SSID /*PCI_ANY_ID */ , M2EG2BPFI6ZX,
6290 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6291 SILICOM_M2EG4BPI6_SSID /*PCI_ANY_ID */ , M2EG4BPI6, "M2EG4BPI6"},
6293 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6294 SILICOM_M2EG4BPFI6_SSID /*PCI_ANY_ID */ , M2EG4BPFI6, "M2EG4BPFI6"},
6295 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6296 SILICOM_M2EG4BPFI6LX_SSID /*PCI_ANY_ID */ , M2EG4BPFI6LX,
6298 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6299 SILICOM_M2EG4BPFI6ZX_SSID /*PCI_ANY_ID */ , M2EG4BPFI6ZX,
6302 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6303 SILICOM_M2EG6BPI6_SSID /*PCI_ANY_ID */ , M2EG6BPI6, "M2EG6BPI6"},
6305 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6306 SILICOM_PEG2DBI6_SSID /*PCI_ANY_ID */ , PEG2DBI6, "PEG2DBI6"},
6307 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6308 SILICOM_PEG2DBFI6_SSID /*PCI_ANY_ID */ , PEG2DBFI6, "PEG2DBFI6"},
6309 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6310 SILICOM_PEG2DBFI6LX_SSID /*PCI_ANY_ID */ , PEG2DBFI6LX, "PEG2DBFI6LX"},
6311 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6312 SILICOM_PEG2DBFI6ZX_SSID /*PCI_ANY_ID */ , PEG2DBFI6ZX, "PEG2DBFI6ZX"},
6314 {0x8086, 0x10F9, SILICOM_SVID /*PCI_ANY_ID */ ,
6315 SILICOM_PE210G2DBi9SR_SSID, PE210G2DBi9SR, "PE210G2DBi9SR"},
6316 {0x8086, 0x10F9, SILICOM_SVID /*PCI_ANY_ID */ ,
6317 SILICOM_PE210G2DBi9LR_SSID, PE210G2DBi9LR, "PE210G2DBi9LR"},
6318 {0x8086, 0x10F9, SILICOM_SVID /*PCI_ANY_ID */ ,
6319 SILICOM_PE310G4DBi940SR_SSID, PE310G4DBi940SR, "PE310G4DBi9SR"},
6321 {0x8086, 0x10Fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6322 SILICOM_PE310G4BPi9T_SSID, PE310G4BPi9T, "PE310G4BPi9T"},
6323 {0x8086, 0x10Fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6324 SILICOM_PE310G4BPi9SR_SSID, PE310G4BPi9SR, "PE310G4BPi9SR"},
6325 {0x8086, 0x10Fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6326 SILICOM_PE310G4BPi9LR_SSID, PE310G4BPi9LR, "PE310G4BPi9LR"},
6328 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6329 SILICOM_PE2G4BPi80_SSID /*PCI_ANY_ID */ , PE2G4BPi80, "PE2G4BPi80"},
6330 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6331 SILICOM_PE2G4BPFi80_SSID /*PCI_ANY_ID */ , PE2G4BPFi80, "PE2G4BPFi80"},
6332 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6333 SILICOM_PE2G4BPFi80LX_SSID /*PCI_ANY_ID */ , PE2G4BPFi80LX,
6335 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6336 SILICOM_PE2G4BPFi80ZX_SSID /*PCI_ANY_ID */ , PE2G4BPFi80ZX,
6339 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6340 SILICOM_PE2G4BPi80L_SSID /*PCI_ANY_ID */ , PE2G4BPi80L, "PE2G4BPi80L"},
6342 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6343 SILICOM_M6E2G8BPi80A_SSID /*PCI_ANY_ID */ , M6E2G8BPi80A,
6346 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6347 SILICOM_PE2G2BPi35_SSID /*PCI_ANY_ID */ , PE2G2BPi35, "PE2G2BPi35"},
6348 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6349 SILICOM_PAC1200BPi35_SSID /*PCI_ANY_ID */ , PAC1200BPi35,
6352 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6353 SILICOM_PE2G2BPFi35_SSID /*PCI_ANY_ID */ , PE2G2BPFi35, "PE2G2BPFi35"},
6354 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6355 SILICOM_PE2G2BPFi35LX_SSID /*PCI_ANY_ID */ , PE2G2BPFi35LX,
6357 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6358 SILICOM_PE2G2BPFi35ZX_SSID /*PCI_ANY_ID */ , PE2G2BPFi35ZX,
6361 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6362 SILICOM_PE2G4BPi35_SSID /*PCI_ANY_ID */ , PE2G4BPi35, "PE2G4BPi35"},
6364 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6365 SILICOM_PE2G4BPi35L_SSID /*PCI_ANY_ID */ , PE2G4BPi35L, "PE2G4BPi35L"},
6367 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6368 SILICOM_PE2G4BPFi35_SSID /*PCI_ANY_ID */ , PE2G4BPFi35, "PE2G4BPFi35"},
6369 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6370 SILICOM_PE2G4BPFi35LX_SSID /*PCI_ANY_ID */ , PE2G4BPFi35LX,
6372 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6373 SILICOM_PE2G4BPFi35ZX_SSID /*PCI_ANY_ID */ , PE2G4BPFi35ZX,
6376 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6377 SILICOM_PE2G6BPi35_SSID /*PCI_ANY_ID */ , PE2G6BPi35, "PE2G6BPi35"},
6380 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa0, PE2G6BPi35CX,
6382 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa1, PE2G6BPi35CX,
6384 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa2, PE2G6BPi35CX,
6386 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa3, PE2G6BPi35CX,
6388 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa4, PE2G6BPi35CX,
6390 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa5, PE2G6BPi35CX,
6392 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa6, PE2G6BPi35CX,
6394 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa7, PE2G6BPi35CX,
6396 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa8, PE2G6BPi35CX,
6398 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa9, PE2G6BPi35CX,
6400 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaaa, PE2G6BPi35CX,
6402 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaab, PE2G6BPi35CX,
6404 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaac, PE2G6BPi35CX,
6406 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaad, PE2G6BPi35CX,
6408 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaae, PE2G6BPi35CX,
6410 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaaf, PE2G6BPi35CX,
6412 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab0, PE2G6BPi35CX,
6414 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab1, PE2G6BPi35CX,
6416 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab2, PE2G6BPi35CX,
6418 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab3, PE2G6BPi35CX,
6420 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab4, PE2G6BPi35CX,
6422 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab5, PE2G6BPi35CX,
6424 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab6, PE2G6BPi35CX,
6426 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab7, PE2G6BPi35CX,
6428 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab8, PE2G6BPi35CX,
6430 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab9, PE2G6BPi35CX,
6432 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaba, PE2G6BPi35CX,
6434 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabb, PE2G6BPi35CX,
6436 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabc, PE2G6BPi35CX,
6438 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabd, PE2G6BPi35CX,
6440 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabe, PE2G6BPi35CX,
6442 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabf, PE2G6BPi35CX,
6445 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6446 SILICOM_PE2G2BPi80_SSID /*PCI_ANY_ID */ , PE2G2BPi80, "PE2G2BPi80"},
6447 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6448 SILICOM_PE2G2BPFi80_SSID /*PCI_ANY_ID */ , PE2G2BPFi80, "PE2G2BPFi80"},
6449 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6450 SILICOM_PE2G2BPFi80LX_SSID /*PCI_ANY_ID */ , PE2G2BPFi80LX,
6452 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6453 SILICOM_PE2G2BPFi80ZX_SSID /*PCI_ANY_ID */ , PE2G2BPFi80ZX,
6456 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6457 SILICOM_MEG2BPI6_SSID /*PCI_ANY_ID */ , MEG2BPI6, "MEG2BPI6"},
6458 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6459 SILICOM_XEG2BPI6_SSID /*PCI_ANY_ID */ , XEG2BPI6, "XEG2BPI6"},
6462 {0x8086, 0x10fb, 0x8086, INTEL_PE210G2SPI9_SSID, PE210G2SPI9,
6465 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6466 SILICOM_M1E10G2BPI9CX4_SSID /*PCI_ANY_ID */ , M1E10G2BPI9CX4,
6468 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6469 SILICOM_M1E10G2BPI9SR_SSID /*PCI_ANY_ID */ , M1E10G2BPI9SR,
6471 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6472 SILICOM_M1E10G2BPI9LR_SSID /*PCI_ANY_ID */ , M1E10G2BPI9LR,
6474 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6475 SILICOM_M1E10G2BPI9T_SSID /*PCI_ANY_ID */ , M1E10G2BPI9T,
6478 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6479 SILICOM_M2E10G2BPI9CX4_SSID /*PCI_ANY_ID */ , M2E10G2BPI9CX4,
6481 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6482 SILICOM_M2E10G2BPI9SR_SSID /*PCI_ANY_ID */ , M2E10G2BPI9SR,
6484 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6485 SILICOM_M2E10G2BPI9LR_SSID /*PCI_ANY_ID */ , M2E10G2BPI9LR,
6487 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6488 SILICOM_M2E10G2BPI9T_SSID /*PCI_ANY_ID */ , M2E10G2BPI9T,
6491 {0x8086, 0x10fb, SILICOM_SVID, SILICOM_PE210G2BPI9CX4_SSID,
6492 PE210G2BPI9CX4, "PE210G2BPI9CX4"},
6493 {0x8086, 0x10fb, SILICOM_SVID, SILICOM_PE210G2BPI9SR_SSID,
6494 PE210G2BPI9SR, "PE210G2BPI9SR"},
6495 {0x8086, 0x10fb, SILICOM_SVID, SILICOM_PE210G2BPI9LR_SSID,
6496 PE210G2BPI9LR, "PE210G2BPI9LR"},
6497 {0x8086, 0x10fb, SILICOM_SVID, SILICOM_PE210G2BPI9T_SSID, PE210G2BPI9T,
6501 {0x1374, 0x2c, SILICOM_SVID, SILICOM_PXG4BPI_SSID, PXG4BPI,
6504 {0x1374, 0x2d, SILICOM_SVID, SILICOM_PXG4BPFI_SSID, PXG4BPFI,
6507 {0x1374, 0x3f, SILICOM_SVID, SILICOM_PXG2TBI_SSID, PXG2TBI,
6510 {0x1374, 0x3d, SILICOM_SVID, SILICOM_PXG2BISC1_SSID, PXG2BISC1,
6513 {0x1374, 0x40, SILICOM_SVID, SILICOM_PEG4BPFI_SSID, PEG4BPFI,
6517 {0x1374, 0x28, SILICOM_SVID, 0x28, PXGBPI, "PXG2BPI-SD"},
6520 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6521 SILICOM_M6E2G8BPi80_SSID /*PCI_ANY_ID */ , M6E2G8BPi80, "MxE2G8BPi80"},
6522 {0x8086, 0x1528, SILICOM_SVID /*PCI_ANY_ID */ ,
6523 SILICOM_PE210G2BPi40_SSID /*PCI_ANY_ID */ , PE210G2BPi40,
6526 /* required last entry */
6530 static void find_fw(struct bpctl_dev *dev)
6532 unsigned long mmio_start, mmio_len;
6533 struct pci_dev *pdev1 = dev->pdev;
6535 if ((OLD_IF_SERIES(dev->subdevice)) ||
6536 (INTEL_IF_SERIES(dev->subdevice)))
6537 dev->bp_fw_ver = 0xff;
6539 dev->bp_fw_ver = bypass_fw_ver(dev);
6541 if (dev->bp_10gb == 1 && dev->bp_fw_ver == 0xff) {
6544 iounmap((void *)dev->mem_map);
6545 mmio_start = pci_resource_start(pdev1, 0);
6546 mmio_len = pci_resource_len(pdev1, 0);
6548 dev->mem_map = (unsigned long)
6549 ioremap(mmio_start, mmio_len);
6551 dev->bp_fw_ver = bypass_fw_ver(dev);
6552 if (dev->bp_fw_ver == 0xa8)
6556 /* dev->bp_fw_ver=0xa8; */
6557 printk("firmware version: 0x%x\n", dev->bp_fw_ver);
6560 static int init_one(struct bpctl_dev *dev, struct bpmod_info *info, struct pci_dev *pdev1)
6562 unsigned long mmio_start, mmio_len;
6565 mmio_start = pci_resource_start(pdev1, 0);
6566 mmio_len = pci_resource_len(pdev1, 0);
6568 dev->desc = dev_desc[info->index].name;
6569 dev->name = info->bp_name;
6570 dev->device = info->device;
6571 dev->vendor = info->vendor;
6572 dev->subdevice = info->subdevice;
6573 dev->subvendor = info->subvendor;
6574 dev->func = PCI_FUNC(pdev1->devfn);
6575 dev->slot = PCI_SLOT(pdev1->devfn);
6576 dev->bus = pdev1->bus->number;
6577 dev->mem_map = (unsigned long)ioremap(mmio_start, mmio_len);
6579 spin_lock_init(&dev->bypass_wr_lock);
6581 if (BP10G9_IF_SERIES(dev->subdevice))
6583 if (BP10G_IF_SERIES(dev->subdevice))
6585 if (PEG540_IF_SERIES(dev->subdevice))
6587 if (PEGF5_IF_SERIES(dev->subdevice))
6589 if (PEG80_IF_SERIES(dev->subdevice))
6591 if (PEGF80_IF_SERIES(dev->subdevice))
6593 if ((dev->subdevice & 0xa00) == 0xa00)
6595 if (BP10GB_IF_SERIES(dev->subdevice)) {
6596 if (dev->ifindex == 0) {
6597 unregister_chrdev(major_num, DEVICE_NAME);
6598 printk("Please load network driver for %s adapter!\n",
6603 if (dev->ndev && !(dev->ndev->flags & IFF_UP)) {
6604 unregister_chrdev(major_num, DEVICE_NAME);
6605 printk("Please bring up network interfaces for %s adapter!\n",
6612 if (!dev->bp_10g9) {
6613 if (is_bypass_fn(dev)) {
6614 printk(KERN_INFO "%s found, ",
6618 dev->wdt_status = WDT_STATUS_UNKNOWN;
6619 dev->reset_time = 0;
6620 atomic_set(&dev->wdt_busy, 0);
6621 dev->bp_status_un = 1;
6623 bypass_caps_init(dev);
6625 init_bypass_wd_auto(dev);
6626 init_bypass_tpl_auto(dev);
6627 if (NOKIA_SERIES(dev->subdevice))
6631 dev->bp_tx_data = kzalloc(BPTEST_DATA_LEN, GFP_KERNEL);
6632 if (dev->bp_tx_data) {
6633 memset(dev->bp_tx_data, 0xff, 6);
6634 memset(dev->bp_tx_data + 6, 0x0, 1);
6635 memset(dev->bp_tx_data + 7, 0xaa, 5);
6636 *(__be16 *)(dev->bp_tx_data + 12) = htons(ETH_P_BPTEST);
6638 printk("bp_ctl: Memory allocation error!\n");
6644 * Initialize the module - Register the character device
6647 static int __init bypass_init_module(void)
6649 int ret_val, idx, idx_dev = 0;
6650 struct pci_dev *pdev1 = NULL;
6651 struct bpctl_dev *dev;
6653 printk(BP_MOD_DESCR " v" BP_MOD_VER "\n");
6654 ret_val = register_chrdev(major_num, DEVICE_NAME, &Fops);
6656 printk("%s failed with %d\n", DEVICE_NAME, ret_val);
6659 major_num = ret_val; /* dynamic */
6660 for (idx = 0; tx_ctl_pci_tbl[idx].vendor; idx++) {
6661 while ((pdev1 = pci_get_subsys(tx_ctl_pci_tbl[idx].vendor,
6662 tx_ctl_pci_tbl[idx].device,
6663 tx_ctl_pci_tbl[idx].subvendor,
6664 tx_ctl_pci_tbl[idx].subdevice,
6671 printk("No such device\n");
6672 unregister_chrdev(major_num, DEVICE_NAME);
6676 bpctl_dev_arr = kmalloc((device_num) * sizeof(struct bpctl_dev), GFP_KERNEL);
6678 if (!bpctl_dev_arr) {
6679 printk("Allocation error\n");
6680 unregister_chrdev(major_num, DEVICE_NAME);
6683 memset(bpctl_dev_arr, 0, ((device_num) * sizeof(struct bpctl_dev)));
6686 dev = bpctl_dev_arr;
6687 for (idx = 0; tx_ctl_pci_tbl[idx].vendor; idx++) {
6688 while ((pdev1 = pci_get_subsys(tx_ctl_pci_tbl[idx].vendor,
6689 tx_ctl_pci_tbl[idx].device,
6690 tx_ctl_pci_tbl[idx].subvendor,
6691 tx_ctl_pci_tbl[idx].subdevice,
6693 if (init_one(dev, &tx_ctl_pci_tbl[idx], pdev1) < 0)
6700 sema_init(&bpctl_sema, 1);
6701 spin_lock_init(&bpvm_lock);
6704 struct bpctl_dev *pbpctl_dev_c = NULL;
6705 for (idx_dev = 0, dev = bpctl_dev_arr;
6706 idx_dev < device_num && dev->pdev;
6709 pbpctl_dev_c = get_status_port_fn(dev);
6710 if (is_bypass_fn(dev)) {
6711 printk(KERN_INFO "%s found, ",
6713 dev->bp_fw_ver = bypass_fw_ver(dev);
6714 printk("firmware version: 0x%x\n",
6717 dev->wdt_status = WDT_STATUS_UNKNOWN;
6718 dev->reset_time = 0;
6719 atomic_set(&dev->wdt_busy, 0);
6720 dev->bp_status_un = 1;
6722 bypass_caps_init(dev);
6724 init_bypass_wd_auto(dev);
6725 init_bypass_tpl_auto(dev);
6732 register_netdevice_notifier(&bp_notifier_block);
6733 #ifdef BP_PROC_SUPPORT
6736 /* unsigned long flags; */
6737 /* rcu_read_lock(); */
6739 for (i = 0; i < device_num; i++) {
6740 if (bpctl_dev_arr[i].ifindex) {
6741 /* spin_lock_irqsave(&bpvm_lock, flags); */
6742 bypass_proc_remove_dev_sd(&bpctl_dev_arr[i]);
6743 bypass_proc_create_dev_sd(&bpctl_dev_arr[i]);
6744 /* spin_unlock_irqrestore(&bpvm_lock, flags); */
6748 /* rcu_read_unlock(); */
6756 * Cleanup - unregister the appropriate file from /proc
6758 static void __exit bypass_cleanup_module(void)
6761 unregister_netdevice_notifier(&bp_notifier_block);
6763 for (i = 0; i < device_num; i++) {
6764 /* unsigned long flags; */
6765 #ifdef BP_PROC_SUPPORT
6766 /* spin_lock_irqsave(&bpvm_lock, flags);
6768 bypass_proc_remove_dev_sd(&bpctl_dev_arr[i]);
6769 /* spin_unlock_irqrestore(&bpvm_lock, flags);
6770 rcu_read_unlock(); */
6772 remove_bypass_wd_auto(&bpctl_dev_arr[i]);
6773 bpctl_dev_arr[i].reset_time = 0;
6775 remove_bypass_tpl_auto(&bpctl_dev_arr[i]);
6778 /* unmap all devices */
6779 for (i = 0; i < device_num; i++) {
6781 kfree(bpctl_dev_arr[i].bp_tx_data);
6783 iounmap((void *)(bpctl_dev_arr[i].mem_map));
6786 /* free all devices space */
6787 kfree(bpctl_dev_arr);
6790 * Unregister the device
6792 unregister_chrdev(major_num, DEVICE_NAME);
6795 module_init(bypass_init_module);
6796 module_exit(bypass_cleanup_module);
6798 int is_bypass_sd(int ifindex)
6800 return is_bypass(get_dev_idx_p(ifindex));
6802 EXPORT_SYMBOL(is_bypass_sd);
6804 int set_bypass_sd(int ifindex, int bypass_mode)
6807 return set_bypass_fn(get_dev_idx_p(ifindex), bypass_mode);
6809 EXPORT_SYMBOL(set_bypass_sd);
6811 int get_bypass_sd(int ifindex)
6814 return get_bypass_fn(get_dev_idx_p(ifindex));
6816 EXPORT_SYMBOL(get_bypass_sd);
6818 int get_bypass_change_sd(int ifindex)
6821 return get_bypass_change_fn(get_dev_idx_p(ifindex));
6823 EXPORT_SYMBOL(get_bypass_change_sd);
6825 int set_dis_bypass_sd(int ifindex, int dis_param)
6827 return set_dis_bypass_fn(get_dev_idx_p(ifindex), dis_param);
6829 EXPORT_SYMBOL(set_dis_bypass_sd);
6831 int get_dis_bypass_sd(int ifindex)
6834 return get_dis_bypass_fn(get_dev_idx_p(ifindex));
6836 EXPORT_SYMBOL(get_dis_bypass_sd);
6838 int set_bypass_pwoff_sd(int ifindex, int bypass_mode)
6840 return set_bypass_pwoff_fn(get_dev_idx_p(ifindex), bypass_mode);
6843 EXPORT_SYMBOL(set_bypass_pwoff_sd);
6845 int get_bypass_pwoff_sd(int ifindex)
6847 return get_bypass_pwoff_fn(get_dev_idx_p(ifindex));
6850 EXPORT_SYMBOL(get_bypass_pwoff_sd);
6852 int set_bypass_pwup_sd(int ifindex, int bypass_mode)
6854 return set_bypass_pwup_fn(get_dev_idx_p(ifindex), bypass_mode);
6857 EXPORT_SYMBOL(set_bypass_pwup_sd);
6859 int get_bypass_pwup_sd(int ifindex)
6861 return get_bypass_pwup_fn(get_dev_idx_p(ifindex));
6864 EXPORT_SYMBOL(get_bypass_pwup_sd);
6866 int set_bypass_wd_sd(int if_index, int ms_timeout, int *ms_timeout_set)
6868 if ((is_bypass(get_dev_idx_p(if_index))) <= 0)
6870 *ms_timeout_set = set_bypass_wd_fn(get_dev_idx_p(if_index), ms_timeout);
6873 EXPORT_SYMBOL(set_bypass_wd_sd);
6875 int get_bypass_wd_sd(int ifindex, int *timeout)
6877 return get_bypass_wd_fn(get_dev_idx_p(ifindex), timeout);
6880 EXPORT_SYMBOL(get_bypass_wd_sd);
6882 int get_wd_expire_time_sd(int ifindex, int *time_left)
6884 return get_wd_expire_time_fn(get_dev_idx_p(ifindex), time_left);
6886 EXPORT_SYMBOL(get_wd_expire_time_sd);
6888 int reset_bypass_wd_timer_sd(int ifindex)
6890 return reset_bypass_wd_timer_fn(get_dev_idx_p(ifindex));
6893 EXPORT_SYMBOL(reset_bypass_wd_timer_sd);
6895 int get_wd_set_caps_sd(int ifindex)
6897 return get_wd_set_caps_fn(get_dev_idx_p(ifindex));
6900 EXPORT_SYMBOL(get_wd_set_caps_sd);
6902 int set_std_nic_sd(int ifindex, int nic_mode)
6904 return set_std_nic_fn(get_dev_idx_p(ifindex), nic_mode);
6907 EXPORT_SYMBOL(set_std_nic_sd);
6909 int get_std_nic_sd(int ifindex)
6911 return get_std_nic_fn(get_dev_idx_p(ifindex));
6914 EXPORT_SYMBOL(get_std_nic_sd);
6916 int set_tap_sd(int ifindex, int tap_mode)
6918 return set_tap_fn(get_dev_idx_p(ifindex), tap_mode);
6921 EXPORT_SYMBOL(set_tap_sd);
6923 int get_tap_sd(int ifindex)
6925 return get_tap_fn(get_dev_idx_p(ifindex));
6928 EXPORT_SYMBOL(get_tap_sd);
6930 int set_tap_pwup_sd(int ifindex, int tap_mode)
6932 return set_tap_pwup_fn(get_dev_idx_p(ifindex), tap_mode);
6935 EXPORT_SYMBOL(set_tap_pwup_sd);
6937 int get_tap_pwup_sd(int ifindex)
6939 return get_tap_pwup_fn(get_dev_idx_p(ifindex));
6942 EXPORT_SYMBOL(get_tap_pwup_sd);
6944 int get_tap_change_sd(int ifindex)
6946 return get_tap_change_fn(get_dev_idx_p(ifindex));
6949 EXPORT_SYMBOL(get_tap_change_sd);
6951 int set_dis_tap_sd(int ifindex, int dis_param)
6953 return set_dis_tap_fn(get_dev_idx_p(ifindex), dis_param);
6956 EXPORT_SYMBOL(set_dis_tap_sd);
6958 int get_dis_tap_sd(int ifindex)
6960 return get_dis_tap_fn(get_dev_idx_p(ifindex));
6963 EXPORT_SYMBOL(get_dis_tap_sd);
6965 int set_bp_disc_sd(int ifindex, int disc_mode)
6967 return set_disc_fn(get_dev_idx_p(ifindex), disc_mode);
6970 EXPORT_SYMBOL(set_bp_disc_sd);
6972 int get_bp_disc_sd(int ifindex)
6974 return get_disc_fn(get_dev_idx_p(ifindex));
6977 EXPORT_SYMBOL(get_bp_disc_sd);
6979 int set_bp_disc_pwup_sd(int ifindex, int disc_mode)
6981 return set_disc_pwup_fn(get_dev_idx_p(ifindex), disc_mode);
6984 EXPORT_SYMBOL(set_bp_disc_pwup_sd);
6986 int get_bp_disc_pwup_sd(int ifindex)
6988 return get_disc_pwup_fn(get_dev_idx_p(ifindex));
6991 EXPORT_SYMBOL(get_bp_disc_pwup_sd);
6993 int get_bp_disc_change_sd(int ifindex)
6995 return get_disc_change_fn(get_dev_idx_p(ifindex));
6998 EXPORT_SYMBOL(get_bp_disc_change_sd);
7000 int set_bp_dis_disc_sd(int ifindex, int dis_param)
7002 return set_dis_disc_fn(get_dev_idx_p(ifindex), dis_param);
7005 EXPORT_SYMBOL(set_bp_dis_disc_sd);
7007 int get_bp_dis_disc_sd(int ifindex)
7009 return get_dis_disc_fn(get_dev_idx_p(ifindex));
7012 EXPORT_SYMBOL(get_bp_dis_disc_sd);
7014 int get_wd_exp_mode_sd(int ifindex)
7016 return get_wd_exp_mode_fn(get_dev_idx_p(ifindex));
7018 EXPORT_SYMBOL(get_wd_exp_mode_sd);
7020 int set_wd_exp_mode_sd(int ifindex, int param)
7022 return set_wd_exp_mode_fn(get_dev_idx_p(ifindex), param);
7025 EXPORT_SYMBOL(set_wd_exp_mode_sd);
7027 int reset_cont_sd(int ifindex)
7029 return reset_cont_fn(get_dev_idx_p(ifindex));
7033 int set_tx_sd(int ifindex, int tx_state)
7035 return set_tx_fn(get_dev_idx_p(ifindex), tx_state);
7038 EXPORT_SYMBOL(set_tx_sd);
7040 int set_tpl_sd(int ifindex, int tpl_state)
7042 return set_tpl_fn(get_dev_idx_p(ifindex), tpl_state);
7045 EXPORT_SYMBOL(set_tpl_sd);
7047 int set_bp_hw_reset_sd(int ifindex, int status)
7049 return set_bp_hw_reset_fn(get_dev_idx_p(ifindex), status);
7052 EXPORT_SYMBOL(set_bp_hw_reset_sd);
7054 int set_wd_autoreset_sd(int ifindex, int param)
7056 return set_wd_autoreset_fn(get_dev_idx_p(ifindex), param);
7059 EXPORT_SYMBOL(set_wd_autoreset_sd);
7061 int get_wd_autoreset_sd(int ifindex)
7063 return get_wd_autoreset_fn(get_dev_idx_p(ifindex));
7066 EXPORT_SYMBOL(get_wd_autoreset_sd);
7068 int get_bypass_caps_sd(int ifindex)
7070 return get_bypass_caps_fn(get_dev_idx_p(ifindex));
7072 EXPORT_SYMBOL(get_bypass_caps_sd);
7074 int get_bypass_slave_sd(int ifindex)
7076 struct bpctl_dev *pbpctl_dev_out;
7077 int ret = get_bypass_slave_fn(get_dev_idx_p(ifindex), &pbpctl_dev_out);
7079 return pbpctl_dev_out->ifindex;
7083 EXPORT_SYMBOL(get_bypass_slave_sd);
7085 int get_tx_sd(int ifindex)
7087 return get_tx_fn(get_dev_idx_p(ifindex));
7090 EXPORT_SYMBOL(get_tx_sd);
7092 int get_tpl_sd(int ifindex)
7094 return get_tpl_fn(get_dev_idx_p(ifindex));
7097 EXPORT_SYMBOL(get_tpl_sd);
7099 int get_bp_hw_reset_sd(int ifindex)
7101 return get_bp_hw_reset_fn(get_dev_idx_p(ifindex));
7104 EXPORT_SYMBOL(get_bp_hw_reset_sd);
7106 int get_bypass_info_sd(int ifindex, struct bp_info *bp_info)
7108 return get_bypass_info_fn(get_dev_idx_p(ifindex), bp_info->prod_name, &bp_info->fw_ver);
7110 EXPORT_SYMBOL(get_bypass_info_sd);
7112 int bp_if_scan_sd(void)
7117 EXPORT_SYMBOL(bp_if_scan_sd);
7119 #define BP_PROC_DIR "bypass"
7121 static struct proc_dir_entry *bp_procfs_dir;
7123 int bp_proc_create(void)
7125 bp_procfs_dir = proc_mkdir(BP_PROC_DIR, init_net.proc_net);
7126 if (bp_procfs_dir == (struct proc_dir_entry *)0) {
7128 "Could not create procfs nicinfo directory %s\n",
7135 static int procfs_add(char *proc_name, const struct file_operations *fops,
7136 struct bpctl_dev *dev)
7138 struct bypass_pfs_sd *pfs = &dev->bypass_pfs_set;
7139 if (!proc_create_data(proc_name, 0644, pfs->bypass_entry, fops, dev))
7144 #define RO_FOPS(name) \
7145 static int name##_open(struct inode *inode, struct file *file) \
7147 return single_open(file, show_##name, PDE_DATA(inode));\
7149 static const struct file_operations name##_ops = { \
7150 .open = name##_open, \
7152 .llseek = seq_lseek, \
7153 .release = single_release, \
7156 #define RW_FOPS(name) \
7157 static int name##_open(struct inode *inode, struct file *file) \
7159 return single_open(file, show_##name, PDE_DATA(inode));\
7161 static const struct file_operations name##_ops = { \
7162 .open = name##_open, \
7164 .write = name##_write, \
7165 .llseek = seq_lseek, \
7166 .release = single_release, \
7169 static int show_bypass_info(struct seq_file *m, void *v)
7171 struct bpctl_dev *dev = m->private;
7173 seq_printf(m, "Name\t\t\t%s\n", dev->name);
7174 seq_printf(m, "Firmware version\t0x%x\n", dev->bp_fw_ver);
7177 RO_FOPS(bypass_info)
7179 static int show_bypass_slave(struct seq_file *m, void *v)
7181 struct bpctl_dev *dev = m->private;
7182 struct bpctl_dev *slave = get_status_port_fn(dev);
7186 seq_puts(m, "fail\n");
7187 else if (slave->ndev)
7188 seq_printf(m, "%s\n", slave->ndev->name);
7191 RO_FOPS(bypass_slave)
7193 static int show_bypass_caps(struct seq_file *m, void *v)
7195 struct bpctl_dev *dev = m->private;
7196 int ret = get_bypass_caps_fn(dev);
7197 if (ret == BP_NOT_CAP)
7198 seq_puts(m, "-1\n");
7200 seq_printf(m, "0x%x\n", ret);
7203 RO_FOPS(bypass_caps)
7205 static int show_wd_set_caps(struct seq_file *m, void *v)
7207 struct bpctl_dev *dev = m->private;
7208 int ret = get_wd_set_caps_fn(dev);
7209 if (ret == BP_NOT_CAP)
7210 seq_puts(m, "-1\n");
7212 seq_printf(m, "0x%x\n", ret);
7215 RO_FOPS(wd_set_caps)
7217 static int user_on_off(const void __user *buffer, size_t count)
7223 if (count > (sizeof(kbuf) - 1))
7226 if (copy_from_user(&kbuf, buffer, count))
7230 length = strlen(kbuf);
7231 if (kbuf[length - 1] == '\n')
7232 kbuf[--length] = '\0';
7234 if (strcmp(kbuf, "on") == 0)
7236 if (strcmp(kbuf, "off") == 0)
7241 static ssize_t bypass_write(struct file *file, const char __user *buffer,
7242 size_t count, loff_t *pos)
7244 int bypass_param = user_on_off(buffer, count);
7245 if (bypass_param < 0)
7248 set_bypass_fn(PDE_DATA(file_inode(file)), bypass_param);
7251 static int show_bypass(struct seq_file *m, void *v)
7253 struct bpctl_dev *dev = m->private;
7254 int ret = get_bypass_fn(dev);
7255 if (ret == BP_NOT_CAP)
7256 seq_puts(m, "fail\n");
7258 seq_puts(m, "on\n");
7260 seq_puts(m, "off\n");
7265 static ssize_t tap_write(struct file *file, const char __user *buffer,
7266 size_t count, loff_t *pos)
7268 int tap_param = user_on_off(buffer, count);
7272 set_tap_fn(PDE_DATA(file_inode(file)), tap_param);
7275 static int show_tap(struct seq_file *m, void *v)
7277 struct bpctl_dev *dev = m->private;
7278 int ret = get_tap_fn(dev);
7279 if (ret == BP_NOT_CAP)
7280 seq_puts(m, "fail\n");
7282 seq_puts(m, "on\n");
7284 seq_puts(m, "off\n");
7289 static ssize_t disc_write(struct file *file, const char __user *buffer,
7290 size_t count, loff_t *pos)
7292 int tap_param = user_on_off(buffer, count);
7296 set_disc_fn(PDE_DATA(file_inode(file)), tap_param);
7299 static int show_disc(struct seq_file *m, void *v)
7301 struct bpctl_dev *dev = m->private;
7302 int ret = get_disc_fn(dev);
7303 if (ret == BP_NOT_CAP)
7304 seq_puts(m, "fail\n");
7306 seq_puts(m, "on\n");
7308 seq_puts(m, "off\n");
7313 static int show_bypass_change(struct seq_file *m, void *v)
7315 struct bpctl_dev *dev = m->private;
7316 int ret = get_bypass_change_fn(dev);
7318 seq_puts(m, "on\n");
7320 seq_puts(m, "off\n");
7322 seq_puts(m, "fail\n");
7325 RO_FOPS(bypass_change)
7327 static int show_tap_change(struct seq_file *m, void *v)
7329 struct bpctl_dev *dev = m->private;
7330 int ret = get_tap_change_fn(dev);
7332 seq_puts(m, "on\n");
7334 seq_puts(m, "off\n");
7336 seq_puts(m, "fail\n");
7341 static int show_disc_change(struct seq_file *m, void *v)
7343 struct bpctl_dev *dev = m->private;
7344 int ret = get_disc_change_fn(dev);
7346 seq_puts(m, "on\n");
7348 seq_puts(m, "off\n");
7350 seq_puts(m, "fail\n");
7353 RO_FOPS(disc_change)
7355 static ssize_t bypass_wd_write(struct file *file, const char __user *buffer,
7356 size_t count, loff_t *pos)
7358 struct bpctl_dev *dev = PDE_DATA(file_inode(file));
7360 int ret = kstrtoint_from_user(buffer, count, 10, &timeout);
7363 set_bypass_wd_fn(dev, timeout);
7366 static int show_bypass_wd(struct seq_file *m, void *v)
7368 struct bpctl_dev *dev = m->private;
7369 int ret = 0, timeout = 0;
7371 ret = get_bypass_wd_fn(dev, &timeout);
7372 if (ret == BP_NOT_CAP)
7373 seq_puts(m, "fail\n");
7374 else if (timeout == -1)
7375 seq_puts(m, "unknown\n");
7376 else if (timeout == 0)
7377 seq_puts(m, "disable\n");
7379 seq_printf(m, "%d\n", timeout);
7384 static int show_wd_expire_time(struct seq_file *m, void *v)
7386 struct bpctl_dev *dev = m->private;
7387 int ret = 0, timeout = 0;
7388 ret = get_wd_expire_time_fn(dev, &timeout);
7389 if (ret == BP_NOT_CAP)
7390 seq_puts(m, "fail\n");
7391 else if (timeout == -1)
7392 seq_puts(m, "expire\n");
7393 else if (timeout == 0)
7394 seq_puts(m, "disable\n");
7396 seq_printf(m, "%d\n", timeout);
7399 RO_FOPS(wd_expire_time)
7401 static ssize_t tpl_write(struct file *file, const char __user *buffer,
7402 size_t count, loff_t *pos)
7404 struct bpctl_dev *dev = PDE_DATA(file_inode(file));
7405 int tpl_param = user_on_off(buffer, count);
7409 set_tpl_fn(dev, tpl_param);
7412 static int show_tpl(struct seq_file *m, void *v)
7414 struct bpctl_dev *dev = m->private;
7415 int ret = get_tpl_fn(dev);
7416 if (ret == BP_NOT_CAP)
7417 seq_puts(m, "fail\n");
7419 seq_puts(m, "on\n");
7421 seq_puts(m, "off\n");
7427 static ssize_t wait_at_pwup_write(struct file *file, const char __user *buffer,
7428 size_t count, loff_t *pos)
7430 struct bpctl_dev *dev = PDE_DATA(file_inode(file));
7431 int tpl_param = user_on_off(buffer, count);
7435 set_bp_wait_at_pwup_fn(dev, tpl_param);
7438 static int show_wait_at_pwup(struct seq_file *m, void *v)
7440 struct bpctl_dev *dev = m->private;
7441 int ret = get_bp_wait_at_pwup_fn(dev);
7442 if (ret == BP_NOT_CAP)
7443 seq_puts(m, "fail\n");
7445 seq_puts(m, "on\n");
7447 seq_puts(m, "off\n");
7450 RW_FOPS(wait_at_pwup)
7452 static ssize_t hw_reset_write(struct file *file, const char __user *buffer,
7453 size_t count, loff_t *pos)
7455 struct bpctl_dev *dev = PDE_DATA(file_inode(file));
7456 int tpl_param = user_on_off(buffer, count);
7460 set_bp_hw_reset_fn(dev, tpl_param);
7463 static int show_hw_reset(struct seq_file *m, void *v)
7465 struct bpctl_dev *dev = m->private;
7466 int ret = get_bp_hw_reset_fn(dev);
7467 if (ret == BP_NOT_CAP)
7468 seq_puts(m, "fail\n");
7470 seq_puts(m, "on\n");
7472 seq_puts(m, "off\n");
7477 #endif /*PMC_WAIT_FLAG */
7479 static int show_reset_bypass_wd(struct seq_file *m, void *v)
7481 struct bpctl_dev *dev = m->private;
7482 int ret = reset_bypass_wd_timer_fn(dev);
7483 if (ret == BP_NOT_CAP)
7484 seq_puts(m, "fail\n");
7486 seq_puts(m, "disable\n");
7488 seq_puts(m, "success\n");
7491 RO_FOPS(reset_bypass_wd)
7493 static ssize_t dis_bypass_write(struct file *file, const char __user *buffer,
7494 size_t count, loff_t *pos)
7496 int bypass_param = user_on_off(buffer, count);
7497 if (bypass_param < 0)
7500 set_dis_bypass_fn(PDE_DATA(file_inode(file)), bypass_param);
7503 static int show_dis_bypass(struct seq_file *m, void *v)
7505 struct bpctl_dev *dev = m->private;
7506 int ret = get_dis_bypass_fn(dev);
7507 if (ret == BP_NOT_CAP)
7508 seq_puts(m, "fail\n");
7510 seq_puts(m, "off\n");
7512 seq_puts(m, "on\n");
7517 static ssize_t dis_tap_write(struct file *file, const char __user *buffer,
7518 size_t count, loff_t *pos)
7520 int tap_param = user_on_off(buffer, count);
7524 set_dis_tap_fn(PDE_DATA(file_inode(file)), tap_param);
7527 static int show_dis_tap(struct seq_file *m, void *v)
7529 struct bpctl_dev *dev = m->private;
7530 int ret = get_dis_tap_fn(dev);
7531 if (ret == BP_NOT_CAP)
7532 seq_puts(m, "fail\n");
7534 seq_puts(m, "off\n");
7536 seq_puts(m, "on\n");
7541 static ssize_t dis_disc_write(struct file *file, const char __user *buffer,
7542 size_t count, loff_t *pos)
7544 int tap_param = user_on_off(buffer, count);
7548 set_dis_disc_fn(PDE_DATA(file_inode(file)), tap_param);
7551 static int show_dis_disc(struct seq_file *m, void *v)
7553 struct bpctl_dev *dev = m->private;
7554 int ret = get_dis_disc_fn(dev);
7555 if (ret == BP_NOT_CAP)
7556 seq_puts(m, "fail\n");
7558 seq_puts(m, "off\n");
7560 seq_puts(m, "on\n");
7565 static ssize_t bypass_pwup_write(struct file *file, const char __user *buffer,
7566 size_t count, loff_t *pos)
7568 int bypass_param = user_on_off(buffer, count);
7569 if (bypass_param < 0)
7572 set_bypass_pwup_fn(PDE_DATA(file_inode(file)), bypass_param);
7575 static int show_bypass_pwup(struct seq_file *m, void *v)
7577 struct bpctl_dev *dev = m->private;
7578 int ret = get_bypass_pwup_fn(dev);
7579 if (ret == BP_NOT_CAP)
7580 seq_puts(m, "fail\n");
7582 seq_puts(m, "off\n");
7584 seq_puts(m, "on\n");
7587 RW_FOPS(bypass_pwup)
7589 static ssize_t bypass_pwoff_write(struct file *file, const char __user *buffer,
7590 size_t count, loff_t *pos)
7592 int bypass_param = user_on_off(buffer, count);
7593 if (bypass_param < 0)
7596 set_bypass_pwoff_fn(PDE_DATA(file_inode(file)), bypass_param);
7599 static int show_bypass_pwoff(struct seq_file *m, void *v)
7601 struct bpctl_dev *dev = m->private;
7602 int ret = get_bypass_pwoff_fn(dev);
7603 if (ret == BP_NOT_CAP)
7604 seq_puts(m, "fail\n");
7606 seq_puts(m, "off\n");
7608 seq_puts(m, "on\n");
7611 RW_FOPS(bypass_pwoff)
7613 static ssize_t tap_pwup_write(struct file *file, const char __user *buffer,
7614 size_t count, loff_t *pos)
7616 int tap_param = user_on_off(buffer, count);
7620 set_tap_pwup_fn(PDE_DATA(file_inode(file)), tap_param);
7623 static int show_tap_pwup(struct seq_file *m, void *v)
7625 struct bpctl_dev *dev = m->private;
7626 int ret = get_tap_pwup_fn(dev);
7627 if (ret == BP_NOT_CAP)
7628 seq_puts(m, "fail\n");
7630 seq_puts(m, "off\n");
7632 seq_puts(m, "on\n");
7637 static ssize_t disc_pwup_write(struct file *file, const char __user *buffer,
7638 size_t count, loff_t *pos)
7640 int tap_param = user_on_off(buffer, count);
7644 set_disc_pwup_fn(PDE_DATA(file_inode(file)), tap_param);
7647 static int show_disc_pwup(struct seq_file *m, void *v)
7649 struct bpctl_dev *dev = m->private;
7650 int ret = get_disc_pwup_fn(dev);
7651 if (ret == BP_NOT_CAP)
7652 seq_puts(m, "fail\n");
7654 seq_puts(m, "off\n");
7656 seq_puts(m, "on\n");
7661 static ssize_t std_nic_write(struct file *file, const char __user *buffer,
7662 size_t count, loff_t *pos)
7664 int bypass_param = user_on_off(buffer, count);
7665 if (bypass_param < 0)
7668 set_std_nic_fn(PDE_DATA(file_inode(file)), bypass_param);
7671 static int show_std_nic(struct seq_file *m, void *v)
7673 struct bpctl_dev *dev = m->private;
7674 int ret = get_std_nic_fn(dev);
7675 if (ret == BP_NOT_CAP)
7676 seq_puts(m, "fail\n");
7678 seq_puts(m, "off\n");
7680 seq_puts(m, "on\n");
7685 static ssize_t wd_exp_mode_write(struct file *file, const char __user *buffer,
7686 size_t count, loff_t *pos)
7689 int bypass_param = 0, length = 0;
7691 if (count > (sizeof(kbuf) - 1))
7694 if (copy_from_user(&kbuf, buffer, count))
7698 length = strlen(kbuf);
7699 if (kbuf[length - 1] == '\n')
7700 kbuf[--length] = '\0';
7702 if (strcmp(kbuf, "tap") == 0)
7704 else if (strcmp(kbuf, "bypass") == 0)
7706 else if (strcmp(kbuf, "disc") == 0)
7709 set_wd_exp_mode_fn(PDE_DATA(file_inode(file)), bypass_param);
7713 static int show_wd_exp_mode(struct seq_file *m, void *v)
7715 struct bpctl_dev *dev = m->private;
7716 int ret = get_wd_exp_mode_fn(dev);
7718 seq_puts(m, "tap\n");
7720 seq_puts(m, "bypass\n");
7722 seq_puts(m, "disc\n");
7724 seq_puts(m, "fail\n");
7727 RW_FOPS(wd_exp_mode)
7729 static ssize_t wd_autoreset_write(struct file *file, const char __user *buffer,
7730 size_t count, loff_t *pos)
7733 int ret = kstrtoint_from_user(buffer, count, 10, &timeout);
7736 set_wd_autoreset_fn(PDE_DATA(file_inode(file)), timeout);
7739 static int show_wd_autoreset(struct seq_file *m, void *v)
7741 struct bpctl_dev *dev = m->private;
7742 int ret = get_wd_autoreset_fn(dev);
7744 seq_printf(m, "%d\n", ret);
7746 seq_puts(m, "fail\n");
7749 RW_FOPS(wd_autoreset)
7751 int bypass_proc_create_dev_sd(struct bpctl_dev *pbp_device_block)
7753 struct bypass_pfs_sd *current_pfs = &(pbp_device_block->bypass_pfs_set);
7754 static struct proc_dir_entry *procfs_dir;
7757 if (!pbp_device_block->ndev)
7759 sprintf(current_pfs->dir_name, "bypass_%s",
7760 pbp_device_block->ndev->name);
7765 /* create device proc dir */
7766 procfs_dir = proc_mkdir(current_pfs->dir_name, bp_procfs_dir);
7768 printk(KERN_DEBUG "Could not create procfs directory %s\n",
7769 current_pfs->dir_name);
7772 current_pfs->bypass_entry = procfs_dir;
7774 #define ENTRY(x) (ret |= procfs_add(#x, &x##_ops, pbp_device_block))
7777 if (pbp_device_block->bp_caps & SW_CTL_CAP) {
7778 /* Create set param proc's */
7779 ENTRY(bypass_slave);
7783 ENTRY(wd_expire_time);
7784 ENTRY(reset_bypass_wd);
7786 if (pbp_device_block->bp_caps & BP_CAP) {
7790 ENTRY(bypass_pwoff);
7791 ENTRY(bypass_change);
7793 if (pbp_device_block->bp_caps & TAP_CAP) {
7799 if (pbp_device_block->bp_caps & DISC_CAP) {
7807 ENTRY(wd_autoreset);
7810 ENTRY(wait_at_pwup);
7816 printk(KERN_DEBUG "Create proc entry failed\n");
7821 int bypass_proc_remove_dev_sd(struct bpctl_dev *pbp_device_block)
7824 struct bypass_pfs_sd *current_pfs = &pbp_device_block->bypass_pfs_set;
7825 remove_proc_subtree(current_pfs->dir_name, bp_procfs_dir);
7826 current_pfs->bypass_entry = NULL;